src/mainboard/system76/oryp6/devicetree.cb

   1 # SPDX-License-Identifier: GPL-2.0-only
   2
   3 chip soc/intel/cannonlake
   4         register "common_soc_config" = "{
   5                 // Touchpad I2C bus
   6                 .i2c[0] = {
   7                         .speed = I2C_SPEED_FAST,
   8                         .rise_time_ns = 80,
   9                         .fall_time_ns = 110,
  10                 },
  11         }"
  12
  13 # CPU (soc/intel/cannonlake/cpu.c)
  14         # Power limit
  15         register "power_limits_config" = "{
  16                 .tdp_pl1_override = 45,
  17                 .tdp_pl2_override = 90,
  18         }"
  19
  20         # Enable Enhanced Intel SpeedStep
  21         register "eist_enable" = "true"
  22
  23 # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
  24         register "enable_c6dram" = "1"
  25
  26 # FSP Silicon (soc/intel/cannonlake/fsp_params.c)
  27         # Serial I/O
  28         register "SerialIoDevMode" = "{
  29                 [PchSerialIoIndexI2C0] = PchSerialIoPci, // Touchpad I2C bus
  30         }"
  31
  32         # Misc
  33         register "AcousticNoiseMitigation" = "1"
  34
  35         # Power
  36         register "PchPmSlpS3MinAssert" = "3" # 50ms
  37         register "PchPmSlpS4MinAssert" = "1" # 1s
  38         register "PchPmSlpSusMinAssert" = "4" # 4s
  39         register "PchPmSlpAMinAssert" = "4" # 2s
  40
  41         # Thermal
  42         register "tcc_offset" = "8"
  43
  44         # Serial IRQ Continuous
  45         register "serirq_mode" = "SERIRQ_CONTINUOUS"
  46
  47 # PM Util (soc/intel/cannonlake/pmutil.c)
  48         # GPE configuration
  49         # Note that GPE events called out in ASL code rely on this
  50         # route. i.e. If this route changes then the affected GPE
  51         # offset bits also need to be changed.
  52         register "gpe0_dw0" = "PMC_GPP_K"
  53         register "gpe0_dw1" = "PMC_GPP_G"
  54         register "gpe0_dw2" = "PMC_GPP_E"
  55
  56 # Actual device tree
  57         device domain 0 on
  58                 device ref peg0         on
  59                         # PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
  60                         register "PcieClkSrcUsage[8]" = "0x40"
  61                         register "PcieClkSrcClkReq[8]" = "8"
  62                 end
  63                 device ref igpu         on
  64                         register "gfx" = "GMA_DEFAULT_PANEL(0)"
  65                 end
  66                 device ref dptf         on
  67                         register "Device4Enable" = "1"
  68                 end
  69                 device ref thermal      on      end
  70                 device ref xhci         on
  71                         register "usb2_ports" = "{
  72                                 [0] = USB2_PORT_MID(OC_SKIP),           /* USB 3 Left */
  73                                 [1] = USB2_PORT_TYPE_C(OC_SKIP),        /* Type-C */
  74                                 [2] = USB2_PORT_MID(OC_SKIP),           /* USB 3 Right 1 */
  75                                 [3] = USB2_PORT_MID(OC_SKIP),           /* USB 3 Right 2 */
  76                                 [4] = USB2_PORT_MID(OC_SKIP),           /* Per-key RGB */
  77                                 [7] = USB2_PORT_MID(OC_SKIP),           /* Camera */
  78                                 [10] = USB2_PORT_MID(OC_SKIP),          /* Fingerprint */
  79                                 [13] = USB2_PORT_MID(OC_SKIP),          /* Bluetooth */
  80                         }"
  81                         register "usb3_ports" = "{
  82                                 [0] = USB3_PORT_DEFAULT(OC_SKIP),       /* USB 3 Left */
  83                                 [2] = USB3_PORT_DEFAULT(OC_SKIP),       /* USB 3 right 1 */
  84                                 [3] = USB3_PORT_DEFAULT(OC_SKIP),       /* USB 3 right 2 */
  85                         }"
  86                 end
  87                 device ref shared_sram  on      end
  88                 device ref cnvi_wifi    on
  89                         chip drivers/wifi/generic
  90                                 register "wake" = "PME_B0_EN_BIT"
  91                                 device generic 0 on end
  92                         end
  93                 end
  94                 device ref i2c0         on
  95                         chip drivers/i2c/hid
  96                                 register "generic.hid" = ""SYNA1202""
  97                                 register "generic.desc" = ""Synaptics Touchpad""
  98                                 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)"
  99                                 register "generic.detect" = "1"
 100                                 register "hid_desc_reg_offset" = "0x20"
 101                                 device i2c 2c on end
 102                         end
 103                 end
 104                 device ref sata         on
 105                         register "SataPortsEnable[1]" = "1" # SSD (SATA1A)
 106                 end
 107                 device ref pcie_rp17    on
 108                         # PCI Express root port #17 x4, Clock 0 (Thunderbolt)
 109                         register "PcieRpEnable[16]" = "1"
 110                         register "PcieRpLtrEnable[16]" = "1"
 111                         register "PcieRpHotPlug[16]" = "1"
 112                         register "PcieClkSrcUsage[0]" = "16"
 113                         register "PcieClkSrcClkReq[0]" = "0"
 114                         register "PcieRpSlotImplemented[16]" = "1"
 115                 end
 116                 device ref pcie_rp21    on
 117                         # PCI Express root port #21 x4, Clock 11 (SSD2)
 118                         register "PcieRpEnable[20]" = "1"
 119                         register "PcieRpLtrEnable[20]" = "1"
 120                         register "PcieClkSrcUsage[11]" = "20"
 121                         register "PcieClkSrcClkReq[11]" = "11"
 122                         register "PcieRpSlotImplemented[20]" = "1"
 123                 end
 124                 device ref pcie_rp9     on
 125                         # PCI Express root port #9 x4, Clock 12 (SSD1)
 126                         register "PcieRpEnable[8]" = "1"
 127                         register "PcieRpLtrEnable[8]" = "1"
 128                         register "PcieClkSrcUsage[12]" = "8"
 129                         register "PcieClkSrcClkReq[12]" = "12"
 130                         register "PcieRpSlotImplemented[8]" = "1"
 131                 end
 132                 device ref pcie_rp14    on
 133                         # PCI Express root port #14 x1, Clock 7 (GLAN)
 134                         register "PcieRpEnable[13]" = "1"
 135                         register "PcieRpLtrEnable[13]" = "1"
 136                         register "PcieClkSrcUsage[7]" = "13"
 137                         register "PcieClkSrcClkReq[7]" = "7"
 138                         register "PcieRpSlotImplemented[13]" = "1"
 139                 end
 140                 device ref pcie_rp15    on
 141                         # PCI Express root port #15 x1, Clock 9 (Card Reader)
 142                         register "PcieRpEnable[14]" = "1"
 143                         register "PcieRpLtrEnable[14]" = "1"
 144                         register "PcieClkSrcUsage[9]" = "14"
 145                         register "PcieClkSrcClkReq[9]" = "9"
 146                         register "PcieRpSlotImplemented[14]" = "1"
 147                 end
 148                 device ref pcie_rp16    on
 149                         # PCI Express root port #16 x1, Clock 6 (WLAN)
 150                         register "PcieRpEnable[15]" = "1"
 151                         register "PcieRpLtrEnable[15]" = "1"
 152                         register "PcieClkSrcUsage[6]" = "15"
 153                         register "PcieClkSrcClkReq[6]" = "6"
 154                         register "PcieRpSlotImplemented[15]" = "1"
 155                 end
 156                 device ref lpc_espi     on
 157                         register "gen1_dec" = "0x00040069" # EC PM channel
 158                         register "gen2_dec" = "0x00fc0e01" # AP/EC command
 159                         register "gen3_dec" = "0x00fc0f01" # AP/EC debug
 160                         chip drivers/pc80/tpm
 161                                 device pnp 0c31.0 on end
 162                         end
 163                 end
 164                 device ref hda          on
 165                         register "PchHdaAudioLinkHda" = "1"
 166                 end
 167                 device ref smbus        on
 168                         chip drivers/i2c/tas5825m
 169                                 register "id" = "0"
 170                                 device i2c 4e on end # (8bit address: 0x9c)
 171                         end
 172                 end
 173         end
 174 end