src/vendorcode/amd/pi/00730F01/AMD.h

   1 /* SPDX-License-Identifier: BSD-3-Clause */
   2
   3 /* $NoKeywords:$ */
   4 /**
   5  * @file
   6  *
   7  * Agesa structures and definitions
   8  *
   9  * Contains AMD AGESA core interface
  10  *
  11  * @xrefitem bom "File Content Label" "Release Content"
  12  * @e project:      AGESA
  13  * @e sub-project:  Include
  14  * @e \$Revision: 281178 $   @e \$Date: 2013-12-18 02:14:15 -0600 (Wed, 18 Dec 2013) $
  15  */
  16 /*****************************************************************************
  17  *
  18  * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
  19  * All rights reserved.
  20  *
  21  * Redistribution and use in source and binary forms, with or without
  22  * modification, are permitted provided that the following conditions are met:
  23  *     * Redistributions of source code must retain the above copyright
  24  *       notice, this list of conditions and the following disclaimer.
  25  *     * Redistributions in binary form must reproduce the above copyright
  26  *       notice, this list of conditions and the following disclaimer in the
  27  *       documentation and/or other materials provided with the distribution.
  28  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
  29  *       its contributors may be used to endorse or promote products derived
  30  *       from this software without specific prior written permission.
  31  *
  32  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  33  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  34  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  35  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
  36  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  37  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  38  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  39  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  40  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  41  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42  *
  43  ***************************************************************************/
  44
  45
  46 #ifndef _AMD_H_
  47 #define _AMD_H_
  48
  49 #define Int16FromChar(a,b) (UINT16)((a) << 0 | (b) << 8)
  50 #define Int32FromChar(a,b,c,d) (UINT32)((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24)
  51 #define Int64FromChar(a,b,c,d,e,f,g,h) ((UINT64)(Int32FromChar(a,b,c,d)<<32) | (UINT64)Int32FromChar(e,f,g,h))
  52
  53 #define AGESA_REVISION  "Arch2008"
  54 #define AGESA_ID        {'A', 'G', 'E', 'S', 'A', 0x00, 0x00, 0x00}
  55
  56 //
  57 //
  58 // AGESA Types and Definitions
  59 //
  60 //
  61 #define LAST_ENTRY          0xFFFFFFFFul
  62 #define IMAGE_SIGNATURE     Int32FromChar ('$', 'A', 'M', 'D')
  63 #define MODULE_SIGNATURE    Int32FromChar ('$', 'M', 'O', 'D')
  64 #define IOCF8 0xCF8
  65 #define IOCFC 0xCFC
  66
  67 /// The return status for all AGESA public services.
  68 ///
  69 /// Services return the most severe status of any logged event.  Status other than SUCCESS, UNSUPPORTED, and BOUNDS_CHK
  70 /// will have log entries with more detail.
  71 ///
  72 typedef enum {
  73   AGESA_SUCCESS = 0,             ///< The service completed normally. Info may be logged.
  74   AGESA_UNSUPPORTED,             ///< The dispatcher or create struct had an unimplemented function requested.
  75                                  ///<  Not logged.
  76   AGESA_BOUNDS_CHK,              ///< A dynamic parameter was out of range and the service was not provided.
  77                                  ///< Example, memory address not installed, heap buffer handle not found.
  78                                  ///< Not Logged.
  79   // AGESA_STATUS of greater severity (the ones below this line), always have a log entry available.
  80   AGESA_ALERT,                   ///< An observed condition, but no loss of function.  See Log.
  81   AGESA_WARNING,                 ///< Possible or minor loss of function.  See Log.
  82   AGESA_ERROR,                   ///< Significant loss of function, boot may be possible.  See Log.
  83   AGESA_CRITICAL,                ///< Continue boot only to notify user.  See Log.
  84   AGESA_FATAL,                   ///< Halt booting.  See Log, however Fatal errors pertaining to heap problems
  85                                  ///< may not be able to reliably produce log events.
  86   AgesaStatusMax                 ///< Not a status, for limit checking.
  87 } AGESA_STATUS;
  88
  89 /// For checking whether a status is at or above the mandatory log level.
  90 #define AGESA_STATUS_LOG_LEVEL AGESA_ALERT
  91
  92 /**
  93  * Callout method to the host environment.
  94  *
  95  * Callout using a dispatch with appropriate thunk layer, which is determined by the host environment.
  96  *
  97  * @param[in]        Function      The specific callout function being invoked.
  98  * @param[in]        FcnData       Function specific data item.
  99  * @param[in,out]    ConfigPtr     Reference to Callout params.
 100  */
 101 typedef AGESA_STATUS (*CALLOUT_ENTRY) (
 102   IN       UINT32  Function,
 103   IN       UINTN   FcnData,
 104   IN OUT   VOID    *ConfigPtr
 105   );
 106
 107 typedef AGESA_STATUS (*IMAGE_ENTRY) (VOID *ConfigPtr);
 108 typedef AGESA_STATUS (*MODULE_ENTRY) (VOID *ConfigPtr);
 109
 110 ///This allocation type is used by the AmdCreateStruct entry point
 111 typedef enum {
 112   PreMemHeap = 0,                                           ///< Create heap in cache.
 113   PostMemDram,                                              ///< Create heap in memory.
 114   ByHost                                                    ///< Create heap by Host.
 115 } ALLOCATION_METHOD;
 116
 117 /// These width descriptors are used by the library function, and others, to specify the data size
 118 typedef enum ACCESS_WIDTH {
 119   AccessWidth8 = 1,                                         ///< Access width is 8 bits.
 120   AccessWidth16,                                            ///< Access width is 16 bits.
 121   AccessWidth32,                                            ///< Access width is 32 bits.
 122   AccessWidth64,                                            ///< Access width is 64 bits.
 123
 124   AccessS3SaveWidth8 = 0x81,                                ///< Save 8 bits data.
 125   AccessS3SaveWidth16,                                      ///< Save 16 bits data.
 126   AccessS3SaveWidth32,                                      ///< Save 32 bits data.
 127   AccessS3SaveWidth64,                                      ///< Save 64 bits data.
 128 } ACCESS_WIDTH;
 129
 130 /// AGESA struct name
 131 typedef enum {
 132   // AGESA BASIC FUNCTIONS
 133   AMD_INIT_RECOVERY          = 0x00021000,                  ///< AmdInitRecovery entry point handle
 134   AMD_CREATE_STRUCT          = 0x00022000,                  ///< AmdCreateStruct handle
 135   AMD_INIT_EARLY             = 0x00023000,                  ///< AmdInitEarly entry point handle
 136   AMD_INIT_ENV               = 0x00024000,                  ///< AmdInitEnv entry point handle
 137   AMD_INIT_LATE              = 0x00025000,                  ///< AmdInitLate entry point handle
 138   AMD_INIT_MID               = 0x00026000,                  ///< AmdInitMid entry point handle
 139   AMD_INIT_POST              = 0x00027000,                  ///< AmdInitPost entry point handle
 140   AMD_INIT_RESET             = 0x00028000,                  ///< AmdInitReset entry point handle
 141   AMD_INIT_RESUME            = 0x00029000,                  ///< AmdInitResume entry point handle
 142   AMD_RELEASE_STRUCT         = 0x0002A000,                  ///< AmdReleaseStruct handle
 143   AMD_S3LATE_RESTORE         = 0x0002B000,                  ///< AmdS3LateRestore entry point handle
 144   AMD_S3_SAVE                = 0x0002C000,                  ///< AmdS3Save entry point handle
 145   AMD_GET_APIC_ID            = 0x0002D000,                  ///< AmdGetApicId entry point handle
 146   AMD_GET_PCI_ADDRESS        = 0x0002E000,                  ///< AmdGetPciAddress entry point handle
 147   AMD_IDENTIFY_CORE          = 0x0002F000,                  ///< AmdIdentifyCore general service handle
 148   AMD_READ_EVENT_LOG         = 0x00030000,                  ///< AmdReadEventLog general service handle
 149   AMD_GET_EXECACHE_SIZE      = 0x00031000,                  ///< AmdGetAvailableExeCacheSize general service handle
 150   AMD_LATE_RUN_AP_TASK       = 0x00032000,                  ///< AmdLateRunApTask entry point handle
 151   AMD_IDENTIFY_DIMMS         = 0x00033000,                  ///< AmdIdentifyDimm general service handle
 152   AMD_GET_2D_DATA_EYE        = 0x00034000,                  ///< AmdGet2DDataEye general service handle
 153   AMD_S3FINAL_RESTORE        = 0x00035000, /* reserved */
 154   AMD_INIT_RTB               = 0x00036000, /* reserved */
 155
 156   AMD_HEAP_ALLOCATE_BUFFER   = 0x00038000,
 157   AMD_HEAP_DEALLOCATE_BUFFER = 0x00039000,
 158   FCH_INIT_RESET             = 0x00040000,
 159   FCH_INIT_ENV               = 0x00041000,
 160   FCH_INIT_MID               = 0x00042000,
 161   FCH_INIT_LATE              = 0x00043000,
 162   FCH_INIT_S3_EARLY_RESTORE  = 0x00044000,
 163   FCH_INIT_S3_LATE_RESTORE   = 0x00045000,
 164   AMD_SET_VALUE_invalid      = 0x00081000,
 165   AMD_GET_VALUE_invalid      = 0x00082000,
 166 } AGESA_STRUCT_NAME;
 167
 168   /*  ResetType constant values */
 169 #define WARM_RESET_WHENEVER 1
 170 #define COLD_RESET_WHENEVER 2
 171 #define WARM_RESET_IMMEDIATELY 3
 172 #define COLD_RESET_IMMEDIATELY 4
 173
 174
 175 // AGESA Structures
 176
 177 /// The standard header for all AGESA services.
 178 /// For internal AGESA naming conventions, see @ref amdconfigparamname .
 179 typedef struct {
 180   IN       VOID *          ImageBasePtr;     ///< The AGESA Image base address.
 181   IN       UINT32          Func;             ///< The service desired
 182   IN       VOID *          AltImageBasePtr;  ///< Alternate Image location
 183   IN       CALLOUT_ENTRY   CalloutPtr;       ///< For Callout from AGESA
 184   IN       UINT8           HeapStatus;       ///< For heap status from boot time slide.
 185   IN       UINT64          HeapBasePtr;      ///< Location of the heap
 186   IN OUT   UINT8           Reserved[7];      ///< This space is reserved for future use.
 187 } AMD_CONFIG_PARAMS;
 188
 189
 190 /// Create Struct Interface.
 191 typedef struct {
 192   IN       AMD_CONFIG_PARAMS   StdHeader;          ///< Standard configuration header
 193   IN       AGESA_STRUCT_NAME   AgesaFunctionName;  ///< The service to init
 194   IN       ALLOCATION_METHOD   AllocationMethod;   ///< How to handle buffer allocation
 195   IN OUT   UINT32              NewStructSize;      ///< The size of the allocated data, in for ByHost, else out only.
 196   IN OUT   VOID                *NewStructPtr;      ///< The struct for the service.
 197                                                    ///< The struct to init for ByHost allocation,
 198                                                    ///< the initialized struct on return.
 199 } AMD_INTERFACE_PARAMS;
 200
 201 #define FUNC_0    0   // bit-placed for PCI address creation
 202 #define FUNC_1    1
 203 #define FUNC_2    2
 204 #define FUNC_3    3
 205 #define FUNC_4    4
 206 #define FUNC_5    5
 207 #define FUNC_6    6
 208 #define FUNC_7    7
 209
 210 /// AGESA Binary module header structure
 211 typedef struct {
 212   IN  UINT32  Signature;                          ///< Binary Signature
 213   IN  CHAR8   CreatorID[8];                       ///< 8 characters ID
 214   IN  CHAR8   Version[12];                        ///< 12 characters version
 215   IN  UINT32  ModuleInfoOffset;                   ///< Offset of module
 216   IN  UINT32  EntryPointAddress;                  ///< Entry address
 217   IN  UINT32  ImageBase;                          ///< Image base
 218   IN  UINT32  RelocTableOffset;                   ///< Relocate Table offset
 219   IN  UINT32  ImageSize;                          ///< Size
 220   IN  UINT16  Checksum;                           ///< Checksum
 221   IN  UINT8   ImageType;                          ///< Type
 222   IN  UINT8   V_Reserved;                         ///< Reserved
 223 } AMD_IMAGE_HEADER;
 224
 225 /// AGESA Binary module header structure
 226 typedef struct _AMD_MODULE_HEADER {
 227   IN  UINT32          ModuleHeaderSignature;      ///< Module signature
 228   IN  CHAR8           ModuleIdentifier[8];        ///< 8 characters ID
 229   IN  CHAR8           ModuleVersion[12];          ///< 12 characters version
 230   IN  VOID            *ModuleDispatcher;          ///< A pointer point to dispatcher
 231   IN  struct _AMD_MODULE_HEADER  *NextBlock;      ///< Next module header link
 232 } AMD_MODULE_HEADER;
 233
 234 // AMD_CODE_HEADER Signatures.
 235 #define AGESA_CODE_SIGNATURE  {'!', '!', '!', 'A', 'G', 'E', 'S', 'A'}
 236 #define CIMXNB_CODE_SIGNATURE {'!', '!', 'C', 'I', 'M', 'X', 'N', 'B'}
 237 #define CIMXSB_CODE_SIGNATURE {'!', '!', 'C', 'I', 'M', 'X', 'S', 'B'}
 238
 239 /// AGESA_CODE_SIGNATURE
 240 typedef struct {
 241   IN  CHAR8   Signature[8];                       ///< code header Signature
 242   IN  CHAR8   ComponentName[16];                  ///< 16 character name of the code module
 243   IN  CHAR8   Version[12];                        ///< 12 character version string
 244   IN  CHAR8   TerminatorNull;                     ///< null terminated string
 245   IN  CHAR8   VerReserved[7];                     ///< reserved space
 246 } AMD_CODE_HEADER;
 247
 248 /// Extended PCI address format
 249 typedef struct {
 250   IN OUT  UINT32      Register:12;                ///< Register offset
 251   IN OUT  UINT32      Function:3;                 ///< Function number
 252   IN OUT  UINT32      Device:5;                   ///< Device number
 253   IN OUT  UINT32      Bus:8;                      ///< Bus number
 254   IN OUT  UINT32      Segment:4;                  ///< Segment
 255 } EXT_PCI_ADDR;
 256
 257 /// Union type for PCI address
 258 typedef union _PCI_ADDR {
 259   IN  UINT32          AddressValue;               ///< Formal address
 260   IN  EXT_PCI_ADDR    Address;                    ///< Extended address
 261 } PCI_ADDR;
 262
 263 //   SBDFO - Segment Bus Device Function Offset
 264 //   31:28   Segment (4-bits)
 265 //   27:20   Bus     (8-bits)
 266 //   19:15   Device  (5-bits)
 267 //   14:12   Function(3-bits)
 268 //   11:00   Offset  (12-bits)
 269
 270 #define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((UINT32) (Seg)) << 28) | (((UINT32) (Bus)) << 20) | \
 271                    (((UINT32)(Dev)) << 15) | (((UINT32)(Fun)) << 12) | ((UINT32)(Off)))
 272 #define ILLEGAL_SBDFO 0xFFFFFFFFul
 273
 274 /// CPUID data received registers format
 275 typedef struct {
 276   OUT UINT32          EAX_Reg;                    ///< CPUID instruction result in EAX
 277   OUT UINT32          EBX_Reg;                    ///< CPUID instruction result in EBX
 278   OUT UINT32          ECX_Reg;                    ///< CPUID instruction result in ECX
 279   OUT UINT32          EDX_Reg;                    ///< CPUID instruction result in EDX
 280 } CPUID_DATA;
 281
 282 // Topology Services definitions and macros
 283 #define TOPOLOGY_LIST_TERMINAL             0xFF             ///< End of list.
 284
 285
 286 #ifndef BIT0
 287   #define BIT0        0x0000000000000001ull
 288 #endif
 289 #ifndef BIT1
 290   #define BIT1        0x0000000000000002ull
 291 #endif
 292 #ifndef BIT2
 293   #define BIT2        0x0000000000000004ull
 294 #endif
 295 #ifndef BIT3
 296   #define BIT3        0x0000000000000008ull
 297 #endif
 298 #ifndef BIT4
 299   #define BIT4        0x0000000000000010ull
 300 #endif
 301 #ifndef BIT5
 302   #define BIT5        0x0000000000000020ull
 303 #endif
 304 #ifndef BIT6
 305   #define BIT6        0x0000000000000040ull
 306 #endif
 307 #ifndef BIT7
 308   #define BIT7        0x0000000000000080ull
 309 #endif
 310 #ifndef BIT8
 311   #define BIT8        0x0000000000000100ull
 312 #endif
 313 #ifndef BIT9
 314   #define BIT9        0x0000000000000200ull
 315 #endif
 316 #ifndef BIT10
 317   #define BIT10       0x0000000000000400ull
 318 #endif
 319 #ifndef BIT11
 320   #define BIT11       0x0000000000000800ull
 321 #endif
 322 #ifndef BIT12
 323   #define BIT12       0x0000000000001000ull
 324 #endif
 325 #ifndef BIT13
 326   #define BIT13       0x0000000000002000ull
 327 #endif
 328 #ifndef BIT14
 329   #define BIT14       0x0000000000004000ull
 330 #endif
 331 #ifndef BIT15
 332   #define BIT15       0x0000000000008000ull
 333 #endif
 334 #ifndef BIT16
 335   #define BIT16       0x0000000000010000ull
 336 #endif
 337 #ifndef BIT17
 338   #define BIT17       0x0000000000020000ull
 339 #endif
 340 #ifndef BIT18
 341   #define BIT18       0x0000000000040000ull
 342 #endif
 343 #ifndef BIT19
 344   #define BIT19       0x0000000000080000ull
 345 #endif
 346 #ifndef BIT20
 347   #define BIT20       0x0000000000100000ull
 348 #endif
 349 #ifndef BIT21
 350   #define BIT21       0x0000000000200000ull
 351 #endif
 352 #ifndef BIT22
 353   #define BIT22       0x0000000000400000ull
 354 #endif
 355 #ifndef BIT23
 356   #define BIT23       0x0000000000800000ull
 357 #endif
 358 #ifndef BIT24
 359   #define BIT24       0x0000000001000000ull
 360 #endif
 361 #ifndef BIT25
 362   #define BIT25       0x0000000002000000ull
 363 #endif
 364 #ifndef BIT26
 365   #define BIT26       0x0000000004000000ull
 366 #endif
 367 #ifndef BIT27
 368   #define BIT27       0x0000000008000000ull
 369 #endif
 370 #ifndef BIT28
 371   #define BIT28       0x0000000010000000ull
 372 #endif
 373 #ifndef BIT29
 374   #define BIT29       0x0000000020000000ull
 375 #endif
 376 #ifndef BIT30
 377   #define BIT30       0x0000000040000000ull
 378 #endif
 379 #ifndef BIT31
 380   #define BIT31       0x0000000080000000ull
 381 #endif
 382 #ifndef BIT32
 383   #define BIT32       0x0000000100000000ull
 384 #endif
 385 #ifndef BIT33
 386   #define BIT33       0x0000000200000000ull
 387 #endif
 388 #ifndef BIT34
 389   #define BIT34       0x0000000400000000ull
 390 #endif
 391 #ifndef BIT35
 392   #define BIT35       0x0000000800000000ull
 393 #endif
 394 #ifndef BIT36
 395   #define BIT36       0x0000001000000000ull
 396 #endif
 397 #ifndef BIT37
 398   #define BIT37       0x0000002000000000ull
 399 #endif
 400 #ifndef BIT38
 401   #define BIT38       0x0000004000000000ull
 402 #endif
 403 #ifndef BIT39
 404   #define BIT39       0x0000008000000000ull
 405 #endif
 406 #ifndef BIT40
 407   #define BIT40       0x0000010000000000ull
 408 #endif
 409 #ifndef BIT41
 410   #define BIT41       0x0000020000000000ull
 411 #endif
 412 #ifndef BIT42
 413   #define BIT42       0x0000040000000000ull
 414 #endif
 415 #ifndef BIT43
 416   #define BIT43       0x0000080000000000ull
 417 #endif
 418 #ifndef BIT44
 419   #define BIT44       0x0000100000000000ull
 420 #endif
 421 #ifndef BIT45
 422   #define BIT45       0x0000200000000000ull
 423 #endif
 424 #ifndef BIT46
 425   #define BIT46       0x0000400000000000ull
 426 #endif
 427 #ifndef BIT47
 428   #define BIT47       0x0000800000000000ull
 429 #endif
 430 #ifndef BIT48
 431   #define BIT48       0x0001000000000000ull
 432 #endif
 433 #ifndef BIT49
 434   #define BIT49       0x0002000000000000ull
 435 #endif
 436 #ifndef BIT50
 437   #define BIT50       0x0004000000000000ull
 438 #endif
 439 #ifndef BIT51
 440   #define BIT51       0x0008000000000000ull
 441 #endif
 442 #ifndef BIT52
 443   #define BIT52       0x0010000000000000ull
 444 #endif
 445 #ifndef BIT53
 446   #define BIT53       0x0020000000000000ull
 447 #endif
 448 #ifndef BIT54
 449   #define BIT54       0x0040000000000000ull
 450 #endif
 451 #ifndef BIT55
 452   #define BIT55       0x0080000000000000ull
 453 #endif
 454 #ifndef BIT56
 455   #define BIT56       0x0100000000000000ull
 456 #endif
 457 #ifndef BIT57
 458   #define BIT57       0x0200000000000000ull
 459 #endif
 460 #ifndef BIT58
 461   #define BIT58       0x0400000000000000ull
 462 #endif
 463 #ifndef BIT59
 464   #define BIT59       0x0800000000000000ull
 465 #endif
 466 #ifndef BIT60
 467   #define BIT60       0x1000000000000000ull
 468 #endif
 469 #ifndef BIT61
 470   #define BIT61       0x2000000000000000ull
 471 #endif
 472 #ifndef BIT62
 473   #define BIT62       0x4000000000000000ull
 474 #endif
 475 #ifndef BIT63
 476   #define BIT63       0x8000000000000000ull
 477 #endif
 478
 479 #endif // _AMD_H_