payloads/libpayload/include/arm/arch/barrier.h

   1 /*
   2  *
   3  * Copyright 2014 Google Inc.
   4  * Copyright (C) 2003-2004 Olivier Houchard
   5  * Copyright (C) 1994-1997 Mark Brinicombe
   6  * Copyright (C) 1994 Brini
   7  * All rights reserved.
   8  *
   9  * This code is derived from software written for Brini by Mark Brinicombe
  10  *
  11  * Redistribution and use in source and binary forms, with or without
  12  * modification, are permitted provided that the following conditions
  13  * are met:
  14  * 1. Redistributions of source code must retain the above copyright
  15  *    notice, this list of conditions and the following disclaimer.
  16  * 2. Redistributions in binary form must reproduce the above copyright
  17  *    notice, this list of conditions and the following disclaimer in the
  18  *    documentation and/or other materials provided with the distribution.
  19  * 3. The name of the author may not be used to endorse or promote products
  20  *    derived from this software without specific prior written permission.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  27  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  28  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  29  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  30  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  31  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  32  * SUCH DAMAGE.
  33  *
  34  */
  35
  36 #ifndef __ARCH_BARRIER_H__
  37 #define __ARCH_BARRIER_H__
  38
  39 #include <arch/cache.h>
  40
  41 /*
  42  * Description of different memory barriers introduced:
  43  *
  44  * Memory barrier(mb) - Guarantees that all memory accesses specified before the
  45  * barrier will happen before all memory accesses specified after the barrier
  46  *
  47  * Read memory barrier (rmb) - Guarantees that all read memory accesses
  48  * specified before the barrier will happen before all read memory accesses
  49  * specified after the barrier
  50  *
  51  * Write memory barrier (wmb) - Guarantees that all write memory accesses
  52  * specified before the barrier will happen before all write memory accesses
  53  *  specified after the barrier
  54  */
  55
  56 /*
  57  * According to ARM Reference Manual (ARMv7-A), by default dmb ensures:
  58  * Full system is the required shareability domain
  59  *  Reads and writes are the required access types.
  60  */
  61 #define mb()       dmb()
  62 #define rmb()      dmb()
  63 #define wmb()      dmb()
  64
  65 #endif /* __ARCH_BARRIER_H__ */