payloads/libpayload/include/usb/dwc2_registers.h

   1 /*
   2  *
   3  * Copyright (C) 2015 Rockchip Electronics
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; version 2 of the License.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14 #ifndef __DWC2_REGISTERS__
  15 #define __DWC2_REGISTERS__
  16
  17 #define MAX_EPS_CHANNELS 16
  18
  19 typedef struct core_reg {
  20         uint32_t gotgctl;
  21         uint32_t gotgint;
  22         uint32_t gahbcfg;
  23         uint32_t gusbcfg;
  24         uint32_t grstctl;
  25         uint32_t gintsts;
  26         uint32_t gintmsk;
  27         uint32_t grxstsr;
  28         uint32_t grxstsp;
  29         uint32_t grxfsiz;
  30         uint32_t gnptxfsiz;
  31         uint32_t gnptxsts;
  32         uint32_t gi2cctl;
  33         uint32_t gpvndctl;
  34         uint32_t ggpio;
  35         uint32_t guid;
  36         uint32_t gsnpsid;
  37         uint32_t ghwcfg1;
  38         uint32_t ghwcfg2;
  39         uint32_t ghwcfg3;
  40         uint32_t ghwcfg4;
  41         uint32_t reserved1[(0x100 - 0x54) / 4];
  42         uint32_t hptxfsiz;
  43         uint32_t dptxfsiz_dieptxf[MAX_EPS_CHANNELS - 1];
  44         uint32_t reserved2[(0x400 - 0x140) / 4];
  45 } core_reg_t;
  46
  47 typedef struct hc_reg {
  48         uint32_t hccharn;
  49         uint32_t hcspltn;
  50         uint32_t hcintn;
  51         uint32_t hcintmaskn;
  52         uint32_t hctsizn;
  53         uint32_t hcdman;
  54         uint32_t reserved[2];
  55 } hc_reg_t;
  56
  57 /* Host Mode Register Structures */
  58 typedef struct host_reg {
  59         uint32_t hcfg;
  60         uint32_t hfir;
  61         uint32_t hfnum;
  62         uint32_t reserved0;
  63         uint32_t hptxsts;
  64         uint32_t haint;
  65         uint32_t haintmsk;
  66         uint32_t reserved1[(0x440 - 0x41c) / 4];
  67         uint32_t hprt;
  68         uint32_t reserved2[(0x500 - 0x444) / 4];
  69         hc_reg_t hchn[MAX_EPS_CHANNELS];
  70         uint32_t reserved3[(0x800 - 0x700) / 4];
  71 } host_reg_t;
  72
  73 typedef struct ep_reg {
  74         uint32_t depctl;
  75         uint32_t reserved04;
  76         uint32_t depint;
  77         uint32_t reserved0c;
  78         uint32_t deptsiz;
  79         uint32_t depdma;
  80         uint32_t reserved18;
  81         uint32_t depdmab;
  82 } dwc2_ep_reg_t;
  83
  84 /* Device Mode Registers Structures */
  85 typedef struct device_reg {
  86         uint32_t dcfg;
  87         uint32_t dctl;
  88         uint32_t dsts;
  89         uint32_t unused;
  90         uint32_t diepmsk;
  91         uint32_t doepmsk;
  92         uint32_t daint;
  93         uint32_t daintmsk;
  94         uint32_t dtknqr1;
  95         uint32_t dtknqr2;
  96         uint32_t dvbusdis;
  97         uint32_t dvbuspulse;
  98         uint32_t dtknqr3_dthrctl;
  99         uint32_t dtknqr4_fifoemptymsk;
 100         uint32_t reserved1[(0x900 - 0x838) / 4];
 101
 102         dwc2_ep_reg_t inep[MAX_EPS_CHANNELS];
 103         dwc2_ep_reg_t outep[MAX_EPS_CHANNELS];
 104         uint32_t reserved8[(0xe00 - 0xd00) / 4];
 105 } device_reg_t;
 106
 107 typedef struct pwr_clk_ctrl_reg {
 108         uint32_t pcgcctl;
 109         uint32_t reserved[(0x1000 - 0xe04) / 4];
 110 } pwr_clk_ctrl_reg_t;
 111
 112 typedef struct data_fifo {
 113         uint32_t dataport;
 114         uint32_t reserved[(0x1000 - 0x004) / 4];
 115 } data_fifo_t;
 116
 117 typedef struct dwc2_otg_reg {
 118         core_reg_t core;
 119         host_reg_t host;
 120         device_reg_t device;
 121         pwr_clk_ctrl_reg_t pcgr;
 122         data_fifo_t dfifo[MAX_EPS_CHANNELS];
 123         uint32_t reserved[(0x40000 - 0x11000) / 4];
 124 } dwc2_reg_t;
 125
 126 /**
 127  * This union represents the bit fields of the Core AHB Configuration
 128  * Register (GAHBCFG).
 129  */
 130 typedef union {
 131         /* raw register data */
 132         uint32_t d32;
 133         /* register bits */
 134         struct {
 135                 unsigned glblintrmsk:1;
 136 #define GLBINT_ENABLE 1
 137
 138                 unsigned hbstlen:4;
 139 #define DMA_BURST_SINGLE 0
 140 #define DMA_BURST_INCR 1
 141 #define DMA_BURST_INCR4 3
 142 #define DMA_BURST_INCR8 5
 143 #define DMA_BURST_INCR16 7
 144
 145                 unsigned dmaen:1;
 146                 unsigned reserved:1;
 147                 unsigned nptxfemplvl:1;
 148                 unsigned ptxfemplvl:1;
 149                 unsigned reserved9_31:23;
 150         };
 151 } gahbcfg_t;
 152
 153 /**
 154  * This union represents the bit fields of the Core USB Configuration
 155  * Register (GUSBCFG).
 156  */
 157 typedef union {
 158         /* raw register data */
 159         uint32_t d32;
 160         /* register bits */
 161         struct {
 162                 unsigned toutcal:3;
 163                 unsigned phyif:1;
 164                 unsigned ulpiutmisel:1;
 165                 unsigned fsintf:1;
 166                 unsigned physel:1;
 167                 unsigned ddrsel:1;
 168                 unsigned srpcap:1;
 169                 unsigned hnpcap:1;
 170                 unsigned usbtrdtim:4;
 171                 unsigned reserved14:1;
 172                 unsigned phylpwrclksel:1;
 173                 unsigned otgi2csel:1;
 174                 unsigned ulpifsls:1;
 175                 unsigned ulpiautores:1;
 176                 unsigned ulpiclksusm:1;
 177                 unsigned ulpiextvbusdrv:1;
 178                 unsigned ulpiextvbusindicator:1;
 179                 unsigned termseldlpulse:1;
 180                 unsigned reserved23_28:6;
 181                 unsigned forcehstmode:1;
 182                 unsigned forcedevmode:1;
 183                 unsigned cortxpkt:1;
 184         };
 185 } gusbcfg_t;
 186
 187 /**
 188  * This union represents the bit fields of the Core Reset Register
 189  * (GRSTCTL).
 190  */
 191 typedef union {
 192         /* raw register data */
 193         uint32_t d32;
 194         /* register bits */
 195         struct {
 196                 /** Core Soft Reset (CSftRst) (Device and Host)
 197                  *
 198                  * The application can flush the control logic in the
 199                  * entire core using this bit. This bit resets the
 200                  * pipelines in the AHB Clock domain as well as the
 201                  * PHY Clock domain.
 202                  *
 203                  * The state machines are reset to an IDLE state, the
 204                  * control bits in the CSRs are cleared, all the
 205                  * transmit FIFOs and the receive FIFO are flushed.
 206                  *
 207                  * The status mask bits that control the generation of
 208                  * the interrupt, are cleared, to clear the
 209                  * interrupt. The interrupt status bits are not
 210                  * cleared, so the application can get the status of
 211                  * any events that occurred in the core after it has
 212                  * set this bit.
 213                  *
 214                  * Any transactions on the AHB are terminated as soon
 215                  * as possible following the protocol. Any
 216                  * transactions on the USB are terminated immediately.
 217                  *
 218                  * The configuration settings in the CSRs are
 219                  * unchanged, so the software doesn't have to
 220                  * reprogram these registers (Device
 221                  * Configuration/Host Configuration/Core System
 222                  * Configuration/Core PHY Configuration).
 223                  *
 224                  * The application can write to this bit, any time it
 225                  * wants to reset the core. This is a self clearing
 226                  * bit and the core clears this bit after all the
 227                  * necessary logic is reset in the core, which may
 228                  * take several clocks, depending on the current state
 229                  * of the core.
 230                  */
 231                 unsigned csftrst:1;
 232                 /** Hclk Soft Reset
 233                  *
 234                  * The application uses this bit to reset the control logic in
 235                  * the AHB clock domain. Only AHB clock domain pipelines are
 236                  * reset.
 237                  */
 238                 unsigned hsftrst:1;
 239                 /** Host Frame Counter Reset (Host Only)<br>
 240                  *
 241                  * The application can reset the (micro)frame number
 242                  * counter inside the core, using this bit. When the
 243                  * (micro)frame counter is reset, the subsequent SOF
 244                  * sent out by the core, will have a (micro)frame
 245                  * number of 0.
 246                  */
 247                 unsigned frmcntrrst:1;
 248                 /** In Token Sequence Learning Queue Flush
 249                  * (INTknQFlsh) (Device Only)
 250                  */
 251                 unsigned intknqflsh:1;
 252                 /** RxFIFO Flush (RxFFlsh) (Device and Host)
 253                  *
 254                  * The application can flush the entire Receive FIFO
 255                  * using this bit.      <p>The application must first
 256                  * ensure that the core is not in the middle of a
 257                  * transaction.  <p>The application should write into
 258                  * this bit, only after making sure that neither the
 259                  * DMA engine is reading from the RxFIFO nor the MAC
 260                  * is writing the data in to the FIFO.  <p>The
 261                  * application should wait until the bit is cleared
 262                  * before performing any other operations. This bit
 263                  * will takes 8 clocks (slowest of PHY or AHB clock)
 264                  * to clear.
 265                  */
 266                 unsigned rxfflsh:1;
 267                 /** TxFIFO Flush (TxFFlsh) (Device and Host).
 268                  *
 269                  * This bit is used to selectively flush a single or
 270                  * all transmit FIFOs.  The application must first
 271                  * ensure that the core is not in the middle of a
 272                  * transaction.  <p>The application should write into
 273                  * this bit, only after making sure that neither the
 274                  * DMA engine is writing into the TxFIFO nor the MAC
 275                  * is reading the data out of the FIFO.  <p>The
 276                  * application should wait until the core clears this
 277                  * bit, before performing any operations. This bit
 278                  * will takes 8 clocks (slowest of PHY or AHB clock)
 279                  * to clear.
 280                  */
 281                 unsigned txfflsh:1;
 282
 283                 /** TxFIFO Number (TxFNum) (Device and Host).
 284                  *
 285                  * This is the FIFO number which needs to be flushed,
 286                  * using the TxFIFO Flush bit. This field should not
 287                  * be changed until the TxFIFO Flush bit is cleared by
 288                  * the core.
 289                  *       - 0x0 : Non Periodic TxFIFO Flush
 290                  *       - 0x1 : Periodic TxFIFO #1 Flush in device mode
 291                  *         or Periodic TxFIFO in host mode
 292                  *       - 0x2 : Periodic TxFIFO #2 Flush in device mode.
 293                  *       - ...
 294                  *       - 0xF : Periodic TxFIFO #15 Flush in device mode
 295                  *       - 0x10: Flush all the Transmit NonPeriodic and
 296                  *         Transmit Periodic FIFOs in the core
 297                  */
 298                 unsigned txfnum:5;
 299                 /** Reserved */
 300                 unsigned reserved11_29:19;
 301                 /** DMA Request Signal.  Indicated DMA request is in
 302                  * probress.  Used for debug purpose. */
 303                 unsigned dmareq:1;
 304                 /** AHB Master Idle.  Indicates the AHB Master State
 305                  * Machine is in IDLE condition. */
 306                 unsigned ahbidle:1;
 307         };
 308 } grstctl_t;
 309
 310 /**
 311  * This union represents the bit fields of the Core Interrupt Mask
 312  * Register (GINTMSK).
 313  */
 314 typedef union {
 315         /* raw register data */
 316         uint32_t d32;
 317         /* register bits */
 318         struct {
 319                 unsigned curmod:1;
 320                 unsigned modemis:1;
 321                 unsigned otgint:1;
 322                 unsigned sof:1;
 323                 unsigned rxflvl:1;
 324                 unsigned nptxfemp:1;
 325                 unsigned ginnakeff:1;
 326                 unsigned goutnakeff:1;
 327                 unsigned reserved8:1;
 328                 unsigned i2cint:1;
 329                 unsigned erlysusp:1;
 330                 unsigned usbsusp:1;
 331                 unsigned usbrst:1;
 332                 unsigned enumdone:1;
 333                 unsigned isooutdrop:1;
 334                 unsigned eopf:1;
 335                 unsigned reserved16:1;
 336                 unsigned epmis:1;
 337                 unsigned iepint:1;
 338                 unsigned oepint:1;
 339                 unsigned incompisoin:1;
 340                 unsigned incompip:1;
 341                 unsigned reserved22_23:2;
 342                 unsigned prtint:1;
 343                 unsigned hchint:1;
 344                 unsigned ptxfemp:1;
 345                 unsigned reserved27:1;
 346                 unsigned conidstschng:1;
 347                 unsigned disconnint:1;
 348                 unsigned sessreqint:1;
 349                 unsigned wkupint:1;
 350         };
 351 } gintmsk_t;
 352
 353 /**
 354 * This union represents the bit fields of the Core Non-Periodic
 355 * Transmit FIFO Size Register(GNPTXFSIZ).
 356 */
 357 typedef union {
 358         /* raw register data */
 359         uint32_t d32;
 360         /* register bits */
 361         struct {
 362                 unsigned txfstaddr:16;
 363                 unsigned txfdep:16;
 364         };
 365 } gtxfsiz_t;
 366
 367 /**
 368  * This union represents the bit fields of the Core Receive FIFO Size
 369  * Register(GRXFSIZ).
 370  */
 371 typedef union {
 372         /* raw register data */
 373         uint32_t d32;
 374         /* register bits */
 375         /*The value in this fieles is in terms of 32-bit words size.
 376          */
 377         struct {
 378                 unsigned rxfdep:16;
 379                 unsigned reserved:16;
 380         };
 381 } grxfsiz_t;
 382
 383 /**
 384 * This union represents the bit fields of the Core Device
 385 * Transmit FIFO Size Register(GNPTXFSIZ).
 386 */
 387 typedef union {
 388         /* raw register data */
 389         uint32_t d32;
 390         /* register bits */
 391         struct {
 392                 unsigned dtxfstaddr:16;
 393                 unsigned dtxfdep:16;
 394         };
 395 } dtxfsiz_t;
 396
 397 /**
 398  * This union represents the bit fields of the Core Interrupt Register
 399  * (GINTSTS).
 400  */
 401 typedef union {
 402         /* raw register data */
 403         uint32_t d32;
 404 #define SOF_INTR_MASK 0x0008
 405         /* register bits */
 406         struct {
 407                 unsigned curmod:1;
 408 #define HOST_MODE 1
 409 #define DEVICE_MODE 0
 410                 unsigned modemis:1;
 411                 unsigned otgint:1;
 412                 unsigned sof:1;
 413                 unsigned rxflvl:1;
 414                 unsigned nptxfemp:1;
 415                 unsigned ginnakeff:1;
 416                 unsigned goutnakeff:1;
 417                 unsigned reserved8:1;
 418                 unsigned i2cint:1;
 419                 unsigned erlysusp:1;
 420                 unsigned usbsusp:1;
 421                 unsigned usbrst:1;
 422                 unsigned enumdone:1;
 423                 unsigned isooutdrop:1;
 424                 unsigned eopf:1;
 425                 unsigned reserved16_17:2;
 426                 unsigned iepint:1;
 427                 unsigned oepint:1;
 428                 unsigned reserved20:1;
 429                 unsigned incompip:1;
 430                 unsigned reserved22_23:2;
 431                 unsigned prtint:1;
 432                 unsigned hchint:1;
 433                 unsigned ptxfemp:1;
 434                 unsigned reserved27:1;
 435                 unsigned conidstschng:1;
 436                 unsigned disconnint:1;
 437                 unsigned sessreqint:1;
 438                 unsigned wkupint:1;
 439         };
 440 } gintsts_t;
 441
 442 #define GINTSTS_WKUPINT                 (1 << 31)
 443 #define GINTSTS_SESSREQINT              (1 << 30)
 444 #define GINTSTS_DISCONNINT              (1 << 29)
 445 #define GINTSTS_CONIDSTSCHNG            (1 << 28)
 446 #define GINTSTS_LPMTRANRCVD             (1 << 27)
 447 #define GINTSTS_PTXFEMP                 (1 << 26)
 448 #define GINTSTS_HCHINT                  (1 << 25)
 449 #define GINTSTS_PRTINT                  (1 << 24)
 450 #define GINTSTS_RESETDET                (1 << 23)
 451 #define GINTSTS_FET_SUSP                (1 << 22)
 452 #define GINTSTS_INCOMPL_IP              (1 << 21)
 453 #define GINTSTS_INCOMPL_SOIN            (1 << 20)
 454 #define GINTSTS_OEPINT                  (1 << 19)
 455 #define GINTSTS_IEPINT                  (1 << 18)
 456 #define GINTSTS_EPMIS                   (1 << 17)
 457 #define GINTSTS_RESTOREDONE             (1 << 16)
 458 #define GINTSTS_EOPF                    (1 << 15)
 459 #define GINTSTS_ISOUTDROP               (1 << 14)
 460 #define GINTSTS_ENUMDONE                (1 << 13)
 461 #define GINTSTS_USBRST                  (1 << 12)
 462 #define GINTSTS_USBSUSP                 (1 << 11)
 463 #define GINTSTS_ERLYSUSP                (1 << 10)
 464 #define GINTSTS_I2CINT                  (1 << 9)
 465 #define GINTSTS_ULPI_CK_INT             (1 << 8)
 466 #define GINTSTS_GOUTNAKEFF              (1 << 7)
 467 #define GINTSTS_GINNAKEFF               (1 << 6)
 468 #define GINTSTS_NPTXFEMP                (1 << 5)
 469 #define GINTSTS_RXFLVL                  (1 << 4)
 470 #define GINTSTS_SOF                     (1 << 3)
 471 #define GINTSTS_OTGINT                  (1 << 2)
 472 #define GINTSTS_MODEMIS                 (1 << 1)
 473 #define GINTSTS_CURMODE_HOST            (1 << 0)
 474
 475 /**
 476  * This union represents the bit fields of the User HW Config3 Register
 477  * (GHWCFG3).
 478  */
 479 typedef union {
 480         /* raw register data */
 481         uint32_t d32;
 482         /* register bits */
 483         struct {
 484                 unsigned reserved:16;
 485                 unsigned dfifodepth:16;
 486         };
 487 } ghwcfg3_t;
 488
 489 /**
 490  * This union represents the bit fields in the Host Configuration Register.
 491  */
 492 typedef union {
 493         /* raw register data */
 494         uint32_t d32;
 495
 496         /* register bits */
 497         struct {
 498                 /** FS/LS Phy Clock Select */
 499                 unsigned fslspclksel:2;
 500 #define PHYCLK_30_60_MHZ 0
 501 #define PHYCLK_48_MHZ 1
 502 #define PHYCLK_6_MHZ 2
 503
 504                 /** FS/LS Only Support */
 505                 unsigned fslssupp:1;
 506         };
 507 } hcfg_t;
 508
 509 /**
 510  * This union represents the bit fields in the Host Frame Number/Frame Time
 511  * Remaining Register
 512  */
 513 typedef union {
 514         /* raw register data */
 515         uint32_t d32;
 516
 517         /* register bits */
 518         struct {
 519                 /** Frame Number */
 520                 unsigned frnum:16;
 521                 /** Frame Time Remaining */
 522                 unsigned frrem:16;
 523         };
 524 } hfnum_t;
 525
 526 /**
 527  * This union represents the bit fields in the Host Port Control and status
 528  * Register.
 529  */
 530 typedef union {
 531         /* raw register data */
 532         uint32_t d32;
 533         /* register bits */
 534         struct {
 535                 unsigned prtconnsts:1;
 536                 unsigned prtconndet:1;
 537                 unsigned prtena:1;
 538                 unsigned prtenchng:1;
 539                 unsigned prtovrcurract:1;
 540                 unsigned prtovrcurrchng:1;
 541                 unsigned prtres:1;
 542                 unsigned prtsusp:1;
 543                 unsigned prtrst:1;
 544                 unsigned reserved9:1;
 545                 unsigned prtlnsts:2;
 546                 unsigned prtpwr:1;
 547                 unsigned prttstctl:4;
 548                 unsigned prtspd:2;
 549 #define PRTSPD_HIGH 0
 550 #define PRTSPD_FULL 1
 551 #define PRTSPD_LOW      2
 552                 unsigned reserved19_31:13;
 553         };
 554 } hprt_t;
 555 /* Mask W1C bits */
 556 #define HPRT_W1C_MASK (~((1 << 1) | (1 << 2) | (1 << 3) | (1 << 5)))
 557
 558 /**
 559  * This union represents the bit fields in the Host Channel Characteristics
 560  * Register.
 561  */
 562 typedef union {
 563         /* raw register data */
 564         uint32_t d32;
 565
 566         /* register bits */
 567         struct {
 568                 /** Maximum packet size in bytes */
 569                 unsigned mps:11;
 570                 /** Endpoint number */
 571                 unsigned epnum:4;
 572                 /** 0: OUT, 1: IN */
 573                 unsigned epdir:1;
 574                 unsigned reserved:1;
 575                 /** 0: Full/high speed device, 1: Low speed device */
 576                 unsigned lspddev:1;
 577                 /** 0: Control, 1: Isoc, 2: Bulk, 3: Intr */
 578                 unsigned eptype:2;
 579                 /** Packets per frame for periodic transfers. 0 is reserved. */
 580                 unsigned multicnt:2;
 581                 /** Device address */
 582                 unsigned devaddr:7;
 583                 /**
 584                  * Frame to transmit periodic transaction.
 585                  * 0: even, 1: odd
 586                  */
 587                 unsigned oddfrm:1;
 588                 /** Channel disable */
 589                 unsigned chdis:1;
 590                 /** Channel enable */
 591                 unsigned chen:1;
 592         };
 593 } hcchar_t;
 594
 595 /**
 596  * This union represents the bit fields in the Host Channel-n Split Control
 597  * Register.
 598  */
 599 typedef union {
 600         /* raw register data */
 601         uint32_t d32;
 602
 603         /* register bits */
 604         struct {
 605                 /** Port Address */
 606                 unsigned prtaddr:7;
 607                 /** Hub Address */
 608                 unsigned hubaddr:7;
 609                 /** Transaction Position */
 610                 unsigned xactpos:2;
 611                 /** Do Complete Split */
 612                 unsigned compsplt:1;
 613                 unsigned reserved:14;
 614                 /** Split Enable */
 615                 unsigned spltena:1;
 616         };
 617 } hcsplit_t;
 618
 619 typedef enum {
 620         EPDIR_OUT = 0,
 621         EPDIR_IN,
 622 } ep_dir_t;
 623
 624 /**
 625  * This union represents the bit fields in the Host All Interrupt
 626  * Register.
 627  */
 628 typedef union {
 629         /* raw register data */
 630         uint32_t d32;
 631         /* register bits */
 632         struct {
 633                 /** Transfer Complete */
 634                 unsigned xfercomp:1;
 635                 /** Channel Halted */
 636                 unsigned chhltd:1;
 637                 /** AHB Error */
 638                 unsigned ahberr:1;
 639                 /** STALL Response Received */
 640                 unsigned stall:1;
 641                 /** NAK Response Received */
 642                 unsigned nak:1;
 643                 /** ACK Response Received */
 644                 unsigned ack:1;
 645                 /** NYET Response Received */
 646                 unsigned nyet:1;
 647                 /** Transaction Err */
 648                 unsigned xacterr:1;
 649                 /** Babble Error */
 650                 unsigned bblerr:1;
 651                 /** Frame Overrun */
 652                 unsigned frmovrun:1;
 653                 /** Data Toggle Error */
 654                 unsigned datatglerr:1;
 655                 /** Reserved */
 656                 unsigned reserved:21;
 657         };
 658 } hcint_t;
 659
 660 /**
 661  * This union represents the bit fields in the Host Channel Transfer Size
 662  * Register.
 663  */
 664 typedef union {
 665         /* raw register data */
 666         uint32_t d32;
 667
 668         /* register bits */
 669         struct {
 670                 /* Total transfer size in bytes */
 671                 unsigned xfersize:19;
 672                 /** Data packets to transfer */
 673                 unsigned pktcnt:10;
 674                 /**
 675                  * Packet ID for next data packet
 676                  * 0: DATA0
 677                  * 1: DATA2
 678                  * 2: DATA1
 679                  * 3: MDATA (non-Control), SETUP (Control)
 680                  */
 681                 unsigned pid:2;
 682 #define PID_DATA0 0
 683 #define PID_DATA1 2
 684 #define PID_DATA2 1
 685 #define PID_MDATA 3
 686 #define PID_SETUP 3
 687                 /* Do PING protocol when 1 */
 688                 unsigned dopng:1;
 689         };
 690 } hctsiz_t;
 691
 692 /**
 693  * This union represents the bit fields in the Host Channel Interrupt Mask
 694  * Register.
 695  */
 696 typedef union {
 697         /* raw register data */
 698         uint32_t d32;
 699         /* register bits */
 700         struct {
 701                 unsigned xfercomp:1;
 702                 unsigned chhltd:1;
 703                 unsigned ahberr:1;
 704                 unsigned stall:1;
 705                 unsigned nak:1;
 706                 unsigned ack:1;
 707                 unsigned nyet:1;
 708                 unsigned xacterr:1;
 709                 unsigned bblerr:1;
 710                 unsigned frmovrun:1;
 711                 unsigned datatglerr:1;
 712                 unsigned reserved:21;
 713         };
 714 } hcintmsk_t;
 715
 716 typedef union {
 717         /* raw register data */
 718         uint32_t d32;
 719         /* register bits */
 720         struct {
 721                 unsigned devspd:2;
 722                 unsigned nzstsouthshk:1;
 723                 unsigned ena32ksusp:1;
 724                 unsigned devaddr:7;
 725                 unsigned perfrint:2;
 726                 unsigned endevoutnak:1;
 727                 unsigned reservedi14_17:4;
 728                 unsigned epmiscnt:5;
 729                 unsigned reserved26_31:9;
 730         };
 731 } dcfg_t;
 732
 733 typedef union {
 734         /* raw register data */
 735         uint32_t d32;
 736         /* register bits */
 737         struct {
 738                 unsigned suspsts:1;
 739                 unsigned enumspd:2;
 740                 unsigned errticerr:1;
 741                 unsigned reserved4_31:28;
 742         };
 743 } dsts_t;
 744
 745 typedef union {
 746         /* raw register data */
 747         uint32_t d32;
 748         /* register bits */
 749         struct {
 750                 unsigned rmtwkupsig:1;
 751                 unsigned sftdiscon:1;
 752                 unsigned gnpinnaksts:1;
 753                 unsigned goutnaksts:1;
 754                 unsigned tstctl:3;
 755                 unsigned sgnpinnak:1;
 756                 unsigned cgnpinnak:1;
 757                 unsigned sgoutnak:1;
 758                 unsigned cgoutnak:1;
 759                 unsigned pwronprgdone:1;
 760                 unsigned reserved12:1;
 761                 unsigned gmc:2;
 762                 unsigned ignrfrmnum:1;
 763                 unsigned nakonbble:1;
 764                 unsigned encontbna:1;
 765                 unsigned reserved19_31:14;
 766         };
 767 } dctl_t;
 768
 769 typedef union {
 770         /* raw register data */
 771         uint32_t d32;
 772         /* register bits */
 773         struct {
 774 #define D0EPCTL_MPS_SHIFT               0
 775 #define D0EPCTL_MPS_64                  0
 776 #define D0EPCTL_MPS_32                  1
 777 #define D0EPCTL_MPS_16                  2
 778 #define D0EPCTL_MPS_8                   3
 779                 unsigned mps:11;
 780                 unsigned nextep:4;
 781                 unsigned usbactep:1;
 782                 unsigned dpid:1;
 783                 unsigned naksts:1;
 784                 unsigned eptype:2;
 785                 unsigned reserved20:1;
 786                 unsigned stall:1;
 787                 unsigned txfnum:4;
 788                 unsigned cnak:1;
 789                 unsigned snak:1;
 790                 unsigned setd0pid:1;
 791                 unsigned setd1pid:1;
 792                 unsigned epdis:1;
 793                 unsigned epena:1;
 794         };
 795 } depctl_t;
 796
 797 typedef union {
 798         /* raw register data */
 799         uint32_t d32;
 800         /* register bits */
 801         struct {
 802                 unsigned xfercompl:1;
 803                 unsigned epdisbld:1;
 804                 unsigned ahberr:1;
 805                 unsigned setup:1;
 806                 unsigned reserved4_14:12;
 807                 unsigned stuppktrcvd:1;
 808                 unsigned reserved16_31:15;
 809         };
 810 } depint_t;
 811
 812 #define DXEPINT_SETUP_RCVD              (1 << 15)
 813 #define DXEPINT_INEPNAKEFF              (1 << 6)
 814 #define DXEPINT_BACK2BACKSETUP          (1 << 6)
 815 #define DXEPINT_INTKNEPMIS              (1 << 5)
 816 #define DXEPINT_INTKNTXFEMP             (1 << 4)
 817 #define DXEPINT_OUTTKNEPDIS             (1 << 4)
 818 #define DXEPINT_TIMEOUT                 (1 << 3)
 819 #define DXEPINT_SETUP                   (1 << 3)
 820 #define DXEPINT_AHBERR                  (1 << 2)
 821 #define DXEPINT_EPDISBLD                (1 << 1)
 822 #define DXEPINT_XFERCOMPL               (1 << 0)
 823
 824 typedef union {
 825         /* raw register data */
 826         uint32_t d32;
 827         /* register bits */
 828         struct {
 829                 unsigned xfersize:19;
 830                 unsigned pktcnt:10;
 831                 unsigned mc:2;
 832                 unsigned reserved31:1;
 833         };
 834 } depsiz_t;
 835
 836 #define DAINT_OUTEP_SHIFT       MAX_EPS_CHANNELS
 837
 838 #endif