| blob | 823240cab0c8090900f8fe30f3f07db5abc13483 |
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 /dts-v1/;
5 / {
6 #address-cells = <2>;
7 #size-cells = <2>;
8 compatible = "sifive,fu740-c000", "sifive,fu740";
10 aliases {
11 serial0 = &uart0;
12 serial1 = &uart1;
13 ethernet0 = ð0;
14 };
16 chosen {
17 };
19 cpus {
20 #address-cells = <1>;
21 #size-cells = <0>;
22 cpu0: cpu@0 {
23 compatible = "sifive,bullet0", "riscv";
24 device_type = "cpu";
25 i-cache-block-size = <64>;
26 i-cache-sets = <128>;
27 i-cache-size = <16384>;
28 next-level-cache = <&ccache>;
29 reg = <0x0>;
30 riscv,isa = "rv64imac";
31 // the S7 core does not support Supervisor mode and has no FPU
32 status = "disabled";
33 cpu0_intc: interrupt-controller {
34 #interrupt-cells = <1>;
35 compatible = "riscv,cpu-intc";
36 interrupt-controller;
37 };
38 };
39 cpu1: cpu@1 {
40 compatible = "sifive,bullet0", "riscv";
41 d-cache-block-size = <64>;
42 d-cache-sets = <64>;
43 d-cache-size = <32768>;
44 d-tlb-sets = <1>;
45 d-tlb-size = <40>;
46 device_type = "cpu";
47 i-cache-block-size = <64>;
48 i-cache-sets = <128>;
49 i-cache-size = <32768>;
50 i-tlb-sets = <1>;
51 i-tlb-size = <40>;
52 mmu-type = "riscv,sv39";
53 next-level-cache = <&ccache>;
54 reg = <0x1>;
55 riscv,isa = "rv64imafdc";
56 tlb-split;
57 cpu1_intc: interrupt-controller {
58 #interrupt-cells = <1>;
59 compatible = "riscv,cpu-intc";
60 interrupt-controller;
61 };
62 };
63 cpu2: cpu@2 {
64 compatible = "sifive,bullet0", "riscv";
65 d-cache-block-size = <64>;
66 d-cache-sets = <64>;
67 d-cache-size = <32768>;
68 d-tlb-sets = <1>;
69 d-tlb-size = <40>;
70 device_type = "cpu";
71 i-cache-block-size = <64>;
72 i-cache-sets = <128>;
73 i-cache-size = <32768>;
74 i-tlb-sets = <1>;
75 i-tlb-size = <40>;
76 mmu-type = "riscv,sv39";
77 next-level-cache = <&ccache>;
78 reg = <0x2>;
79 riscv,isa = "rv64imafdc";
80 tlb-split;
81 cpu2_intc: interrupt-controller {
82 #interrupt-cells = <1>;
83 compatible = "riscv,cpu-intc";
84 interrupt-controller;
85 };
86 };
87 cpu3: cpu@3 {
88 compatible = "sifive,bullet0", "riscv";
89 d-cache-block-size = <64>;
90 d-cache-sets = <64>;
91 d-cache-size = <32768>;
92 d-tlb-sets = <1>;
93 d-tlb-size = <40>;
94 device_type = "cpu";
95 i-cache-block-size = <64>;
96 i-cache-sets = <128>;
97 i-cache-size = <32768>;
98 i-tlb-sets = <1>;
99 i-tlb-size = <40>;
100 mmu-type = "riscv,sv39";
101 next-level-cache = <&ccache>;
102 reg = <0x3>;
103 riscv,isa = "rv64imafdc";
104 tlb-split;
105 cpu3_intc: interrupt-controller {
106 #interrupt-cells = <1>;
107 compatible = "riscv,cpu-intc";
108 interrupt-controller;
109 };
110 };
111 cpu4: cpu@4 {
112 compatible = "sifive,bullet0", "riscv";
113 d-cache-block-size = <64>;
114 d-cache-sets = <64>;
115 d-cache-size = <32768>;
116 d-tlb-sets = <1>;
117 d-tlb-size = <40>;
118 device_type = "cpu";
119 i-cache-block-size = <64>;
120 i-cache-sets = <128>;
121 i-cache-size = <32768>;
122 i-tlb-sets = <1>;
123 i-tlb-size = <40>;
124 mmu-type = "riscv,sv39";
125 next-level-cache = <&ccache>;
126 reg = <0x4>;
127 riscv,isa = "rv64imafdc";
128 tlb-split;
129 cpu4_intc: interrupt-controller {
130 #interrupt-cells = <1>;
131 compatible = "riscv,cpu-intc";
132 interrupt-controller;
133 };
134 };
136 cpu-map {
137 cluster0 {
138 core0 {
139 cpu = <&cpu0>;
140 };
142 core1 {
143 cpu = <&cpu1>;
144 };
146 core2 {
147 cpu = <&cpu2>;
148 };
150 core3 {
151 cpu = <&cpu3>;
152 };
154 core4 {
155 cpu = <&cpu4>;
156 };
157 };
158 };
159 };
160 soc {
161 #address-cells = <2>;
162 #size-cells = <2>;
163 compatible = "simple-bus";
164 ranges;
165 // clint is mainly used by openSBI and not the OS, since interrupts-extended currently only
166 // contains machine mode interrupts which the OS will ignore if not running in machine mode
167 clint: clint@2000000 {
168 compatible = "riscv,clint0";
169 //TODO Add RISCV_M_SOFT_IRQ and RISCV_M_TIME_IRQ macros for better readability
170 interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
171 &cpu1_intc 3 &cpu1_intc 7
172 &cpu2_intc 3 &cpu2_intc 7
173 &cpu3_intc 3 &cpu3_intc 7
174 &cpu4_intc 3 &cpu4_intc 7>;
175 reg = <0x0 0x2000000 0x0 0x10000>;
176 };
177 plic0: interrupt-controller@c000000 {
178 #interrupt-cells = <1>;
179 #address-cells = <0>;
180 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
181 reg = <0x0 0xc000000 0x0 0x4000000>;
182 riscv,ndev = <69>;
183 interrupt-controller;
184 interrupts-extended =
185 <&cpu0_intc 0xffffffff>,
186 <&cpu1_intc 0xffffffff>, <&cpu1_intc 9>,
187 <&cpu2_intc 0xffffffff>, <&cpu2_intc 9>,
188 <&cpu3_intc 0xffffffff>, <&cpu3_intc 9>,
189 <&cpu4_intc 0xffffffff>, <&cpu4_intc 9>;
190 };
191 prci: clock-controller@10000000 {
192 compatible = "sifive,fu740-c000-prci";
193 reg = <0x0 0x10000000 0x0 0x1000>;
194 clocks = <&hfclk>, <&rtcclk>;
195 #clock-cells = <1>;
196 #reset-cells = <1>;
197 };
198 uart0: serial@10010000 {
199 compatible = "sifive,fu740-c000-uart", "sifive,uart0";
200 reg = <0x0 0x10010000 0x0 0x1000>;
201 interrupt-parent = <&plic0>;
202 interrupts = <39>;
203 clocks = <&prci 7>;
204 status = "disabled";
205 };
206 uart1: serial@10011000 {
207 compatible = "sifive,fu740-c000-uart", "sifive,uart0";
208 reg = <0x0 0x10011000 0x0 0x1000>;
209 interrupt-parent = <&plic0>;
210 interrupts = <40>;
211 clocks = <&prci 7>;
212 status = "disabled";
213 };
214 i2c0: i2c@10030000 {
215 compatible = "sifive,fu740-c000-i2c", "sifive,i2c0";
216 reg = <0x0 0x10030000 0x0 0x1000>;
217 interrupt-parent = <&plic0>;
218 interrupts = <52>;
219 clocks = <&prci 7>;
220 reg-shift = <2>;
221 reg-io-width = <1>;
222 #address-cells = <1>;
223 #size-cells = <0>;
224 status = "disabled";
225 };
226 i2c1: i2c@10031000 {
227 compatible = "sifive,fu740-c000-i2c", "sifive,i2c0";
228 reg = <0x0 0x10031000 0x0 0x1000>;
229 interrupt-parent = <&plic0>;
230 interrupts = <53>;
231 clocks = <&prci 7>;
232 reg-shift = <2>;
233 reg-io-width = <1>;
234 #address-cells = <1>;
235 #size-cells = <0>;
236 status = "disabled";
237 };
238 qspi0: spi@10040000 {
239 compatible = "sifive,fu740-c000-spi", "sifive,spi0";
240 reg = <0x0 0x10040000 0x0 0x1000>,
241 <0x0 0x20000000 0x0 0x10000000>;
242 interrupt-parent = <&plic0>;
243 interrupts = <41>;
244 clocks = <&prci 7>;
245 #address-cells = <1>;
246 #size-cells = <0>;
247 status = "disabled";
248 };
249 qspi1: spi@10041000 {
250 compatible = "sifive,fu740-c000-spi", "sifive,spi0";
251 reg = <0x0 0x10041000 0x0 0x1000>,
252 <0x0 0x30000000 0x0 0x10000000>;
253 interrupt-parent = <&plic0>;
254 interrupts = <42>;
255 clocks = <&prci 7>;
256 #address-cells = <1>;
257 #size-cells = <0>;
258 status = "disabled";
259 };
260 spi0: spi@10050000 {
261 compatible = "sifive,fu740-c000-spi", "sifive,spi0";
262 reg = <0x0 0x10050000 0x0 0x1000>;
263 interrupt-parent = <&plic0>;
264 interrupts = <43>;
265 clocks = <&prci 7>;
266 #address-cells = <1>;
267 #size-cells = <0>;
268 status = "disabled";
269 };
270 eth0: ethernet@10090000 {
271 compatible = "sifive,fu540-c000-gem";
272 interrupt-parent = <&plic0>;
273 interrupts = <55>;
274 reg = <0x0 0x10090000 0x0 0x2000>,
275 <0x0 0x100a0000 0x0 0x1000>;
276 local-mac-address = [00 00 00 00 00 00];
277 clock-names = "pclk", "hclk";
278 clocks = <&prci 2>,
279 <&prci 2>;
280 #address-cells = <1>;
281 #size-cells = <0>;
282 status = "disabled";
283 phandle = <0x13>; //TODO remove
284 };
285 pwm0: pwm@10020000 {
286 compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
287 reg = <0x0 0x10020000 0x0 0x1000>;
288 interrupt-parent = <&plic0>;
289 interrupts = <44>, <45>, <46>, <47>;
290 clocks = <&prci 7>;
291 #pwm-cells = <3>;
292 status = "disabled";
293 };
294 pwm1: pwm@10021000 {
295 compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
296 reg = <0x0 0x10021000 0x0 0x1000>;
297 interrupt-parent = <&plic0>;
298 interrupts = <48>, <49>, <50>, <51>;
299 clocks = <&prci 7>;
300 #pwm-cells = <3>;
301 status = "disabled";
302 };
303 ccache: cache-controller@2010000 {
304 compatible = "sifive,fu740-c000-ccache", "cache";
305 cache-block-size = <64>;
306 cache-level = <2>;
307 cache-sets = <2048>;
308 cache-size = <2097152>;
309 cache-unified;
310 interrupt-parent = <&plic0>;
311 interrupts = <19>, <21>, <22>, <20>;
312 reg = <0x0 0x2010000 0x0 0x1000>;
313 };
314 gpio: gpio@10060000 {
315 compatible = "sifive,fu740-c000-gpio", "sifive,gpio0";
316 interrupt-parent = <&plic0>;
317 interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>,
318 <30>, <31>, <32>, <33>, <34>, <35>, <36>,
319 <37>, <38>;
320 reg = <0x0 0x10060000 0x0 0x1000>;
321 gpio-controller;
322 #gpio-cells = <2>;
323 interrupt-controller;
324 #interrupt-cells = <2>;
325 clocks = <&prci 7>;
326 status = "disabled";
327 };
328 pcie@e00000000 {
329 compatible = "sifive,fu740-pcie";
330 #address-cells = <3>;
331 #size-cells = <2>;
332 #interrupt-cells = <1>;
333 reg = <0xe 0x00000000 0x0 0x80000000>,
334 <0xd 0xf0000000 0x0 0x10000000>,
335 <0x0 0x100d0000 0x0 0x1000>;
336 reg-names = "dbi", "config", "mgmt";
337 device_type = "pci";
338 dma-coherent;
339 bus-range = <0x0 0xff>;
340 //TODO
341 //ranges = <0x81000000 0x0 0x60080000 0x0 0x60080000 0x0 0x10000>, /* I/O */
342 // <0x82000000 0x0 0x60090000 0x0 0x60090000 0x0 0xff70000>, /* mem */
343 // <0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x1000000>, /* mem */
344 // <0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>; /* mem prefetchable */
345 ranges = <0x81000000 0x00 0x60080000 0x00 0x60080000 0x00 0x10000 0x82000000 0x00 0x60090000 0x00 0x60090000 0x00 0xff70000 0x82000000 0x00 0x70000000 0x00 0x70000000 0x00 0x10000000 0xc3000000 0x20 0x00 0x20 0x00 0x20 0x00>;
346 num-lanes = <0x8>;
347 interrupts = <56>, <57>, <58>, <59>, <60>, <61>, <62>, <63>, <64>;
348 interrupt-names = "msi", "inta", "intb", "intc", "intd";
349 interrupt-parent = <&plic0>;
350 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
351 interrupt-map = <0x0 0x0 0x0 0x1 &plic0 57>,
352 <0x0 0x0 0x0 0x2 &plic0 58>,
353 <0x0 0x0 0x0 0x3 &plic0 59>,
354 <0x0 0x0 0x0 0x4 &plic0 60>;
355 clock-names = "pcie_aux";
356 clocks = <&prci 8>;
357 pwren-gpios = <&gpio 5 0>;
358 reset-gpios = <&gpio 8 0>;
359 resets = <&prci 4>;
360 status = "okay";
361 };
362 };
363 };