src/northbridge/intel/i945/early_init.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <cbmem.h>
   4 #include <cf9_reset.h>
   5 #include <console/console.h>
   6 #include <device/pci_ops.h>
   7 #include <device/pci.h>
   8 #include <option.h>
   9 #include <romstage_handoff.h>
  10 #include <types.h>
  11
  12 #include "i945.h"
  13
  14 int i945_silicon_revision(void)
  15 {
  16         return pci_read_config8(HOST_BRIDGE, PCI_CLASS_REVISION);
  17 }
  18
  19 static void i945m_detect_chipset(void)
  20 {
  21         u8 reg8;
  22
  23         printk(BIOS_INFO, "\n");
  24         reg8 = (pci_read_config8(HOST_BRIDGE, 0xe7) & 0x70) >> 4;
  25         switch (reg8) {
  26         case 1:
  27                 printk(BIOS_INFO, "Mobile Intel(R) 82945GM/GME Express");
  28                 break;
  29         case 2:
  30                 printk(BIOS_INFO, "Mobile Intel(R) 82945GMS/GU/GSE Express");
  31                 break;
  32         case 3:
  33                 printk(BIOS_INFO, "Mobile Intel(R) 82945PM Express");
  34                 break;
  35         case 5:
  36                 printk(BIOS_INFO, "Intel(R) 82945GT Express");
  37                 break;
  38         case 6:
  39                 printk(BIOS_INFO, "Mobile Intel(R) 82943/82940GML Express");
  40                 break;
  41         default: /* Others reserved. */
  42                 printk(BIOS_INFO, "Unknown (%02x)", reg8);
  43         }
  44         printk(BIOS_INFO, " Chipset\n");
  45
  46         printk(BIOS_DEBUG, "(G)MCH capable of up to FSB ");
  47         reg8 = (pci_read_config8(HOST_BRIDGE, 0xe3) & 0xe0) >> 5;
  48         switch (reg8) {
  49         case 2:
  50                 printk(BIOS_DEBUG, "800 MHz"); /* According to 965 spec */
  51                 break;
  52         case 3:
  53                 printk(BIOS_DEBUG, "667 MHz");
  54                 break;
  55         case 4:
  56                 printk(BIOS_DEBUG, "533 MHz");
  57                 break;
  58         default:
  59                 printk(BIOS_DEBUG, "N/A MHz (%02x)", reg8);
  60         }
  61         printk(BIOS_DEBUG, "\n");
  62
  63         printk(BIOS_DEBUG, "(G)MCH capable of ");
  64         reg8 = (pci_read_config8(HOST_BRIDGE, 0xe4) & 0x07);
  65         switch (reg8) {
  66         case 2:
  67                 printk(BIOS_DEBUG, "up to DDR2-667");
  68                 break;
  69         case 3:
  70                 printk(BIOS_DEBUG, "up to DDR2-533");
  71                 break;
  72         case 4:
  73                 printk(BIOS_DEBUG, "DDR2-400");
  74                 break;
  75         default: /* Others reserved. */
  76                 printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8);
  77         }
  78         printk(BIOS_DEBUG, "\n");
  79
  80         if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC))
  81                 printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n");
  82 }
  83
  84 static void i945_detect_chipset(void)
  85 {
  86         u8 reg8;
  87
  88         printk(BIOS_INFO, "\nIntel(R) ");
  89
  90         reg8 = ((pci_read_config8(HOST_BRIDGE, 0xe7) >> 5) & 4)
  91              | ((pci_read_config8(HOST_BRIDGE, 0xe4) >> 4) & 3);
  92         switch (reg8) {
  93         case 0:
  94         case 1:
  95                 printk(BIOS_INFO, "82945G");
  96                 break;
  97         case 2:
  98         case 3:
  99                 printk(BIOS_INFO, "82945P");
 100                 break;
 101         case 4:
 102                 printk(BIOS_INFO, "82945GC");
 103                 break;
 104         case 5:
 105                 printk(BIOS_INFO, "82945GZ");
 106                 break;
 107         case 6:
 108         case 7:
 109                 printk(BIOS_INFO, "82945PL");
 110                 break;
 111         default:
 112                 break;
 113         }
 114         printk(BIOS_INFO, " Chipset\n");
 115
 116         printk(BIOS_DEBUG, "(G)MCH capable of ");
 117         reg8 = (pci_read_config8(HOST_BRIDGE, 0xe4) & 0x07);
 118         switch (reg8) {
 119         case 0:
 120         case 2:
 121                 printk(BIOS_DEBUG, "up to DDR2-667");
 122                 break;
 123         case 3:
 124                 printk(BIOS_DEBUG, "up to DDR2-533");
 125                 break;
 126         default: /* Others reserved. */
 127                 printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8);
 128         }
 129         printk(BIOS_DEBUG, "\n");
 130
 131         if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM))
 132                 printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n");
 133 }
 134
 135 static void i945_setup_bars(void)
 136 {
 137         u8 reg8, gfxsize;
 138
 139         /* As of now, we don't have all the A0 workarounds implemented */
 140         if (i945_silicon_revision() == 0)
 141                 printk(BIOS_INFO, "Warning: i945 silicon revision A0 might not work correctly.\n");
 142
 143         printk(BIOS_DEBUG, "Setting up static northbridge registers...");
 144         /* Set up all hardcoded northbridge BARs */
 145         pci_write_config32(HOST_BRIDGE, EPBAR,  CONFIG_FIXED_EPBAR_MMIO_BASE  | 1);
 146         pci_write_config32(HOST_BRIDGE, MCHBAR, CONFIG_FIXED_MCHBAR_MMIO_BASE | 1);
 147         pci_write_config32(HOST_BRIDGE, DMIBAR, CONFIG_FIXED_DMIBAR_MMIO_BASE | 1);
 148         pci_write_config32(HOST_BRIDGE, X60BAR, DEFAULT_X60BAR | 1);
 149
 150         /* vram size from CMOS option */
 151         gfxsize = get_uint_option("gfx_uma_size", 2);   /* 2 for 8MB */
 152         /* make sure no invalid setting is used */
 153         if (gfxsize > 6)
 154                 gfxsize = 2;
 155         pci_write_config16(HOST_BRIDGE, GGC, ((gfxsize + 1) << 4));
 156         /* TSEG 2M, This amount can easily be covered by SMRR MTRR's,
 157            which requires to have TSEG_BASE aligned to TSEG_SIZE. */
 158         pci_update_config8(HOST_BRIDGE, ESMRAMC, ~0x07, (1 << 1) | (1 << 0));
 159
 160         /* Set C0000-FFFFF to access RAM on both reads and writes */
 161         pci_write_config8(HOST_BRIDGE, PAM0, 0x30);
 162         pci_write_config8(HOST_BRIDGE, PAM1, 0x33);
 163         pci_write_config8(HOST_BRIDGE, PAM2, 0x33);
 164         pci_write_config8(HOST_BRIDGE, PAM3, 0x33);
 165         pci_write_config8(HOST_BRIDGE, PAM4, 0x33);
 166         pci_write_config8(HOST_BRIDGE, PAM5, 0x33);
 167         pci_write_config8(HOST_BRIDGE, PAM6, 0x33);
 168
 169         printk(BIOS_DEBUG, " done.\n");
 170
 171         /* Wait for MCH BAR to come up */
 172         printk(BIOS_DEBUG, "Waiting for MCHBAR to come up...");
 173         if ((pci_read_config32(HOST_BRIDGE, 0xe4) & 0x20000) == 0x00) { /* Bit 49 of CAPID0 */
 174                 do {
 175                         reg8 = *(volatile u8 *)0xfed40000;
 176                 } while (!(reg8 & 0x80));
 177         }
 178         printk(BIOS_DEBUG, "ok\n");
 179 }
 180
 181 static void i945_setup_egress_port(void)
 182 {
 183         u32 reg32;
 184         u32 timeout;
 185
 186         printk(BIOS_DEBUG, "Setting up Egress Port RCRB\n");
 187
 188         /* Egress Port Virtual Channel 0 Configuration */
 189
 190         /* map only TC0 to VC0 */
 191         reg32 = epbar_read32(EPVC0RCTL);
 192         reg32 &= 0xffffff01;
 193         epbar_write32(EPVC0RCTL, reg32);
 194
 195         reg32 = epbar_read32(EPPVCCAP1);
 196         reg32 &= ~(7 << 0);
 197         reg32 |= 1;
 198         epbar_write32(EPPVCCAP1, reg32);
 199
 200         /* Egress Port Virtual Channel 1 Configuration */
 201         reg32 = epbar_read32(0x2c);
 202         reg32 &= 0xffffff00;
 203         if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) {
 204                 if ((mchbar_read32(CLKCFG) & 7) == 0)
 205                         reg32 |= 0x1a;  /* 1067MHz */
 206         }
 207         if ((mchbar_read32(CLKCFG) & 7) == 1)
 208                 reg32 |= 0x0d;  /* 533MHz */
 209         if ((mchbar_read32(CLKCFG) & 7) == 2)
 210                 reg32 |= 0x14;  /* 800MHz */
 211         if ((mchbar_read32(CLKCFG) & 7) == 3)
 212                 reg32 |= 0x10;  /* 667MHz */
 213         epbar_write32(0x2c, reg32);
 214
 215         epbar_write32(EPVC1MTS, 0x0a0a0a0a);
 216
 217         reg32 = epbar_read32(EPVC1RCAP);
 218         reg32 &= ~(0x7f << 16);
 219         reg32 |= (0x0a << 16);
 220         epbar_write32(EPVC1RCAP, reg32);
 221
 222         if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) {
 223                 if ((mchbar_read32(CLKCFG) & 7) == 0) { /* 1067MHz */
 224                         epbar_write32(EPVC1IST + 0, 0x01380138);
 225                         epbar_write32(EPVC1IST + 4, 0x01380138);
 226                 }
 227         }
 228
 229         if ((mchbar_read32(CLKCFG) & 7) == 1) { /* 533MHz */
 230                 epbar_write32(EPVC1IST + 0, 0x009c009c);
 231                 epbar_write32(EPVC1IST + 4, 0x009c009c);
 232         }
 233
 234         if ((mchbar_read32(CLKCFG) & 7) == 2) { /* 800MHz */
 235                 epbar_write32(EPVC1IST + 0, 0x00f000f0);
 236                 epbar_write32(EPVC1IST + 4, 0x00f000f0);
 237         }
 238
 239         if ((mchbar_read32(CLKCFG) & 7) == 3) { /* 667MHz */
 240                 epbar_write32(EPVC1IST + 0, 0x00c000c0);
 241                 epbar_write32(EPVC1IST + 4, 0x00c000c0);
 242         }
 243
 244         /* Is internal graphics enabled? */
 245         if (pci_read_config8(HOST_BRIDGE, DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1))
 246                 mchbar_setbits32(MMARB1, 1 << 17);
 247
 248         /* Assign Virtual Channel ID 1 to VC1 */
 249         reg32 = epbar_read32(EPVC1RCTL);
 250         reg32 &= ~(7 << 24);
 251         reg32 |= (1 << 24);
 252         epbar_write32(EPVC1RCTL, reg32);
 253
 254         reg32 = epbar_read32(EPVC1RCTL);
 255         reg32 &= 0xffffff01;
 256         reg32 |= (1 << 7);
 257         epbar_write32(EPVC1RCTL, reg32);
 258
 259         epbar_write32(PORTARB + 0x00, 0x01000001);
 260         epbar_write32(PORTARB + 0x04, 0x00040000);
 261         epbar_write32(PORTARB + 0x08, 0x00001000);
 262         epbar_write32(PORTARB + 0x0c, 0x00000040);
 263         epbar_write32(PORTARB + 0x10, 0x01000001);
 264         epbar_write32(PORTARB + 0x14, 0x00040000);
 265         epbar_write32(PORTARB + 0x18, 0x00001000);
 266         epbar_write32(PORTARB + 0x1c, 0x00000040);
 267
 268         epbar_setbits32(EPVC1RCTL, 1 << 16);
 269         epbar_setbits32(EPVC1RCTL, 1 << 16);
 270
 271         printk(BIOS_DEBUG, "Loading port arbitration table ...");
 272         /* Loop until bit 0 becomes 0 */
 273         timeout = 0x7fffff;
 274         while ((epbar_read16(EPVC1RSTS) & (1 << 0)) && --timeout)
 275                 ;
 276         if (!timeout)
 277                 printk(BIOS_DEBUG, "timeout!\n");
 278         else
 279                 printk(BIOS_DEBUG, "ok\n");
 280
 281         /* Now enable VC1 */
 282         epbar_setbits32(EPVC1RCTL, 1 << 31);
 283
 284         printk(BIOS_DEBUG, "Wait for VC1 negotiation ...");
 285         /* Wait for VC1 negotiation pending */
 286         timeout = 0x7fff;
 287         while ((epbar_read16(EPVC1RSTS) & (1 << 1)) && --timeout)
 288                 ;
 289         if (!timeout)
 290                 printk(BIOS_DEBUG, "timeout!\n");
 291         else
 292                 printk(BIOS_DEBUG, "ok\n");
 293 }
 294
 295 static void ich7_setup_dmi_rcrb(void)
 296 {
 297         u16 reg16;
 298         u32 reg32;
 299
 300         reg16 = RCBA16(LCTL);
 301         reg16 &= ~(3 << 0);
 302         reg16 |= 3;
 303         RCBA16(LCTL) = reg16;
 304
 305         RCBA32(V0CTL) = 0x80000001;
 306         RCBA32(V1CAP) = 0x03128010;
 307
 308         pci_write_config16(PCI_DEV(0, 0x1c, 0), 0x42, 0x0141);
 309         pci_write_config16(PCI_DEV(0, 0x1c, 4), 0x42, 0x0141);
 310         pci_write_config16(PCI_DEV(0, 0x1c, 5), 0x42, 0x0141);
 311
 312         pci_write_config32(PCI_DEV(0, 0x1c, 4), 0x54, 0x00480ce0);
 313         pci_write_config32(PCI_DEV(0, 0x1c, 5), 0x54, 0x00500ce0);
 314
 315         reg32 = RCBA32(V1CTL);
 316         reg32 &= ~((0x7f << 1) | (7 << 17) | (7 << 24));
 317         reg32 |= (0x40 << 1) | (4 << 17) | (1 << 24) | (1 << 31);
 318         RCBA32(V1CTL) = reg32;
 319
 320         RCBA32(LCAP) |= (3 << 10);
 321 }
 322
 323 static void i945_setup_dmi_rcrb(void)
 324 {
 325         u32 reg32;
 326         u32 timeout;
 327         int activate_aspm = 1; /* hardcode ASPM for now */
 328
 329         printk(BIOS_DEBUG, "Setting up DMI RCRB\n");
 330
 331         /* Virtual Channel 0 Configuration */
 332         reg32 = dmibar_read32(DMIVC0RCTL0);
 333         reg32 &= 0xffffff01;
 334         dmibar_write32(DMIVC0RCTL0, reg32);
 335
 336         reg32 = dmibar_read32(DMIPVCCAP1);
 337         reg32 &= ~(7 << 0);
 338         reg32 |= 1;
 339         dmibar_write32(DMIPVCCAP1, reg32);
 340
 341         reg32 = dmibar_read32(DMIVC1RCTL);
 342         reg32 &= ~(7 << 24);
 343         reg32 |= (1 << 24);     /* NOTE: This ID must match ICH7 side */
 344         dmibar_write32(DMIVC1RCTL, reg32);
 345
 346         reg32 = dmibar_read32(DMIVC1RCTL);
 347         reg32 &= 0xffffff01;
 348         reg32 |= (1 << 7);
 349         dmibar_write32(DMIVC1RCTL, reg32);
 350
 351         /* Now enable VC1 */
 352         dmibar_setbits32(DMIVC1RCTL, 1 << 31);
 353
 354         printk(BIOS_DEBUG, "Wait for VC1 negotiation ...");
 355         /* Wait for VC1 negotiation pending */
 356         timeout = 0x7ffff;
 357         while ((dmibar_read16(DMIVC1RSTS) & (1 << 1)) && --timeout)
 358                 ;
 359         if (!timeout)
 360                 printk(BIOS_DEBUG, "timeout!\n");
 361         else
 362                 printk(BIOS_DEBUG, "done..\n");
 363
 364         /* Enable Active State Power Management (ASPM) L0 state */
 365
 366         reg32 = dmibar_read32(DMILCAP);
 367         reg32 &= ~(7 << 12);
 368         reg32 |= (2 << 12);
 369
 370         reg32 &= ~(7 << 15);
 371
 372         reg32 |= (2 << 15);
 373         dmibar_write32(DMILCAP, reg32);
 374
 375         reg32 = dmibar_read32(DMICC);
 376         reg32 &= 0x00ffffff;
 377         reg32 &= ~(3 << 0);
 378         reg32 |= (1 << 0);
 379         reg32 &= ~(3 << 20);
 380         reg32 |= (1 << 20);
 381
 382         dmibar_write32(DMICC, reg32);
 383
 384         if (activate_aspm)
 385                 dmibar_setbits32(DMILCTL, 3 << 0);
 386
 387         /* Last but not least, some additional steps */
 388         reg32 = mchbar_read32(FSBSNPCTL);
 389         reg32 &= ~(0xff << 2);
 390         reg32 |= (0xaa << 2);
 391         mchbar_write32(FSBSNPCTL, reg32);
 392
 393         dmibar_write32(0x2c, 0x86000040);
 394
 395         reg32 = dmibar_read32(0x204);
 396         reg32 &= ~0x3ff;
 397 #if 1
 398         reg32 |= 0x13f; /* for x4 DMI only */
 399 #else
 400         reg32 |= 0x1e4; /* for x2 DMI only */
 401 #endif
 402         dmibar_write32(0x204, reg32);
 403
 404         if (pci_read_config8(HOST_BRIDGE, DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) {
 405                 printk(BIOS_DEBUG, "Internal graphics: enabled\n");
 406                 dmibar_setbits32(0x200, 1 << 21);
 407         } else {
 408                 printk(BIOS_DEBUG, "Internal graphics: disabled\n");
 409                 dmibar_clrbits32(0x200, 1 << 21);
 410         }
 411
 412         reg32 = dmibar_read32(0x204);
 413         reg32 &= ~((1 << 11) | (1 << 10));
 414         dmibar_write32(0x204, reg32);
 415
 416         reg32 = dmibar_read32(0x204);
 417         reg32 &= ~(0xff << 12);
 418         reg32 |= (0x0d << 12);
 419         dmibar_write32(0x204, reg32);
 420
 421         dmibar_setbits32(DMICTL1, 3 << 24);
 422
 423         reg32 = dmibar_read32(0x200);
 424         reg32 &= ~(0x3 << 26);
 425         reg32 |= (0x02 << 26);
 426         dmibar_write32(0x200, reg32);
 427
 428         dmibar_clrbits32(DMIDRCCFG, 1 << 31);
 429         dmibar_setbits32(DMICTL2, 1 << 31);
 430
 431         if (i945_silicon_revision() >= 3) {
 432                 reg32 = dmibar_read32(0xec0);
 433                 reg32 &= 0x0fffffff;
 434                 reg32 |= (2 << 28);
 435                 dmibar_write32(0xec0, reg32);
 436
 437                 reg32 = dmibar_read32(0xed4);
 438                 reg32 &= 0x0fffffff;
 439                 reg32 |= (2 << 28);
 440                 dmibar_write32(0xed4, reg32);
 441
 442                 reg32 = dmibar_read32(0xee8);
 443                 reg32 &= 0x0fffffff;
 444                 reg32 |= (2 << 28);
 445                 dmibar_write32(0xee8, reg32);
 446
 447                 reg32 = dmibar_read32(0xefc);
 448                 reg32 &= 0x0fffffff;
 449                 reg32 |= (2 << 28);
 450                 dmibar_write32(0xefc, reg32);
 451         }
 452
 453         /* wait for bit toggle to 0 */
 454         printk(BIOS_DEBUG, "Waiting for DMI hardware...");
 455         timeout = 0x7fffff;
 456         while ((dmibar_read8(0x32) & (1 << 1)) && --timeout)
 457                 ;
 458         if (!timeout)
 459                 printk(BIOS_DEBUG, "timeout!\n");
 460         else
 461                 printk(BIOS_DEBUG, "ok\n");
 462
 463         /* Clear Error Status Bits! */
 464         dmibar_write32(0x1c4, 0xffffffff);
 465         dmibar_write32(0x1d0, 0xffffffff);
 466         dmibar_write32(0x228, 0xffffffff);
 467
 468         /* Program Read-Only Write-Once Registers */
 469         dmibar_setbits32(0x308, 0);
 470         dmibar_setbits32(0x314, 0);
 471         dmibar_setbits32(0x324, 0);
 472         dmibar_setbits32(0x328, 0);
 473         dmibar_setbits32(0x334, 0);
 474         dmibar_setbits32(0x338, 0);
 475
 476         if (i945_silicon_revision() == 1 && (mchbar_read8(DFT_STRAP1) & (1 << 5))) {
 477                 if ((mchbar_read32(0x214) & 0xf) != 0x3) {
 478                         printk(BIOS_INFO, "DMI link requires A1 stepping workaround. Rebooting.\n");
 479                         reg32 = dmibar_read32(0x224);
 480                         reg32 &= ~(7 << 0);
 481                         reg32 |= (3 << 0);
 482                         dmibar_write32(0x224, reg32);
 483                         system_reset();
 484                 }
 485         }
 486 }
 487
 488 static void i945_setup_pci_express_x16(void)
 489 {
 490         u32 timeout;
 491         u32 reg32;
 492         u16 reg16;
 493         const pci_devfn_t p2peg = PCI_DEV(0, 0x01, 0);
 494
 495         u8 tmp_secondary = 0x0a;
 496         const pci_devfn_t peg_plugin = PCI_DEV(tmp_secondary, 0, 0);
 497
 498         printk(BIOS_DEBUG, "Enabling PCI Express x16 Link\n");
 499
 500         pci_or_config16(HOST_BRIDGE, DEVEN, DEVEN_D1F0);
 501
 502         pci_and_config32(p2peg, PEGCC, ~(1 << 8));
 503
 504         /* We have no success with querying the usual PCIe registers
 505          * for link setup success on the i945. Hence we assign a temporary
 506          * PCI bus 0x0a and check whether we find a device on 0:a.0
 507          */
 508
 509         /* Force PCIRST# */
 510         pci_s_assert_secondary_reset(p2peg);
 511         pci_s_deassert_secondary_reset(p2peg);
 512
 513         reg16 = pci_read_config16(p2peg, SLOTSTS);
 514         printk(BIOS_DEBUG, "SLOTSTS: %04x\n", reg16);
 515         if (!(reg16 & 0x48))
 516                 goto disable_pciexpress_x16_link;
 517         reg16 |= (1 << 4) | (1 << 0);
 518         pci_write_config16(p2peg, SLOTSTS, reg16);
 519
 520         pci_s_bridge_set_secondary(p2peg, tmp_secondary);
 521
 522         pci_and_config32(p2peg, 0x224, ~(1 << 8));
 523
 524         mchbar_clrbits16(UPMC1, 1 << 5 | 1 << 0);
 525
 526         /* Initialize PEG_CAP */
 527         pci_or_config16(p2peg, PEG_CAP, 1 << 8);
 528
 529         /* Setup SLOTCAP */
 530         /* TODO: These values are mainboard dependent and should be set from devicetree.cb.
 531          */
 532         /* NOTE: SLOTCAP becomes RO after the first write! */
 533         reg32 = pci_read_config32(p2peg, SLOTCAP);
 534         reg32 &= 0x0007ffff;
 535
 536         reg32 &= 0xfffe007f;
 537
 538         pci_write_config32(p2peg, SLOTCAP, reg32);
 539
 540         /* Wait for training to succeed */
 541         printk(BIOS_DEBUG, "PCIe link training ...");
 542         timeout = 0x7ffff;
 543         while ((((pci_read_config32(p2peg, PEGSTS) >> 16) & 3) != 3) && --timeout)
 544                 ;
 545
 546         reg32 = pci_read_config32(peg_plugin, PCI_VENDOR_ID);
 547         if (reg32 != 0x00000000 && reg32 != 0xffffffff) {
 548                 printk(BIOS_DEBUG, " Detected PCIe device %04x:%04x\n",
 549                                 reg32 & 0xffff, reg32 >> 16);
 550         } else {
 551                 printk(BIOS_DEBUG, " timeout!\n");
 552
 553                 printk(BIOS_DEBUG, "Restrain PCIe port to x1\n");
 554
 555                 pci_update_config32(p2peg, PEGSTS, ~(0xf << 1), 1);
 556
 557                 /* Force PCIRST# */
 558                 pci_s_assert_secondary_reset(p2peg);
 559                 pci_s_deassert_secondary_reset(p2peg);
 560
 561                 printk(BIOS_DEBUG, "PCIe link training ...");
 562                 timeout = 0x7ffff;
 563                 while ((((pci_read_config32(p2peg, PEGSTS) >> 16) & 3) != 3) && --timeout)
 564                         ;
 565
 566                 reg32 = pci_read_config32(peg_plugin, PCI_VENDOR_ID);
 567                 if (reg32 != 0x00000000 && reg32 != 0xffffffff) {
 568                         printk(BIOS_DEBUG, " Detected PCIe x1 device %04x:%04x\n",
 569                                 reg32 & 0xffff, reg32 >> 16);
 570                 } else {
 571                         printk(BIOS_DEBUG, " timeout!\n");
 572                         printk(BIOS_DEBUG, "Disabling PCIe x16 port completely.\n");
 573                         goto disable_pciexpress_x16_link;
 574                 }
 575         }
 576
 577         reg16 = pci_read_config16(p2peg, 0xb2);
 578         reg16 >>= 4;
 579         reg16 &= 0x3f;
 580         /* reg16 == 1 -> x1; reg16 == 16 -> x16 */
 581         printk(BIOS_DEBUG, "PCIe x%d link training succeeded.\n", reg16);
 582
 583         reg32 = pci_read_config32(p2peg, PEGTC);
 584         reg32 &= 0xfffffc00; /* clear [9:0] */
 585         if (reg16 == 1)
 586                 reg32 |= 0x32b;
 587                 // TODO
 588                 /* pci_write_config32(p2peg, PEGTC, reg32); */
 589         else if (reg16 == 16)
 590                 reg32 |= 0x0f4;
 591                 // TODO
 592                 /* pci_write_config32(p2peg, PEGTC, reg32); */
 593
 594         reg32 = (pci_read_config32(peg_plugin, 0x8) >> 8);
 595         printk(BIOS_DEBUG, "PCIe device class: %06x\n", reg32);
 596         if (reg32 == 0x030000) {
 597                 printk(BIOS_DEBUG, "PCIe device is VGA. Disabling IGD.\n");
 598                 reg16 = (1 << 1);
 599                 pci_write_config16(HOST_BRIDGE, GGC, reg16);
 600
 601                 pci_and_config32(HOST_BRIDGE, DEVEN, ~(DEVEN_D2F0 | DEVEN_D2F1));
 602         }
 603
 604         /* Enable GPEs: PMEGPE, HPGPE, GENGPE */
 605         pci_or_config32(p2peg, PEG_LC, (1 << 2) | (1 << 1) | (1 << 0));
 606
 607         /* Virtual Channel Configuration: Only VC0 on PCIe x16 */
 608         pci_and_config32(p2peg, VC0RCTL, ~0x000000fe);
 609
 610         /* Extended VC count */
 611         pci_and_config32(p2peg, PVCCAP1, ~(7 << 0));
 612
 613         /* Active State Power Management ASPM */
 614
 615         /* TODO */
 616
 617         /* Clear error bits */
 618         pci_write_config16(p2peg, PCISTS1, 0xffff);
 619         pci_write_config16(p2peg, SSTS1, 0xffff);
 620         pci_write_config16(p2peg, DSTS, 0xffff);
 621         pci_write_config32(p2peg, UESTS, 0xffffffff);
 622         pci_write_config32(p2peg, CESTS, 0xffffffff);
 623         pci_write_config32(p2peg, 0x1f0, 0xffffffff);
 624         pci_write_config32(p2peg, 0x228, 0xffffffff);
 625
 626         /* Program R/WO registers */
 627         pci_update_config32(p2peg, 0x308, ~0, 0);
 628         pci_update_config32(p2peg, 0x314, ~0, 0);
 629         pci_update_config32(p2peg, 0x324, ~0, 0);
 630         pci_update_config32(p2peg, 0x328, ~0, 0);
 631
 632         /* Additional PCIe graphics setup */
 633         pci_or_config32(p2peg, 0xf0, 3 << 26);
 634         pci_or_config32(p2peg, 0xf0, 3 << 24);
 635         pci_or_config32(p2peg, 0xf0, 1 <<  5);
 636
 637         pci_update_config32(p2peg, 0x200, ~(3 << 26), 2 << 26);
 638
 639         reg32 = pci_read_config32(p2peg, 0xe80);
 640         if (i945_silicon_revision() >= 2)
 641                 reg32 |= (1 << 12);
 642         else
 643                 reg32 &= ~(1 << 12);
 644         pci_write_config32(p2peg, 0xe80, reg32);
 645
 646         pci_and_config32(p2peg, 0xeb4, ~(1 << 31));
 647
 648         pci_or_config32(p2peg, 0xfc, 1 << 31);
 649
 650         if (i945_silicon_revision() >= 3) {
 651                 static const u32 reglist[] = {
 652                         0xec0, 0xed4, 0xee8, 0xefc, 0xf10, 0xf24, 0xf38, 0xf4c,
 653                         0xf60, 0xf74, 0xf88, 0xf9c, 0xfb0, 0xfc4, 0xfd8, 0xfec
 654                 };
 655
 656                 int i;
 657                 for (i = 0; i < ARRAY_SIZE(reglist); i++)
 658                         pci_update_config32(p2peg, reglist[i], ~(0xf << 28), 2 << 28);
 659         }
 660
 661         if (i945_silicon_revision() <= 2) {
 662                 /* Set voltage specific parameters */
 663                 reg32 = pci_read_config32(p2peg, 0xe80);
 664                 reg32 &= (0xf << 4);    /* Default case 1.05V */
 665                 if ((mchbar_read32(DFT_STRAP1) & (1 << 20)) == 0) {     /* 1.50V */
 666                         reg32 |= (7 << 4);
 667                 }
 668                 pci_write_config32(p2peg, 0xe80, reg32);
 669         }
 670
 671         return;
 672
 673 disable_pciexpress_x16_link:
 674         /* For now we just disable the x16 link */
 675         printk(BIOS_DEBUG, "Disabling PCI Express x16 Link\n");
 676
 677         mchbar_setbits16(UPMC1, 1 << 5 | 1 << 0);
 678
 679         /* Toggle PCIRST# */
 680         pci_s_assert_secondary_reset(p2peg);
 681
 682         pci_or_config32(p2peg, 0x224, 1 << 8);
 683
 684         pci_s_deassert_secondary_reset(p2peg);
 685
 686         printk(BIOS_DEBUG, "Wait for link to enter detect state... ");
 687         timeout = 0x7fffff;
 688         for (reg32 = pci_read_config32(p2peg, PEGSTS);
 689              (reg32 & 0x000f0000) && --timeout;)
 690                 ;
 691         if (!timeout)
 692                 printk(BIOS_DEBUG, "timeout!\n");
 693         else
 694                 printk(BIOS_DEBUG, "ok\n");
 695
 696         /* Finally: Disable the PCI config header */
 697         pci_and_config16(HOST_BRIDGE, DEVEN, ~DEVEN_D1F0);
 698 }
 699
 700 static void i945_setup_root_complex_topology(void)
 701 {
 702         u32 reg32;
 703         const pci_devfn_t p2peg = PCI_DEV(0, 0x01, 0);
 704
 705         printk(BIOS_DEBUG, "Setting up Root Complex Topology\n");
 706         /* Egress Port Root Topology */
 707
 708         reg32 = epbar_read32(EPESD);
 709         reg32 &= 0xff00ffff;
 710         reg32 |= (1 << 16);
 711         epbar_write32(EPESD, reg32);
 712
 713         epbar_setbits32(EPLE1D, 1 << 16 | 1 << 0);
 714
 715         epbar_write32(EPLE1A, CONFIG_FIXED_DMIBAR_MMIO_BASE);
 716
 717         epbar_setbits32(EPLE2D, 1 << 16 | 1 << 0);
 718
 719         /* DMI Port Root Topology */
 720
 721         reg32 = dmibar_read32(DMILE1D);
 722         reg32 &= 0x00ffffff;
 723
 724         reg32 &= 0xff00ffff;
 725         reg32 |= (2 << 16);
 726
 727         reg32 |= (1 << 0);
 728         dmibar_write32(DMILE1D, reg32);
 729
 730         dmibar_write32(DMILE1A, CONFIG_FIXED_RCBA_MMIO_BASE);
 731
 732         dmibar_setbits32(DMILE2D, 1 << 16 | 1 << 0);
 733
 734         dmibar_write32(DMILE2A, CONFIG_FIXED_EPBAR_MMIO_BASE);
 735
 736         /* PCI Express x16 Port Root Topology */
 737         if (pci_read_config8(HOST_BRIDGE, DEVEN) & DEVEN_D1F0) {
 738                 pci_write_config32(p2peg, LE1A, CONFIG_FIXED_EPBAR_MMIO_BASE);
 739                 pci_or_config32(p2peg, LE1D, 1 << 0);
 740         }
 741 }
 742
 743 static void ich7_setup_root_complex_topology(void)
 744 {
 745         /* Write the R/WO registers */
 746
 747         RCBA32(ESD) |= (2 << 16);
 748
 749         RCBA32(ULD) |= (1 << 24) | (1 << 16);
 750
 751         RCBA32(ULBA) = CONFIG_FIXED_DMIBAR_MMIO_BASE;
 752         /* Write ESD.CID to TCID */
 753         RCBA32(RP1D) |= (2 << 16);
 754         RCBA32(RP2D) |= (2 << 16);
 755         RCBA32(RP3D) |= (2 << 16);
 756         RCBA32(RP4D) |= (2 << 16);
 757         RCBA32(HDD)  |= (2 << 16);
 758         RCBA32(RP5D) |= (2 << 16);
 759         RCBA32(RP6D) |= (2 << 16);
 760 }
 761
 762 static void ich7_setup_pci_express(void)
 763 {
 764         /* Enable PCIe Root Port Clock Gate */
 765         RCBA32(CG) |= (1 << 0);
 766
 767         /* Initialize slot power limit for root ports */
 768         pci_write_config32(PCI_DEV(0, 0x1c, 0), 0x54, 0x00000060);
 769
 770         pci_write_config32(PCI_DEV(0, 0x1c, 0), 0xd8, 0x00110000);
 771 }
 772
 773 void i945_early_initialization(void)
 774 {
 775         /* Print some chipset specific information */
 776         switch (pci_read_config32(HOST_BRIDGE, 0)) {
 777         case 0x27708086: /* 82945G/GZ/GC/P/PL */
 778                 i945_detect_chipset();
 779                 break;
 780         case 0x27a08086: /* 945GME/GSE */
 781         case 0x27ac8086: /* 945GM/PM/GMS/GU/GT, 943/940GML */
 782                 i945m_detect_chipset();
 783                 break;
 784         }
 785
 786         /* Setup all BARs required for early PCIe and raminit */
 787         i945_setup_bars();
 788
 789         /* Change port80 to LPC */
 790         RCBA32(GCS) &= (~0x04);
 791
 792         /* Just do it that way */
 793         RCBA32(0x2010) |= (1 << 10);
 794 }
 795
 796 static void i945_prepare_resume(int s3resume)
 797 {
 798         int cbmem_was_initted;
 799
 800         cbmem_was_initted = !cbmem_recovery(s3resume);
 801
 802         romstage_handoff_init(cbmem_was_initted && s3resume);
 803 }
 804
 805 void i945_late_initialization(int s3resume)
 806 {
 807         i945_setup_egress_port();
 808
 809         ich7_setup_root_complex_topology();
 810
 811         ich7_setup_pci_express();
 812
 813         ich7_setup_dmi_rcrb();
 814
 815         i945_setup_dmi_rcrb();
 816
 817         if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM))
 818                 i945_setup_pci_express_x16();
 819
 820         i945_setup_root_complex_topology();
 821
 822         if (CONFIG(DEBUG_RAM_SETUP))
 823                 sdram_dump_mchbar_registers();
 824
 825         mchbar_write16(SSKPD, 0xcafe);
 826
 827         i945_prepare_resume(s3resume);
 828 }