src/northbridge/intel/i945/memmap.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 // Use simple device model for this file even in ramstage
   4 #define __SIMPLE_DEVICE__
   5
   6 #include <arch/romstage.h>
   7 #include <cbmem.h>
   8 #include <console/console.h>
   9 #include <cpu/x86/mtrr.h>
  10 #include <cpu/x86/smm.h>
  11 #include <device/pci_ops.h>
  12 #include <types.h>
  13
  14 #include "i945.h"
  15
  16 /* Decodes TSEG region size to bytes. */
  17 u32 decode_tseg_size(const u8 esmramc)
  18 {
  19         if (!(esmramc & 1))
  20                 return 0;
  21         switch ((esmramc >> 1) & 3) {
  22         case 0:
  23                 return 1 << 20;
  24         case 1:
  25                 return 2 << 20;
  26         case 2:
  27                 return 8 << 20;
  28         case 3:
  29         default:
  30                 die("Bad TSEG setting.\n");
  31         }
  32 }
  33
  34 static uintptr_t northbridge_get_tseg_base(void)
  35 {
  36         uintptr_t tom;
  37
  38         if (pci_read_config8(HOST_BRIDGE, DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1))
  39                 /* IGD enabled, get top of Memory from BSM register */
  40                 tom = pci_read_config32(IGD_DEV, BSM);
  41         else
  42                 tom = (pci_read_config8(HOST_BRIDGE, TOLUD) & 0xf8) << 24;
  43
  44         /* subtract TSEG size */
  45         tom -= decode_tseg_size(pci_read_config8(HOST_BRIDGE, ESMRAMC));
  46         return tom;
  47 }
  48
  49 static size_t northbridge_get_tseg_size(void)
  50 {
  51         const u8 esmramc = pci_read_config8(HOST_BRIDGE, ESMRAMC);
  52         return decode_tseg_size(esmramc);
  53 }
  54
  55 /*
  56  * Depending of UMA and TSEG configuration, TSEG might start at any
  57  * 1 MiB alignment. As this may cause very greedy MTRR setup, push
  58  * CBMEM top downwards to 4 MiB boundary.
  59  */
  60 uintptr_t cbmem_top_chipset(void)
  61 {
  62         return ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB);
  63 }
  64
  65 /* Decodes used Graphics Mode Select (GMS) to kilobytes. */
  66 u32 decode_igd_memory_size(const u32 gms)
  67 {
  68         static const u16 ggc2uma[] = { 0, 1, 4, 8, 16, 32, 48, 64 };
  69
  70         if (gms >= ARRAY_SIZE(ggc2uma))
  71                 die("Bad Graphics Mode Select (GMS) setting.\n");
  72
  73         return ggc2uma[gms] << 10;
  74 }
  75
  76 void smm_region(uintptr_t *start, size_t *size)
  77 {
  78         *start = northbridge_get_tseg_base();
  79         *size = northbridge_get_tseg_size();
  80 }
  81
  82 void fill_postcar_frame(struct postcar_frame *pcf)
  83 {
  84         /* Cache 8 MiB region below the top of RAM and 2 MiB above top of
  85          * RAM to cover both cbmem as the TSEG region.
  86          */
  87         const uintptr_t top_of_ram = cbmem_top();
  88         postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK);
  89         postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(),
  90                                northbridge_get_tseg_size(), MTRR_TYPE_WRBACK);
  91 }