src/soc/intel/braswell/include/soc/pcie.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef _SOC_PCIE_H_
   4 #define _SOC_PCIE_H_
   5
   6 /* PCIe root port config space registers. */
   7 #define XCAP                    0x40
   8 # define SI                     (1 << 24)
   9 #define DCAP                    0x44
  10 # define MPS_MASK               0x7
  11 #define DCTL_DSTS               0x48
  12 # define URE                    (1 << 3)
  13 # define FEE                    (1 << 2)
  14 # define NFE                    (1 << 1)
  15 # define CEE                    (1 << 0)
  16 #define LCAP                    0x4c
  17 # define L1EXIT_SHIFT           15
  18 # define L1EXIT_MASK            (0x7 << L1EXIT_SHIFT)
  19 #define LCTL                    0x50
  20 # define CCC                    (1 << 6)
  21 # define RL                     (1 << 5)
  22 # define LD                     (1 << 4)
  23 #define LSTS                    0x52
  24 #define SLCAP                   0x54
  25 # define SLN_SHIFT              19
  26 # define SLS_SHIFT              15
  27 # define SLV_SHIFT              7
  28 # define HPC                    (1 << 6)
  29 # define HPS                    (1 << 5)
  30 #define SLCTL_SLSTS             0x58
  31 # define PDS                    (1 << 22)
  32 #define DCAP2                   0x64
  33 # define OBFFS                  (0x3 << 18)
  34 # define LTRMS                  (1 << 11)
  35 #define DSTS2                   0x68
  36 # define OBFFEN                 (3 << 13)
  37 # define LTRME                  (1 << 10)
  38 # define CTD                    (1 <<  4)
  39 #define CHCFG                   0xd0
  40 # define UPSD                   (1 << 24)
  41 # define UNRS                   (1 << 15)
  42 # define UPRS                   (1 << 14)
  43 #define MPC2                    0xd4
  44 # define IPF                    (1 << 11)
  45 # define LSTP                   (1 <<  6)
  46 # define EOIFD                  (1 <<  1)
  47 #define MPC                     0xd8
  48 # define CCEL_SHIFT             15
  49 # define CCEL_MASK              (0x7 << CCEL_SHIFT)
  50 #define RPPGEN                  0xe0
  51 # define RPSCGEN                (1 << 15)
  52 # define LCLKREQEN              (1 << 13)
  53 # define BBCLKREQEN             (1 << 12)
  54 # define SRDLCGEN               (1 << 11)
  55 # define SRDBCGEN               (1 << 10)
  56 # define RPDLCGEN               (1 << 9)
  57 # define RPDBCGEN               (1 << 8)
  58 #define PWRCTL                  0xe8
  59 # define RPL1SQPOL              (1 << 1)
  60 # define RPDTSQPOL              (1 << 0)
  61 #define PHYCTL2_IOSFBCTL        0xf4
  62 # define PLL_OFF_EN             (1 << 8)
  63 # define TDFT                   (3 << 14)
  64 # define TXCFGCHWAIT            (3 << 12)
  65 # define SIID                   (3 << 26)
  66 #define STRPFUSECFG             0xfc
  67 # define LANECFG_SHIFT          14
  68 # define LANECFG_MASK           (0x3 << LANECFG_SHIFT)
  69 #define AERCH                   0x100
  70 #define NFTS                    0x314
  71 #define L0SC                    0x318
  72 #define CFG2                    0x320
  73 # define CSREN                  (1 << 22)
  74 # define LATGC_SHIFT            6
  75 # define LATGC_MASK             (0x7 << LATGC_SHIFT)
  76 #define PCIEDBG                 0x324
  77 # define SPCE                   (1 << 5)
  78 #define PCIESTS1                0x328
  79 #define PCIEALC                 0x338
  80 #define RTP                     0x33c
  81 #define PHYCTL4                 0x408
  82 # define SQDIS                  (1 << 27)
  83
  84 #endif /* _SOC_PCIE_H_ */