src/soc/intel/common/block/crashlog/crashlog.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <console/console.h>
   4 #include <delay.h>
   5 #include <device/mmio.h>
   6 #include <intelblocks/crashlog.h>
   7 #include <intelblocks/pmc_ipc.h>
   8 #include <string.h>
   9
  10 int __weak cl_get_cpu_record_size(void)
  11 {
  12         return 0;
  13 }
  14
  15 int __weak cl_get_pmc_record_size(void)
  16 {
  17         return 0;
  18 }
  19
  20 uintptr_t __weak cl_get_cpu_bar_addr(void)
  21 {
  22         return 0;
  23 }
  24
  25 int __weak cl_get_ioe_record_size(void)
  26 {
  27         return 0;
  28 }
  29
  30 uintptr_t __weak cl_get_cpu_tmp_bar(void)
  31 {
  32         return 0;
  33 }
  34
  35 uintptr_t __weak cl_get_cpu_mb_int_addr(void)
  36 {
  37         return 0;
  38 }
  39
  40 int __weak cl_get_total_data_size(void)
  41 {
  42         return cl_get_cpu_record_size() + cl_get_pmc_record_size();
  43 }
  44
  45 bool __weak cl_pmc_sram_has_mmio_access(void)
  46 {
  47         return false;
  48 }
  49
  50 bool __weak cl_ioe_sram_has_mmio_access(void)
  51 {
  52         return false;
  53 }
  54
  55 bool __weak cpu_crashlog_support(void)
  56 {
  57         return false;
  58 }
  59
  60 bool __weak pmc_crashlog_support(void)
  61 {
  62         return false;
  63 }
  64
  65 bool __weak cl_cpu_data_present(void)
  66 {
  67         return false;
  68 }
  69
  70 bool __weak cl_pmc_data_present(void)
  71 {
  72         return false;
  73 }
  74
  75 bool __weak cl_ioe_data_present(void)
  76 {
  77         return false;
  78 }
  79
  80 __weak void reset_discovery_buffers(void) {}
  81
  82 __weak void update_new_pmc_crashlog_size(u32 *pmc_crash_size) {}
  83
  84 __weak void update_new_cpu_crashlog_size(u32 *cpu_crash_size) {}
  85
  86 __weak void update_new_ioe_crashlog_size(u32 *ioe_crash_size) {}
  87
  88 pmc_ipc_discovery_buf_t __weak cl_get_pmc_discovery_buf(void)
  89 {
  90         pmc_ipc_discovery_buf_t discov_buf;
  91         memset(&discov_buf, 0, sizeof(pmc_ipc_discovery_buf_t));
  92         return discov_buf;
  93 }
  94
  95 pmc_crashlog_desc_table_t __weak cl_get_pmc_descriptor_table(void)
  96 {
  97         pmc_crashlog_desc_table_t desc_tab;
  98         memset(&desc_tab, 0, sizeof(pmc_crashlog_desc_table_t));
  99         return desc_tab;
 100 }
 101
 102 cpu_crashlog_discovery_table_t __weak cl_get_cpu_discovery_table(void)
 103 {
 104         cpu_crashlog_discovery_table_t cpu_disc_tab;
 105         memset(&cpu_disc_tab, 0, sizeof(cpu_crashlog_discovery_table_t));
 106         return cpu_disc_tab;
 107 }
 108
 109 int cpu_cl_poll_mailbox_ready(uintptr_t cl_mailbox_addr)
 110 {
 111         cpu_crashlog_mailbox_t cl_mailbox_interface;
 112         u16 stall_cnt = 0;
 113
 114         do {
 115                 cl_mailbox_interface.data = read32p(cl_mailbox_addr);
 116                 udelay(CPU_CRASHLOG_WAIT_STALL);
 117                 stall_cnt++;
 118         } while ((cl_mailbox_interface.fields.busy == 1)
 119                  && stall_cnt < CPU_CRASHLOG_WAIT_TIMEOUT);
 120
 121         if ((cl_mailbox_interface.fields.busy == 1)
 122             && (stall_cnt >= CPU_CRASHLOG_WAIT_TIMEOUT)) {
 123                 printk(BIOS_ERR, "CPU crashlog mailbox timed out.\n");
 124                 return 0;
 125         }
 126
 127         return 1;
 128 }
 129
 130 int cpu_cl_mailbox_cmd(u8 cmd, u8 param)
 131 {
 132         cpu_crashlog_mailbox_t cl_mailbox_intf;
 133         uintptr_t cl_base_addr;
 134
 135         memset(&cl_mailbox_intf, 0, sizeof(cpu_crashlog_mailbox_t));
 136
 137         cl_base_addr = cl_get_cpu_bar_addr();
 138
 139         cl_mailbox_intf.fields.command = cmd;
 140         cl_mailbox_intf.fields.param = param;
 141         cl_mailbox_intf.fields.busy = 1;
 142
 143         write32p((cl_base_addr + cl_get_cpu_mb_int_addr()),
 144                 cl_mailbox_intf.data);
 145
 146         cpu_cl_poll_mailbox_ready(cl_base_addr + cl_get_cpu_mb_int_addr());
 147
 148         return 1;
 149 }
 150
 151 int __weak cpu_cl_clear_data(void)
 152 {
 153         return cpu_cl_mailbox_cmd(CPU_CRASHLOG_CMD_CLEAR, 0);
 154 }
 155
 156 void __weak cpu_cl_rearm(void)
 157 {
 158         /* empty implementation */
 159 }
 160
 161 void __weak cpu_cl_cleanup(void)
 162 {
 163         /* empty implementation */
 164 }
 165
 166 int pmc_cl_gen_descriptor_table(uintptr_t desc_table_addr,
 167                                 pmc_crashlog_desc_table_t *descriptor_table)
 168 {
 169         int total_data_size = 0;
 170         descriptor_table->numb_regions = read32p(desc_table_addr);
 171         printk(BIOS_DEBUG, "CL PMC desc table: numb of regions is 0x%x at addr 0x%lx\n",
 172                descriptor_table->numb_regions, desc_table_addr);
 173         for (int i = 0; i < descriptor_table->numb_regions; i++) {
 174                 if (i >= ARRAY_SIZE(descriptor_table->regions)) {
 175                         printk(BIOS_ERR, "Maximum number of PMC crashLog descriptor table exceeded (%u/%zu)\n",
 176                         descriptor_table->numb_regions,
 177                         ARRAY_SIZE(descriptor_table->regions));
 178                         break;
 179                 }
 180                 desc_table_addr += sizeof(u32);
 181                 descriptor_table->regions[i].data = read32p(desc_table_addr);
 182                 total_data_size += descriptor_table->regions[i].bits.size * sizeof(u32);
 183                 printk(BIOS_DEBUG, "CL PMC desc table: region 0x%x has size 0x%x at offset 0x%x\n",
 184                         i, descriptor_table->regions[i].bits.size,
 185                         descriptor_table->regions[i].bits.offset);
 186         }
 187         return total_data_size;
 188 }
 189
 190 bool __weak pmc_cl_discovery(void)
 191 {
 192         return false;
 193 }
 194
 195 bool __weak cpu_cl_discovery(void)
 196 {
 197         return false;
 198 }
 199
 200 int cl_pmc_re_arm_after_reset(void)
 201 {
 202         const struct pmc_ipc_buffer req = { 0 };
 203         struct pmc_ipc_buffer res;
 204         uint32_t cmd_reg;
 205         int r;
 206
 207         cmd_reg = pmc_make_ipc_cmd(PMC_IPC_CMD_CRASHLOG,
 208                                 PMC_IPC_CMD_ID_CRASHLOG_RE_ARM_ON_RESET,
 209                                 PMC_IPC_CMD_SIZE_SHIFT);
 210
 211         r = pmc_send_ipc_cmd(cmd_reg, &req, &res);
 212
 213         if (r < 0) {
 214                 printk(BIOS_ERR, "pmc_send_ipc_cmd failed in %s\n", __func__);
 215                 return 0;
 216         }
 217
 218         return r;
 219 }
 220
 221 /* Sends PMC IPC to clear CrashLog from PMC SSRAM area */
 222 int cl_pmc_clear(void)
 223 {
 224         const struct pmc_ipc_buffer req = { 0 };
 225         struct pmc_ipc_buffer res;
 226         uint32_t cmd_reg;
 227         int r;
 228
 229         cmd_reg = pmc_make_ipc_cmd(PMC_IPC_CMD_CRASHLOG,
 230                                 PMC_IPC_CMD_ID_CRASHLOG_ERASE,
 231                                 PMC_IPC_CMD_SIZE_SHIFT);
 232
 233         r = pmc_send_ipc_cmd(cmd_reg, &req, &res);
 234
 235         if (r < 0) {
 236                 printk(BIOS_ERR, "pmc_send_ipc_cmd failed in %s\n", __func__);
 237                 return 0;
 238         }
 239
 240         return r;
 241 }
 242
 243 /*
 244  * Sends PMC IPC to populate CrashLog on all reboot.
 245  * The SSRAM area will be cleared on G3 by PMC automatically
 246  */
 247 int cl_pmc_en_gen_on_all_reboot(void)
 248 {
 249         const struct pmc_ipc_buffer req = { 0 };
 250         struct pmc_ipc_buffer res;
 251         uint32_t cmd_reg;
 252         int r;
 253
 254         cmd_reg = pmc_make_ipc_cmd(PMC_IPC_CMD_CRASHLOG,
 255                                 PMC_IPC_CMD_ID_CRASHLOG_ON_RESET,
 256                                 PMC_IPC_CMD_SIZE_SHIFT);
 257
 258         r = pmc_send_ipc_cmd(cmd_reg, &req, &res);
 259
 260         if (r < 0) {
 261                 printk(BIOS_ERR, "pmc_send_ipc_cmd failed in %s\n", __func__);
 262                 return 0;
 263         }
 264
 265         return r;
 266 }
 267
 268 bool discover_crashlog(void)
 269 {
 270         bool cpu_cl_discovered = false, pmc_cl_discovered = false;
 271
 272         reset_discovery_buffers();
 273
 274         /* PCH crashLog discovery */
 275         pmc_cl_discovered = pmc_cl_discovery();
 276
 277         /* CPU crashLog discovery */
 278         cpu_cl_discovered = cpu_cl_discovery();
 279
 280         return (cpu_cl_discovered || pmc_cl_discovered);
 281 }
 282
 283 bool cl_copy_data_from_sram(uintptr_t src_bar, u32 offset, size_t size, u32 *dest_addr,
 284                                                         u32 buffer_index, bool pmc_sram)
 285 {
 286         if (src_bar == 0) {
 287                 printk(BIOS_ERR, "Invalid bar 0x%lx and offset 0x%x for %s\n",
 288                        src_bar, offset, __func__);
 289                 return false;
 290         }
 291
 292         uintptr_t src_addr = src_bar + offset;
 293
 294         u32 data =  read32p(src_addr);
 295
 296         /* First 32bits of the record must not be 0xdeadbeef */
 297         if (data == INVALID_CRASHLOG_RECORD) {
 298                 printk(BIOS_DEBUG, "Invalid data 0x%x at offset 0x%x from addr 0x%lx\n",
 299                                 data, offset, src_bar);
 300                 return false;
 301         }
 302
 303         /* PMC: copy if 1st DWORD in buffer is not zero and its 31st bit is not set */
 304         if (pmc_sram && !(data && !(data & BIT(31)))) {
 305                 printk(BIOS_DEBUG, "Invalid data 0x%x at offset 0x%x from addr 0x%lx"
 306                         " of PMC SRAM.\n", data, offset, src_bar);
 307                 return false;
 308         }
 309         /*CPU: don't copy if 1st DWORD in first buffer is zero */
 310         if (!pmc_sram && !data && (buffer_index == 0)) {
 311                 printk(BIOS_DEBUG, "Invalid data 0x%x at offset 0x%x from addr 0x%lx"
 312                         " of telemetry SRAM.\n", data, offset, src_bar);
 313                 return false;
 314         }
 315
 316         size_t copied = 0;
 317         while (copied < size) {
 318                 /* DW by DW copy: byte access to PMC SRAM not allowed */
 319                 *dest_addr = read32p(src_addr);
 320                 dest_addr++;
 321                 src_addr += sizeof(u32);
 322                 copied++;
 323         }
 324         return true;
 325 }
 326
 327 cl_node_t *malloc_cl_node(size_t len)
 328 {
 329         cl_node_t *node = malloc(sizeof(cl_node_t));
 330         if (!node)
 331                 return NULL;
 332
 333         node->data = malloc(len * sizeof(u32));
 334         if (!(node->data))
 335                 return NULL;
 336
 337         node->size = len * sizeof(u32);
 338         node->next = NULL;
 339
 340         return node;
 341 }
 342
 343 void free_cl_node(cl_node_t *node)
 344 {
 345         if (!node)
 346                 return;
 347         if (node->data)
 348                 free(node->data);
 349         free(node);
 350 }
 351
 352 void __weak cl_get_pmc_sram_data(cl_node_t *head)
 353 {
 354         uintptr_t tmp_bar_addr = cl_get_cpu_tmp_bar();
 355         u32 pmc_crashLog_size = cl_get_pmc_record_size();
 356         cl_node_t *cl_cur = head;
 357
 358         if (!cl_pmc_sram_has_mmio_access() || !tmp_bar_addr)
 359                 return;
 360
 361         pmc_ipc_discovery_buf_t discovery_buf = cl_get_pmc_discovery_buf();
 362
 363         if (discovery_buf.bits.supported != 1) {
 364                 printk(BIOS_DEBUG, "PCH crashlog feature not supported.\n");
 365                 goto pmc_send_re_arm_after_reset;
 366         }
 367
 368         /* Get the size of data to copy */
 369         if (discovery_buf.bits.discov_mechanism == 1) {
 370                 if (discovery_buf.bits.base_offset & BIT(31)) {
 371                         printk(BIOS_DEBUG, "PCH discovery to be used is disabled.\n");
 372                         goto pmc_send_re_arm_after_reset;
 373                 }
 374                 printk(BIOS_DEBUG, "PMC crashLog size in discovery mode : 0x%X\n",
 375                                 pmc_crashLog_size);
 376         } else {
 377                 if (discovery_buf.bits.dis) {
 378                         printk(BIOS_DEBUG, "PCH crashlog is disabled in legacy mode.\n");
 379                         return;
 380                 }
 381                 pmc_crashLog_size = (discovery_buf.bits.size != 0) ?
 382                                         discovery_buf.bits.size * sizeof(u32) : 0xC00;
 383                 printk(BIOS_DEBUG, "PMC crashLog size in legacy mode : 0x%X\n",
 384                                 pmc_crashLog_size);
 385         }
 386
 387         bool pmc_sram = true;
 388         pmc_crashlog_desc_table_t descriptor_table = cl_get_pmc_descriptor_table();
 389
 390         /* goto tail node */
 391         while (cl_cur && cl_cur->next) {
 392                 cl_cur = cl_cur->next;
 393         }
 394
 395         if (discovery_buf.bits.discov_mechanism == 1) {
 396                 for (int i = 0; i < descriptor_table.numb_regions; i++) {
 397                         cl_node_t *cl_node = malloc_cl_node(descriptor_table.regions[i].bits.size);
 398                         if (!cl_node) {
 399                                 printk(BIOS_DEBUG, "failed to allocate cl_node [region = %d]\n", i);
 400                                 goto pmc_send_re_arm_after_reset;
 401                         }
 402
 403                         if (cl_copy_data_from_sram(tmp_bar_addr,
 404                                                 descriptor_table.regions[i].bits.offset,
 405                                                 descriptor_table.regions[i].bits.size,
 406                                                 cl_node->data,
 407                                                 i,
 408                                                 pmc_sram)) {
 409                                 cl_cur->next = cl_node;
 410                                 cl_cur = cl_cur->next;
 411                         } else {
 412                                 pmc_crashLog_size -= descriptor_table.regions[i].bits.size *
 413                                                         sizeof(u32);
 414                                 printk(BIOS_DEBUG, "discover mode PMC crashlog size adjusted"
 415                                                 " to: 0x%x\n", pmc_crashLog_size);
 416                                 /* free cl_node */
 417                                 free_cl_node(cl_node);
 418                         }
 419                 }
 420         } else {
 421                 cl_node_t *cl_node = malloc_cl_node(discovery_buf.bits.size);
 422                 if (!cl_node) {
 423                         printk(BIOS_DEBUG, "failed to allocate cl_node\n");
 424                         goto pmc_send_re_arm_after_reset;
 425                 }
 426
 427                 if (cl_copy_data_from_sram(tmp_bar_addr,
 428                                         discovery_buf.bits.base_offset,
 429                                         discovery_buf.bits.size,
 430                                         cl_node->data,
 431                                         0,
 432                                         pmc_sram)) {
 433                         cl_cur->next = cl_node;
 434                         cl_cur = cl_cur->next;
 435                 } else {
 436                         pmc_crashLog_size -= discovery_buf.bits.size * sizeof(u32);
 437                         printk(BIOS_DEBUG, "legacy mode PMC crashlog size adjusted to: 0x%x\n",
 438                                         pmc_crashLog_size);
 439                         /* free cl_node */
 440                         free_cl_node(cl_node);
 441                 }
 442         }
 443
 444         update_new_pmc_crashlog_size(&pmc_crashLog_size);
 445
 446 pmc_send_re_arm_after_reset:
 447         /* when bit 7 of discov cmd resp is set -> bit 2 of size field */
 448         if (discovery_buf.bits.size & BIT(2))
 449                 cl_pmc_re_arm_after_reset();
 450
 451         /* Clear the SSRAM region after copying the error log */
 452         cl_pmc_clear();
 453 }
 454
 455 void cl_get_cpu_sram_data(cl_node_t *head)
 456 {
 457         cl_node_t *cl_cur = head;
 458         u32 m_cpu_crashLog_size = cl_get_cpu_record_size();
 459         cpu_crashlog_discovery_table_t cpu_cl_disc_tab = cl_get_cpu_discovery_table();
 460
 461         if (m_cpu_crashLog_size < 1) {
 462                 printk(BIOS_DEBUG, "%s: no data to collect.\n", __func__);
 463                 return;
 464         }
 465
 466         printk(BIOS_DEBUG, "CPU crash data size: 0x%X bytes in 0x%X region(s).\n",
 467                         m_cpu_crashLog_size, cpu_cl_disc_tab.header.fields.count);
 468
 469         /* goto tail node */
 470         while (cl_cur && cl_cur->next) {
 471                 cl_cur = cl_cur->next;
 472         }
 473
 474         for (int i = 0 ; i < cpu_cl_disc_tab.header.fields.count ; i++) {
 475                 uintptr_t cpu_bar_addr = cl_get_cpu_bar_addr();
 476                 bool pmc_sram = false;
 477                 if (!cpu_cl_disc_tab.buffers[i].fields.size) {
 478                         continue;
 479                 }
 480
 481                 cl_node_t *cl_node = malloc_cl_node(cpu_cl_disc_tab.buffers[i].fields.size);
 482                 if (!cl_node) {
 483                         printk(BIOS_DEBUG, "failed to allocate cl_node [buffer = %d]\n", i);
 484                         return;
 485                 }
 486
 487                 if (cl_copy_data_from_sram(cpu_bar_addr,
 488                                         cpu_cl_disc_tab.buffers[i].fields.offset,
 489                                         cpu_cl_disc_tab.buffers[i].fields.size,
 490                                         cl_node->data,
 491                                         i,
 492                                         pmc_sram)) {
 493                         cl_cur->next = cl_node;
 494                         cl_cur = cl_cur->next;
 495
 496                 } else {
 497                         m_cpu_crashLog_size -= cpu_cl_disc_tab.buffers[i].fields.size
 498                                 * sizeof(u32);
 499                         free_cl_node(cl_node);
 500                         /* for CPU skip all buffers if the 1st one is not valid */
 501                         if (i == 0) {
 502                                 m_cpu_crashLog_size = 0;
 503                                 break;
 504                         }
 505                 }
 506         }
 507
 508         update_new_cpu_crashlog_size(&m_cpu_crashLog_size);
 509
 510         /* clear telemetry SRAM region */
 511         cpu_cl_clear_data();
 512         /* perform any SOC specific cleanup */
 513         cpu_cl_cleanup();
 514         /* rearm crashlog */
 515         cpu_cl_rearm();
 516 }
 517
 518 void collect_pmc_and_cpu_crashlog_from_srams(cl_node_t *head)
 519 {
 520         if (pmc_crashlog_support() && cl_pmc_data_present()
 521                 && (cl_get_pmc_record_size() > 0)) {
 522                 if (CONFIG(SOC_INTEL_CRASHLOG_ON_RESET)) {
 523                         cl_pmc_en_gen_on_all_reboot();
 524                         printk(BIOS_DEBUG, "Crashlog collection enabled on every reboot.\n");
 525                 }
 526                 cl_get_pmc_sram_data(head);
 527         } else {
 528                 printk(BIOS_DEBUG, "Skipping PMC crashLog collection. Data not present.\n");
 529         }
 530
 531         printk(BIOS_DEBUG, "m_cpu_crashLog_size : 0x%X bytes\n", cl_get_cpu_record_size());
 532
 533         if (cpu_crashlog_support() && cl_cpu_data_present()
 534                 && (cl_get_cpu_record_size() > 0)) {
 535                 printk(BIOS_DEBUG, "CPU crashLog present.\n");
 536                 cl_get_cpu_sram_data(head);
 537         } else {
 538                 printk(BIOS_DEBUG, "Skipping CPU crashLog collection. Data not present.\n");
 539         }
 540 }