src/soc/intel/common/block/lpc/lpc.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <device/device.h>
   4 #include <device/pci.h>
   5 #include <device/pci_ids.h>
   6 #include <intelblocks/lpc_lib.h>
   7 #include <soc/pm.h>
   8
   9 #include "lpc_def.h"
  10
  11 /* SoC overrides */
  12
  13 /* Common weak definition, needs to be implemented in each soc LPC driver. */
  14 __weak void lpc_soc_init(struct device *dev)
  15 {
  16         /* no-op */
  17 }
  18
  19 /* Fill up LPC IO resource structure inside SoC directory */
  20 __weak void pch_lpc_soc_fill_io_resources(struct device *dev)
  21 {
  22         /* no-op */
  23 }
  24
  25 void pch_lpc_add_new_resource(struct device *dev, uint8_t offset,
  26         uintptr_t base, size_t size, unsigned long flags)
  27 {
  28         struct resource *res;
  29         res = new_resource(dev, offset);
  30         res->base = base;
  31         res->size = size;
  32         res->flags = flags;
  33 }
  34
  35 static void pch_lpc_add_io_resources(struct device *dev)
  36 {
  37         uint32_t gen_io_dec;
  38         uint16_t base, size;
  39
  40         /* Add the default claimed legacy IO range for the LPC device. */
  41         pch_lpc_add_new_resource(dev, 0, 0, 0x1000, IORESOURCE_IO |
  42                         IORESOURCE_ASSIGNED | IORESOURCE_FIXED);
  43
  44         /* LPC Generic IO Decode ranges */
  45         for (size_t i = 0; i < LPC_NUM_GENERIC_IO_RANGES; i++) {
  46                 gen_io_dec = pci_read_config32(dev, LPC_GENERIC_IO_RANGE(i));
  47                 if (gen_io_dec & LPC_LGIR_EN) {
  48                         base = gen_io_dec & LPC_LGIR_ADDR_MASK;
  49                         size = (0x3 | ((gen_io_dec >> 16) & 0xfc)) + 1;
  50                         pch_lpc_add_new_resource(dev, LPC_GENERIC_IO_RANGE(i), base, size,
  51                                                  IORESOURCE_IO | IORESOURCE_ASSIGNED |
  52                                                  IORESOURCE_FIXED);
  53                 }
  54         }
  55
  56         /* SoC IO resource overrides */
  57         pch_lpc_soc_fill_io_resources(dev);
  58 }
  59
  60 static void pch_lpc_add_mmio_resources(struct device *dev)
  61 {
  62         /* LPC Memory Decode */
  63         uint32_t lgmr = pci_read_config32(dev, LPC_GENERIC_MEM_RANGE);
  64         if (lgmr & LPC_LGMR_EN) {
  65                 lgmr &= LPC_LGMR_ADDR_MASK;
  66                 pch_lpc_add_new_resource(dev, LPC_GENERIC_MEM_RANGE, lgmr, LPC_LGMR_WINDOW_SIZE,
  67                                          IORESOURCE_MEM | IORESOURCE_ASSIGNED |
  68                                          IORESOURCE_FIXED | IORESOURCE_RESERVE);
  69         }
  70 }
  71
  72 static void pch_lpc_read_resources(struct device *dev)
  73 {
  74         /* Get the PCI resources of this device. */
  75         pci_dev_read_resources(dev);
  76
  77         /* Add IO resources to LPC. */
  78         pch_lpc_add_io_resources(dev);
  79
  80         /* Add non-standard MMIO resources. */
  81         pch_lpc_add_mmio_resources(dev);
  82 }
  83
  84 static void pch_lpc_set_child_resources(struct device *dev);
  85
  86 static void pch_lpc_loop_resources(struct device *dev)
  87 {
  88         struct resource *res;
  89
  90         if (!dev->enabled)
  91                 return;
  92
  93         for (res = dev->resource_list; res; res = res->next) {
  94                 if ((res->flags & IORESOURCE_IO) && (res->flags & IORESOURCE_ASSIGNED))
  95                         lpc_open_pmio_window(res->base, res->size);
  96         }
  97         pch_lpc_set_child_resources(dev);
  98 }
  99
 100 /*
 101  * Loop through all the child devices' resources, and open up windows to the
 102  * LPC bus, as appropriate.
 103  */
 104 static void pch_lpc_set_child_resources(struct device *dev)
 105 {
 106         struct device *child;
 107
 108         if (!dev->downstream)
 109                 return;
 110
 111         for (child = dev->downstream->children; child; child = child->sibling)
 112                 pch_lpc_loop_resources(child);
 113 }
 114
 115 static void pch_lpc_set_resources(struct device *dev)
 116 {
 117         pci_dev_set_resources(dev);
 118
 119         /* Now open up windows to devices which have declared resources. */
 120         pch_lpc_set_child_resources(dev);
 121 }
 122
 123 #if CONFIG(HAVE_ACPI_TABLES)
 124 static const char *lpc_acpi_name(const struct device *dev)
 125 {
 126         return "LPCB";
 127 }
 128 #endif
 129
 130 struct device_operations lpc_ops = {
 131         .read_resources         = pch_lpc_read_resources,
 132         .set_resources          = pch_lpc_set_resources,
 133         .enable_resources       = pci_dev_enable_resources,
 134 #if CONFIG(HAVE_ACPI_TABLES)
 135         .write_acpi_tables      = southbridge_write_acpi_tables,
 136         .acpi_name              = lpc_acpi_name,
 137 #endif
 138         .init                   = lpc_soc_init,
 139         .scan_bus               = scan_static_bus,
 140         .ops_pci                = &pci_dev_ops_pci,
 141 };
 142
 143 static const unsigned short pci_device_ids[] = {
 144         PCI_DID_INTEL_PTL_U_H_ESPI_0,
 145         PCI_DID_INTEL_PTL_U_H_ESPI_1,
 146         PCI_DID_INTEL_PTL_U_H_ESPI_2,
 147         PCI_DID_INTEL_PTL_U_H_ESPI_3,
 148         PCI_DID_INTEL_PTL_U_H_ESPI_4,
 149         PCI_DID_INTEL_PTL_U_H_ESPI_5,
 150         PCI_DID_INTEL_PTL_U_H_ESPI_6,
 151         PCI_DID_INTEL_PTL_U_H_ESPI_7,
 152         PCI_DID_INTEL_PTL_U_H_ESPI_8,
 153         PCI_DID_INTEL_PTL_U_H_ESPI_9,
 154         PCI_DID_INTEL_PTL_U_H_ESPI_10,
 155         PCI_DID_INTEL_PTL_U_H_ESPI_11,
 156         PCI_DID_INTEL_PTL_U_H_ESPI_12,
 157         PCI_DID_INTEL_PTL_U_H_ESPI_13,
 158         PCI_DID_INTEL_PTL_U_H_ESPI_14,
 159         PCI_DID_INTEL_PTL_U_H_ESPI_15,
 160         PCI_DID_INTEL_PTL_U_H_ESPI_16,
 161         PCI_DID_INTEL_PTL_U_H_ESPI_17,
 162         PCI_DID_INTEL_PTL_U_H_ESPI_18,
 163         PCI_DID_INTEL_PTL_U_H_ESPI_19,
 164         PCI_DID_INTEL_PTL_U_H_ESPI_20,
 165         PCI_DID_INTEL_PTL_U_H_ESPI_21,
 166         PCI_DID_INTEL_PTL_U_H_ESPI_22,
 167         PCI_DID_INTEL_PTL_U_H_ESPI_23,
 168         PCI_DID_INTEL_PTL_U_H_ESPI_24,
 169         PCI_DID_INTEL_PTL_U_H_ESPI_25,
 170         PCI_DID_INTEL_PTL_U_H_ESPI_26,
 171         PCI_DID_INTEL_PTL_U_H_ESPI_27,
 172         PCI_DID_INTEL_PTL_U_H_ESPI_28,
 173         PCI_DID_INTEL_PTL_U_H_ESPI_29,
 174         PCI_DID_INTEL_PTL_U_H_ESPI_30,
 175         PCI_DID_INTEL_PTL_U_H_ESPI_31,
 176         PCI_DID_INTEL_PTL_H_ESPI_0,
 177         PCI_DID_INTEL_PTL_H_ESPI_1,
 178         PCI_DID_INTEL_PTL_H_ESPI_2,
 179         PCI_DID_INTEL_PTL_H_ESPI_3,
 180         PCI_DID_INTEL_PTL_H_ESPI_4,
 181         PCI_DID_INTEL_PTL_H_ESPI_5,
 182         PCI_DID_INTEL_PTL_H_ESPI_6,
 183         PCI_DID_INTEL_PTL_H_ESPI_7,
 184         PCI_DID_INTEL_PTL_H_ESPI_8,
 185         PCI_DID_INTEL_PTL_H_ESPI_9,
 186         PCI_DID_INTEL_PTL_H_ESPI_10,
 187         PCI_DID_INTEL_PTL_H_ESPI_11,
 188         PCI_DID_INTEL_PTL_H_ESPI_12,
 189         PCI_DID_INTEL_PTL_H_ESPI_13,
 190         PCI_DID_INTEL_PTL_H_ESPI_14,
 191         PCI_DID_INTEL_PTL_H_ESPI_15,
 192         PCI_DID_INTEL_PTL_H_ESPI_16,
 193         PCI_DID_INTEL_PTL_H_ESPI_17,
 194         PCI_DID_INTEL_PTL_H_ESPI_18,
 195         PCI_DID_INTEL_PTL_H_ESPI_19,
 196         PCI_DID_INTEL_PTL_H_ESPI_20,
 197         PCI_DID_INTEL_PTL_H_ESPI_21,
 198         PCI_DID_INTEL_PTL_H_ESPI_22,
 199         PCI_DID_INTEL_PTL_H_ESPI_23,
 200         PCI_DID_INTEL_PTL_H_ESPI_24,
 201         PCI_DID_INTEL_PTL_H_ESPI_25,
 202         PCI_DID_INTEL_PTL_H_ESPI_26,
 203         PCI_DID_INTEL_PTL_H_ESPI_27,
 204         PCI_DID_INTEL_PTL_H_ESPI_28,
 205         PCI_DID_INTEL_PTL_H_ESPI_29,
 206         PCI_DID_INTEL_PTL_H_ESPI_30,
 207         PCI_DID_INTEL_PTL_H_ESPI_31,
 208         PCI_DID_INTEL_LNL_ESPI_0,
 209         PCI_DID_INTEL_LNL_ESPI_1,
 210         PCI_DID_INTEL_LNL_ESPI_2,
 211         PCI_DID_INTEL_LNL_ESPI_3,
 212         PCI_DID_INTEL_LNL_ESPI_4,
 213         PCI_DID_INTEL_LNL_ESPI_5,
 214         PCI_DID_INTEL_LNL_ESPI_6,
 215         PCI_DID_INTEL_LNL_ESPI_7,
 216         PCI_DID_INTEL_MTL_ESPI_0,
 217         PCI_DID_INTEL_MTL_ESPI_1,
 218         PCI_DID_INTEL_MTL_ESPI_2,
 219         PCI_DID_INTEL_MTL_ESPI_3,
 220         PCI_DID_INTEL_MTL_ESPI_4,
 221         PCI_DID_INTEL_MTL_ESPI_5,
 222         PCI_DID_INTEL_MTL_ESPI_6,
 223         PCI_DID_INTEL_MTL_ESPI_7,
 224         PCI_DID_INTEL_RPP_P_ESPI_0,
 225         PCI_DID_INTEL_RPP_P_ADP_P_ESPI_1,
 226         PCI_DID_INTEL_RPP_P_ADP_P_ESPI_2,
 227         PCI_DID_INTEL_RPP_P_ESPI_3,
 228         PCI_DID_INTEL_RPP_P_ESPI_4,
 229         PCI_DID_INTEL_RPP_P_ESPI_5,
 230         PCI_DID_INTEL_RPP_P_ADP_M_ESPI_6,
 231         PCI_DID_INTEL_RPP_P_ESPI_7,
 232         PCI_DID_INTEL_RPP_P_ESPI_8,
 233         PCI_DID_INTEL_RPP_P_ESPI_9,
 234         PCI_DID_INTEL_RPP_P_ESPI_10,
 235         PCI_DID_INTEL_RPP_P_ESPI_11,
 236         PCI_DID_INTEL_RPP_P_ESPI_12,
 237         PCI_DID_INTEL_RPP_P_ESPI_13,
 238         PCI_DID_INTEL_RPP_P_ESPI_14,
 239         PCI_DID_INTEL_RPP_P_ESPI_15,
 240         PCI_DID_INTEL_RPP_P_ESPI_16,
 241         PCI_DID_INTEL_RPP_P_ESPI_17,
 242         PCI_DID_INTEL_RPP_P_ESPI_18,
 243         PCI_DID_INTEL_RPP_P_ESPI_19,
 244         PCI_DID_INTEL_RPP_P_ESPI_20,
 245         PCI_DID_INTEL_RPP_P_ESPI_21,
 246         PCI_DID_INTEL_RPP_P_ESPI_22,
 247         PCI_DID_INTEL_RPP_P_ESPI_23,
 248         PCI_DID_INTEL_RPP_P_ESPI_24,
 249         PCI_DID_INTEL_RPP_P_ESPI_25,
 250         PCI_DID_INTEL_RPP_P_ESPI_26,
 251         PCI_DID_INTEL_RPP_P_ESPI_27,
 252         PCI_DID_INTEL_RPP_P_ESPI_28,
 253         PCI_DID_INTEL_RPP_P_ESPI_29,
 254         PCI_DID_INTEL_RPP_P_ESPI_30,
 255         PCI_DID_INTEL_RPP_P_ESPI_31,
 256         PCI_DID_INTEL_RPP_S_ESPI_0,
 257         PCI_DID_INTEL_RPP_S_ESPI_1,
 258         PCI_DID_INTEL_RPP_S_ESPI_2,
 259         PCI_DID_INTEL_RPP_S_ESPI_3,
 260         PCI_DID_INTEL_RPP_S_ESPI_Z790,
 261         PCI_DID_INTEL_RPP_S_ESPI_H770,
 262         PCI_DID_INTEL_RPP_S_ESPI_B760,
 263         PCI_DID_INTEL_RPP_S_ESPI_7,
 264         PCI_DID_INTEL_RPP_S_ESPI_8,
 265         PCI_DID_INTEL_RPP_S_ESPI_9,
 266         PCI_DID_INTEL_RPP_S_ESPI_10,
 267         PCI_DID_INTEL_RPP_S_ESPI_11,
 268         PCI_DID_INTEL_RPP_S_ESPI_HM770,
 269         PCI_DID_INTEL_RPP_S_ESPI_WM790,
 270         PCI_DID_INTEL_RPP_S_ESPI_14,
 271         PCI_DID_INTEL_RPP_S_ESPI_15,
 272         PCI_DID_INTEL_RPP_S_ESPI_16,
 273         PCI_DID_INTEL_RPP_S_ESPI_17,
 274         PCI_DID_INTEL_RPP_S_ESPI_18,
 275         PCI_DID_INTEL_RPP_S_ESPI_19,
 276         PCI_DID_INTEL_RPP_S_ESPI_20,
 277         PCI_DID_INTEL_RPP_S_ESPI_21,
 278         PCI_DID_INTEL_RPP_S_ESPI_22,
 279         PCI_DID_INTEL_RPP_S_ESPI_23,
 280         PCI_DID_INTEL_RPP_S_ESPI_24,
 281         PCI_DID_INTEL_RPP_S_ESPI_25,
 282         PCI_DID_INTEL_RPP_S_ESPI_26,
 283         PCI_DID_INTEL_RPP_S_ESPI_27,
 284         PCI_DID_INTEL_RPP_S_ESPI_28,
 285         PCI_DID_INTEL_RPP_S_ESPI_29,
 286         PCI_DID_INTEL_RPP_S_ESPI_30,
 287         PCI_DID_INTEL_RPP_S_ESPI_31,
 288         PCI_DID_INTEL_LWB_C621,
 289         PCI_DID_INTEL_LWB_C622,
 290         PCI_DID_INTEL_LWB_C624,
 291         PCI_DID_INTEL_LWB_C625,
 292         PCI_DID_INTEL_LWB_C626,
 293         PCI_DID_INTEL_LWB_C627,
 294         PCI_DID_INTEL_LWB_C628,
 295         PCI_DID_INTEL_LWB_C629,
 296         PCI_DID_INTEL_LWB_C621A,
 297         PCI_DID_INTEL_LWB_C627A,
 298         PCI_DID_INTEL_LWB_C629A,
 299         PCI_DID_INTEL_LWB_C624_SUPER,
 300         PCI_DID_INTEL_LWB_C627_SUPER_1,
 301         PCI_DID_INTEL_LWB_C621_SUPER,
 302         PCI_DID_INTEL_LWB_C627_SUPER_2,
 303         PCI_DID_INTEL_LWB_C628_SUPER,
 304         PCI_DID_INTEL_LWB_C621A_SUPER,
 305         PCI_DID_INTEL_LWB_C627A_SUPER,
 306         PCI_DID_INTEL_LWB_C629A_SUPER,
 307         PCI_DID_INTEL_EMB_SUPER,
 308         PCI_DID_INTEL_APL_LPC,
 309         PCI_DID_INTEL_GLK_LPC,
 310         PCI_DID_INTEL_GLK_ESPI,
 311         PCI_DID_INTEL_CNL_BASE_U_LPC,
 312         PCI_DID_INTEL_CNL_U_PREMIUM_LPC,
 313         PCI_DID_INTEL_CNL_Y_PREMIUM_LPC,
 314         PCI_DID_INTEL_CNP_H_LPC_H310,
 315         PCI_DID_INTEL_CNP_H_LPC_H370,
 316         PCI_DID_INTEL_CNP_H_LPC_Z390,
 317         PCI_DID_INTEL_CNP_H_LPC_Q370,
 318         PCI_DID_INTEL_CNP_H_LPC_B360,
 319         PCI_DID_INTEL_CNP_H_LPC_C246,
 320         PCI_DID_INTEL_CNP_H_LPC_C242,
 321         PCI_DID_INTEL_CNP_H_LPC_QM370,
 322         PCI_DID_INTEL_CNP_H_LPC_HM370,
 323         PCI_DID_INTEL_CNP_H_LPC_CM246,
 324         PCI_DID_INTEL_CMP_SUPER_U_LPC,
 325         PCI_DID_INTEL_CMP_PREMIUM_Y_LPC,
 326         PCI_DID_INTEL_CMP_PREMIUM_U_LPC,
 327         PCI_DID_INTEL_CMP_BASE_U_LPC,
 328         PCI_DID_INTEL_CMP_SUPER_Y_LPC,
 329         PCI_DID_INTEL_CMP_H_LPC_HM470,
 330         PCI_DID_INTEL_CMP_H_LPC_WM490,
 331         PCI_DID_INTEL_CMP_H_LPC_QM480,
 332         PCI_DID_INTEL_CMP_H_LPC_W480,
 333         PCI_DID_INTEL_CMP_H_LPC_H470,
 334         PCI_DID_INTEL_CMP_H_LPC_Z490,
 335         PCI_DID_INTEL_CMP_H_LPC_Q470,
 336         PCI_DID_INTEL_TGP_ESPI_0,
 337         PCI_DID_INTEL_TGP_SUPER_U_ESPI,
 338         PCI_DID_INTEL_TGP_PREMIUM_U_ESPI,
 339         PCI_DID_INTEL_TGP_BASE_U_ESPI,
 340         PCI_DID_INTEL_TGP_ESPI_1,
 341         PCI_DID_INTEL_TGP_ESPI_2,
 342         PCI_DID_INTEL_TGP_SUPER_Y_ESPI,
 343         PCI_DID_INTEL_TGP_PREMIUM_Y_ESPI,
 344         PCI_DID_INTEL_TGP_ESPI_3,
 345         PCI_DID_INTEL_TGP_ESPI_4,
 346         PCI_DID_INTEL_TGP_ESPI_5,
 347         PCI_DID_INTEL_TGP_ESPI_6,
 348         PCI_DID_INTEL_TGP_ESPI_7,
 349         PCI_DID_INTEL_TGP_ESPI_8,
 350         PCI_DID_INTEL_TGP_ESPI_9,
 351         PCI_DID_INTEL_TGP_ESPI_10,
 352         PCI_DID_INTEL_TGP_ESPI_11,
 353         PCI_DID_INTEL_TGP_ESPI_12,
 354         PCI_DID_INTEL_TGP_ESPI_13,
 355         PCI_DID_INTEL_TGP_ESPI_14,
 356         PCI_DID_INTEL_TGP_ESPI_15,
 357         PCI_DID_INTEL_TGP_ESPI_16,
 358         PCI_DID_INTEL_TGP_ESPI_17,
 359         PCI_DID_INTEL_TGP_ESPI_18,
 360         PCI_DID_INTEL_TGP_ESPI_19,
 361         PCI_DID_INTEL_TGP_ESPI_20,
 362         PCI_DID_INTEL_TGP_ESPI_21,
 363         PCI_DID_INTEL_TGP_ESPI_22,
 364         PCI_DID_INTEL_TGP_ESPI_23,
 365         PCI_DID_INTEL_TGP_ESPI_24,
 366         PCI_DID_INTEL_TGP_ESPI_25,
 367         PCI_DID_INTEL_TGP_ESPI_26,
 368         PCI_DID_INTEL_TGP_H_ESPI_B560,
 369         PCI_DID_INTEL_TGP_H_ESPI_H510,
 370         PCI_DID_INTEL_TGP_H_ESPI_H570,
 371         PCI_DID_INTEL_TGP_H_ESPI_Q570,
 372         PCI_DID_INTEL_TGP_H_ESPI_W580,
 373         PCI_DID_INTEL_TGP_H_ESPI_Z590,
 374         PCI_DID_INTEL_TGP_H_ESPI_HM570,
 375         PCI_DID_INTEL_TGP_H_ESPI_QM580,
 376         PCI_DID_INTEL_TGP_H_ESPI_WM590,
 377         PCI_DID_INTEL_MCC_ESPI_0,
 378         PCI_DID_INTEL_MCC_ESPI_1,
 379         PCI_DID_INTEL_MCC_BASE_ESPI,
 380         PCI_DID_INTEL_MCC_PREMIUM_ESPI,
 381         PCI_DID_INTEL_MCC_SUPER_ESPI,
 382         PCI_DID_INTEL_MCC_ESPI_2,
 383         PCI_DID_INTEL_MCC_ESPI_3,
 384         PCI_DID_INTEL_MCC_ESPI_4,
 385         PCI_DID_INTEL_JSP_SUPER_ESPI,
 386         PCI_DID_INTEL_ADP_S_ESPI_WM690,
 387         PCI_DID_INTEL_ADP_S_ESPI_HM670,
 388         PCI_DID_INTEL_ADP_S_ESPI_W790,
 389         PCI_DID_INTEL_ADP_S_ESPI_W680,
 390         PCI_DID_INTEL_ADP_S_ESPI_H610,
 391         PCI_DID_INTEL_ADP_S_ESPI_B660,
 392         PCI_DID_INTEL_ADP_S_ESPI_H670,
 393         PCI_DID_INTEL_ADP_S_ESPI_Z690,
 394         PCI_DID_INTEL_ADP_S_ESPI_Q670,
 395         PCI_DID_INTEL_ADP_S_ESPI_0,
 396         PCI_DID_INTEL_ADP_S_ESPI_1,
 397         PCI_DID_INTEL_ADP_S_ESPI_2,
 398         PCI_DID_INTEL_ADP_S_ESPI_9,
 399         PCI_DID_INTEL_ADP_S_ESPI_11,
 400         PCI_DID_INTEL_ADP_S_ESPI_14,
 401         PCI_DID_INTEL_ADP_S_ESPI_15,
 402         PCI_DID_INTEL_ADP_S_ESPI_19,
 403         PCI_DID_INTEL_ADP_S_ESPI_20,
 404         PCI_DID_INTEL_ADP_S_ESPI_21,
 405         PCI_DID_INTEL_ADP_S_ESPI_22,
 406         PCI_DID_INTEL_ADP_S_ESPI_23,
 407         PCI_DID_INTEL_ADP_S_ESPI_24,
 408         PCI_DID_INTEL_ADP_S_ESPI_25,
 409         PCI_DID_INTEL_ADP_S_ESPI_26,
 410         PCI_DID_INTEL_ADP_S_ESPI_27,
 411         PCI_DID_INTEL_ADP_S_ESPI_28,
 412         PCI_DID_INTEL_ADP_S_ESPI_29,
 413         PCI_DID_INTEL_ADP_S_ESPI_30,
 414         PCI_DID_INTEL_ADP_S_ESPI_31,
 415         PCI_DID_INTEL_ADP_S_ESPI_H610E,
 416         PCI_DID_INTEL_ADP_S_ESPI_Q670E,
 417         PCI_DID_INTEL_ADP_S_ESPI_R680E,
 418         PCI_DID_INTEL_ADP_M_N_ESPI_0,
 419         PCI_DID_INTEL_ADP_M_N_ESPI_1,
 420         PCI_DID_INTEL_ADP_M_N_ESPI_2,
 421         PCI_DID_INTEL_ADP_M_N_ESPI_3,
 422         PCI_DID_INTEL_ADP_M_N_ESPI_4,
 423         PCI_DID_INTEL_ADP_M_N_ESPI_5,
 424         PCI_DID_INTEL_ADP_M_N_ESPI_7,
 425         PCI_DID_INTEL_ADP_M_N_ESPI_8,
 426         PCI_DID_INTEL_ADP_M_N_ESPI_9,
 427         PCI_DID_INTEL_ADP_M_N_ESPI_10,
 428         PCI_DID_INTEL_ADP_M_N_ESPI_11,
 429         PCI_DID_INTEL_ADP_M_N_ESPI_12,
 430         PCI_DID_INTEL_ADP_M_N_ESPI_13,
 431         PCI_DID_INTEL_ADP_M_N_ESPI_14,
 432         PCI_DID_INTEL_ADP_M_N_ESPI_15,
 433         PCI_DID_INTEL_ADP_M_N_ESPI_16,
 434         PCI_DID_INTEL_ADP_M_N_ESPI_17,
 435         PCI_DID_INTEL_ADP_M_N_ESPI_18,
 436         PCI_DID_INTEL_ADP_M_N_ESPI_19,
 437         PCI_DID_INTEL_ADP_M_N_ESPI_20,
 438         PCI_DID_INTEL_ADP_M_N_ESPI_21,
 439         PCI_DID_INTEL_ADP_M_N_ESPI_22,
 440         PCI_DID_INTEL_ADP_M_N_ESPI_23,
 441         PCI_DID_INTEL_ADP_M_N_ESPI_24,
 442         PCI_DID_INTEL_ADP_M_N_ESPI_25,
 443         PCI_DID_INTEL_ADP_M_N_ESPI_26,
 444         PCI_DID_INTEL_ADP_M_N_ESPI_27,
 445         PCI_DID_INTEL_ADP_M_N_ESPI_28,
 446         PCI_DID_INTEL_ADP_M_N_ESPI_29,
 447         PCI_DID_INTEL_ADP_M_N_ESPI_30,
 448         PCI_DID_INTEL_ADP_M_N_ESPI_31,
 449         PCI_DID_INTEL_SPR_ESPI_1,
 450         PCI_DID_INTEL_SNR_LPC,
 451         PCI_DID_INTEL_IBL_ESPI_0,
 452         0
 453 };
 454
 455 static const struct pci_driver pch_lpc __pci_driver = {
 456         .ops = &lpc_ops,
 457         .vendor = PCI_VID_INTEL,
 458         .devices = pci_device_ids,
 459 };