soc/intel/pantherlake: Remove soc_info.[hc] interface
[coreboot2.git] / src / soc / intel / common / block / xhci / elog.c
blob2f94ba6025062c6ea7712633783f7ecd1c05489f
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <device/mmio.h>
4 #include <device/pci_ops.h>
5 #include <device/xhci.h>
6 #include <elog.h>
7 #include <intelblocks/xhci.h>
8 #include <soc/pci_devs.h>
9 #include <stdint.h>
12 * Check if a particular USB port caused wake by:
13 * 1. Change in connect/disconnect status (if enabled)
14 * 2. USB device activity
16 * Params:
17 * base : MMIO address of first port.
18 * num : Number of ports.
19 * event : Event that needs to be added in case wake source is found.
21 * Return value:
22 * true : Wake source was found.
23 * false : Wake source was not found.
25 static bool xhci_port_wake_check(uintptr_t base, uint8_t num, uint8_t host_event, uint8_t event)
27 uint32_t i, port_status;
28 bool found = false;
30 for (i = 0; i < num; i++, base += 0x10) {
31 /* Read port status and control register for the port. */
32 port_status = read32p(base);
34 /* Ensure that the status is not all 1s. */
35 if (port_status == 0xffffffff)
36 continue;
39 * Check if CSC bit is set and port is capable of wake on
40 * connect/disconnect to identify if the port caused wake
41 * event for USB attach/detach.
43 if (xhci_portsc_csc(port_status) &&
44 xhci_portsc_wake_capable(port_status)) {
45 elog_add_event_wake(host_event, 0);
46 elog_add_event_wake(event, i + 1);
47 found = true;
48 continue;
52 * Check if PLC is set and PLS indicates resume to identify if
53 * the port caused wake event for USB activity.
55 if (xhci_portsc_plc(port_status) &&
56 xhci_portsc_resume(port_status)) {
57 elog_add_event_wake(host_event, 0);
58 elog_add_event_wake(event, i + 1);
59 found = true;
62 return found;
65 bool xhci_update_wake_event(const struct xhci_wake_info *wake_info,
66 size_t wake_info_count)
68 const struct xhci_usb_info *usb_info;
69 uintptr_t mmio_base;
70 bool event_found = false;
71 size_t i;
73 for (i = 0; i < wake_info_count; ++i) {
74 /* Assumes BAR0 is MBAR */
75 pci_devfn_t devfn = PCI_DEV(0, PCI_SLOT(wake_info[i].xhci_dev),
76 PCI_FUNC(wake_info[i].xhci_dev));
77 mmio_base = pci_s_read_config32(devfn, PCI_BASE_ADDRESS_0);
78 mmio_base &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
79 usb_info = soc_get_xhci_usb_info(wake_info[i].xhci_dev);
81 /* Check USB2 port status & control registers */
82 if (xhci_port_wake_check(mmio_base + usb_info->usb2_port_status_reg,
83 usb_info->num_usb2_ports,
84 wake_info[i].elog_wake_type_host,
85 ELOG_WAKE_SOURCE_PME_XHCI_USB_2))
86 event_found = true;
88 /* Check USB3 port status & control registers */
89 if (xhci_port_wake_check(mmio_base + usb_info->usb3_port_status_reg,
90 usb_info->num_usb3_ports,
91 wake_info[i].elog_wake_type_host,
92 ELOG_WAKE_SOURCE_PME_XHCI_USB_3))
93 event_found = true;
96 return event_found;