src/soc/intel/elkhartlake/chip.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/device.h>
   4 #include <device/pci.h>
   5 #include <fsp/api.h>
   6 #include <fsp/util.h>
   7 #include <gpio.h>
   8 #include <intelblocks/acpi.h>
   9 #include <intelblocks/cfg.h>
  10 #include <intelblocks/itss.h>
  11 #include <intelblocks/pcie_rp.h>
  12 #include <intelblocks/systemagent.h>
  13 #include <intelblocks/xdci.h>
  14 #include <soc/intel/common/vbt.h>
  15 #include <soc/pci_devs.h>
  16 #include <soc/pcie.h>
  17 #include <soc/ramstage.h>
  18 #include <soc/soc_chip.h>
  19
  20 #if CONFIG(HAVE_ACPI_TABLES)
  21 const char *soc_acpi_name(const struct device *dev)
  22 {
  23         if (dev->path.type == DEVICE_PATH_DOMAIN)
  24                 return "PCI0";
  25
  26         if (dev->path.type == DEVICE_PATH_USB) {
  27                 switch (dev->path.usb.port_type) {
  28                 case 0:
  29                         /* Root Hub */
  30                         return "RHUB";
  31                 case 2:
  32                         /* USB2 ports */
  33                         switch (dev->path.usb.port_id) {
  34                         case 0: return "HS01";
  35                         case 1: return "HS02";
  36                         case 2: return "HS03";
  37                         case 3: return "HS04";
  38                         case 4: return "HS05";
  39                         case 5: return "HS06";
  40                         case 6: return "HS07";
  41                         case 7: return "HS08";
  42                         case 8: return "HS09";
  43                         case 9: return "HS10";
  44                         }
  45                         break;
  46                 case 3:
  47                         /* USB3 ports */
  48                         switch (dev->path.usb.port_id) {
  49                         case 0: return "SS01";
  50                         case 1: return "SS02";
  51                         case 2: return "SS03";
  52                         case 3: return "SS04";
  53                         }
  54                         break;
  55                 }
  56                 return NULL;
  57         }
  58         if (dev->path.type != DEVICE_PATH_PCI)
  59                 return NULL;
  60
  61         switch (dev->path.pci.devfn) {
  62         case SA_DEVFN_ROOT:     return "MCHC";
  63         case PCH_DEVFN_I2C6:    return "I2C6";
  64         case PCH_DEVFN_I2C7:    return "I2C7";
  65         case PCH_DEVFN_XHCI:    return "XHCI";
  66         case PCH_DEVFN_I2C0:    return "I2C0";
  67         case PCH_DEVFN_I2C1:    return "I2C1";
  68         case PCH_DEVFN_I2C2:    return "I2C2";
  69         case PCH_DEVFN_I2C3:    return "I2C3";
  70         case PCH_DEVFN_SATA:    return "SATA";
  71         case PCH_DEVFN_UART2:   return "UAR2";
  72         case PCH_DEVFN_I2C4:    return "I2C4";
  73         case PCH_DEVFN_I2C5:    return "I2C5";
  74         case PCH_DEVFN_PCIE1:   return "RP01";
  75         case PCH_DEVFN_PCIE2:   return "RP02";
  76         case PCH_DEVFN_PCIE3:   return "RP03";
  77         case PCH_DEVFN_PCIE4:   return "RP04";
  78         case PCH_DEVFN_PCIE5:   return "RP05";
  79         case PCH_DEVFN_PCIE6:   return "RP06";
  80         case PCH_DEVFN_PCIE7:   return "RP07";
  81         case PCH_DEVFN_PSEGBE0: return "OTN0";
  82         case PCH_DEVFN_PSEGBE1: return "OTN1";
  83         case PCH_DEVFN_UART0:   return "UAR0";
  84         case PCH_DEVFN_UART1:   return "UAR1";
  85         case PCH_DEVFN_GSPI0:   return "SPI0";
  86         case PCH_DEVFN_GSPI1:   return "SPI1";
  87         case PCH_DEVFN_GBE:     return "GTSN";
  88         case PCH_DEVFN_GSPI2:   return "SPI2";
  89         case PCH_DEVFN_EMMC:    return "EMMC";
  90         case PCH_DEVFN_SDCARD:  return "SDXC";
  91         case PCH_DEVFN_HDA:     return "HDAS";
  92         case PCH_DEVFN_SMBUS:   return "SBUS";
  93         }
  94
  95         return NULL;
  96 }
  97 #endif
  98
  99 /* SoC routine to fill GPIO PM mask and value for GPIO_MISCCFG register */
 100 static void soc_fill_gpio_pm_configuration(void)
 101 {
 102         uint8_t value[TOTAL_GPIO_COMM];
 103         const config_t *config = config_of_soc();
 104
 105         if (config->gpio_override_pm)
 106                 memcpy(value, config->gpio_pm, sizeof(value));
 107         else
 108                 memset(value, MISCCFG_GPIO_PM_CONFIG_BITS, sizeof(value));
 109
 110         gpio_pm_configure(value, TOTAL_GPIO_COMM);
 111 }
 112
 113 void soc_init_pre_device(void *chip_info)
 114 {
 115         /* Perform silicon specific init. */
 116         fsp_silicon_init();
 117
 118          /* Display FIRMWARE_VERSION_INFO_HOB */
 119         fsp_display_fvi_version_hob();
 120
 121         soc_fill_gpio_pm_configuration();
 122
 123         /* swap enabled PCI ports in device tree if needed */
 124         pcie_rp_update_devicetree(pch_rp_groups);
 125 }
 126
 127 static struct device_operations pci_domain_ops = {
 128         .read_resources   = &pci_domain_read_resources,
 129         .set_resources    = &pci_domain_set_resources,
 130         .scan_bus         = &pci_host_bridge_scan_bus,
 131 #if CONFIG(HAVE_ACPI_TABLES)
 132         .acpi_name        = &soc_acpi_name,
 133         .acpi_fill_ssdt   = ssdt_set_above_4g_pci,
 134 #endif
 135 };
 136
 137 static struct device_operations cpu_bus_ops = {
 138         .read_resources   = noop_read_resources,
 139         .set_resources    = noop_set_resources,
 140 #if CONFIG(HAVE_ACPI_TABLES)
 141         .acpi_fill_ssdt   = generate_cpu_entries,
 142 #endif
 143 };
 144
 145 extern struct device_operations pmc_ops;
 146 static void soc_enable(struct device *dev)
 147 {
 148         /* Set the operations if it is a special bus type */
 149         if (dev->path.type == DEVICE_PATH_DOMAIN)
 150                 dev->ops = &pci_domain_ops;
 151         else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
 152                 dev->ops = &cpu_bus_ops;
 153         else if (dev->path.type == DEVICE_PATH_PCI &&
 154                  dev->path.pci.devfn == PCH_DEVFN_PMC)
 155                 dev->ops = &pmc_ops;
 156         else if (dev->path.type == DEVICE_PATH_GPIO)
 157                 block_gpio_enable(dev);
 158 }
 159
 160 struct chip_operations soc_intel_elkhartlake_ops = {
 161         .name = "Intel Elkhartlake",
 162         .enable_dev     = &soc_enable,
 163         .init           = &soc_init_pre_device,
 164 };