src/soc/intel/jasperlake/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <gpio.h>
   4 #include <intelblocks/pcr.h>
   5 #include <soc/pcr_ids.h>
   6 #include <soc/pmc.h>
   7
   8 static const struct reset_mapping rst_map[] = {
   9         { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30 },
  10         { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
  11         { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
  12 };
  13
  14 static const struct reset_mapping rst_map_com0[] = {
  15         { .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 },
  16         { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
  17         { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
  18         { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30 },
  19 };
  20
  21 /*
  22  * The GPIO driver for Jasperlake on Windows/Linux expects 32 GPIOs per pad
  23  * group, regardless of whether or not there is a physical pad for each
  24  * exposed GPIO number.
  25  *
  26  * This results in the OS having a sparse GPIO map, and devices that need
  27  * to export an ACPI GPIO must use the OS expected number.
  28  *
  29  * Not all pins are usable as GPIO and those groups do not have a pad base.
  30  *
  31  * This layout matches the Linux kernel pinctrl map for JSP at:
  32  * linux/drivers/pinctrl/intel/pinctrl-jasperlake.c
  33  */
  34 static const struct pad_group jsl_community0_groups[] = {
  35         INTEL_GPP_BASE(GPP_F0, GPP_F0, GPP_F19, 320),           /* GPP_F */
  36         INTEL_GPP(GPP_F0, GPIO_SPI0_IO_2, GPIO_SPI0_CLK_LOOPBK),/* SPI0 */
  37         INTEL_GPP_BASE(GPP_F0, GPP_B0, GPIO_GSPI1_CLK_LOOPBK, 32),/* GPP_B */
  38         INTEL_GPP_BASE(GPP_F0, GPP_A0, GPIO_ESPI_CLK_LOOPBK, 64),/* GPP_A */
  39         INTEL_GPP_BASE(GPP_F0, GPP_S0, GPP_S7, 96),             /* GPP_S */
  40         INTEL_GPP_BASE(GPP_F0, GPP_R0, GPP_R7, 128),            /* GPP_R */
  41 };
  42
  43 static const struct pad_group jsl_community1_groups[] = {
  44         INTEL_GPP_BASE(GPP_H0, GPP_H0, GPP_H23, 160),           /* GPP_H */
  45         INTEL_GPP_BASE(GPP_H0, GPP_D0, GPIO_SPI1_CLK_LOOPBK, 192),/* GPP_D */
  46         INTEL_GPP_BASE(GPP_H0, VGPIO_0, VGPIO_39, 224),         /* VGPIO */
  47         INTEL_GPP_BASE(GPP_H0, GPP_C0, GPP_C23, 256),           /* GPP_C */
  48 };
  49
  50 /* This community is not visible to the OS */
  51 static const struct pad_group jsl_community2_groups[] = {
  52         INTEL_GPP(GPD0, GPD0, GPIO_DRAM_RESETB),                /* GPD */
  53 };
  54
  55 static const struct pad_group jsl_community4_groups[] = {
  56         INTEL_GPP(GPIO_L_BKLTEN, GPIO_L_BKLTEN, GPIO_MLK_RSTB), /* Reserved */
  57         INTEL_GPP_BASE(GPIO_L_BKLTEN, GPP_E0, GPP_E23, 288),    /* GPP_E */
  58 };
  59
  60 static const struct pad_group jsl_community5_groups[] = {
  61         INTEL_GPP_BASE(GPP_G0, GPP_G0, GPP_G7, 0),              /* GPP_G */
  62 };
  63
  64 static const struct pad_community jsl_communities[TOTAL_GPIO_COMM] = {
  65         /* GPP F, B, A, S, R */
  66         [COMM_0] = {
  67                 .port = PID_GPIOCOM0,
  68                 .first_pad = GPIO_COM0_START,
  69                 .last_pad = GPIO_COM0_END,
  70                 .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS,
  71                 .pad_cfg_base = PAD_CFG_BASE,
  72                 .pad_cfg_lock_offset = PAD_CFG_LOCK,
  73                 .host_own_reg_0 = HOSTSW_OWN_REG_0,
  74                 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
  75                 .gpi_int_en_reg_0 = GPI_INT_EN_0,
  76                 .gpi_gpe_sts_reg_0 = GPI_GPE_STS_0,
  77                 .gpi_gpe_en_reg_0 = GPI_GPE_EN_0,
  78                 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
  79                 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
  80                 .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
  81                 .gpi_nmi_en_reg_0 = GPI_NMI_EN_0,
  82                 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
  83                 .name = "GPP_FBASR",
  84                 .acpi_path = "\\_SB.PCI0.GPIO",
  85                 .reset_map = rst_map_com0,
  86                 .num_reset_vals = ARRAY_SIZE(rst_map_com0),
  87                 .groups = jsl_community0_groups,
  88                 .num_groups = ARRAY_SIZE(jsl_community0_groups),
  89         },
  90         /* GPP H, D, VGPIO, C */
  91         [COMM_1] = {
  92                 .port = PID_GPIOCOM1,
  93                 .first_pad = GPIO_COM1_START,
  94                 .last_pad = GPIO_COM1_END,
  95                 .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS,
  96                 .pad_cfg_base = PAD_CFG_BASE,
  97                 .host_own_reg_0 = HOSTSW_OWN_REG_0,
  98                 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
  99                 .gpi_int_en_reg_0 = GPI_INT_EN_0,
 100                 .gpi_gpe_sts_reg_0 = GPI_GPE_STS_0,
 101                 .gpi_gpe_en_reg_0 = GPI_GPE_EN_0,
 102                 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
 103                 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
 104                 .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
 105                 .gpi_nmi_en_reg_0 = GPI_NMI_EN_0,
 106                 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
 107                 .name = "GPP_HDC",
 108                 .acpi_path = "\\_SB.PCI0.GPIO",
 109                 .reset_map = rst_map,
 110                 .num_reset_vals = ARRAY_SIZE(rst_map),
 111                 .groups = jsl_community1_groups,
 112                 .num_groups = ARRAY_SIZE(jsl_community1_groups),
 113         },
 114         /* GPD */
 115         [COMM_2] = {
 116                 .port = PID_GPIOCOM2,
 117                 .first_pad = GPIO_COM2_START,
 118                 .last_pad = GPIO_COM2_END,
 119                 .num_gpi_regs = NUM_GPIO_COM2_GPI_REGS,
 120                 .pad_cfg_base = PAD_CFG_BASE,
 121                 .host_own_reg_0 = HOSTSW_OWN_REG_0,
 122                 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
 123                 .gpi_int_en_reg_0 = GPI_INT_EN_0,
 124                 .gpi_gpe_sts_reg_0 = GPI_GPE_STS_0,
 125                 .gpi_gpe_en_reg_0 = GPI_GPE_EN_0,
 126                 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
 127                 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
 128                 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
 129                 .name = "GPD",
 130                 .acpi_path = "\\_SB.PCI0.GPIO",
 131                 .reset_map = rst_map,
 132                 .num_reset_vals = ARRAY_SIZE(rst_map),
 133                 .groups = jsl_community2_groups,
 134                 .num_groups = ARRAY_SIZE(jsl_community2_groups),
 135         },
 136         /* GPP E */
 137         [COMM_4] = {
 138                 .port = PID_GPIOCOM4,
 139                 .first_pad = GPIO_COM4_START,
 140                 .last_pad = GPIO_COM4_END,
 141                 .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS,
 142                 .pad_cfg_base = PAD_CFG_BASE,
 143                 .host_own_reg_0 = HOSTSW_OWN_REG_0,
 144                 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
 145                 .gpi_int_en_reg_0 = GPI_INT_EN_0,
 146                 .gpi_gpe_sts_reg_0 = GPI_GPE_STS_0,
 147                 .gpi_gpe_en_reg_0 = GPI_GPE_EN_0,
 148                 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
 149                 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
 150                 .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
 151                 .gpi_nmi_en_reg_0 = GPI_NMI_EN_0,
 152                 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
 153                 .name = "GPP_E",
 154                 .acpi_path = "\\_SB.PCI0.GPIO",
 155                 .reset_map = rst_map,
 156                 .num_reset_vals = ARRAY_SIZE(rst_map),
 157                 .groups = jsl_community4_groups,
 158                 .num_groups = ARRAY_SIZE(jsl_community4_groups),
 159         },
 160         /* GPP G */
 161         [COMM_5] = {
 162                 .port = PID_GPIOCOM5,
 163                 .first_pad = GPIO_COM5_START,
 164                 .last_pad = GPIO_COM5_END,
 165                 .num_gpi_regs = NUM_GPIO_COM5_GPI_REGS,
 166                 .pad_cfg_base = PAD_CFG_BASE,
 167                 .host_own_reg_0 = HOSTSW_OWN_REG_0,
 168                 .gpi_int_sts_reg_0 = GPI_INT_STS_0,
 169                 .gpi_int_en_reg_0 = GPI_INT_EN_0,
 170                 .gpi_gpe_sts_reg_0 = GPI_GPE_STS_0,
 171                 .gpi_gpe_en_reg_0 = GPI_GPE_EN_0,
 172                 .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
 173                 .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
 174                 .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
 175                 .gpi_nmi_en_reg_0 = GPI_NMI_EN_0,
 176                 .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
 177                 .name = "GPP_G",
 178                 .acpi_path = "\\_SB.PCI0.GPIO",
 179                 .reset_map = rst_map,
 180                 .num_reset_vals = ARRAY_SIZE(rst_map),
 181                 .groups = jsl_community5_groups,
 182                 .num_groups = ARRAY_SIZE(jsl_community5_groups),
 183         }
 184 };
 185
 186 const struct pad_community *soc_gpio_get_community(size_t *num_communities)
 187 {
 188         *num_communities = ARRAY_SIZE(jsl_communities);
 189         return jsl_communities;
 190 }
 191
 192 const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num)
 193 {
 194         static const struct pmc_to_gpio_route routes[] = {
 195                 { PMC_GPP_A, GPP_A },
 196                 { PMC_GPP_B, GPP_B },
 197                 { PMC_GPP_G, GPP_G },
 198                 { PMC_GPP_C, GPP_C },
 199                 { PMC_GPP_R, GPP_R },
 200                 { PMC_GPP_D, GPP_D },
 201                 { PMC_GPP_S, GPP_S },
 202                 { PMC_GPP_H, GPP_H },
 203                 { PMC_GPP_F, GPP_F },
 204                 { PMC_GPD,   GPP_GPD },
 205                 { PMC_GPP_E, GPP_E }
 206         };
 207
 208         *num = ARRAY_SIZE(routes);
 209         return routes;
 210 }