src/soc/intel/skylake/Kconfig

   1 ## SPDX-License-Identifier: GPL-2.0-only
   2
   3 config SOC_INTEL_COMMON_SKYLAKE_BASE
   4         bool
   5         select ACPI_INTEL_HARDWARE_SLEEP_VALUES
   6         select ACPI_NHLT
   7         select ARCH_X86
   8         select BOOT_DEVICE_SUPPORTS_WRITES
   9         select CACHE_MRC_SETTINGS
  10         select CPU_INTEL_COMMON
  11         select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
  12         select CPU_SUPPORTS_PM_TIMER_EMULATION
  13         select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2
  14         select FSP_COMPRESS_FSP_S_LZ4
  15         select FSP_M_XIP
  16         select GENERIC_GPIO_LIB
  17         select HAVE_FSP_GOP
  18         select HAVE_FSP_LOGO_SUPPORT
  19         select HAVE_HYPERTHREADING
  20         select HAVE_INTEL_FSP_REPO
  21         select INTEL_CAR_NEM_ENHANCED
  22         select HAVE_SMI_HANDLER
  23         select INTEL_DESCRIPTOR_MODE_CAPABLE
  24         select INTEL_GMA_ACPI
  25         select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
  26         select MRC_SETTINGS_PROTECT
  27         select PARALLEL_MP_AP_WORK
  28         select PLATFORM_USES_FSP2_0
  29         select PMC_GLOBAL_RESET_ENABLE_LOCK
  30         select SA_ENABLE_DPR
  31         select SOC_INTEL_COMMON
  32         select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
  33         select SOC_INTEL_COMMON_BLOCK
  34         select SOC_INTEL_COMMON_BLOCK_ACPI
  35         select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC
  36         select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO
  37         select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT
  38         select SOC_INTEL_COMMON_BLOCK_ACPI_PEP
  39         select SOC_INTEL_COMMON_BLOCK_CAR
  40         select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
  41         select SOC_INTEL_COMMON_BLOCK_CPU
  42         select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
  43         select SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE
  44         select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
  45         select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL
  46         select SOC_INTEL_COMMON_BLOCK_GSPI
  47         select SOC_INTEL_COMMON_BLOCK_HDA
  48         select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR
  49         select SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE
  50         select SOC_INTEL_COMMON_BLOCK_SA
  51         select SOC_INTEL_COMMON_BLOCK_SCS
  52         select SOC_INTEL_COMMON_BLOCK_SGX
  53         select SOC_INTEL_COMMON_BLOCK_SGX_LOCK_MEMORY
  54         select SOC_INTEL_COMMON_BLOCK_SMM
  55         select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
  56         select SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV
  57         select SOC_INTEL_COMMON_BLOCK_UART
  58         select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
  59         select SOC_INTEL_COMMON_FSP_RESET
  60         select SOC_INTEL_COMMON_PCH_CLIENT
  61         select SOC_INTEL_COMMON_NHLT
  62         select SOC_INTEL_COMMON_RESET
  63         select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
  64         select SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION
  65         select SSE2
  66         select SUPPORT_CPU_UCODE_IN_CBFS
  67         select TSC_MONOTONIC_TIMER
  68         select TSC_SYNC_MFENCE
  69         select UDELAY_TSC
  70         select UDK_2017_BINDING
  71         select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
  72         select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
  73         select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
  74
  75 config SOC_INTEL_SKYLAKE
  76         bool
  77         select SOC_INTEL_COMMON_SKYLAKE_BASE
  78
  79 config SOC_INTEL_KABYLAKE
  80         bool
  81         select SOC_INTEL_COMMON_SKYLAKE_BASE
  82
  83 config SOC_INTEL_SKYLAKE_LGA1151_V2
  84         bool
  85         select PLATFORM_USES_FSP2_1
  86         select SOC_INTEL_COMMON_SKYLAKE_BASE
  87         select SKYLAKE_SOC_PCH_H
  88         help
  89           Selected by mainboards with a LGA1151 v2 socket and a Z370, H310C or B365 PCH
  90
  91 if SOC_INTEL_COMMON_SKYLAKE_BASE
  92
  93 config MAX_HECI_DEVICES
  94         int
  95         default 5
  96
  97 config MAX_CPUS
  98         int
  99         default 16 if MAINBOARD_SUPPORTS_COFFEELAKE_CPU
 100         default 8
 101
 102 config ENABLE_SATA_TEST_MODE
 103         bool "Enable SATA test mode"
 104         default n
 105         help
 106           Enable SATA test mode in FSP-S.
 107
 108 config CPU_INTEL_NUM_FIT_ENTRIES
 109         int
 110         default 10
 111
 112 config VBOOT
 113         select VBOOT_MUST_REQUEST_DISPLAY
 114         select VBOOT_STARTS_IN_BOOTBLOCK
 115         select VBOOT_VBNV_CMOS
 116         select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
 117
 118 config CBFS_SIZE
 119         default 0x200000
 120
 121 config DCACHE_RAM_BASE
 122         hex
 123         default 0xfef00000
 124
 125 config DCACHE_RAM_SIZE
 126         hex
 127         default 0x40000
 128         help
 129           The size of the cache-as-ram region required during bootblock
 130           and/or romstage.
 131
 132 config DCACHE_BSP_STACK_SIZE
 133         hex
 134         default 0x20400 if FSP_USES_CB_STACK
 135         default 0x4000
 136         help
 137           The amount of anticipated stack usage in CAR by bootblock and
 138           other stages.
 139
 140 config FSP_TEMP_RAM_SIZE
 141         hex
 142         depends on FSP_USES_CB_STACK
 143         default 0x10000
 144         help
 145           The amount of anticipated heap usage in CAR by FSP.
 146           Refer to Platform FSP integration guide document to know
 147           the exact FSP requirement for Heap setup.
 148
 149 config EXCLUDE_NATIVE_SD_INTERFACE
 150         bool
 151         default n
 152         help
 153           If you set this option to n, will not use native SD controller.
 154
 155 config IED_REGION_SIZE
 156         hex
 157         default 0x400000
 158
 159 config PCR_BASE_ADDRESS
 160         hex
 161         default 0xfd000000
 162         help
 163           This option allows you to select MMIO Base Address of sideband bus.
 164
 165 config SMM_RESERVED_SIZE
 166         hex
 167         default 0x200000
 168
 169 config SMM_TSEG_SIZE
 170         hex
 171         default 0x800000
 172
 173 config VGA_BIOS_ID
 174         string
 175         default "8086,0406"
 176
 177 config SKYLAKE_SOC_PCH_H
 178         bool
 179         default n
 180
 181 config NHLT_DMIC_1CH
 182         bool
 183         default n
 184         help
 185           Include DSP firmware settings for 1 channel DMIC array.
 186
 187 config NHLT_DMIC_2CH
 188         bool
 189         default n
 190         help
 191           Include DSP firmware settings for 2 channel DMIC array.
 192
 193 config NHLT_DMIC_4CH
 194         bool
 195         default n
 196         help
 197           Include DSP firmware settings for 4 channel DMIC array.
 198
 199 config NHLT_NAU88L25
 200         bool
 201         default n
 202         help
 203           Include DSP firmware settings for nau88l25 headset codec.
 204
 205 config NHLT_MAX98357
 206         bool
 207         default n
 208         help
 209           Include DSP firmware settings for max98357 amplifier.
 210
 211 config NHLT_MAX98373
 212         bool
 213         default n
 214         help
 215           Include DSP firmware settings for max98373 amplifier.
 216
 217 config NHLT_SSM4567
 218         bool
 219         default n
 220         help
 221           Include DSP firmware settings for ssm4567 smart amplifier.
 222
 223 config NHLT_RT5514
 224         bool
 225         default n
 226         help
 227           Include DSP firmware settings for rt5514 DSP.
 228
 229 config NHLT_RT5663
 230         bool
 231         default n
 232         help
 233           Include DSP firmware settings for rt5663 headset codec.
 234
 235 config NHLT_MAX98927
 236         bool
 237         default n
 238         help
 239           Include DSP firmware settings for max98927 amplifier.
 240
 241 config NHLT_DA7219
 242         bool
 243         default n
 244         help
 245           Include DSP firmware settings for DA7219 headset codec.
 246
 247 # Use KabylakeFsp for both Skylake and Kabylake as it supports both.
 248 # SkylakeFsp is FSP 1.1 and therefore incompatible.
 249 config FSP_HEADER_PATH
 250         default "3rdparty/fsp/AmberLakeFspBinPkg/Include/" if SOC_INTEL_SKYLAKE_LGA1151_V2
 251         default "3rdparty/fsp/KabylakeFspBinPkg/Include/"
 252
 253 config FSP_FD_PATH
 254         default "3rdparty/fsp/AmberLakeFspBinPkg/Fsp.fd" if SOC_INTEL_SKYLAKE_LGA1151_V2
 255         default "3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd"
 256
 257 config MAX_ROOT_PORTS
 258         int
 259         default 24
 260
 261 config NO_FADT_8042
 262         bool
 263         default n
 264         help
 265           Choose this option if you want to disable 8042 Keyboard
 266
 267 config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
 268         int
 269         default 120
 270
 271 config CPU_XTAL_HZ
 272         default 24000000
 273
 274 config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
 275         int
 276         default SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
 277
 278 config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
 279         int
 280         default 2
 281
 282 config SOC_INTEL_I2C_DEV_MAX
 283         int
 284         default 6
 285
 286 config CPU_BCLK_MHZ
 287         int
 288         default 100
 289
 290 config CONSOLE_UART_BASE_ADDRESS
 291         hex
 292         default 0xfe030000
 293         depends on INTEL_LPSS_UART_FOR_CONSOLE
 294
 295 # Clock divider parameters for 115200 baud rate
 296 config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
 297         hex
 298         default 0x30
 299
 300 config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
 301         hex
 302         default 0xc35
 303
 304 config CHIPSET_DEVICETREE
 305         string
 306         default "soc/intel/skylake/chipset.cb"
 307
 308 config IFD_CHIPSET
 309         string
 310         default "sklkbl"
 311
 312 config INTEL_TXT_BIOSACM_ALIGNMENT
 313         hex
 314         default 0x40000 # 256KB
 315
 316 config MAINBOARD_SUPPORTS_SKYLAKE_CPU
 317         bool "Board can contain Skylake CPU"
 318         default !SOC_INTEL_SKYLAKE_LGA1151_V2
 319
 320 if SKYLAKE_SOC_PCH_H
 321
 322 config MAINBOARD_SUPPORTS_KABYLAKE_CPU
 323         bool "Board can contain Kaby Lake CPU"
 324         default !SOC_INTEL_SKYLAKE_LGA1151_V2 && SOC_INTEL_KABYLAKE
 325
 326 config MAINBOARD_SUPPORTS_COFFEELAKE_CPU
 327         bool "Board can contain Coffee Lake CPU"
 328         default y if SOC_INTEL_SKYLAKE_LGA1151_V2
 329
 330 endif
 331
 332 if !SKYLAKE_SOC_PCH_H
 333
 334 config MAINBOARD_SUPPORTS_KABYLAKE_DUAL
 335         bool "Board can contain Kaby Lake DUAL core"
 336         default y
 337
 338 config MAINBOARD_SUPPORTS_KABYLAKE_QUAD
 339         bool "Board can contain Kaby Lake QUAD core"
 340         default y
 341
 342 endif
 343
 344 endif