src/soc/intel/skylake/cpu.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <console/console.h>
   4 #include <device/device.h>
   5 #include <device/pci.h>
   6 #include <cpu/x86/mtrr.h>
   7 #include <cpu/x86/msr.h>
   8 #include <cpu/x86/mp.h>
   9 #include <cpu/intel/common/common.h>
  10 #include <cpu/intel/microcode.h>
  11 #include <cpu/intel/speedstep.h>
  12 #include <cpu/intel/turbo.h>
  13 #include <cpu/x86/name.h>
  14 #include <cpu/intel/smm_reloc.h>
  15 #include <intelblocks/cpulib.h>
  16 #include <intelblocks/fast_spi.h>
  17 #include <intelblocks/mp_init.h>
  18 #include <intelblocks/sgx.h>
  19 #include <soc/cpu.h>
  20 #include <soc/msr.h>
  21 #include <soc/pci_devs.h>
  22 #include <soc/ramstage.h>
  23 #include <soc/systemagent.h>
  24 #include <types.h>
  25
  26 #include "chip.h"
  27
  28 bool cpu_soc_is_in_untrusted_mode(void)
  29 {
  30         /*
  31          * TODO: Add dynamic detection to identify if skylake SoC
  32          * is in coffeelake board.
  33          */
  34         if (!CONFIG(MAINBOARD_SUPPORTS_COFFEELAKE_CPU))
  35                 return false;
  36
  37         /* IA_UNTRUSTED_MODE is not supported in Sky Lake */
  38         msr_t msr = rdmsr(MSR_BIOS_DONE);
  39         return !!(msr.lo & ENABLE_IA_UNTRUSTED);
  40 }
  41
  42 void cpu_soc_bios_done(void)
  43 {
  44         if (!CONFIG(MAINBOARD_SUPPORTS_COFFEELAKE_CPU))
  45                 return;
  46
  47         msr_t msr;
  48
  49         msr = rdmsr(MSR_BIOS_DONE);
  50         msr.lo |= ENABLE_IA_UNTRUSTED;
  51         wrmsr(MSR_BIOS_DONE, msr);
  52 }
  53
  54 static void configure_misc(void)
  55 {
  56         config_t *conf = config_of_soc();
  57         msr_t msr;
  58
  59         msr = rdmsr(IA32_MISC_ENABLE);
  60         msr.lo |= (1 << 0);     /* Fast String enable */
  61         msr.lo |= (1 << 3);     /* TM1/TM2/EMTTM enable */
  62         wrmsr(IA32_MISC_ENABLE, msr);
  63
  64         /* Set EIST status */
  65         cpu_set_eist(conf->eist_enable);
  66
  67         /* Disable Thermal interrupts */
  68         msr.lo = 0;
  69         msr.hi = 0;
  70         wrmsr(IA32_THERM_INTERRUPT, msr);
  71
  72         /* Enable package critical interrupt only */
  73         msr.lo = 1 << 4;
  74         msr.hi = 0;
  75         wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr);
  76
  77         msr = rdmsr(MSR_POWER_CTL);
  78         msr.lo |= (1 << 0);     /* Enable Bi-directional PROCHOT as an input */
  79         msr.lo |= (1 << 18);    /* Enable Energy/Performance Bias control */
  80         msr.lo &= ~POWER_CTL_C1E_MASK;  /* Disable C1E */
  81         msr.lo |= (1 << 23);    /* Lock it */
  82         wrmsr(MSR_POWER_CTL, msr);
  83 }
  84
  85 static void configure_c_states(void)
  86 {
  87         msr_t msr;
  88
  89         /* C-state Interrupt Response Latency Control 0 - package C3 latency */
  90         msr.hi = 0;
  91         msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_0_LIMIT;
  92         wrmsr(MSR_C_STATE_LATENCY_CONTROL_0, msr);
  93
  94         /* C-state Interrupt Response Latency Control 1 - package C6/C7 short */
  95         msr.hi = 0;
  96         msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_1_LIMIT;
  97         wrmsr(MSR_C_STATE_LATENCY_CONTROL_1, msr);
  98
  99         /* C-state Interrupt Response Latency Control 2 - package C6/C7 long */
 100         msr.hi = 0;
 101         msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_2_LIMIT;
 102         wrmsr(MSR_C_STATE_LATENCY_CONTROL_2, msr);
 103
 104         /* C-state Interrupt Response Latency Control 3 - package C8 */
 105         msr.hi = 0;
 106         msr.lo = IRTL_VALID | IRTL_1024_NS |
 107                 C_STATE_LATENCY_CONTROL_3_LIMIT;
 108         wrmsr(MSR_C_STATE_LATENCY_CONTROL_3, msr);
 109
 110         /* C-state Interrupt Response Latency Control 4 - package C9 */
 111         msr.hi = 0;
 112         msr.lo = IRTL_VALID | IRTL_1024_NS |
 113                 C_STATE_LATENCY_CONTROL_4_LIMIT;
 114         wrmsr(MSR_C_STATE_LATENCY_CONTROL_4, msr);
 115
 116         /* C-state Interrupt Response Latency Control 5 - package C10 */
 117         msr.hi = 0;
 118         msr.lo = IRTL_VALID | IRTL_1024_NS |
 119                 C_STATE_LATENCY_CONTROL_5_LIMIT;
 120         wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr);
 121 }
 122
 123 /* All CPUs including BSP will run the following function. */
 124 void soc_core_init(struct device *cpu)
 125 {
 126         /* Configure Core PRMRR for SGX. */
 127         if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE))
 128                 prmrr_core_configure();
 129
 130         /* Clear out pending MCEs */
 131         /* TODO(adurbin): This should only be done on a cold boot. Also, some
 132          * of these banks are core vs package scope. For now every CPU clears
 133          * every bank. */
 134         mca_configure();
 135
 136         enable_lapic_tpr();
 137
 138         /* Configure c-state interrupt response time */
 139         configure_c_states();
 140
 141         /* Configure Enhanced SpeedStep and Thermal Sensors */
 142         configure_misc();
 143
 144         set_aesni_lock();
 145
 146         /* Enable ACPI Timer Emulation via MSR 0x121 */
 147         enable_pm_timer_emulation();
 148
 149         /* Enable Direct Cache Access */
 150         configure_dca_cap();
 151
 152         /* Set energy policy */
 153         set_energy_perf_bias(ENERGY_POLICY_NORMAL);
 154
 155         /* Enable Turbo */
 156         enable_turbo();
 157 }
 158
 159 static void per_cpu_smm_trigger(void)
 160 {
 161         /* Relocate the SMM handler. */
 162         smm_relocate();
 163 }
 164
 165 void smm_lock(void)
 166 {
 167         /*
 168          * LOCK the SMM memory window and enable normal SMM.
 169          * After running this function, only a full reset can
 170          * make the SMM registers writable again. D_LCK bit
 171          * requires the PCI 0xcf8/0xcfc I/O access.
 172          */
 173         printk(BIOS_DEBUG, "Locking SMM.\n");
 174         pci_io_write_config8(SA_DEVFN_ROOT, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG);
 175 }
 176
 177 static void vmx_configure(void *unused)
 178 {
 179         set_feature_ctrl_vmx();
 180 }
 181
 182 static void fc_lock_configure(void *unused)
 183 {
 184         set_feature_ctrl_lock();
 185 }
 186
 187 static void post_mp_init(void)
 188 {
 189         bool failure = false;
 190
 191         /* Set Max Ratio */
 192         cpu_set_max_ratio();
 193
 194         /*
 195          * Now that all APs have been relocated as well as the BSP let SMIs
 196          * start flowing.
 197          */
 198         global_smi_enable_no_pwrbtn();
 199
 200         /* Lock down the SMRAM space. */
 201         if (CONFIG(HAVE_SMI_HANDLER))
 202                 smm_lock();
 203
 204         if (mp_run_on_all_cpus(vmx_configure, NULL) != CB_SUCCESS)
 205                 failure = true;
 206
 207         if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE))
 208                 if (mp_run_on_all_cpus(sgx_configure, NULL) != CB_SUCCESS)
 209                         failure = true;
 210
 211         if (mp_run_on_all_cpus(fc_lock_configure, NULL) != CB_SUCCESS)
 212                 failure = true;
 213
 214         if (failure)
 215                 printk(BIOS_CRIT, "CRITICAL ERROR: MP post init failed\n");
 216 }
 217
 218 static void soc_fsp_load(void)
 219 {
 220         fsps_load();
 221 }
 222
 223 static const struct mp_ops mp_ops = {
 224         /*
 225          * Skip Pre MP init MTRR programming as MTRRs are mirrored from BSP,
 226          * that are set prior to ramstage.
 227          * Real MTRRs programming are being done after resource allocation.
 228          */
 229         .pre_mp_init = soc_fsp_load,
 230         .get_cpu_count = get_cpu_count,
 231         .get_smm_info = smm_info,
 232         .get_microcode_info = get_microcode_info,
 233         .pre_mp_smm_init = smm_initialize,
 234         .per_cpu_smm_trigger = per_cpu_smm_trigger,
 235         .relocation_handler = smm_relocation_handler,
 236         .post_mp_init = post_mp_init,
 237 };
 238
 239 void mp_init_cpus(struct bus *cpu_bus)
 240 {
 241         /* TODO: Handle mp_init_with_smm failure? */
 242         mp_init_with_smm(cpu_bus, &mp_ops);
 243
 244         /* Thermal throttle activation offset */
 245         configure_tcc_thermal_target();
 246 }
 247
 248 int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id)
 249 {
 250         msr_t msr1;
 251         msr_t msr2;
 252
 253         /*
 254          * If PRMRR/SGX is supported the FIT microcode load will set the msr
 255          * 0x08b with the Patch revision id one less than the id in the
 256          * microcode binary. The PRMRR support is indicated in the MSR
 257          * MTRRCAP[12]. If SGX is not enabled, check and avoid reloading the
 258          * same microcode during CPU initialization. If SGX is enabled, as
 259          * part of SGX BIOS initialization steps, the same microcode needs to
 260          * be reloaded after the core PRMRR MSRs are programmed.
 261          */
 262         msr1 = rdmsr(MTRR_CAP_MSR);
 263         msr2 = rdmsr(MSR_PRMRR_PHYS_BASE);
 264         if (msr2.lo && (current_patch_id == new_patch_id - 1))
 265                 return 0;
 266         else
 267                 return (msr1.lo & MTRR_CAP_PRMRR) &&
 268                         (current_patch_id == new_patch_id - 1);
 269 }