src/soc/intel/tigerlake/bootblock/pch.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 /*
   4  * This file is created based on Intel Tiger Lake Processor PCH Datasheet
   5  * Document number: 575857
   6  * Chapter number: 2, 3, 4, 27, 28
   7  */
   8
   9 #include <commonlib/console/post_codes.h>
  10 #include <console/console.h>
  11 #include <device/device.h>
  12 #include <device/mmio.h>
  13 #include <device/pci_ops.h>
  14 #include <intelblocks/fast_spi.h>
  15 #include <intelblocks/gspi.h>
  16 #include <intelblocks/lpc_lib.h>
  17 #include <intelblocks/p2sb.h>
  18 #include <intelblocks/pcr.h>
  19 #include <intelblocks/pmclib.h>
  20 #include <intelblocks/rtc.h>
  21 #include <intelpch/espi.h>
  22 #include <soc/bootblock.h>
  23 #include <soc/soc_chip.h>
  24 #include <soc/iomap.h>
  25 #include <soc/p2sb.h>
  26 #include <soc/pch.h>
  27 #include <soc/pci_devs.h>
  28 #include <soc/pcr_ids.h>
  29 #include <soc/pm.h>
  30
  31 #if CONFIG(SOC_INTEL_TIGERLAKE_PCH_H)
  32 #define PCR_PSF3_TO_SHDW_PMC_REG_BASE   0x1000
  33 #else
  34 #define PCR_PSF3_TO_SHDW_PMC_REG_BASE   0x1100
  35 #endif
  36 #define PCR_PSFX_TO_SHDW_BAR0   0
  37 #define PCR_PSFX_TO_SHDW_BAR1   0x4
  38 #define PCR_PSFX_TO_SHDW_BAR2   0x8
  39 #define PCR_PSFX_TO_SHDW_BAR3   0xC
  40 #define PCR_PSFX_TO_SHDW_BAR4   0x10
  41 #define PCR_PSFX_TO_SHDW_PCIEN_IOEN     0x01
  42 #define PCR_PSFX_T0_SHDW_PCIEN  0x1C
  43
  44 static void soc_config_pwrmbase(void)
  45 {
  46         /*
  47          * Assign Resources to PWRMBASE
  48          * Clear BIT 1-2 Command Register
  49          */
  50         pci_and_config16(PCH_DEV_PMC, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
  51
  52         /* Program PWRM Base */
  53         pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS);
  54
  55         /* Enable Bus Master and MMIO Space */
  56         pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
  57
  58         /* Enable PWRM in PMC */
  59         setbits32((void *)PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN);
  60 }
  61
  62 void bootblock_pch_early_init(void)
  63 {
  64         /*
  65          * Perform P2SB configuration before any another controller initialization as the
  66          * controller might want to perform PCR settings.
  67          */
  68         p2sb_enable_bar();
  69         p2sb_configure_hpet();
  70
  71         fast_spi_early_init(SPI_BASE_ADDRESS);
  72         gspi_early_bar_init();
  73
  74         /*
  75          * Enabling PWRM Base for accessing
  76          * Global Reset Cause Register.
  77          */
  78         soc_config_pwrmbase();
  79 }
  80
  81 static void soc_config_acpibase(void)
  82 {
  83         uint32_t pmc_reg_value;
  84         uint32_t pmc_base_reg = PCR_PSF3_TO_SHDW_PMC_REG_BASE;
  85
  86         pmc_reg_value = pcr_read32(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4);
  87
  88         if (pmc_reg_value != 0xffffffff) {
  89                 /* Disable Io Space before changing the address */
  90                 pcr_rmw32(PID_PSF3, pmc_base_reg + PCR_PSFX_T0_SHDW_PCIEN,
  91                                 ~PCR_PSFX_TO_SHDW_PCIEN_IOEN, 0);
  92                 /* Program ABASE in PSF3 PMC space BAR4*/
  93                 pcr_write32(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4,
  94                                 ACPI_BASE_ADDRESS);
  95                 /* Enable IO Space */
  96                 pcr_rmw32(PID_PSF3, pmc_base_reg + PCR_PSFX_T0_SHDW_PCIEN,
  97                                 ~0, PCR_PSFX_TO_SHDW_PCIEN_IOEN);
  98         }
  99 }
 100
 101 void pch_early_iorange_init(void)
 102 {
 103         uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 |
 104                 LPC_IOE_EC_62_66 | LPC_IOE_LGE_200;
 105
 106         const uint16_t lpc_ioe_enable_mask = LPC_IOE_COMA_EN | LPC_IOE_COMB_EN |
 107                                              LPC_IOE_LPT_EN | LPC_IOE_FDD_EN |
 108                                              LPC_IOE_LGE_200 | LPC_IOE_HGE_208 |
 109                                              LPC_IOE_KBC_60_64 | LPC_IOE_EC_62_66 |
 110                                              LPC_IOE_SUPERIO_2E_2F | LPC_IOE_EC_4E_4F;
 111
 112         const config_t *config = config_of_soc();
 113
 114         if (config->lpc_ioe) {
 115                 io_enables = config->lpc_ioe & lpc_ioe_enable_mask;
 116         } else {
 117                 /* IO Decode Range */
 118                 if (CONFIG(DRIVERS_UART_8250IO))
 119                         lpc_io_setup_comm_a_b();
 120         }
 121
 122         /* IO Decode Enable */
 123         lpc_enable_fixed_io_ranges(io_enables);
 124
 125         /* Program generic IO Decode Range */
 126         pch_enable_lpc();
 127 }
 128
 129 void bootblock_pch_init(void)
 130 {
 131         /*
 132          * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT,
 133          * GPE0_STS, GPE0_EN registers.
 134          */
 135         soc_config_acpibase();
 136
 137         /* Set up GPE configuration */
 138         pmc_gpe_init();
 139
 140         enable_rtc_upper_bank();
 141 }