src/southbridge/intel/common/acpi_pirq_gen.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef INTEL_COMMON_ACPI_PIRQ_GEN_H
   4 #define INTEL_COMMON_ACPI_PIRQ_GEN_H
   5
   6 #include <assert.h>
   7 #include <device/device.h>
   8
   9 #define MAX_SLOTS       32
  10
  11 enum pci_pin {
  12         PCI_INT_NONE = 0,
  13         PCI_INT_A,
  14         PCI_INT_B,
  15         PCI_INT_C,
  16         PCI_INT_D,
  17         PCI_INT_MAX = PCI_INT_D,
  18 };
  19
  20 enum pirq {
  21         PIRQ_INVALID,
  22         PIRQ_A,
  23         PIRQ_B,
  24         PIRQ_C,
  25         PIRQ_D,
  26         PIRQ_E,
  27         PIRQ_F,
  28         PIRQ_G,
  29         PIRQ_H,
  30         PIRQ_COUNT = PIRQ_H,
  31 };
  32
  33 static inline size_t pirq_idx(enum pirq pirq)
  34 {
  35         assert(pirq > PIRQ_INVALID && pirq <= PIRQ_H);
  36         return (size_t)(pirq - PIRQ_A);
  37 }
  38
  39 /*
  40  * This struct represents an assignment of slot/pin -> IRQ. Some chipsets may
  41  * want to provide both PIC-mode and APIC-mode IRQs (e.g. selected using PICM
  42  * set by the OS), therefore a field for each of a PIRQ for PIC-mode and a
  43  * GSI for APIC-mode are provided.
  44  *
  45  * For APIC mode, only GSIs are supported (`acpi_gsi`).
  46  *
  47  * For PIC mode, if the pirq_map_type is PIRQ_GSI, then `pic_pirq` is used as an
  48  * index into `struct pic_pirq_map.gsi`, or for SOURCE_PATH, `pic_pirq` indexes
  49  * into `struct pic_pirq_map.source_path` to pick the path to the LNKx device.
  50  *
  51  * The reasoning for this structure is related to older vs. newer Intel
  52  * platforms; older platforms supported routing of PCI IRQs to a PIRQ
  53  * only. Newer platforms support routing IRQs to either a PIRQ or (for some PCI
  54  * devices) a non-PIRQ GSI.
  55  */
  56 struct slot_pin_irq_map {
  57         unsigned int slot;
  58         enum pci_pin pin;
  59         /* PIRQ # for PIC mode */
  60         unsigned int pic_pirq;
  61         /* GSI # for APIC mode */
  62         unsigned int apic_gsi;
  63 };
  64
  65 enum pirq_map_type {
  66         PIRQ_GSI,
  67         PIRQ_SOURCE_PATH,
  68 };
  69
  70 /*
  71  * A PIRQ can be either be statically assigned a GSI or OSPM can use the Methods
  72  * on the ACPI device (source_path) to assign IRQs at runtime.
  73  */
  74 struct pic_pirq_map {
  75         enum pirq_map_type type;
  76         union {
  77                 unsigned int gsi[PIRQ_COUNT];
  78                 char source_path[PIRQ_COUNT][DEVICE_PATH_MAX];
  79         };
  80 };
  81
  82 /*
  83  * Generate an ACPI _PRT table by providing PIRQ and/or GSI information for each
  84  * slot/pin combination, and optionally providing paths to LNKx devices that can
  85  * provide IRQs in PIC mode.
  86  */
  87 void intel_write_pci0_PRT(const struct slot_pin_irq_map *pin_irq_map,
  88                           unsigned int map_count,
  89                           const struct pic_pirq_map *pirq_map);
  90
  91 bool is_slot_pin_assigned(const struct slot_pin_irq_map *pin_irq_map,
  92                           unsigned int map_count, unsigned int slot,
  93                           enum pci_pin pin);
  94
  95 #endif