src/southbridge/intel/common/usb_debug.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 // Use simple device model for this file even in ramstage
   4 #define __SIMPLE_DEVICE__
   5
   6 #include <stdint.h>
   7 #include <device/pci_ops.h>
   8 #include <device/pci_ehci.h>
   9 #include <device/pci_def.h>
  10
  11 pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
  12 {
  13         u32 class;
  14         pci_devfn_t dev;
  15
  16         if (!CONFIG(HAVE_USBDEBUG_OPTIONS))
  17                 return PCI_DEV(0, 0x1d, 7);
  18
  19         if (hcd_idx == 2)
  20                 dev = PCI_DEV(0, 0x1a, 0);
  21         else
  22                 dev = PCI_DEV(0, 0x1d, 0);
  23
  24         /* If we enter here before RCBA programming, EHCI function may
  25          * appear with the highest function number instead.
  26          */
  27         class = pci_read_config32(dev, PCI_CLASS_REVISION) >> 8;
  28         if (class != PCI_EHCI_CLASSCODE)
  29                 dev |= PCI_DEV(0, 0, 7);
  30
  31         return dev;
  32 }
  33
  34 /* Required for successful build, but currently empty. */
  35 void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
  36 {
  37         /* Not needed, the ICH* southbridges hardcode physical USB port 1. */
  38 }