soc/intel/pantherlake: Remove soc_info.[hc] interface
[coreboot2.git] / src / southbridge / intel / i82801jx / Kconfig
blob1a6b883c30e0f1bafd09e24c4803dc1e1a909ff1
1 # SPDX-License-Identifier: GPL-2.0-only
3 config SOUTHBRIDGE_INTEL_I82801JX
4         bool
5         select ACPI_COMMON_MADT_IOAPIC
6         select ACPI_COMMON_MADT_LAPIC
7         select ACPI_INTEL_HARDWARE_SLEEP_VALUES
8         select AZALIA_HDA_CODEC_SUPPORT
9         select HAVE_POWER_STATE_AFTER_FAILURE
10         select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
11         select HAVE_SMI_HANDLER
12         select HAVE_USBDEBUG_OPTIONS
13         select INTEL_DESCRIPTOR_MODE_CAPABLE
14         select SOUTHBRIDGE_INTEL_COMMON_GPIO
15         select SOUTHBRIDGE_INTEL_COMMON_PMBASE
16         select SOUTHBRIDGE_INTEL_COMMON_PMCLIB
17         select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
18         select SOUTHBRIDGE_INTEL_COMMON_RESET
19         select SOUTHBRIDGE_INTEL_COMMON_RTC
20         select SOUTHBRIDGE_INTEL_COMMON_SMBUS
21         select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS
22         select SOUTHBRIDGE_INTEL_COMMON_SMM
23         select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9
24         select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG
25         select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG
26         select TCO_SPACE_NOT_YET_SPLIT
27         select USE_WATCHDOG_ON_BOOT
29 if SOUTHBRIDGE_INTEL_I82801JX
31 config EHCI_BAR
32         hex
33         default 0xfef00000
35 config HPET_MIN_TICKS
36         default 0x80
38 ## Some enterprise variants may require an IFD
39 config INTEL_DESCRIPTOR_MODE_REQUIRED
40         bool
41         default n
43 config PCIEXP_HOTPLUG
44         default y
46 endif