src/southbridge/intel/ibexpeak/early_pch.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <arch/io.h>
   4 #include <console/console.h>
   5 #include <device/pci_def.h>
   6 #include <device/pci_ops.h>
   7 #include <device/smbus_host.h>
   8 #include <northbridge/intel/ironlake/ironlake.h>
   9 #include <southbridge/intel/ibexpeak/pch.h>
  10 #include <southbridge/intel/common/gpio.h>
  11
  12 static void early_gpio_init(void)
  13 {
  14         pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1);
  15         pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
  16
  17         setup_pch_gpios(&mainboard_gpio_map);
  18 }
  19
  20 static void pch_default_disable(void)
  21 {
  22         /* Must set BIT0 (hides performance counters PCI device).
  23            coreboot enables the Rate Matching Hub which makes the UHCI PCI
  24            devices disappear, so BIT5-12 and BIT28 can be set to hide those. */
  25         RCBA32(FD) = (1 << 28) | (0xff << 5) | 1;
  26
  27         /* Set reserved bit to 1 */
  28         RCBA32(FD2) = 1;
  29 }
  30
  31 void ibexpeak_setup_bars(void)
  32 {
  33         printk(BIOS_DEBUG, "Setting up static southbridge registers...");
  34         pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1);
  35
  36         pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
  37         /* Enable ACPI BAR */
  38         pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, ACPI_EN);
  39
  40         printk(BIOS_DEBUG, " done.\n");
  41
  42         printk(BIOS_DEBUG, "Disabling Watchdog reboot...");
  43         /* No reset */
  44         RCBA32(GCS) = RCBA32(GCS) | (1 << 5);
  45         /* halt timer */
  46         outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08);
  47         /* halt timer */
  48         outw(inw(DEFAULT_PMBASE | 0x60 | 0x06) | 2, DEFAULT_PMBASE | 0x60 | 0x06);
  49         printk(BIOS_DEBUG, " done.\n");
  50
  51         pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_BASE_ADDRESS_0,
  52                            (uintptr_t)DEFAULT_HECIBAR);
  53         pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_COMMAND,
  54                            PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
  55 }
  56
  57 void early_pch_init(void)
  58 {
  59         early_gpio_init();
  60         enable_smbus();
  61         /* TODO, make this configurable */
  62         pch_setup_cir(IRONLAKE_MOBILE);
  63         southbridge_configure_default_intmap();
  64         pch_default_disable();
  65         early_usb_init(mainboard_usb_ports);
  66 }