src/southbridge/intel/ibexpeak/lpc.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <console/console.h>
   4 #include <device/device.h>
   5 #include <device/pci.h>
   6 #include <device/pci_ids.h>
   7 #include <option.h>
   8 #include <pc80/mc146818rtc.h>
   9 #include <pc80/isa-dma.h>
  10 #include <pc80/i8259.h>
  11 #include <arch/io.h>
  12 #include <device/mmio.h>
  13 #include <device/pci_ops.h>
  14 #include <arch/ioapic.h>
  15 #include <acpi/acpi.h>
  16 #include <elog.h>
  17 #include <acpi/acpigen.h>
  18 #include <cpu/x86/smm.h>
  19 #include "chip.h"
  20 #include "pch.h"
  21 #include <southbridge/intel/common/pciehp.h>
  22 #include <southbridge/intel/common/acpi_pirq_gen.h>
  23 #include <southbridge/intel/common/spi.h>
  24 #include <southbridge/intel/common/rcba_pirq.h>
  25
  26 #define NMI_OFF 0
  27
  28 /**
  29  * Set miscellaneous static southbridge features.
  30  *
  31  * @param dev PCI device with I/O APIC control registers
  32  */
  33 static void pch_enable_ioapic(struct device *dev)
  34 {
  35         /* affirm full set of redirection table entries ("write once") */
  36         ioapic_lock_max_vectors(IO_APIC_ADDR);
  37
  38         register_new_ioapic_gsi0(IO_APIC_ADDR);
  39 }
  40
  41 static void pch_enable_serial_irqs(struct device *dev)
  42 {
  43         /* Set packet length and toggle silent mode bit for one frame. */
  44         pci_write_config8(dev, SERIRQ_CNTL,
  45                           (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
  46 #if !CONFIG(SERIRQ_CONTINUOUS_MODE)
  47         pci_write_config8(dev, SERIRQ_CNTL,
  48                           (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0));
  49 #endif
  50 }
  51
  52 /* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
  53  * 0x00 - 0000 = Reserved
  54  * 0x01 - 0001 = Reserved
  55  * 0x02 - 0010 = Reserved
  56  * 0x03 - 0011 = IRQ3
  57  * 0x04 - 0100 = IRQ4
  58  * 0x05 - 0101 = IRQ5
  59  * 0x06 - 0110 = IRQ6
  60  * 0x07 - 0111 = IRQ7
  61  * 0x08 - 1000 = Reserved
  62  * 0x09 - 1001 = IRQ9
  63  * 0x0A - 1010 = IRQ10
  64  * 0x0B - 1011 = IRQ11
  65  * 0x0C - 1100 = IRQ12
  66  * 0x0D - 1101 = Reserved
  67  * 0x0E - 1110 = IRQ14
  68  * 0x0F - 1111 = IRQ15
  69  * PIRQ[n]_ROUT[7] - PIRQ Routing Control
  70  * 0x80 - The PIRQ is not routed.
  71  */
  72
  73 static void pch_pirq_init(struct device *dev)
  74 {
  75         struct device *irq_dev;
  76         /*
  77          * Interrupt 11 is not used by legacy devices and so can always be used for
  78          * PCI interrupts. Full legacy IRQ routing is complicated and hard to
  79          * get right. Fortunately all modern OS use MSI and so it's not that big of
  80          * an issue anyway. Still we have to provide a reasonable default. Using
  81          * interrupt 11 for it everywhere is a working default. ACPI-aware OS can
  82          * move it to any interrupt and others will just leave them at default.
  83          */
  84         const u8 pirq_routing = 11;
  85
  86         pci_write_config8(dev, PIRQA_ROUT, pirq_routing);
  87         pci_write_config8(dev, PIRQB_ROUT, pirq_routing);
  88         pci_write_config8(dev, PIRQC_ROUT, pirq_routing);
  89         pci_write_config8(dev, PIRQD_ROUT, pirq_routing);
  90
  91         pci_write_config8(dev, PIRQE_ROUT, pirq_routing);
  92         pci_write_config8(dev, PIRQF_ROUT, pirq_routing);
  93         pci_write_config8(dev, PIRQG_ROUT, pirq_routing);
  94         pci_write_config8(dev, PIRQH_ROUT, pirq_routing);
  95
  96         for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
  97                 u8 int_pin=0;
  98
  99                 if (!is_enabled_pci(irq_dev))
 100                         continue;
 101
 102                 int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
 103
 104                 if (int_pin == 0)
 105                         continue;
 106
 107                 pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, pirq_routing);
 108         }
 109 }
 110
 111 static void pch_gpi_routing(struct device *dev)
 112 {
 113         /* Get the chip configuration */
 114         const struct southbridge_intel_ibexpeak_config *config = dev->chip_info;
 115         u32 reg32 = 0;
 116
 117         /* An array would be much nicer here, or some
 118          * other method of doing this.
 119          */
 120         reg32 |= (config->gpi0_routing & 0x03) << 0;
 121         reg32 |= (config->gpi1_routing & 0x03) << 2;
 122         reg32 |= (config->gpi2_routing & 0x03) << 4;
 123         reg32 |= (config->gpi3_routing & 0x03) << 6;
 124         reg32 |= (config->gpi4_routing & 0x03) << 8;
 125         reg32 |= (config->gpi5_routing & 0x03) << 10;
 126         reg32 |= (config->gpi6_routing & 0x03) << 12;
 127         reg32 |= (config->gpi7_routing & 0x03) << 14;
 128         reg32 |= (config->gpi8_routing & 0x03) << 16;
 129         reg32 |= (config->gpi9_routing & 0x03) << 18;
 130         reg32 |= (config->gpi10_routing & 0x03) << 20;
 131         reg32 |= (config->gpi11_routing & 0x03) << 22;
 132         reg32 |= (config->gpi12_routing & 0x03) << 24;
 133         reg32 |= (config->gpi13_routing & 0x03) << 26;
 134         reg32 |= (config->gpi14_routing & 0x03) << 28;
 135         reg32 |= (config->gpi15_routing & 0x03) << 30;
 136
 137         pci_write_config32(dev, GPIO_ROUT, reg32);
 138 }
 139
 140 static void pch_power_options(struct device *dev)
 141 {
 142         u8 reg8;
 143         u16 reg16, pmbase;
 144         u32 reg32;
 145         const char *state;
 146         /* Get the chip configuration */
 147         const struct southbridge_intel_ibexpeak_config *config = dev->chip_info;
 148
 149         /* Which state do we want to goto after g3 (power restored)?
 150          * 0 == S0 Full On
 151          * 1 == S5 Soft Off
 152          *
 153          * If the option is not existent (Laptops), use Kconfig setting.
 154          */
 155         const unsigned int pwr_on = get_uint_option("power_on_after_fail",
 156                                           CONFIG_MAINBOARD_POWER_FAILURE_STATE);
 157
 158         reg16 = pci_read_config16(dev, GEN_PMCON_3);
 159         reg16 &= 0xfffe;
 160         switch (pwr_on) {
 161         case MAINBOARD_POWER_OFF:
 162                 reg16 |= 1;
 163                 state = "off";
 164                 break;
 165         case MAINBOARD_POWER_ON:
 166                 reg16 &= ~1;
 167                 state = "on";
 168                 break;
 169         case MAINBOARD_POWER_KEEP:
 170                 reg16 &= ~1;
 171                 state = "state keep";
 172                 break;
 173         default:
 174                 state = "undefined";
 175         }
 176
 177         reg16 &= ~(3 << 4);     /* SLP_S4# Assertion Stretch 4s */
 178         reg16 |= (1 << 3);      /* SLP_S4# Assertion Stretch Enable */
 179
 180         reg16 &= ~(1 << 10);
 181         reg16 |= (1 << 11);     /* SLP_S3# Min Assertion Width 50ms */
 182
 183         reg16 |= (1 << 12);     /* Disable SLP stretch after SUS well */
 184
 185         pci_write_config16(dev, GEN_PMCON_3, reg16);
 186         printk(BIOS_INFO, "Set power %s after power failure.\n", state);
 187
 188         /* Set up NMI on errors. */
 189         reg8 = inb(0x61);
 190         reg8 &= 0x0f;           /* Higher Nibble must be 0 */
 191         reg8 &= ~(1 << 3);      /* IOCHK# NMI Enable */
 192         // reg8 &= ~(1 << 2);   /* PCI SERR# Enable */
 193         reg8 |= (1 << 2); /* PCI SERR# Disable for now */
 194         outb(reg8, 0x61);
 195
 196         reg8 = inb(0x70);
 197         const unsigned int nmi_option = get_uint_option("nmi", NMI_OFF);
 198         if (nmi_option) {
 199                 printk(BIOS_INFO, "NMI sources enabled.\n");
 200                 reg8 &= ~(1 << 7);      /* Set NMI. */
 201         } else {
 202                 printk(BIOS_INFO, "NMI sources disabled.\n");
 203                 reg8 |= (1 << 7);       /* Can't mask NMI from PCI-E and NMI_NOW */
 204         }
 205         outb(reg8, 0x70);
 206
 207         /* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */
 208         reg16 = pci_read_config16(dev, GEN_PMCON_1);
 209         reg16 &= ~(3 << 0);     // SMI# rate 1 minute
 210         reg16 &= ~(1 << 10);    // Disable BIOS_PCI_EXP_EN for native PME
 211         if (CONFIG(DEBUG_PERIODIC_SMI))
 212                 reg16 |= (3 << 0); // Periodic SMI every 8s
 213         pci_write_config16(dev, GEN_PMCON_1, reg16);
 214
 215         // Set the board's GPI routing.
 216         pch_gpi_routing(dev);
 217
 218         pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
 219
 220         outl(config->gpe0_en, pmbase + GPE0_EN);
 221         outw(config->alt_gp_smi_en, pmbase + ALT_GP_SMI_EN);
 222
 223         /* Set up power management block and determine sleep mode */
 224         reg32 = inl(pmbase + 0x04); // PM1_CNT
 225         reg32 &= ~(7 << 10);    // SLP_TYP
 226         reg32 |= (1 << 0);      // SCI_EN
 227         outl(reg32, pmbase + 0x04);
 228
 229         /* Clear magic status bits to prevent unexpected wake */
 230         reg32 = RCBA32(PRSTS);
 231         reg32 |= (1 << 5) | (1 << 4) | (1 << 0);
 232         RCBA32(PRSTS) = reg32;
 233
 234         /* FIXME: Does this even exist? */
 235         reg32 = RCBA32(0x3f02);
 236         reg32 &= ~0xf;
 237         RCBA32(0x3f02) = reg32;
 238 }
 239
 240 static void pch_rtc_init(struct device *dev)
 241 {
 242         u8 reg8;
 243         int rtc_failed;
 244
 245         reg8 = pci_read_config8(dev, GEN_PMCON_3);
 246         rtc_failed = reg8 & RTC_BATTERY_DEAD;
 247         if (rtc_failed) {
 248                 reg8 &= ~RTC_BATTERY_DEAD;
 249                 pci_write_config8(dev, GEN_PMCON_3, reg8);
 250                 elog_add_event(ELOG_TYPE_RTC_RESET);
 251         }
 252         printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
 253
 254         cmos_init(rtc_failed);
 255 }
 256
 257 static void mobile5_pm_init(struct device *dev)
 258 {
 259         int i;
 260
 261         printk(BIOS_DEBUG, "Mobile 5 PM init\n");
 262         pci_write_config8(dev, 0xa9, 0x47);
 263
 264         RCBA32(0x1d44) = 0x00000000;
 265         (void)RCBA32(0x1d44);
 266         RCBA32(0x1d48) = 0x00030000;
 267         (void)RCBA32(0x1d48);
 268
 269         const u32 rcba2010[] = {
 270                 /* 2010: */ 0x00188200, 0x14000016, 0xbc4abcb5, 0x00000000,
 271                 /* 2020: */ 0xf0c9605b, 0x13683040, 0x04c8f16e, 0x09e90170
 272         };
 273         for (i = 0; i < ARRAY_SIZE(rcba2010); i++) {
 274                 RCBA32(0x2010 + 4 * i) = rcba2010[i];
 275                 RCBA32(0x2010 + 4 * i);
 276         }
 277
 278         RCBA32(0x2100) = 0x00000000;
 279         (void)RCBA32(0x2100);
 280         RCBA32(0x2104) = 0x00000757;
 281         (void)RCBA32(0x2104);
 282         RCBA32(0x2108) = 0x00170001;
 283         (void)RCBA32(0x2108);
 284
 285         RCBA32(0x211c) = 0x00000000;
 286         (void)RCBA32(0x211c);
 287         RCBA32(0x2120) = 0x00010000;
 288         (void)RCBA32(0x2120);
 289
 290         RCBA32(0x21fc) = 0x00000000;
 291         (void)RCBA32(0x21fc);
 292         RCBA32(0x2200) = 0x20000044;
 293         (void)RCBA32(0x2200);
 294         RCBA32(0x2204) = 0x00000001;
 295         (void)RCBA32(0x2204);
 296         RCBA32(0x2208) = 0x00003457;
 297         (void)RCBA32(0x2208);
 298
 299         const u32 rcba2210[] = {
 300                 /* 2210 */ 0x00000000, 0x00000001, 0xa0fff210, 0x0000df00,
 301                 /* 2220 */ 0x00e30880, 0x00000070, 0x00004000, 0x00000000,
 302                 /* 2230 */ 0x00e30880, 0x00000070, 0x00004000, 0x00000000,
 303                 /* 2240 */ 0x00002301, 0x36000000, 0x00010107, 0x00160000,
 304                 /* 2250 */ 0x00001b01, 0x36000000, 0x00010107, 0x00160000,
 305                 /* 2260 */ 0x00000601, 0x16000000, 0x00010107, 0x00160000,
 306                 /* 2270 */ 0x00001c01, 0x16000000, 0x00010107, 0x00160000
 307         };
 308
 309         for (i = 0; i < ARRAY_SIZE(rcba2210); i++) {
 310                 RCBA32(0x2210 + 4 * i) = rcba2210[i];
 311                 RCBA32(0x2210 + 4 * i);
 312         }
 313
 314         const u32 rcba2300[] = {
 315                 /* 2300: */ 0x00000000, 0x40000000, 0x4646827b, 0x6e803131,
 316                 /* 2310: */ 0x32c77887, 0x00077733, 0x00007447, 0x00000040,
 317                 /* 2320: */ 0xcccc0cfc, 0x0fbb0fff
 318         };
 319
 320         for (i = 0; i < ARRAY_SIZE(rcba2300); i++) {
 321                 RCBA32(0x2300 + 4 * i) = rcba2300[i];
 322                 RCBA32(0x2300 + 4 * i);
 323         }
 324
 325         RCBA32(0x37fc) = 0x00000000;
 326         (void)RCBA32(0x37fc);
 327         RCBA32(0x3dfc) = 0x00000000;
 328         (void)RCBA32(0x3dfc);
 329         RCBA32(0x3e7c) = 0xffffffff;
 330         (void)RCBA32(0x3e7c);
 331         RCBA32(0x3efc) = 0x00000000;
 332         (void)RCBA32(0x3efc);
 333         RCBA32(0x3f00) = 0x0000010b;
 334         (void)RCBA32(0x3f00);
 335 }
 336
 337 static void enable_hpet(void)
 338 {
 339         u32 reg32;
 340
 341         /* Move HPET to default address 0xfed00000 and enable it */
 342         reg32 = RCBA32(HPTC);
 343         reg32 |= (1 << 7); // HPET Address Enable
 344         reg32 &= ~(3 << 0);
 345         RCBA32(HPTC) = reg32;
 346         RCBA32(HPTC); /* Read back for it to work */
 347
 348         write32((u32 *)0xfed00010, read32((u32 *)0xfed00010) | 1);
 349 }
 350
 351 static void enable_clock_gating(struct device *dev)
 352 {
 353         u32 reg32;
 354         u16 reg16;
 355
 356         RCBA32_AND_OR(0x2234, ~0UL, 0xf);
 357
 358         reg16 = pci_read_config16(dev, GEN_PMCON_1);
 359         reg16 |= (1 << 2) | (1 << 11);
 360         pci_write_config16(dev, GEN_PMCON_1, reg16);
 361
 362         reg32 = RCBA32(CG);
 363         reg32 |= (1 << 31);
 364         reg32 |= (1 << 29) | (1 << 28);
 365         reg32 |= (1 << 27) | (1 << 26) | (1 << 25) | (1 << 24);
 366         reg32 |= (1 << 16);
 367         reg32 |= (1 << 17);
 368         reg32 |= (1 << 18);
 369         reg32 |= (1 << 22);
 370         reg32 |= (1 << 23);
 371         reg32 &= ~(1 << 20);
 372         reg32 |= (1 << 19);
 373         reg32 |= (1 << 0);
 374         reg32 |= (0xf << 1);
 375         RCBA32(CG) = reg32;
 376
 377         RCBA32_OR(0x38c0, 0x7);
 378         RCBA32_OR(0x36d4, 0x6680c004);
 379         RCBA32_OR(0x3564, 0x3);
 380 }
 381
 382 static void pch_set_acpi_mode(void)
 383 {
 384         if (!acpi_is_wakeup_s3()) {
 385                 apm_control(APM_CNT_ACPI_DISABLE);
 386         }
 387 }
 388
 389 static void pch_fixups(struct device *dev)
 390 {
 391         /*
 392          * Enable DMI ASPM in the PCH
 393          */
 394         RCBA32_AND_OR(0x2304, ~(1 << 10), 0);
 395         RCBA32_OR(0x21a4, (1 << 11)|(1 << 10));
 396         RCBA32_OR(0x21a8, 0x3);
 397 }
 398
 399 static void lpc_init(struct device *dev)
 400 {
 401         printk(BIOS_DEBUG, "pch: %s\n", __func__);
 402
 403         /* IO APIC initialization. */
 404         pch_enable_ioapic(dev);
 405
 406         pch_enable_serial_irqs(dev);
 407
 408         /* Setup the PIRQ. */
 409         pch_pirq_init(dev);
 410
 411         /* Setup power options. */
 412         pch_power_options(dev);
 413
 414         /* Initialize power management */
 415         mobile5_pm_init(dev);
 416
 417         /* Initialize the real time clock. */
 418         pch_rtc_init(dev);
 419
 420         /* Initialize ISA DMA. */
 421         isa_dma_init();
 422
 423         /* Initialize the High Precision Event Timers, if present. */
 424         enable_hpet();
 425
 426         /* Initialize Clock Gating */
 427         enable_clock_gating(dev);
 428
 429         setup_i8259();
 430
 431         /* The OS should do this? */
 432         /* Interrupt 9 should be level triggered (SCI) */
 433         i8259_configure_irq_trigger(9, 1);
 434
 435         pch_set_acpi_mode();
 436
 437         pch_fixups(dev);
 438 }
 439
 440 static void pch_lpc_read_resources(struct device *dev)
 441 {
 442         struct resource *res;
 443         const struct southbridge_intel_ibexpeak_config *config = dev->chip_info;
 444         u8 io_index = 0;
 445
 446         /* Get the normal PCI resources of this device. */
 447         pci_dev_read_resources(dev);
 448
 449         /* Add an extra subtractive resource for both memory and I/O. */
 450         res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
 451         res->base = 0;
 452         res->size = 0x1000;
 453         res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
 454                      IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 455
 456         res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
 457         res->base = 0xff800000;
 458         res->size = 0x00800000; /* 8 MB for flash */
 459         res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
 460                      IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 461
 462         res = new_resource(dev, 3); /* IOAPIC */
 463         res->base = IO_APIC_ADDR;
 464         res->size = 0x00001000;
 465         res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 466
 467         /* Set PCH IO decode ranges if required.*/
 468         if ((config->gen1_dec & 0xFFFC) > 0x1000) {
 469                 res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
 470                 res->base = config->gen1_dec & 0xFFFC;
 471                 res->size = (config->gen1_dec >> 16) & 0xFC;
 472                 res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
 473                                  IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 474         }
 475
 476         if ((config->gen2_dec & 0xFFFC) > 0x1000) {
 477                 res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
 478                 res->base = config->gen2_dec & 0xFFFC;
 479                 res->size = (config->gen2_dec >> 16) & 0xFC;
 480                 res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
 481                                  IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 482         }
 483
 484         if ((config->gen3_dec & 0xFFFC) > 0x1000) {
 485                 res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
 486                 res->base = config->gen3_dec & 0xFFFC;
 487                 res->size = (config->gen3_dec >> 16) & 0xFC;
 488                 res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
 489                                  IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 490         }
 491
 492         if ((config->gen4_dec & 0xFFFC) > 0x1000) {
 493                 res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
 494                 res->base = config->gen4_dec & 0xFFFC;
 495                 res->size = (config->gen4_dec >> 16) & 0xFC;
 496                 res->flags = IORESOURCE_IO| IORESOURCE_SUBTRACTIVE |
 497                                  IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 498         }
 499 }
 500
 501 static void pch_lpc_enable(struct device *dev)
 502 {
 503         /* Enable PCH Display Port */
 504         RCBA16(DISPBDF) = 0x0010;
 505         RCBA32_OR(FD2, PCH_ENABLE_DBDF);
 506
 507         pch_enable(dev);
 508 }
 509
 510 static const char *lpc_acpi_name(const struct device *dev)
 511 {
 512         return "LPCB";
 513 }
 514
 515 static void southbridge_fill_ssdt(const struct device *device)
 516 {
 517         struct device *dev = pcidev_on_root(0x1f, 0);
 518         struct southbridge_intel_ibexpeak_config *chip = dev->chip_info;
 519
 520         intel_acpi_pcie_hotplug_generator(chip->pcie_hotplug_map, 8);
 521         intel_acpi_gen_def_acpi_pirq(dev);
 522 }
 523
 524 static void lpc_final(struct device *dev)
 525 {
 526         spi_finalize_ops();
 527
 528         /* Call SMM finalize() handlers before resume */
 529         if (CONFIG(INTEL_CHIPSET_LOCKDOWN) ||
 530             acpi_is_wakeup_s3()) {
 531                 apm_control(APM_CNT_FINALIZE);
 532         }
 533 }
 534
 535 static struct device_operations device_ops = {
 536         .read_resources         = pch_lpc_read_resources,
 537         .set_resources          = pci_dev_set_resources,
 538         .enable_resources       = pci_dev_enable_resources,
 539         .acpi_fill_ssdt         = southbridge_fill_ssdt,
 540         .acpi_name              = lpc_acpi_name,
 541         .write_acpi_tables      = acpi_write_hpet,
 542         .init                   = lpc_init,
 543         .final                  = lpc_final,
 544         .enable                 = pch_lpc_enable,
 545         .scan_bus               = scan_static_bus,
 546         .ops_pci                = &pci_dev_ops_pci,
 547 };
 548
 549 static const unsigned short pci_device_ids[] = {
 550         PCI_DID_INTEL_IBEXPEAK_LPC_P55,
 551         PCI_DID_INTEL_IBEXPEAK_LPC_PM55,
 552         PCI_DID_INTEL_IBEXPEAK_LPC_H55,
 553         PCI_DID_INTEL_IBEXPEAK_LPC_QM57,
 554         PCI_DID_INTEL_IBEXPEAK_LPC_H57,
 555         PCI_DID_INTEL_IBEXPEAK_LPC_HM55,
 556         PCI_DID_INTEL_IBEXPEAK_LPC_Q57,
 557         PCI_DID_INTEL_IBEXPEAK_LPC_HM57,
 558         PCI_DID_INTEL_IBEXPEAK_LPC_QS57,
 559         PCI_DID_INTEL_IBEXPEAK_LPC_3400,
 560         PCI_DID_INTEL_IBEXPEAK_LPC_3420,
 561         PCI_DID_INTEL_IBEXPEAK_LPC_3450,
 562         0
 563 };
 564
 565 static const struct pci_driver pch_lpc __pci_driver = {
 566         .ops     = &device_ops,
 567         .vendor  = PCI_VID_INTEL,
 568         .devices = pci_device_ids,
 569 };