src/southbridge/intel/lynxpoint/sata.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/mmio.h>
   4 #include <device/pci_ops.h>
   5 #include <console/console.h>
   6 #include <device/device.h>
   7 #include <device/pci.h>
   8 #include <device/pci_ids.h>
   9 #include <delay.h>
  10 #include "chip.h"
  11 #include "iobp.h"
  12 #include "pch.h"
  13
  14 #if CONFIG(INTEL_LYNXPOINT_LP)
  15 #define SATA_PORT_MASK  0x0f
  16 #else
  17 #define SATA_PORT_MASK  0x3f
  18 #endif
  19
  20 static inline u32 sir_read(struct device *dev, int idx)
  21 {
  22         pci_write_config32(dev, SATA_SIRI, idx);
  23         return pci_read_config32(dev, SATA_SIRD);
  24 }
  25
  26 static inline void sir_write(struct device *dev, int idx, u32 value)
  27 {
  28         pci_write_config32(dev, SATA_SIRI, idx);
  29         pci_write_config32(dev, SATA_SIRD, value);
  30 }
  31
  32 static inline void sir_unset_and_set_mask(struct device *dev, int idx, u32 unset, u32 set)
  33 {
  34         pci_write_config32(dev, SATA_SIRI, idx);
  35
  36         const u32 value = pci_read_config32(dev, SATA_SIRD) & ~unset;
  37         pci_write_config32(dev, SATA_SIRD, value | set);
  38 }
  39
  40 static void sata_init(struct device *dev)
  41 {
  42         u32 reg32;
  43
  44         u32 *abar;
  45
  46         /* Get the chip configuration */
  47         struct southbridge_intel_lynxpoint_config *config = dev->chip_info;
  48
  49         printk(BIOS_DEBUG, "SATA: Initializing...\n");
  50
  51         if (config == NULL) {
  52                 printk(BIOS_ERR, "SATA: ERROR: Device not in devicetree.cb!\n");
  53                 return;
  54         }
  55
  56         /* SATA configuration */
  57
  58         /* Enable memory space decoding for ABAR */
  59         pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
  60
  61         printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n");
  62
  63         /* Set Interrupt Line */
  64         /* Interrupt Pin is set by D31IP.PIP */
  65         pci_write_config8(dev, PCI_INTERRUPT_LINE, 0x0a);
  66
  67         pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE);
  68         pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE);
  69
  70         /* for AHCI, Port Enable is managed in memory mapped space */
  71         pci_update_config16(dev, 0x92, ~SATA_PORT_MASK, 0x8000 | config->sata_port_map);
  72         udelay(2);
  73
  74         /* Setup register 98h */
  75         reg32 = pci_read_config32(dev, 0x98);
  76         reg32 |= 1 << 19;    /* BWG step 6 */
  77         reg32 |= 1 << 22;    /* BWG step 5 */
  78         reg32 &= ~(0x3f << 7);
  79         reg32 |= 0x04 << 7;  /* BWG step 7 */
  80         reg32 |= 1 << 20;    /* BWG step 8 */
  81         reg32 &= ~(0x03 << 5);
  82         reg32 |= 1 << 5;     /* BWG step 9 */
  83         reg32 |= 1 << 18;    /* BWG step 10 */
  84         reg32 |= 1 << 29;    /* BWG step 11 */
  85         if (pch_is_lp()) {
  86                 reg32 &= ~((1 << 31) | (1 << 30));
  87                 reg32 |= 1 << 23;
  88                 reg32 |= 1 << 24; /* Disable listen mode (hotplug) */
  89         }
  90         pci_write_config32(dev, 0x98, reg32);
  91
  92         /* Setup register 9Ch: Disable alternate ID and BWG step 12 */
  93         pci_write_config16(dev, 0x9c, 1 << 5);
  94
  95         /* SATA Initialization register */
  96         reg32 = 0x183;
  97         reg32 |= (config->sata_port_map ^ SATA_PORT_MASK) << 24;
  98         reg32 |= (config->sata_devslp_mux & 1) << 15;
  99         pci_write_config32(dev, 0x94, reg32);
 100
 101         /* Initialize AHCI memory-mapped space */
 102         abar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
 103         printk(BIOS_DEBUG, "ABAR: %p\n", abar);
 104         /* CAP (HBA Capabilities) : enable power management */
 105         reg32 = read32(abar + 0x00);
 106         reg32 |= 0x0c006000;  // set PSC+SSC+SALP+SSS
 107         reg32 &= ~0x00020060; // clear SXS+EMS+PMS
 108         if (pch_is_lp())
 109                 reg32 |= (1 << 18);   // SAM: SATA AHCI MODE ONLY
 110         write32(abar + 0x00, reg32);
 111         /* PI (Ports implemented) */
 112         write32(abar + 0x03, config->sata_port_map);
 113         (void)read32(abar + 0x03); /* Read back 1 */
 114         (void)read32(abar + 0x03); /* Read back 2 */
 115         /* CAP2 (HBA Capabilities Extended)*/
 116         reg32 = read32(abar + 0x09);
 117         /* Enable DEVSLP */
 118         if (pch_is_lp()) {
 119                 if (config->sata_devslp_disable)
 120                         reg32 &= ~(1 << 3);
 121                 else
 122                         reg32 |= (1 << 5)|(1 << 4)|(1 << 3)|(1 << 2);
 123         } else {
 124                 reg32 &= ~0x00000002;
 125         }
 126         write32(abar + 0x09, reg32);
 127
 128         /* Set Gen3 Transmitter settings if needed */
 129         if (config->sata_port0_gen3_tx)
 130                 pch_iobp_update(SATA_IOBP_SP0G3IR, 0,
 131                                 config->sata_port0_gen3_tx);
 132
 133         if (config->sata_port1_gen3_tx)
 134                 pch_iobp_update(SATA_IOBP_SP1G3IR, 0,
 135                                 config->sata_port1_gen3_tx);
 136
 137         /* Set Gen3 DTLE DATA / EDGE registers if needed */
 138         if (config->sata_port0_gen3_dtle) {
 139                 pch_iobp_update(SATA_IOBP_SP0DTLE_DATA,
 140                                 ~(SATA_DTLE_MASK << SATA_DTLE_DATA_SHIFT),
 141                                 (config->sata_port0_gen3_dtle & SATA_DTLE_MASK)
 142                                 << SATA_DTLE_DATA_SHIFT);
 143
 144                 pch_iobp_update(SATA_IOBP_SP0DTLE_EDGE,
 145                                 ~(SATA_DTLE_MASK << SATA_DTLE_EDGE_SHIFT),
 146                                 (config->sata_port0_gen3_dtle & SATA_DTLE_MASK)
 147                                 << SATA_DTLE_EDGE_SHIFT);
 148         }
 149
 150         if (config->sata_port1_gen3_dtle) {
 151                 pch_iobp_update(SATA_IOBP_SP1DTLE_DATA,
 152                                 ~(SATA_DTLE_MASK << SATA_DTLE_DATA_SHIFT),
 153                                 (config->sata_port1_gen3_dtle & SATA_DTLE_MASK)
 154                                 << SATA_DTLE_DATA_SHIFT);
 155
 156                 pch_iobp_update(SATA_IOBP_SP1DTLE_EDGE,
 157                                 ~(SATA_DTLE_MASK << SATA_DTLE_EDGE_SHIFT),
 158                                 (config->sata_port1_gen3_dtle & SATA_DTLE_MASK)
 159                                 << SATA_DTLE_EDGE_SHIFT);
 160         }
 161
 162         /* Additional Programming Requirements */
 163         /* Power Optimizer */
 164
 165         /* Step 1 */
 166         if (pch_is_lp())
 167                 sir_write(dev, 0x64, 0x883c9003);
 168         else
 169                 sir_write(dev, 0x64, 0x883c9001);
 170
 171         /* Step 2: SIR 68h[15:0] = 880Ah */
 172         sir_unset_and_set_mask(dev, 0x68, 0xffff, 0x880a);
 173
 174         /* Step 3: SIR 60h[3] = 1 */
 175         sir_unset_and_set_mask(dev, 0x60, 0, 1 << 3);
 176
 177         /* Step 4: SIR 60h[0] = 1 */
 178         sir_unset_and_set_mask(dev, 0x60, 0, 1 << 0);
 179
 180         /* Step 5: SIR 60h[1] = 1 */
 181         sir_unset_and_set_mask(dev, 0x60, 0, 1 << 1);
 182
 183         /* Clock Gating */
 184         sir_write(dev, 0x70, 0x3f00bf1f);
 185         if (pch_is_lp()) {
 186                 sir_write(dev, 0x54, 0xcf000f0f);
 187                 sir_write(dev, 0x58, 0x00190000);
 188                 RCBA32_AND_OR(0x333c, 0xffcfffff, 0x00c00000);
 189         }
 190
 191         reg32 = pci_read_config32(dev, 0x300);
 192         reg32 |= (1 << 17) | (1 << 16);
 193         reg32 |= (1 << 31) | (1 << 30) | (1 << 29);
 194         pci_write_config32(dev, 0x300, reg32);
 195 }
 196
 197 static void sata_enable(struct device *dev)
 198 {
 199         /* Get the chip configuration */
 200         struct southbridge_intel_lynxpoint_config *config = dev->chip_info;
 201
 202         if (!config)
 203                 return;
 204
 205         /*
 206          * Set SATA controller mode early so the resource allocator can
 207          * properly assign IO/Memory resources for the controller.
 208          */
 209         pci_write_config16(dev, 0x90, 0x0060 | (config->sata_port_map ^ SATA_PORT_MASK) << 8);
 210 }
 211
 212 static struct device_operations sata_ops = {
 213         .read_resources         = pci_dev_read_resources,
 214         .set_resources          = pci_dev_set_resources,
 215         .enable_resources       = pci_dev_enable_resources,
 216         .init                   = sata_init,
 217         .enable                 = sata_enable,
 218         .ops_pci                = &pci_dev_ops_pci,
 219 };
 220
 221 static const unsigned short pci_device_ids[] = {
 222         PCI_DID_INTEL_LPT_H_DESKTOP_SATA_IDE,
 223         PCI_DID_INTEL_LPT_H_DESKTOP_SATA_AHCI,
 224         PCI_DID_INTEL_LPT_H_DESKTOP_SATA_RAID_1,
 225         PCI_DID_INTEL_LPT_H_DESKTOP_SATA_RAID_PREM,
 226         PCI_DID_INTEL_LPT_H_DESKTOP_SATA_IDE_P45,
 227         PCI_DID_INTEL_LPT_H_DESKTOP_SATA_RAID_2,
 228         PCI_DID_INTEL_LPT_H_MOBILE_SATA_IDE,
 229         PCI_DID_INTEL_LPT_H_MOBILE_SATA_AHCI,
 230         PCI_DID_INTEL_LPT_H_MOBILE_SATA_RAID_1,
 231         PCI_DID_INTEL_LPT_H_MOBILE_SATA_RAID_PREM,
 232         PCI_DID_INTEL_LPT_H_MOBILE_SATA_IDE_P45,
 233         PCI_DID_INTEL_LPT_H_MOBILE_SATA_RAID_2,
 234         PCI_DID_INTEL_LPT_H_DESKTOP_SATA_IDE_9,
 235         PCI_DID_INTEL_LPT_H_DESKTOP_SATA_AHCI_9,
 236         PCI_DID_INTEL_LPT_H_DESKTOP_SATA_RAID_1_9,
 237         PCI_DID_INTEL_LPT_H_DESKTOP_SATA_RAID_PREM_9,
 238         PCI_DID_INTEL_LPT_H_DESKTOP_SATA_IDE_P45_9,
 239         PCI_DID_INTEL_LPT_H_DESKTOP_SATA_RAID_2_9,
 240         PCI_DID_INTEL_LPT_H_MOBILE_SATA_IDE_9,
 241         PCI_DID_INTEL_LPT_H_MOBILE_SATA_AHCI_9,
 242         PCI_DID_INTEL_LPT_H_MOBILE_SATA_RAID_1_9,
 243         PCI_DID_INTEL_LPT_H_MOBILE_SATA_RAID_PREM_9,
 244         PCI_DID_INTEL_LPT_H_MOBILE_SATA_IDE_P45_9,
 245         PCI_DID_INTEL_LPT_H_MOBILE_SATA_RAID_2_9,
 246         PCI_DID_INTEL_LPT_LP_SATA_AHCI,
 247         PCI_DID_INTEL_LPT_LP_SATA_RAID_1,
 248         PCI_DID_INTEL_LPT_LP_SATA_RAID_PREM,
 249         PCI_DID_INTEL_LPT_LP_SATA_RAID_2,
 250         0
 251 };
 252
 253 static const struct pci_driver pch_sata __pci_driver = {
 254         .ops     = &sata_ops,
 255         .vendor  = PCI_VID_INTEL,
 256         .devices = pci_device_ids,
 257 };