| commit | 77f6682b95f45716f7ccf8ac8f1fa569a118b6e7 | |
| author | Rui Zhou <zhourui@huaqin.corp-partner.google.com> | |
| Tue, 5 Nov 2024 06:42:02 +0000 (5 14:42 +0800) | ||
| committer | Subrata Banik <subratabanik@google.com> | |
| Thu, 7 Nov 2024 04:15:06 +0000 (7 04:15 +0000) | ||
| tree | ed84d0d8015310262c4cfb1abb1d66323015d91d | treesnapshot (tar.gz zip) |
| parent | 7d8e105420c3d8fc7385cd9ad634fd4e130030b7 | commitdiff |
mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3
The previous GPIO config will cause the SSD device to not be recognized. Based on schematics NB7559_MB_SCH_V1_2024_1010.pdf. So we adjust the position of the enable and reset pins.
BUG=b:374629673
BRANCH=None
TEST=1. emerge-nissa coreboot chromeos-bootimage
2. power on proto board successfully
Change-Id: Idb36f67206450612655cb3efd3cce240475ef3ab
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
The previous GPIO config will cause the SSD device to not be recognized. Based on schematics NB7559_MB_SCH_V1_2024_1010.pdf. So we adjust the position of the enable and reset pins.
BUG=b:374629673
BRANCH=None
TEST=1. emerge-nissa coreboot chromeos-bootimage
2. power on proto board successfully
Change-Id: Idb36f67206450612655cb3efd3cce240475ef3ab
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
| src/mainboard/google/brya/variants/rull/gpio.c | diffblobblamehistory | |
| src/mainboard/google/brya/variants/rull/overridetree.cb | diffblobblamehistory |