mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3

[coreboot2.git] / src / mainboard / google / brya / variants / rull / overridetree.cb

fw_config
        field THERMAL 18 18
                option THERMAL_6W                0
                option THERMAL_15W               1
        end
        field WIFI 8 9
                option WIFI_CNVI_WIFI6E         0
                option WIFI_PCIE_WIFI7          1
        end

end

chip soc/intel/alderlake
        register "sagv" = "SaGv_Enabled"

        # EMMC Tx CMD Delay
        # Refer to EDS-Vol2-42.3.7.
        # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39.
        # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39.
        register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505"

        # EMMC TX DATA Delay 1
        # Refer to EDS-Vol2-42.3.8.
        # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78.
        # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79.
        register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909"

        # EMMC TX DATA Delay 2
        # Refer to EDS-Vol2-42.3.9.
        # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79.
        # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
        # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79.
        # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79.
        register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828"

        # EMMC RX CMD/DATA Delay 1
        # Refer to EDS-Vol2-42.3.10.
        # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119.
        # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
        # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119.
        # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119.
        register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B"

        # EMMC RX CMD/DATA Delay 2
        # Refer to EDS-Vol2-42.3.12.
        # [17:16] stands for Rx Clock before Output Buffer,
        #         00: Rx clock after output buffer,
        #         01: Rx clock before output buffer,
        #         10: Automatic selection based on working mode.
        #         11: Reserved
        # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39.
        # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79.
        register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1004C"

        # EMMC Rx Strobe Delay
        # Refer to EDS-Vol2-42.3.11.
        # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39.
        # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39.
        register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x01515"

        # SOC Aux orientation override:
        # This is a bitfield that corresponds to up to 4 TCSS ports.
        # Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2.
        # TcssAuxOri = 0100b
        # Bit0 set to "0" indicates has retimer on USBC Port0, on the DB.
        # Bit2 set to "1" indicates no retimer on USBC Port1, on the MB.
        # Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the
        # motherboard to USBC connector
        register "tcss_aux_ori" = "5"

        register "typec_aux_bias_pads[0]" = "{
                .pad_auxp_dc = GPP_A19,
                .pad_auxn_dc = GPP_A20
        }"

        register "typec_aux_bias_pads[1]" = "{
                .pad_auxp_dc = GPP_E22,
                .pad_auxn_dc = GPP_E23
        }"

        # FIVR configurations for rull are disabled since the board doesn't have V1p05 and Vnn
        # bypass rails implemented.
        register "ext_fivr_settings" = "{
                .configure_ext_fivr = 0,
        }"

        # Enable the Cnvi BT Audio Offload
        register "cnvi_bt_audio_offload" = "1"

        # Intel Common SoC Config
        #+-------------+------------------------------+
        #| Field        |  Value                        |
        #+-------------+------------------------------+
        #| I2C0 | TPM. Early init is            |
        #|              | required to set up a BAR      |
        #|              | for TPM communication |
        #| I2C1 | Touchscreen                   |
        #| I2C3 | Audio                 |
        #| I2C5 | Trackpad                      |
        #+-------------+------------------------------+
        register "common_soc_config" = "{
                .i2c[0] = {
                        .early_init = 1,
                        .speed = I2C_SPEED_FAST_PLUS,
                        .speed_config[0] = {
                                .speed = I2C_SPEED_FAST_PLUS,
                                .scl_lcnt = 55,
                                .scl_hcnt = 30,
                                .sda_hold = 7,
                        }
                },
                .i2c[1] = {
                        .speed = I2C_SPEED_FAST,
                        .speed_config[0] = {
                                .speed = I2C_SPEED_FAST,
                                .scl_lcnt = 160,
                                .scl_hcnt = 79,
                                .sda_hold = 7,
                        }
                },
                .i2c[3] = {
                        .speed = I2C_SPEED_FAST,
                        .speed_config[0] = {
                                .speed = I2C_SPEED_FAST,
                                .scl_lcnt = 157,
                                .scl_hcnt = 79,
                                .sda_hold = 7,
                        }
                },
                .i2c[5] = {
                        .speed = I2C_SPEED_FAST,
                        .speed_config[0] = {
                                .speed = I2C_SPEED_FAST,
                                .scl_lcnt = 152,
                                .scl_hcnt = 79,
                                .sda_hold = 7,
                        }
                },
        }"

        # Power limit config
        register "power_limits_config[ADL_N_041_6W_CORE]" = "{
                .tdp_pl1_override = 15,
                .tdp_pl2_override = 25,
                .tdp_pl4 = 78,
        }"

        device domain 0 on
                device ref dtt on
                        chip drivers/intel/dptf
                                ## sensor information
                                register "options.tsr[0].desc" = ""CPU_VR""
                                register "options.tsr[1].desc" = ""CPU""
                                register "options.tsr[2].desc" = ""Ambient""
                                register "options.tsr[3].desc" = ""Charger""

                                # TODO: below values are initial reference values only
                                ## Passive Policy
                                register "policies.passive" = "{
                                        [0] = DPTF_PASSIVE(CPU,         CPU,            95, 5000),
                                        [1] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_0,  75, 5000),
                                        [2] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_1,  75, 5000),
                                        [3] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_2,  75, 5000),
                                        [4] = DPTF_PASSIVE(CHARGER,     TEMP_SENSOR_3,  75, 5000),
                                }"

                                ## Critical Policy
                                register "policies.critical" = "{
                                        [0] = DPTF_CRITICAL(TEMP_SENSOR_1,      100, SHUTDOWN),
                                        [1] = DPTF_CRITICAL(TEMP_SENSOR_2,      80, SHUTDOWN),
                                }"

                                register "controls.power_limits" = "{
                                        .pl1 = {
                                                        .min_power = 6000,
                                                        .max_power = 15000,
                                                        .time_window_min = 28 * MSECS_PER_SEC,
                                                        .time_window_max = 32 * MSECS_PER_SEC,
                                                        .granularity = 200
                                                },
                                        .pl2 = {
                                                        .min_power = 25000,
                                                        .max_power = 25000,
                                                        .time_window_min = 28 * MSECS_PER_SEC,
                                                        .time_window_max = 32 * MSECS_PER_SEC,
                                                        .granularity = 1000
                                                }
                                }"

                                ## Charger Performance Control (Control, mA)
                                register "controls.charger_perf" = "{
                                        [0] = { 255, 3000 },
                                        [1] = {  24, 1500 },
                                        [2] = {  16, 1000 },
                                        [3] = {   8,  500 }
                                }"

                                device generic 0 on end
                        end
                end
                device ref igpu on
                        chip drivers/gfx/generic
                                register "device_count" = "4"
                                # DDIA for eDP
                                register "device[0].name" = ""LCD0""
                                # Internal panel on the first port of the graphics chip
                                register "device[0].type" = "panel"
                                # DDIB for HDMI
                                # If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB
                                register "device[1].name" = ""DD01""
                                # TCP0 (DP-1) for port C0
                                register "device[2].name" = ""DD02""
                                register "device[2].use_pld" = "true"
                                register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(1, 1))"
                                # TCP1 (DP-2) for port C1
                                register "device[3].name" = ""DD03""
                                register "device[3].use_pld" = "true"
                                register "device[3].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
                                device generic 0 on end
                        end
                end
                device ref i2c1 off end # Touchscreen
                device ref i2c3 on
                        chip drivers/i2c/rt5645
                                register "hid" = ""10EC5650""
                                register "name" = ""RT58""
                                register "desc" = ""Realtek RT5650""
                                register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
                                register "cbj_sleeve" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"
                                register "jd_mode" = "2"
                                device i2c 1a on end
                        end
                end
                device ref i2c5 off end # Touchpad
                device ref cnvi_wifi on
                        chip drivers/wifi/generic
                                register "wake" = "GPE0_PME_B0"
                                register "enable_cnvi_ddr_rfim" = "true"
                                register "add_acpi_dma_property" = "true"
                                device generic 0 on end
                        end
                        probe WIFI WIFI_CNVI_WIFI6E
                        probe unprovisioned
                end
                device ref pcie_rp4 on
                        # PCIe 4 WLAN
                        register "pch_pcie_rp[PCH_RP(4)]" = "{
                                .clk_src = 2,
                                .clk_req = 2,
                                .flags = PCIE_RP_LTR | PCIE_RP_AER,
                        }"
                        chip drivers/wifi/generic
                                register "wake" = "GPE0_DW1_03"
                                register "add_acpi_dma_property" = "true"
                                device pci 00.0 on end
                        end
                        probe WIFI WIFI_PCIE_WIFI7
                        probe unprovisioned
                end
                device ref pch_espi on
                        chip ec/google/chromeec
                                use conn0 as mux_conn[0]
                                use conn1 as mux_conn[1]
                                device pnp 0c09.0 on end
                        end
                end
                device ref pmc hidden
                        chip drivers/intel/pmc_mux
                                device generic 0 on
                                        chip drivers/intel/pmc_mux/conn
                                                use usb2_port1 as usb2_port
                                                use tcss_usb3_port2 as usb3_port
                                                device generic 0 alias conn0 on end
                                        end
                                        chip drivers/intel/pmc_mux/conn
                                                use usb2_port2 as usb2_port
                                                use tcss_usb3_port1 as usb3_port
                                                device generic 1 alias conn1 on end
                                        end
                                end
                        end
                end
                device ref tcss_xhci on
                        chip drivers/usb/acpi
                                device ref tcss_root_hub on
                                        chip drivers/usb/acpi
                                                register "desc" = ""USB3 Type-C Port C0 (MLB)""
                                                register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
                                                register "use_custom_pld" = "true"
                                                register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
                                                device ref tcss_usb3_port2 on end
                                        end
                                        chip drivers/usb/acpi
                                                register "desc" = ""USB3 Type-C Port C1 (DB)""
                                                register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
                                                register "use_custom_pld" = "true"
                                                register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
                                                device ref tcss_usb3_port1 on end
                                        end
                                end
                        end
                end
                device ref xhci on
                        register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)"  # Type-C MB (7.5 inch)
                        register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)"  # Type-C DB (7.1 inch)
                        register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"             # Type-A MB (6.4 inch)
                        register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"             # Type-A DB (6.2 inch)
                        register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)"   # LTE (3.3 inch)
                        register "usb2_ports[5]" = "USB2_PORT_SHORT(OC_SKIP)"   # UFC (3.7 inch)
                        register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)"     # Bluetooth port for PCIe WLAN (2.5 inch)
                        register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"     # Bluetooth port for CNVi WLAN

                        register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 Type-A port A0(MLB)
                        register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 Type-A port A1(DB)
                        register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 WWAN(LTE)
                        chip drivers/usb/acpi
                                device ref xhci_root_hub on
                                        chip drivers/usb/acpi
                                                register "desc" = ""USB2 Type-C Port C0 (MLB)""
                                                register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
                                                register "use_custom_pld" = "true"
                                                register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
                                                device ref usb2_port1 on end
                                        end
                                        chip drivers/usb/acpi
                                                register "desc" = ""USB2 Type-C Port C1 (DB)""
                                                register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
                                                register "use_custom_pld" = "true"
                                                register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
                                                device ref usb2_port2 on end
                                        end
                                        chip drivers/usb/acpi
                                                register "desc" = ""USB2 Type-A Port A0 (MLB)""
                                                register "type" = "UPC_TYPE_A"
                                                register "use_custom_pld" = "true"
                                                register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
                                                device ref usb2_port3 on end
                                        end
                                        chip drivers/usb/acpi
                                                register "desc" = ""USB2 Type-A Port A1 (DB)""
                                                register "type" = "UPC_TYPE_A"
                                                register "use_custom_pld" = "true"
                                                register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
                                                device ref usb2_port4 on end
                                        end
                                        chip drivers/usb/acpi
                                                register "desc" = ""USB2 LTE""
                                                register "type" = "UPC_TYPE_INTERNAL"
                                                device ref usb2_port5 on end
                                        end
                                        chip drivers/usb/acpi
                                                register "desc" = ""USB2 UFC""
                                                register "type" = "UPC_TYPE_INTERNAL"
                                                device ref usb2_port6 on end
                                        end
                                        chip drivers/usb/acpi
                                                register "desc" = ""PCIe Bluetooth""
                                                register "type" = "UPC_TYPE_INTERNAL"
                                                register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
                                                device ref usb2_port8 on end
                                        end
                                        chip drivers/usb/acpi
                                                register "desc" = ""CNVi Bluetooth""
                                                register "type" = "UPC_TYPE_INTERNAL"
                                                register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
                                                device ref usb2_port10 on
                                                        probe WIFI WIFI_CNVI_WIFI6E
                                                end
                                        end
                                        chip drivers/usb/acpi
                                                register "desc" = ""USB3 Type-A Port A0 (MLB)""
                                                register "type" = "UPC_TYPE_USB3_A"
                                                register "use_custom_pld" = "true"
                                                register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
                                                device ref usb3_port1 on end
                                        end
                                        chip drivers/usb/acpi
                                                register "desc" = ""USB3 Type-A Port A1 (DB)""
                                                register "type" = "UPC_TYPE_USB3_A"
                                                register "use_custom_pld" = "true"
                                                register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
                                                device ref usb3_port2 on end
                                        end
                                        chip drivers/usb/acpi
                                                register "desc" = ""USB3 WWAN""
                                                register "type" = "UPC_TYPE_INTERNAL"
                                                device ref usb3_port3 on end
                                        end
                                        chip drivers/usb/acpi
                                                register "desc" = ""USB3 WLAN""
                                                register "type" = "UPC_TYPE_INTERNAL"
                                                device ref usb3_port4 on end
                                        end
                                end
                        end
                end
                device ref pcie_rp7 off end # SDCard
                device ref pcie_rp9 on
                        # Enable NVMe SSD PCIe 9-12 using clk 1
                        register "pch_pcie_rp[PCH_RP(9)]" = "{
                                .clk_src = 1,
                                .clk_req = 1,
                                .flags = PCIE_RP_LTR | PCIE_RP_AER,
                                .pcie_rp_aspm = ASPM_L1,
                        }"
                        chip soc/intel/common/block/pcie/rtd3
                                # enable_gpio is EN_PP3300_SSD
                                register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)"
                                register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)"
                                register "srcclk_pin" = "1"
                                device generic 0 on
                                        probe STORAGE STORAGE_NVME
                                        probe unprovisioned
                                end
                        end
                end
                device ref emmc on
                        probe STORAGE STORAGE_EMMC
                        probe unprovisioned
                end
                device ref hda on
                        chip drivers/sof
                                register "spkr_tplg" = "rt5650_sp"
                                register "jack_tplg" = "rt5650_hp"
                                register "mic_tplg" = "_2ch_pdm0"
                                device generic 0 on end
                        end
                end
        end
end