soc/intel/common/block/itss: Route PCI INT pin to PIRQ using PIR
[coreboot2.git] / util / chromeos / 
treecb7a09a6d3026cdc20dd73682c1943ced358f880
drwxr-xr-x   ..
-rw-r--r-- 1000 README.md
-rwxr-xr-x 4315 crosfirmware.sh
-rw-r--r-- 200 description.md
-rwxr-xr-x 3053 extract_blobs.sh
-rwxr-xr-x 486 gen_test_hwid.sh
-rwxr-xr-x 2232 update_ec_headers.sh