soc/intel/xeon_sp/gnr: Use default DCACHE_BSP_STACK_SIZE
[coreboot2.git] / util / intelp2m / platforms / cnl / 
tree0bb05bf00235c6a66becaad63fdf980afb2528ab
drwxr-xr-x   ..
-rw-r--r-- 6309 macro.go
-rw-r--r-- 925 template.go