soc/intel/xeon_sp: Allow OS to control LTR and AERmain
[coreboot2.git] / src / mainboard / google / auron / variants / auron_paine / include / 
treeaf1f94e504309150df2c36f1ccb6307c8d32ae1e
drwxr-xr-x   ..
drwxr-xr-x - variant