soc/intel/xeon_sp: Allow OS to control LTR and AERmain
[coreboot2.git] / src / mainboard / google / auron / variants / samus / include / 
treeb245f8e3a1a882a664c5bbed1d0e2061ac8d2501
drwxr-xr-x   ..
drwxr-xr-x - variant