soc/intel/xeon_sp: Allow OS to control LTR and AERmain
[coreboot2.git] / src / mainboard / google / brya / variants / taeko4es / 
tree6c29d7d4dc619f6cc368da8cbab25dfbdb88c232
drwxr-xr-x   ..
-rw-r--r-- 220 Makefile.mk
-rw-r--r-- 2208 fw_config.c
-rw-r--r-- 7649 gpio.c
drwxr-xr-x - include
-rw-r--r-- 2217 memory.c
drwxr-xr-x - memory
-rw-r--r-- 17028 overridetree.cb
-rw-r--r-- 138 variant.c