soc/intel/pantherlake: Enable FSP debug log level control using CBFSmain
[coreboot2.git] / src / mainboard / google / jecht / variants / 
treeb430bcba827ce923bf28faaa841c637b70c0f9ba
drwxr-xr-x   ..
drwxr-xr-x - guado
drwxr-xr-x - jecht
drwxr-xr-x - rikku
drwxr-xr-x - tidus