soc/intel/xeon_sp: Allow OS to control LTR and AERmain
[coreboot2.git] / src / mainboard / google / zork / variants / vilboz / spd / 
tree15434da2ebaef75bbf643c2ba0532a4d8ac26c35
drwxr-xr-x   ..
-rw-r--r-- 1380 Makefile.mk
-rw-r--r-- 749 dram_id.generated.txt
-rw-r--r-- 726 mem_parts_used.txt