ioregs.c

   1 #include <string.h>
   2 #include <stdio.h>
   3 #include <stdlib.h>
   4 #include "disasm.h"
   5 #include "log.h"
   6
   7 static u8 io_space[0x100];
   8
   9 static const char *name_smbsta_bits[8] = {
  10         "master", "unit_busy", "bus_free", "nacked", "sa_rdy", "d_rdy", "d_req", "bus_low",
  11 };
  12
  13 static const char *name_smbctl_bits[8] = {
  14         "sa_en", "isolate", "smb_rst", "bfi_en", "pec_dis", "bli_dis", "bli_edge", "nc_smb",
  15 };
  16
  17 static const char *name_smbpec_bits[8] = {
  18         "pec_vld", "pec_chk", "pec_snd", "rsvd", "rsvd", "rsvd", "rsvd", "rsvd",
  19 };
  20
  21 static const char *name_hdqsta_bits[8] = {
  22         "data_in", "sbit_in", "hdq_drdy", "hdq_drq", "rsvd", "rsvd", "rsvd", "rsvd",
  23 };
  24
  25
  26 static const char *name_hdqout_bits[8] = {
  27         "data_out", "sbit_out", "rsvd", "rsvd", "rsvd", "rsvd", "rsvd", "rsvd",
  28 };
  29
  30 static const char *name_adctl0_bits[8] = {
  31         "chan0", "chan1", "chan2", "chan3", "fast", "adc_on", "vrvdd", "conv",
  32 };
  33
  34 static const char *name_ccctl_bits[8] = {
  35         "cc_cal", "cc_on", "rsvd", "rsvd", "rsvd", "rsvd", "rsvd", "rsvd",
  36 };
  37
  38 static const char *name_clk_bits[8] = {
  39         "pll_en", "osc_en", "osc_ng", "rsvd", "dg0", "dg1", "rsvd", "rsvd",
  40 };
  41
  42 static const char *name_tmrctlw_bits[8] = {
  43         "wdcrst", "wken", "wden", "wdf", "rsvd", "rsvd", "rsvd", "rsvd",
  44 };
  45
  46 static const char *name_tmrctla_bits[8] = {
  47         "tma_ps0", "tma_ps1", "tma_edg", "tma_isrc", "tma_ext", "tma_on", "tm16", "rsvd",
  48 };
  49
  50 static const char *name_tmrctlb_bits[8] = {
  51         "tmb_ps0", "tmb_ps1", "tmb_edg", "tmb_isrc", "tmb_ext", "tmb_on", "pwb0", "pwb1",
  52 };
  53
  54 static const char *name_tmrctlc_bits[8] = {
  55         "cap_ps0", "cap_ps1", "cap_edg", "mode0", "mode1", "mode2", "pwa0", "pwa1",
  56 };
  57
  58 static const char *name_raout_bits[8] = {
  59         "rao0", "rao1/vo", "rao2", "rao3", "rao4", "rao5", "rao6", "rao7",
  60 };
  61
  62 static const char *name_rbout_bits[8] = {
  63         "rbo0", "rbo1", "rbo2", "rbo3", "rbo4", "rbo5", "rbo6", "rbo7",
  64 };
  65
  66 static const char *name_rcout_bits[8] = {
  67         "rco0", "rco1", "rco2", "rco3", "rco4", "rco5", "rco6", "rco7",
  68 };
  69
  70 static const char *name_rain_bits[8] = {
  71         "rai0", "rai1", "rai2", "rai3", "rai4", "rai5", "rai6", "rai7",
  72 };
  73
  74 static const char *name_rbin_bits[8] = {
  75         "rbi0", "rbi1", "rbi2", "rbi3", "rbi4", "rbi5", "rbi6", "rbi7",
  76 };
  77
  78 static const char *name_rcin_bits[8] = {
  79         "rci0", "rci1", "rci2", "rci3", "rci4", "rci5", "rci6", "rci7",
  80 };
  81
  82 static const char *name_raien_bits[8] = {
  83         "raien0", "raien1", "raien2", "raien3", "raien4", "raien5", "raien6", "raien7",
  84 };
  85
  86 static const char *name_rbien_bits[8] = {
  87         "rbien0", "rbien1", "rbien2", "rbien3", "rbien4", "rbien5", "rbien6", "rbien7",
  88 };
  89
  90 static const char *name_rcien_bits[8] = {
  91         "rcien0", "rcien1", "rcien2", "rcien3", "rcien4", "rcien5", "rcien6", "rcien7",
  92 };
  93
  94 static const char *name_ioctl_bits[8] = {
  95         "vouten", "hdqen", "smben", "xinten", "xeven", "pwmben", "pwmaen", "32k_out",
  96 };
  97
  98 static const char *name_rcpup_bits[8] = {
  99         "rcpup0", "rcpup1", "rcpup2", "rcpup3", "rcpup4", "rcpup5", "rcpup6", "rcpup7",
 100 };
 101
 102 static const char *name_pflag_bits[8] = {
 103         "tmbf", "tmaf", "wkf", "timf", "ccf", "adf", "hdqf", "smbf",
 104 };
 105
 106 static const char *name_pie_bits[8] = {
 107         "tmbie", "tmaie", "wkeve", "timie", "ccie", "adie", "hdqie", "smbie",
 108 };
 109
 110 static const char *name_pctl_bits[8] = {
 111         "xev_edg", "xin_edg", "rsvd", "rsvd", "rsvd", "rsvd", "rsvd", "rsvd",
 112 };
 113
 114 void write_io_lowlevel(u8 addr, u8 val)
 115 {
 116         io_space[addr] = val;
 117 }
 118
 119 u8 read_io_lowlevel(u8 addr)
 120 {
 121         u8 val;
 122         val = io_space[addr];
 123         return val;
 124 }
 125
 126 void write_io(u8 addr, u8 val)
 127 {
 128         u8 old = io_space[addr];
 129
 130         switch(addr) {
 131                 //SMB bus region
 132                 case 0x10:
 133                         log_comment_add("SMBMA (Master Address)\n");
 134                         log_comment_add("       addr=%02hhx (%s)\n",
 135                                                         val, val&1?"rd":"wr");
 136                         break;
 137                 case 0x11:
 138                         log_comment_add("SMBDA (Data)\n");
 139                         log_comment_add("       data=%02hhx\n", val);
 140                         break;
 141                 case 0x12:
 142                         log_comment_add("SMBACK (Ack)\n");
 143                         log_comment_add("       %s\n",
 144                                                         val&1?"acked":"weird 0");
 145                         break;
 146                 case 0x13:
 147                         log_comment_add("SMBSTA (Status)\n");
 148                         log_comment_add("       write %02hhx to readonly!\n", val);
 149                         break;
 150                 case 0x14:
 151                         io_space[addr] = val;
 152                         log_comment_reg_bits("SMBCTL (Control)", name_smbctl_bits, old, io_space[addr]);
 153                         break;
 154                 case 0x15:
 155                         io_space[addr] = val & 0x7;
 156                         log_comment_reg_bits("SMBPEC (Packet Error Check)", name_smbpec_bits, old, io_space[addr]);
 157                         break;
 158                 case 0x16:
 159                         log_comment_add("SMBTAR (Target Slave Address)\n");
 160                         log_comment_add("       addr=%02hhx (%s)\n",
 161                                                         val, val&1?"rd":"wr");  //probably rd/wr
 162                         io_space[addr] = val;
 163                         break;
 164                 case 0x17:
 165                         log_comment_add("SMBBUSLO (Bus Low timeout)\n");
 166                         if ((val & 7) == 0) {
 167                                 log_comment_add("       timeout='never'\n");
 168                         } else {
 169                                 log_comment_add("       timeout=%d ms\n", (val & 7)*500);
 170                         }
 171                         io_space[addr] = val & 0x7;
 172                         break;
 173                 //HDQ single pin serial interface region
 174                 case 0x20:
 175                         log_comment_add("HDQSTA (Input and Int Control)\n");
 176                         log_comment_add("       Write to ReadOnly reg (%02hhx)\n", val);
 177                         break;
 178                 case 0x21:
 179                         io_space[addr] = val & 0x3;
 180                         log_comment_reg_bits("HDQOUT (Output Control)", name_hdqout_bits, old, io_space[addr]);
 181                         break;
 182                 //ADC region
 183                 case 0x30:
 184                         //TODO decode chanX vector?
 185                         io_space[addr] = val;
 186                         log_comment_reg_bits("ADCTL0 (Control 0)", name_adctl0_bits, old, io_space[addr]);
 187                         break;
 188                 case 0x31:
 189                         log_comment_add("ADCTL1 (Control 1)\n");
 190                         log_comment_add("       Write to ReadOnly reg (%02hhx)\n", val);
 191                         break;
 192                 case 0x32:
 193                         log_comment_add("ADHI (High byte)\n");
 194                         log_comment_add("       Write to ReadOnly reg (%02hhx)\n", val);
 195                         break;
 196                 case 0x33:
 197                         log_comment_add("ADMID (Middle Byte)\n");
 198                         log_comment_add("       Write to ReadOnly reg (%02hhx)\n", val);
 199                         break;
 200                 case 0x34:
 201                         log_comment_add("ADLO (Low Byte)\n");
 202                         log_comment_add("       Write to ReadOnly reg (%02hhx)\n", val);
 203                         break;
 204                 //coloumb counter region
 205                 case 0x40:
 206                         io_space[addr] = val & 3;
 207                         log_comment_reg_bits("CCCTL (Control)", name_ccctl_bits, old, io_space[addr]);
 208                         break;
 209                 case 0x41:
 210                         log_comment_add("CCHI (High Byte)\n");
 211                         log_comment_add("       Write to ReadOnly reg (%02hhx)\n", val);
 212                         break;
 213                 case 0x42:
 214                         log_comment_add("CCLO (Low Byte)\n");
 215                         log_comment_add("       Write to ReadOnly reg (%02hhx)\n", val);
 216                         break;
 217                 //PLL clock
 218                 case 0x50:
 219                         io_space[addr] = (old & ~3) | (val & 3);
 220                         log_comment_reg_bits("CLK (Clock)", name_clk_bits, old & 3, io_space[addr]);
 221                         break;
 222                 case 0x51:
 223                         log_comment_add("OSC_TRIM (Trim)\n");
 224                         log_comment_add("       Trim=%d\n", val);
 225                         io_space[addr] = val;
 226                         break;
 227                 case 0x52:
 228                         log_comment_add("OSC Unknown!!\n");
 229                         log_comment_add("       val=%02hhx\n", val);
 230                         io_space[addr] = val;
 231                         break;
 232                 //timers
 233                 case 0x60:
 234                         if (val & 8) {
 235                                 io_space[addr] = val & 0x7;
 236                         } else {
 237                                 io_space[addr] = (io_space[addr] & 8) | ( val & 0x7);
 238                         }
 239                         log_comment_reg_bits("TMRCTLW (Control)", name_tmrctlw_bits, old & 0xf, io_space[addr]);
 240                         break;
 241                 case 0x61:
 242                         log_comment_add("TMRPERW (Program)\n");
 243                         log_comment_add("       Time=%d*3.90625 ms\n", val);
 244                         io_space[addr] = val;
 245                         break;
 246                 case 0x62:
 247                         io_space[addr] = val & 0x7f;
 248                         log_comment_reg_bits("TMRCTLA (Control A)", name_ccctl_bits, old & 0x7f, io_space[addr]);
 249                         break;
 250                 case 0x63:
 251                         io_space[addr] = val;
 252                         log_comment_reg_bits("TMRCTLB (Control B)", name_smbctl_bits, old, io_space[addr]);
 253                         break;
 254                 case 0x64:
 255                         io_space[addr] = val;
 256                         log_comment_reg_bits("TMRCTLC (Control C, Capture/Compare/PWM)", name_smbctl_bits, old, io_space[addr]);
 257                         break;
 258                 case 0x65:
 259                         log_comment_add("TMRPERA (Period A)\n");
 260                         log_comment_add("       Period=%d\n", val);
 261                         io_space[addr] = val;
 262                         break;
 263                 case 0x66:
 264                         log_comment_add("TMRPERB (Period B)\n");
 265                         log_comment_add("       Period = %d\n", val);
 266                         io_space[addr] = val;
 267                         break;
 268                 case 0x67:
 269                         log_comment_add("TMRPWA (Pulse Width A)\n");
 270                         log_comment_add("       Pulse Width = %d\n", val);
 271                         io_space[addr] = val;
 272                         break;
 273                 case 0x68:
 274                         log_comment_add("TMRPWB (Pulse Width B)\n");
 275                         log_comment_add("       Pulse Width = %d\n", val);
 276                         io_space[addr] = val;
 277                         break;
 278                 case 0x69:
 279                         log_comment_add("TMRPGMA (Program A)\n");
 280                         log_comment_add("       Init? = %d\n", val);
 281                         io_space[addr] = val;
 282                         break;
 283                 case 0x6a:
 284                         log_comment_add("TMRPGMB (Program B)\n");
 285                         log_comment_add("       Init? = %d\n", val);
 286                         io_space[addr] = val;
 287                         break;
 288                 //IO region
 289                 case 0x70:
 290                         io_space[addr] = val;
 291                         log_comment_reg_bits("RA_OUT (Output A)", name_raout_bits, old, io_space[addr]);
 292                         break;
 293                 case 0x71:
 294                         io_space[addr] = val;
 295                         log_comment_reg_bits("RB_OUT (Output B)", name_rbout_bits, old, io_space[addr]);
 296                         break;
 297                 case 0x72:
 298                         io_space[addr] = val;
 299                         log_comment_reg_bits("RC_OUT (Output C)", name_rcout_bits, old, io_space[addr]);
 300                         break;
 301                 case 0x73:
 302                         log_comment_add("RA_IN (Input A)\n");
 303                         log_comment_add("       Write to ReadOnly reg (%02hhx)\n", val);
 304                         break;
 305                 case 0x74:
 306                         log_comment_add("RB_IN (Input B)\n");
 307                         log_comment_add("       Write to ReadOnly reg (%02hhx)\n", val);
 308                         break;
 309                 case 0x75:
 310                         log_comment_add("RC_IN (Input C)\n");
 311                         log_comment_add("       Write to ReadOnly reg (%02hhx)\n", val);
 312                         break;
 313                 case 0x76:
 314                         io_space[addr] = val;
 315                         log_comment_reg_bits("RA_IEN (Input Enable A)", name_raien_bits, old, io_space[addr]);
 316                         break;
 317                 case 0x77:
 318                         io_space[addr] = val;
 319                         log_comment_reg_bits("RB_IEN (Input Enable B)", name_rbien_bits, old, io_space[addr]);
 320                         break;
 321                 case 0x78:
 322                         io_space[addr] = val;
 323                         log_comment_reg_bits("RC_IEN (Input Enable C)", name_rcien_bits, old, io_space[addr]);
 324                         break;
 325                 case 0x79:
 326                         io_space[addr] = val;
 327                         log_comment_reg_bits("IOCTL (I/O Control)", name_ioctl_bits, old, io_space[addr]);
 328                         break;
 329                 case 0x7c:
 330                         io_space[addr] = val;
 331                         log_comment_reg_bits("RC_PUP (Pullup C)", name_rcpup_bits, old, io_space[addr]);
 332                         break;
 333                 //interrupt controller
 334                 case 0x90:
 335                         //TODO special masking, zero only unset bits
 336                         io_space[addr] = old & val;
 337                         log_comment_reg_bits("PFLAG (Periph irq flags)", name_pflag_bits, old, io_space[addr]);
 338                         break;
 339                 case 0x91:
 340                         io_space[addr] = val;
 341                         log_comment_reg_bits("PIE (Periph irq en)", name_pie_bits, old, io_space[addr]);
 342                         sim_breakpoint_set(SIM_BREAKPOINT_DATA);
 343                         break;
 344                 case 0x92:
 345                         io_space[addr] = val & 3;
 346                         log_comment_reg_bits("PCTL (Periph Ext irq ctrl)", name_pctl_bits, old & 3, io_space[addr]);
 347                         break;
 348                 //voltage reference
 349                 case 0xa0:
 350                         log_comment_add("VTRIM (Reference voltage trim)\n");
 351                         log_comment_add("       %d*1.4 mV (probably)\n", val & 0x3f);
 352                         io_space[addr] = val & 0x3f;
 353                         break;
 354                 //TODO flash interface
 355                 case 0x80:
 356                         log_comment_add("Unknown flash TODO\n");
 357                         log_comment_add("       %02hhx\n", val);
 358                         io_space[addr] = val;
 359                         break;
 360                 default:
 361                         log_comment_add("Unknown IO write TODO!!\n");
 362                         log_comment_add("       Assuming RW register = %02hhx\n", val);
 363                         io_space[addr] = val;
 364                         sim_breakpoint_set(SIM_BREAKPOINT_DATA);
 365                         break;
 366         }
 367
 368         //TODO watch special adresses?
 369 }
 370
 371 u8 read_io(u8 addr)
 372 {
 373         u8 val = 0;
 374
 375         switch(addr) {
 376                 //SMB bus region
 377                 case 0x10:
 378                         log_comment_add("SMBMA (Master Address)\n");
 379                         log_comment_add("       Read of WriteOnly reg\n");
 380                         val = 0;
 381                         break;
 382                 case 0x11:
 383                         log_comment_add("SMBDA (Data)\n");
 384                         val = io_space[addr];
 385                         log_comment_add("       data=%02hhx\n", val);
 386                         break;
 387                 case 0x12:
 388                         log_comment_add("SMBACK (Ack)\n");
 389                         log_comment_add("       Read of WriteOnly reg\n");
 390                         val = 0;
 391                         break;
 392                 case 0x13:
 393                         val = io_space[addr];
 394                         log_comment_reg_bits("SMBSTA (Stat)", name_smbsta_bits, val, val);
 395                         break;
 396                 case 0x14:
 397                         val = io_space[addr];
 398                         log_comment_reg_bits("SMBCTL (Ctrl)", name_smbctl_bits, val, val);
 399                         break;
 400                 case 0x15:
 401                         val = io_space[addr] & 7;
 402                         log_comment_reg_bits("SMBPEC (Packet Error Check)", name_smbpec_bits, val, val);
 403                         break;
 404                 case 0x16:
 405                         val = io_space[addr];
 406                         log_comment_add("SMBTAR (Target Slave Addr)\n");
 407                         log_comment_add("       addr=%02hhx (%s)\n",
 408                                                         val, val&1?"rd":"wr");  //probably rd/wr
 409                         break;
 410                 case 0x17:
 411                         val = io_space[addr];
 412                         log_comment_add("SMBBUSLO (Bus Low timeout)\n");
 413                         if ((val & 7) == 0) {
 414                                 log_comment_add("       timeout='never'\n");
 415                         } else {
 416                                 log_comment_add("       timeout=%d ms\n", (val & 7)*500);
 417                         }
 418                         break;
 419                 //HDQ single pin serial interface region
 420                 case 0x20:
 421                         val = io_space[addr] & 0xf;
 422                         log_comment_reg_bits("HDQSTA (Input and irq ctrl)", name_hdqsta_bits, val, val);
 423                         break;
 424                 case 0x21:
 425                         val = io_space[addr] & 0x3;
 426                         log_comment_reg_bits("HDQOUT (Output ctrl)", name_hdqout_bits, val, val);
 427                         break;
 428                 //ADC region
 429                 case 0x30:
 430                         //TODO decode chanX vector?
 431                         val = io_space[addr];
 432                         log_comment_reg_bits("ADCTL0 (ctrl 0)", name_adctl0_bits, val, val);
 433                         break;
 434                 case 0x31:
 435                         val = io_space[addr] & 1;
 436                         log_comment_add("ADCTL1 (Control 1)\n");
 437                         log_comment_add("       ready = %02hhx\n", val);
 438                         break;
 439                 case 0x32:
 440                         val = io_space[addr] | 0x80;
 441                         log_comment_add("ADHI (High byte)\n");
 442                         log_comment_add("       ADC measurement = %d\n",
 443                                                         (io_space[0x32] << 16) |
 444                                                         (io_space[0x33] << 8) |
 445                                                         io_space[0x34]);
 446                         break;
 447                 case 0x33:
 448                         val = io_space[addr];
 449                         log_comment_add("ADMID (Middle Byte)\n");
 450                         log_comment_add("       ADC measurement = %d\n",
 451                                                         (io_space[0x32] << 16) |
 452                                                         (io_space[0x33] << 8) |
 453                                                         io_space[0x34]);
 454                         break;
 455                 case 0x34:
 456                         val = io_space[addr];
 457                         log_comment_add("ADLO (Low Byte)\n");
 458                         log_comment_add("       ADC measurement = %d\n",
 459                                                         (io_space[0x32] << 16) |
 460                                                         (io_space[0x33] << 8) |
 461                                                         io_space[0x34]);
 462                         break;
 463                 //coloumb counter region
 464                 case 0x40:
 465                         val = io_space[addr] & 3;
 466                         log_comment_reg_bits("CCCTL (Coulomb Ctrl)", name_ccctl_bits, val, val);
 467                         break;
 468                 case 0x41:
 469                         val = io_space[addr];
 470                         log_comment_add("CCHI (High Byte)\n");
 471                         log_comment_add("       Coulomb measurement = %hd\n",
 472                                                         (io_space[0x41] << 8) |
 473                                                         io_space[0x42]);
 474                         break;
 475                 case 0x42:
 476                         val = io_space[addr];
 477                         log_comment_add("CCLO (Low Byte)\n");
 478                         log_comment_add("       Coulomb measurement = %hd\n",
 479                                                         (io_space[0x41] << 8) |
 480                                                         io_space[0x42]);
 481                         break;
 482                 //PLL clock
 483                 case 0x50:
 484                         val = io_space[addr];
 485                         log_comment_reg_bits("CLK (Clock)", name_clk_bits, val, val);
 486                         break;
 487                 case 0x51:
 488                         val = io_space[addr];
 489                         log_comment_add("OSC_TRIM (Trim)\n");
 490                         log_comment_add("       Trim=%d\n", val);
 491                         break;
 492                 case 0x52:
 493                         //NOTICE sim writes 0x6b, IRL read out 0x0b
 494                         val = io_space[addr] & 0x0f;
 495                         log_comment_add("OSC Unknown!!\n");
 496                         log_comment_add("       val=%02hhx\n", val);
 497                         break;
 498                 //timers
 499                 case 0x60:
 500                         val = io_space[addr] & 0xf;
 501                         log_comment_reg_bits("TMRCTLW (Ctrl)", name_tmrctlw_bits, val, val);
 502                         break;
 503                 case 0x61:
 504                         val = io_space[addr];
 505                         log_comment_add("TMRPERW (Program)\n");
 506                         log_comment_add("       Time=%d*3.90625 ms\n", val);
 507                         break;
 508                 case 0x62:
 509                         val = io_space[addr] & 0x7f;
 510                         log_comment_reg_bits("TMRCTLA (Ctrl A)", name_tmrctla_bits, val, val);
 511                         break;
 512                 case 0x63:
 513                         val = io_space[addr];
 514                         log_comment_reg_bits("TMRCTLB (Ctrl B)", name_tmrctlb_bits, val, val);
 515                         break;
 516                 case 0x64:
 517                         val = io_space[addr];
 518                         log_comment_reg_bits("TMRCTLC (Ctrl C, Capture/Compare/PWM)", name_tmrctlc_bits, val, val);
 519                         break;
 520                 case 0x65:
 521                         val = io_space[addr];
 522                         log_comment_add("TMRPERA (Period A)\n");
 523                         log_comment_add("       Period=%d\n", val);
 524                         break;
 525                 case 0x66:
 526                         val = io_space[addr];
 527                         log_comment_add("TMRPERB (Period B)\n");
 528                         log_comment_add("       Period = %d\n", val);
 529                         break;
 530                 case 0x67:
 531                         val = io_space[addr];
 532                         log_comment_add("TMRPWA (Pulse Width A)\n");
 533                         log_comment_add("       Pulse Width = %d\n", val);
 534                         break;
 535                 case 0x68:
 536                         val = io_space[addr];
 537                         log_comment_add("TMRPWB (Pulse Width B)\n");
 538                         log_comment_add("       Pulse Width = %d\n", val);
 539                         break;
 540                 case 0x69:
 541                         val = io_space[addr];
 542                         log_comment_add("TMRPGMA (Program A)\n");
 543                         log_comment_add("       Init? = %d\n", val);
 544                         break;
 545                 case 0x6a:
 546                         val = io_space[addr];
 547                         log_comment_add("TMRPGMB (Program B)\n");
 548                         log_comment_add("       Init? = %d\n", val);
 549                         break;
 550                 //IO region
 551                 case 0x70:
 552                         val = io_space[addr];
 553                         log_comment_reg_bits("RA_OUT (Output A)", name_raout_bits, val, val);
 554                         break;
 555                 case 0x71:
 556                         val = io_space[addr];
 557                         log_comment_reg_bits("RB_OUT (Output B)", name_rbout_bits, val, val);
 558                         break;
 559                 case 0x72:
 560                         val = io_space[addr];
 561                         log_comment_reg_bits("RC_OUT (Output C)", name_rcout_bits, val, val);
 562                         break;
 563                 case 0x73:
 564                         val = io_space[addr];
 565                         log_comment_reg_bits("RA_IN (Input A)", name_rain_bits, val, val);
 566 //                      sim_breakpoint_set(SIM_BREAKPOINT_DATA);
 567                         break;
 568                 case 0x74:
 569                         val = io_space[addr];
 570                         log_comment_reg_bits("RB_IN (Input B)", name_rbin_bits, val, val);
 571 //                      sim_breakpoint_set(SIM_BREAKPOINT_DATA);
 572                         break;
 573                 case 0x75:
 574                         val = io_space[addr];
 575                         log_comment_reg_bits("RC_IN (Input C)", name_rcin_bits, val, val);
 576 //                      sim_breakpoint_set(SIM_BREAKPOINT_DATA);
 577                         break;
 578                 case 0x76:
 579                         val = io_space[addr];
 580                         log_comment_reg_bits("RA_IEN (Input Enable A)", name_raien_bits, val, val);
 581                         break;
 582                 case 0x77:
 583                         val = io_space[addr];
 584                         log_comment_reg_bits("RB_IEN (Input Enable B)", name_rbien_bits, val, val);
 585                         break;
 586                 case 0x78:
 587                         val = io_space[addr];
 588                         log_comment_reg_bits("RC_IEN (Input Enable C)", name_rcien_bits, val, val);
 589                         break;
 590                 case 0x79:
 591                         val = io_space[addr];
 592                         log_comment_reg_bits("IOCTL (I/O Ctrl)", name_ioctl_bits, val, val);
 593                         break;
 594                 case 0x7c:
 595                         val = io_space[addr];
 596                         log_comment_reg_bits("RC_PUP (Pullup C)", name_rcpup_bits, val, val);
 597                         break;
 598                 //interrupt controller
 599                 case 0x90:
 600                         val = io_space[addr];
 601                         log_comment_reg_bits("PFLAG (Periph irq flags)", name_pflag_bits, val, val);
 602                         break;
 603                 case 0x91:
 604                         val = io_space[addr];
 605                         log_comment_reg_bits("PIE (Periph irq enable)", name_pie_bits, val, val);
 606                         break;
 607                 case 0x92:
 608                         val = io_space[addr] & 3;
 609                         log_comment_reg_bits("PCTL (Periph Ext irq ctrl)", name_pctl_bits, val, val);
 610                         break;
 611                 //voltage reference
 612                 case 0xa0:
 613                         val = io_space[addr] & 0x3f;
 614                         log_comment_add("VTRIM (Reference voltage trim)\n");
 615                         log_comment_add("       %d*1.4 mV (probably)\n", val);
 616                         break;
 617                 //TODO flash interface
 618                 case 0x80:
 619                         val = io_space[addr];
 620                         log_comment_add("Unknown flash TODO\n");
 621                         log_comment_add("       %02hhx\n", val);
 622                         break;
 623                 default:
 624                         val = io_space[addr];
 625                         log_comment_add("!!Unknown IO write TODO!!\n");
 626                         log_comment_add("       Assuming RW register = %02hhx\n", val);
 627                         break;
 628         }
 629
 630         //TODO watch special adresses?
 631         return val;
 632 }
 633
 634 void init_ioregs(char * filename)
 635 {
 636         memset(io_space, 0, sizeof(io_space));
 637
 638         if (filename) {
 639                 FILE * fp;
 640                 fp = fopen(filename, "r");
 641                 if (fp == NULL) {
 642                         perror("IO dump opening");
 643                         exit(1);
 644                 }
 645                 fread(io_space, 0x100, 1, fp);
 646                 fclose(fp);
 647         }
 648
 649         //SMBSTA, BUS_FREE
 650         io_space[0x13] = 0x4;
 651         //SMBBUSLO, BUSLO2=1 during reset
 652         io_space[0x17] = 0x4;
 653         //ADCTL1 bit7 =1
 654         io_space[0x31] = 0x80;
 655         //ADHI bit7 =1
 656         io_space[0x32] = 0x80;
 657         //CLK OSC_EN=1, PLL_EN=1
 658         io_space[0x50] = 0x3;
 659         //TMRCTLW WDCRST=1
 660         io_space[0x60] = 0x1;
 661         //TMRPERW
 662         io_space[0x61] = 0xff;
 663         //TMRPERA
 664         io_space[0x65] = 0xff;
 665         //TMRPERB
 666         io_space[0x66] = 0xff;
 667         //TMRPWA
 668         io_space[0x67] = 0xff;
 669         //TMRPWB
 670         io_space[0x68] = 0xff;
 671         //RA_OUT
 672         io_space[0x70] = 0xff;
 673         //RB_OUT
 674         io_space[0x71] = 0xff;
 675         //RC_OUT
 676         io_space[0x72] = 0xff;
 677
 678         //PIE
 679 //      io_space[0x90] |= 0x08;
 680
 681 }