drivers/clk/meson/clk-mpll.c

   1 /*
   2  * This file is provided under a dual BSD/GPLv2 license.  When using or
   3  * redistributing this file, you may do so under either license.
   4  *
   5  * GPL LICENSE SUMMARY
   6  *
   7  * Copyright (c) 2016 AmLogic, Inc.
   8  * Author: Michael Turquette <mturquette@baylibre.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of version 2 of the GNU General Public License as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
  15  * WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  22  * The full GNU General Public License is included in this distribution
  23  * in the file called COPYING
  24  *
  25  * BSD LICENSE
  26  *
  27  * Copyright (c) 2016 AmLogic, Inc.
  28  * Author: Michael Turquette <mturquette@baylibre.com>
  29  *
  30  * Redistribution and use in source and binary forms, with or without
  31  * modification, are permitted provided that the following conditions
  32  * are met:
  33  *
  34  *   * Redistributions of source code must retain the above copyright
  35  *     notice, this list of conditions and the following disclaimer.
  36  *   * Redistributions in binary form must reproduce the above copyright
  37  *     notice, this list of conditions and the following disclaimer in
  38  *     the documentation and/or other materials provided with the
  39  *     distribution.
  40  *   * Neither the name of Intel Corporation nor the names of its
  41  *     contributors may be used to endorse or promote products derived
  42  *     from this software without specific prior written permission.
  43  *
  44  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  45  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  46  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  47  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  48  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  49  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  50  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  51  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  52  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  53  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  54  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  55  */
  56
  57 /*
  58  * MultiPhase Locked Loops are outputs from a PLL with additional frequency
  59  * scaling capabilities. MPLL rates are calculated as:
  60  *
  61  * f(N2_integer, SDM_IN ) = 2.0G/(N2_integer + SDM_IN/16384)
  62  */
  63
  64 #include <linux/clk-provider.h>
  65 #include "clkc.h"
  66
  67 #define SDM_DEN 16384
  68 #define N2_MIN  4
  69 #define N2_MAX  511
  70
  71 #define to_meson_clk_mpll(_hw) container_of(_hw, struct meson_clk_mpll, hw)
  72
  73 static long rate_from_params(unsigned long parent_rate,
  74                                       unsigned long sdm,
  75                                       unsigned long n2)
  76 {
  77         unsigned long divisor = (SDM_DEN * n2) + sdm;
  78
  79         if (n2 < N2_MIN)
  80                 return -EINVAL;
  81
  82         return DIV_ROUND_UP_ULL((u64)parent_rate * SDM_DEN, divisor);
  83 }
  84
  85 static void params_from_rate(unsigned long requested_rate,
  86                              unsigned long parent_rate,
  87                              unsigned long *sdm,
  88                              unsigned long *n2)
  89 {
  90         uint64_t div = parent_rate;
  91         unsigned long rem = do_div(div, requested_rate);
  92
  93         if (div < N2_MIN) {
  94                 *n2 = N2_MIN;
  95                 *sdm = 0;
  96         } else if (div > N2_MAX) {
  97                 *n2 = N2_MAX;
  98                 *sdm = SDM_DEN - 1;
  99         } else {
 100                 *n2 = div;
 101                 *sdm = DIV_ROUND_UP_ULL((u64)rem * SDM_DEN, requested_rate);
 102         }
 103 }
 104
 105 static unsigned long mpll_recalc_rate(struct clk_hw *hw,
 106                 unsigned long parent_rate)
 107 {
 108         struct meson_clk_mpll *mpll = to_meson_clk_mpll(hw);
 109         struct parm *p;
 110         unsigned long reg, sdm, n2;
 111         long rate;
 112
 113         p = &mpll->sdm;
 114         reg = readl(mpll->base + p->reg_off);
 115         sdm = PARM_GET(p->width, p->shift, reg);
 116
 117         p = &mpll->n2;
 118         reg = readl(mpll->base + p->reg_off);
 119         n2 = PARM_GET(p->width, p->shift, reg);
 120
 121         rate = rate_from_params(parent_rate, sdm, n2);
 122         if (rate < 0)
 123                 return 0;
 124
 125         return rate;
 126 }
 127
 128 static long mpll_round_rate(struct clk_hw *hw,
 129                             unsigned long rate,
 130                             unsigned long *parent_rate)
 131 {
 132         unsigned long sdm, n2;
 133
 134         params_from_rate(rate, *parent_rate, &sdm, &n2);
 135         return rate_from_params(*parent_rate, sdm, n2);
 136 }
 137
 138 static int mpll_set_rate(struct clk_hw *hw,
 139                          unsigned long rate,
 140                          unsigned long parent_rate)
 141 {
 142         struct meson_clk_mpll *mpll = to_meson_clk_mpll(hw);
 143         struct parm *p;
 144         unsigned long reg, sdm, n2;
 145         unsigned long flags = 0;
 146
 147         params_from_rate(rate, parent_rate, &sdm, &n2);
 148
 149         if (mpll->lock)
 150                 spin_lock_irqsave(mpll->lock, flags);
 151         else
 152                 __acquire(mpll->lock);
 153
 154         p = &mpll->sdm;
 155         reg = readl(mpll->base + p->reg_off);
 156         reg = PARM_SET(p->width, p->shift, reg, sdm);
 157         writel(reg, mpll->base + p->reg_off);
 158
 159         p = &mpll->sdm_en;
 160         reg = readl(mpll->base + p->reg_off);
 161         reg = PARM_SET(p->width, p->shift, reg, 1);
 162         writel(reg, mpll->base + p->reg_off);
 163
 164         p = &mpll->ssen;
 165         if (p->width != 0) {
 166                 reg = readl(mpll->base + p->reg_off);
 167                 reg = PARM_SET(p->width, p->shift, reg, 1);
 168                 writel(reg, mpll->base + p->reg_off);
 169         }
 170
 171         p = &mpll->n2;
 172         reg = readl(mpll->base + p->reg_off);
 173         reg = PARM_SET(p->width, p->shift, reg, n2);
 174         writel(reg, mpll->base + p->reg_off);
 175
 176         if (mpll->lock)
 177                 spin_unlock_irqrestore(mpll->lock, flags);
 178         else
 179                 __release(mpll->lock);
 180
 181         return 0;
 182 }
 183
 184 static void mpll_enable_core(struct clk_hw *hw, int enable)
 185 {
 186         struct meson_clk_mpll *mpll = to_meson_clk_mpll(hw);
 187         struct parm *p;
 188         unsigned long reg;
 189         unsigned long flags = 0;
 190
 191         if (mpll->lock)
 192                 spin_lock_irqsave(mpll->lock, flags);
 193         else
 194                 __acquire(mpll->lock);
 195
 196         p = &mpll->en;
 197         reg = readl(mpll->base + p->reg_off);
 198         reg = PARM_SET(p->width, p->shift, reg, enable ? 1 : 0);
 199         writel(reg, mpll->base + p->reg_off);
 200
 201         if (mpll->lock)
 202                 spin_unlock_irqrestore(mpll->lock, flags);
 203         else
 204                 __release(mpll->lock);
 205 }
 206
 207
 208 static int mpll_enable(struct clk_hw *hw)
 209 {
 210         mpll_enable_core(hw, 1);
 211
 212         return 0;
 213 }
 214
 215 static void mpll_disable(struct clk_hw *hw)
 216 {
 217         mpll_enable_core(hw, 0);
 218 }
 219
 220 static int mpll_is_enabled(struct clk_hw *hw)
 221 {
 222         struct meson_clk_mpll *mpll = to_meson_clk_mpll(hw);
 223         struct parm *p;
 224         unsigned long reg;
 225         int en;
 226
 227         p = &mpll->en;
 228         reg = readl(mpll->base + p->reg_off);
 229         en = PARM_GET(p->width, p->shift, reg);
 230
 231         return en;
 232 }
 233
 234 const struct clk_ops meson_clk_mpll_ro_ops = {
 235         .recalc_rate    = mpll_recalc_rate,
 236         .round_rate     = mpll_round_rate,
 237         .is_enabled     = mpll_is_enabled,
 238 };
 239
 240 const struct clk_ops meson_clk_mpll_ops = {
 241         .recalc_rate    = mpll_recalc_rate,
 242         .round_rate     = mpll_round_rate,
 243         .set_rate       = mpll_set_rate,
 244         .enable         = mpll_enable,
 245         .disable        = mpll_disable,
 246         .is_enabled     = mpll_is_enabled,
 247 };