drivers/clk/qcom/clk-alpha-pll.c

   1 /*
   2  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/export.h>
  16 #include <linux/clk-provider.h>
  17 #include <linux/regmap.h>
  18 #include <linux/delay.h>
  19
  20 #include "clk-alpha-pll.h"
  21 #include "common.h"
  22
  23 #define PLL_MODE(p)             ((p)->offset + 0x0)
  24 # define PLL_OUTCTRL            BIT(0)
  25 # define PLL_BYPASSNL           BIT(1)
  26 # define PLL_RESET_N            BIT(2)
  27 # define PLL_OFFLINE_REQ        BIT(7)
  28 # define PLL_LOCK_COUNT_SHIFT   8
  29 # define PLL_LOCK_COUNT_MASK    0x3f
  30 # define PLL_BIAS_COUNT_SHIFT   14
  31 # define PLL_BIAS_COUNT_MASK    0x3f
  32 # define PLL_VOTE_FSM_ENA       BIT(20)
  33 # define PLL_FSM_ENA            BIT(20)
  34 # define PLL_VOTE_FSM_RESET     BIT(21)
  35 # define PLL_UPDATE             BIT(22)
  36 # define PLL_UPDATE_BYPASS      BIT(23)
  37 # define PLL_OFFLINE_ACK        BIT(28)
  38 # define ALPHA_PLL_ACK_LATCH    BIT(29)
  39 # define PLL_ACTIVE_FLAG        BIT(30)
  40 # define PLL_LOCK_DET           BIT(31)
  41
  42 #define PLL_L_VAL(p)            ((p)->offset + (p)->regs[PLL_OFF_L_VAL])
  43 #define PLL_ALPHA_VAL(p)        ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL])
  44 #define PLL_ALPHA_VAL_U(p)      ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U])
  45
  46 #define PLL_USER_CTL(p)         ((p)->offset + (p)->regs[PLL_OFF_USER_CTL])
  47 # define PLL_POST_DIV_SHIFT     8
  48 # define PLL_POST_DIV_MASK(p)   GENMASK((p)->width, 0)
  49 # define PLL_ALPHA_EN           BIT(24)
  50 # define PLL_ALPHA_MODE         BIT(25)
  51 # define PLL_VCO_SHIFT          20
  52 # define PLL_VCO_MASK           0x3
  53
  54 #define PLL_USER_CTL_U(p)       ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U])
  55
  56 #define PLL_CONFIG_CTL(p)       ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL])
  57 #define PLL_CONFIG_CTL_U(p)     ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U])
  58 #define PLL_TEST_CTL(p)         ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL])
  59 #define PLL_TEST_CTL_U(p)       ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U])
  60 #define PLL_STATUS(p)           ((p)->offset + (p)->regs[PLL_OFF_STATUS])
  61
  62 const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
  63         [CLK_ALPHA_PLL_TYPE_DEFAULT] =  {
  64                 [PLL_OFF_L_VAL] = 0x04,
  65                 [PLL_OFF_ALPHA_VAL] = 0x08,
  66                 [PLL_OFF_ALPHA_VAL_U] = 0x0c,
  67                 [PLL_OFF_USER_CTL] = 0x10,
  68                 [PLL_OFF_USER_CTL_U] = 0x14,
  69                 [PLL_OFF_CONFIG_CTL] = 0x18,
  70                 [PLL_OFF_TEST_CTL] = 0x1c,
  71                 [PLL_OFF_TEST_CTL_U] = 0x20,
  72                 [PLL_OFF_STATUS] = 0x24,
  73         },
  74         [CLK_ALPHA_PLL_TYPE_HUAYRA] =  {
  75                 [PLL_OFF_L_VAL] = 0x04,
  76                 [PLL_OFF_ALPHA_VAL] = 0x08,
  77                 [PLL_OFF_USER_CTL] = 0x10,
  78                 [PLL_OFF_CONFIG_CTL] = 0x14,
  79                 [PLL_OFF_CONFIG_CTL_U] = 0x18,
  80                 [PLL_OFF_TEST_CTL] = 0x1c,
  81                 [PLL_OFF_TEST_CTL_U] = 0x20,
  82                 [PLL_OFF_STATUS] = 0x24,
  83         },
  84         [CLK_ALPHA_PLL_TYPE_BRAMMO] =  {
  85                 [PLL_OFF_L_VAL] = 0x04,
  86                 [PLL_OFF_ALPHA_VAL] = 0x08,
  87                 [PLL_OFF_ALPHA_VAL_U] = 0x0c,
  88                 [PLL_OFF_USER_CTL] = 0x10,
  89                 [PLL_OFF_CONFIG_CTL] = 0x18,
  90                 [PLL_OFF_TEST_CTL] = 0x1c,
  91                 [PLL_OFF_STATUS] = 0x24,
  92         },
  93 };
  94 EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
  95
  96 /*
  97  * Even though 40 bits are present, use only 32 for ease of calculation.
  98  */
  99 #define ALPHA_REG_BITWIDTH      40
 100 #define ALPHA_REG_16BIT_WIDTH   16
 101 #define ALPHA_BITWIDTH          32U
 102 #define ALPHA_SHIFT(w)          min(w, ALPHA_BITWIDTH)
 103
 104 #define PLL_HUAYRA_M_WIDTH              8
 105 #define PLL_HUAYRA_M_SHIFT              8
 106 #define PLL_HUAYRA_M_MASK               0xff
 107 #define PLL_HUAYRA_N_SHIFT              0
 108 #define PLL_HUAYRA_N_MASK               0xff
 109 #define PLL_HUAYRA_ALPHA_WIDTH          16
 110
 111 #define pll_alpha_width(p)                                      \
 112                 ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
 113                                  ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH)
 114
 115 #define pll_has_64bit_config(p) ((PLL_CONFIG_CTL_U(p) - PLL_CONFIG_CTL(p)) == 4)
 116
 117 #define to_clk_alpha_pll(_hw) container_of(to_clk_regmap(_hw), \
 118                                            struct clk_alpha_pll, clkr)
 119
 120 #define to_clk_alpha_pll_postdiv(_hw) container_of(to_clk_regmap(_hw), \
 121                                            struct clk_alpha_pll_postdiv, clkr)
 122
 123 static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse,
 124                         const char *action)
 125 {
 126         u32 val;
 127         int count;
 128         int ret;
 129         const char *name = clk_hw_get_name(&pll->clkr.hw);
 130
 131         ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
 132         if (ret)
 133                 return ret;
 134
 135         for (count = 100; count > 0; count--) {
 136                 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
 137                 if (ret)
 138                         return ret;
 139                 if (inverse && !(val & mask))
 140                         return 0;
 141                 else if ((val & mask) == mask)
 142                         return 0;
 143
 144                 udelay(1);
 145         }
 146
 147         WARN(1, "%s failed to %s!\n", name, action);
 148         return -ETIMEDOUT;
 149 }
 150
 151 #define wait_for_pll_enable_active(pll) \
 152         wait_for_pll(pll, PLL_ACTIVE_FLAG, 0, "enable")
 153
 154 #define wait_for_pll_enable_lock(pll) \
 155         wait_for_pll(pll, PLL_LOCK_DET, 0, "enable")
 156
 157 #define wait_for_pll_disable(pll) \
 158         wait_for_pll(pll, PLL_ACTIVE_FLAG, 1, "disable")
 159
 160 #define wait_for_pll_offline(pll) \
 161         wait_for_pll(pll, PLL_OFFLINE_ACK, 0, "offline")
 162
 163 #define wait_for_pll_update(pll) \
 164         wait_for_pll(pll, PLL_UPDATE, 1, "update")
 165
 166 #define wait_for_pll_update_ack_set(pll) \
 167         wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 0, "update_ack_set")
 168
 169 #define wait_for_pll_update_ack_clear(pll) \
 170         wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 1, "update_ack_clear")
 171
 172 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
 173                              const struct alpha_pll_config *config)
 174 {
 175         u32 val, mask;
 176
 177         regmap_write(regmap, PLL_L_VAL(pll), config->l);
 178         regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
 179         regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
 180
 181         if (pll_has_64bit_config(pll))
 182                 regmap_write(regmap, PLL_CONFIG_CTL_U(pll),
 183                              config->config_ctl_hi_val);
 184
 185         if (pll_alpha_width(pll) > 32)
 186                 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi);
 187
 188         val = config->main_output_mask;
 189         val |= config->aux_output_mask;
 190         val |= config->aux2_output_mask;
 191         val |= config->early_output_mask;
 192         val |= config->pre_div_val;
 193         val |= config->post_div_val;
 194         val |= config->vco_val;
 195         val |= config->alpha_en_mask;
 196         val |= config->alpha_mode_mask;
 197
 198         mask = config->main_output_mask;
 199         mask |= config->aux_output_mask;
 200         mask |= config->aux2_output_mask;
 201         mask |= config->early_output_mask;
 202         mask |= config->pre_div_mask;
 203         mask |= config->post_div_mask;
 204         mask |= config->vco_mask;
 205
 206         regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
 207
 208         if (pll->flags & SUPPORTS_FSM_MODE)
 209                 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0);
 210 }
 211
 212 static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw)
 213 {
 214         int ret;
 215         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 216         u32 val;
 217
 218         ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
 219         if (ret)
 220                 return ret;
 221
 222         val |= PLL_FSM_ENA;
 223
 224         if (pll->flags & SUPPORTS_OFFLINE_REQ)
 225                 val &= ~PLL_OFFLINE_REQ;
 226
 227         ret = regmap_write(pll->clkr.regmap, PLL_MODE(pll), val);
 228         if (ret)
 229                 return ret;
 230
 231         /* Make sure enable request goes through before waiting for update */
 232         mb();
 233
 234         return wait_for_pll_enable_active(pll);
 235 }
 236
 237 static void clk_alpha_pll_hwfsm_disable(struct clk_hw *hw)
 238 {
 239         int ret;
 240         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 241         u32 val;
 242
 243         ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
 244         if (ret)
 245                 return;
 246
 247         if (pll->flags & SUPPORTS_OFFLINE_REQ) {
 248                 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
 249                                          PLL_OFFLINE_REQ, PLL_OFFLINE_REQ);
 250                 if (ret)
 251                         return;
 252
 253                 ret = wait_for_pll_offline(pll);
 254                 if (ret)
 255                         return;
 256         }
 257
 258         /* Disable hwfsm */
 259         ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
 260                                  PLL_FSM_ENA, 0);
 261         if (ret)
 262                 return;
 263
 264         wait_for_pll_disable(pll);
 265 }
 266
 267 static int pll_is_enabled(struct clk_hw *hw, u32 mask)
 268 {
 269         int ret;
 270         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 271         u32 val;
 272
 273         ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
 274         if (ret)
 275                 return ret;
 276
 277         return !!(val & mask);
 278 }
 279
 280 static int clk_alpha_pll_hwfsm_is_enabled(struct clk_hw *hw)
 281 {
 282         return pll_is_enabled(hw, PLL_ACTIVE_FLAG);
 283 }
 284
 285 static int clk_alpha_pll_is_enabled(struct clk_hw *hw)
 286 {
 287         return pll_is_enabled(hw, PLL_LOCK_DET);
 288 }
 289
 290 static int clk_alpha_pll_enable(struct clk_hw *hw)
 291 {
 292         int ret;
 293         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 294         u32 val, mask;
 295
 296         mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL;
 297         ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
 298         if (ret)
 299                 return ret;
 300
 301         /* If in FSM mode, just vote for it */
 302         if (val & PLL_VOTE_FSM_ENA) {
 303                 ret = clk_enable_regmap(hw);
 304                 if (ret)
 305                         return ret;
 306                 return wait_for_pll_enable_active(pll);
 307         }
 308
 309         /* Skip if already enabled */
 310         if ((val & mask) == mask)
 311                 return 0;
 312
 313         ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
 314                                  PLL_BYPASSNL, PLL_BYPASSNL);
 315         if (ret)
 316                 return ret;
 317
 318         /*
 319          * H/W requires a 5us delay between disabling the bypass and
 320          * de-asserting the reset.
 321          */
 322         mb();
 323         udelay(5);
 324
 325         ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
 326                                  PLL_RESET_N, PLL_RESET_N);
 327         if (ret)
 328                 return ret;
 329
 330         ret = wait_for_pll_enable_lock(pll);
 331         if (ret)
 332                 return ret;
 333
 334         ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
 335                                  PLL_OUTCTRL, PLL_OUTCTRL);
 336
 337         /* Ensure that the write above goes through before returning. */
 338         mb();
 339         return ret;
 340 }
 341
 342 static void clk_alpha_pll_disable(struct clk_hw *hw)
 343 {
 344         int ret;
 345         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 346         u32 val, mask;
 347
 348         ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
 349         if (ret)
 350                 return;
 351
 352         /* If in FSM mode, just unvote it */
 353         if (val & PLL_VOTE_FSM_ENA) {
 354                 clk_disable_regmap(hw);
 355                 return;
 356         }
 357
 358         mask = PLL_OUTCTRL;
 359         regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0);
 360
 361         /* Delay of 2 output clock ticks required until output is disabled */
 362         mb();
 363         udelay(1);
 364
 365         mask = PLL_RESET_N | PLL_BYPASSNL;
 366         regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0);
 367 }
 368
 369 static unsigned long
 370 alpha_pll_calc_rate(u64 prate, u32 l, u32 a, u32 alpha_width)
 371 {
 372         return (prate * l) + ((prate * a) >> ALPHA_SHIFT(alpha_width));
 373 }
 374
 375 static unsigned long
 376 alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a,
 377                      u32 alpha_width)
 378 {
 379         u64 remainder;
 380         u64 quotient;
 381
 382         quotient = rate;
 383         remainder = do_div(quotient, prate);
 384         *l = quotient;
 385
 386         if (!remainder) {
 387                 *a = 0;
 388                 return rate;
 389         }
 390
 391         /* Upper ALPHA_BITWIDTH bits of Alpha */
 392         quotient = remainder << ALPHA_SHIFT(alpha_width);
 393
 394         remainder = do_div(quotient, prate);
 395
 396         if (remainder)
 397                 quotient++;
 398
 399         *a = quotient;
 400         return alpha_pll_calc_rate(prate, *l, *a, alpha_width);
 401 }
 402
 403 static const struct pll_vco *
 404 alpha_pll_find_vco(const struct clk_alpha_pll *pll, unsigned long rate)
 405 {
 406         const struct pll_vco *v = pll->vco_table;
 407         const struct pll_vco *end = v + pll->num_vco;
 408
 409         for (; v < end; v++)
 410                 if (rate >= v->min_freq && rate <= v->max_freq)
 411                         return v;
 412
 413         return NULL;
 414 }
 415
 416 static unsigned long
 417 clk_alpha_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
 418 {
 419         u32 l, low, high, ctl;
 420         u64 a = 0, prate = parent_rate;
 421         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 422         u32 alpha_width = pll_alpha_width(pll);
 423
 424         regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
 425
 426         regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
 427         if (ctl & PLL_ALPHA_EN) {
 428                 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &low);
 429                 if (alpha_width > 32) {
 430                         regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
 431                                     &high);
 432                         a = (u64)high << 32 | low;
 433                 } else {
 434                         a = low & GENMASK(alpha_width - 1, 0);
 435                 }
 436
 437                 if (alpha_width > ALPHA_BITWIDTH)
 438                         a >>= alpha_width - ALPHA_BITWIDTH;
 439         }
 440
 441         return alpha_pll_calc_rate(prate, l, a, alpha_width);
 442 }
 443
 444 static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll,
 445                                       int (*is_enabled)(struct clk_hw *))
 446 {
 447         int ret;
 448         u32 mode;
 449
 450         if (!is_enabled(&pll->clkr.hw) ||
 451             !(pll->flags & SUPPORTS_DYNAMIC_UPDATE))
 452                 return 0;
 453
 454         regmap_read(pll->clkr.regmap, PLL_MODE(pll), &mode);
 455
 456         /* Latch the input to the PLL */
 457         regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE,
 458                            PLL_UPDATE);
 459
 460         /* Wait for 2 reference cycle before checking ACK bit */
 461         udelay(1);
 462
 463         /*
 464          * PLL will latch the new L, Alpha and freq control word.
 465          * PLL will respond by raising PLL_ACK_LATCH output when new programming
 466          * has been latched in and PLL is being updated. When
 467          * UPDATE_LOGIC_BYPASS bit is not set, PLL_UPDATE will be cleared
 468          * automatically by hardware when PLL_ACK_LATCH is asserted by PLL.
 469          */
 470         if (mode & PLL_UPDATE_BYPASS) {
 471                 ret = wait_for_pll_update_ack_set(pll);
 472                 if (ret)
 473                         return ret;
 474
 475                 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 0);
 476         } else {
 477                 ret = wait_for_pll_update(pll);
 478                 if (ret)
 479                         return ret;
 480         }
 481
 482         ret = wait_for_pll_update_ack_clear(pll);
 483         if (ret)
 484                 return ret;
 485
 486         /* Wait for PLL output to stabilize */
 487         udelay(10);
 488
 489         return 0;
 490 }
 491
 492 static int __clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 493                                     unsigned long prate,
 494                                     int (*is_enabled)(struct clk_hw *))
 495 {
 496         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 497         const struct pll_vco *vco;
 498         u32 l, alpha_width = pll_alpha_width(pll);
 499         u64 a;
 500
 501         rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
 502         vco = alpha_pll_find_vco(pll, rate);
 503         if (pll->vco_table && !vco) {
 504                 pr_err("alpha pll not in a valid vco range\n");
 505                 return -EINVAL;
 506         }
 507
 508         regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
 509
 510         if (alpha_width > ALPHA_BITWIDTH)
 511                 a <<= alpha_width - ALPHA_BITWIDTH;
 512
 513         if (alpha_width > 32)
 514                 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), a >> 32);
 515
 516         regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
 517
 518         if (vco) {
 519                 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
 520                                    PLL_VCO_MASK << PLL_VCO_SHIFT,
 521                                    vco->val << PLL_VCO_SHIFT);
 522         }
 523
 524         regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
 525                            PLL_ALPHA_EN, PLL_ALPHA_EN);
 526
 527         return clk_alpha_pll_update_latch(pll, is_enabled);
 528 }
 529
 530 static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 531                                   unsigned long prate)
 532 {
 533         return __clk_alpha_pll_set_rate(hw, rate, prate,
 534                                         clk_alpha_pll_is_enabled);
 535 }
 536
 537 static int clk_alpha_pll_hwfsm_set_rate(struct clk_hw *hw, unsigned long rate,
 538                                         unsigned long prate)
 539 {
 540         return __clk_alpha_pll_set_rate(hw, rate, prate,
 541                                         clk_alpha_pll_hwfsm_is_enabled);
 542 }
 543
 544 static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate,
 545                                      unsigned long *prate)
 546 {
 547         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 548         u32 l, alpha_width = pll_alpha_width(pll);
 549         u64 a;
 550         unsigned long min_freq, max_freq;
 551
 552         rate = alpha_pll_round_rate(rate, *prate, &l, &a, alpha_width);
 553         if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
 554                 return rate;
 555
 556         min_freq = pll->vco_table[0].min_freq;
 557         max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
 558
 559         return clamp(rate, min_freq, max_freq);
 560 }
 561
 562 static unsigned long
 563 alpha_huayra_pll_calc_rate(u64 prate, u32 l, u32 a)
 564 {
 565         /*
 566          * a contains 16 bit alpha_val in two’s compliment number in the range
 567          * of [-0.5, 0.5).
 568          */
 569         if (a >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1))
 570                 l -= 1;
 571
 572         return (prate * l) + (prate * a >> PLL_HUAYRA_ALPHA_WIDTH);
 573 }
 574
 575 static unsigned long
 576 alpha_huayra_pll_round_rate(unsigned long rate, unsigned long prate,
 577                             u32 *l, u32 *a)
 578 {
 579         u64 remainder;
 580         u64 quotient;
 581
 582         quotient = rate;
 583         remainder = do_div(quotient, prate);
 584         *l = quotient;
 585
 586         if (!remainder) {
 587                 *a = 0;
 588                 return rate;
 589         }
 590
 591         quotient = remainder << PLL_HUAYRA_ALPHA_WIDTH;
 592         remainder = do_div(quotient, prate);
 593
 594         if (remainder)
 595                 quotient++;
 596
 597         /*
 598          * alpha_val should be in two’s compliment number in the range
 599          * of [-0.5, 0.5) so if quotient >= 0.5 then increment the l value
 600          * since alpha value will be subtracted in this case.
 601          */
 602         if (quotient >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1))
 603                 *l += 1;
 604
 605         *a = quotient;
 606         return alpha_huayra_pll_calc_rate(prate, *l, *a);
 607 }
 608
 609 static unsigned long
 610 alpha_pll_huayra_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
 611 {
 612         u64 rate = parent_rate, tmp;
 613         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 614         u32 l, alpha = 0, ctl, alpha_m, alpha_n;
 615
 616         regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
 617         regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
 618
 619         if (ctl & PLL_ALPHA_EN) {
 620                 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &alpha);
 621                 /*
 622                  * Depending upon alpha_mode, it can be treated as M/N value or
 623                  * as a two’s compliment number. When alpha_mode=1,
 624                  * pll_alpha_val<15:8>=M and pll_apla_val<7:0>=N
 625                  *
 626                  *              Fout=FIN*(L+(M/N))
 627                  *
 628                  * M is a signed number (-128 to 127) and N is unsigned
 629                  * (0 to 255). M/N has to be within +/-0.5.
 630                  *
 631                  * When alpha_mode=0, it is a two’s compliment number in the
 632                  * range [-0.5, 0.5).
 633                  *
 634                  *              Fout=FIN*(L+(alpha_val)/2^16)
 635                  *
 636                  * where alpha_val is two’s compliment number.
 637                  */
 638                 if (!(ctl & PLL_ALPHA_MODE))
 639                         return alpha_huayra_pll_calc_rate(rate, l, alpha);
 640
 641                 alpha_m = alpha >> PLL_HUAYRA_M_SHIFT & PLL_HUAYRA_M_MASK;
 642                 alpha_n = alpha >> PLL_HUAYRA_N_SHIFT & PLL_HUAYRA_N_MASK;
 643
 644                 rate *= l;
 645                 tmp = parent_rate;
 646                 if (alpha_m >= BIT(PLL_HUAYRA_M_WIDTH - 1)) {
 647                         alpha_m = BIT(PLL_HUAYRA_M_WIDTH) - alpha_m;
 648                         tmp *= alpha_m;
 649                         do_div(tmp, alpha_n);
 650                         rate -= tmp;
 651                 } else {
 652                         tmp *= alpha_m;
 653                         do_div(tmp, alpha_n);
 654                         rate += tmp;
 655                 }
 656
 657                 return rate;
 658         }
 659
 660         return alpha_huayra_pll_calc_rate(rate, l, alpha);
 661 }
 662
 663 static int alpha_pll_huayra_set_rate(struct clk_hw *hw, unsigned long rate,
 664                                      unsigned long prate)
 665 {
 666         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 667         u32 l, a, ctl, cur_alpha = 0;
 668
 669         rate = alpha_huayra_pll_round_rate(rate, prate, &l, &a);
 670
 671         regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
 672
 673         if (ctl & PLL_ALPHA_EN)
 674                 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &cur_alpha);
 675
 676         /*
 677          * Huayra PLL supports PLL dynamic programming. User can change L_VAL,
 678          * without having to go through the power on sequence.
 679          */
 680         if (clk_alpha_pll_is_enabled(hw)) {
 681                 if (cur_alpha != a) {
 682                         pr_err("clock needs to be gated %s\n",
 683                                clk_hw_get_name(hw));
 684                         return -EBUSY;
 685                 }
 686
 687                 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
 688                 /* Ensure that the write above goes to detect L val change. */
 689                 mb();
 690                 return wait_for_pll_enable_lock(pll);
 691         }
 692
 693         regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
 694         regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
 695
 696         if (a == 0)
 697                 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
 698                                    PLL_ALPHA_EN, 0x0);
 699         else
 700                 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
 701                                    PLL_ALPHA_EN | PLL_ALPHA_MODE, PLL_ALPHA_EN);
 702
 703         return 0;
 704 }
 705
 706 static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate,
 707                                         unsigned long *prate)
 708 {
 709         u32 l, a;
 710
 711         return alpha_huayra_pll_round_rate(rate, *prate, &l, &a);
 712 }
 713
 714 const struct clk_ops clk_alpha_pll_ops = {
 715         .enable = clk_alpha_pll_enable,
 716         .disable = clk_alpha_pll_disable,
 717         .is_enabled = clk_alpha_pll_is_enabled,
 718         .recalc_rate = clk_alpha_pll_recalc_rate,
 719         .round_rate = clk_alpha_pll_round_rate,
 720         .set_rate = clk_alpha_pll_set_rate,
 721 };
 722 EXPORT_SYMBOL_GPL(clk_alpha_pll_ops);
 723
 724 const struct clk_ops clk_alpha_pll_huayra_ops = {
 725         .enable = clk_alpha_pll_enable,
 726         .disable = clk_alpha_pll_disable,
 727         .is_enabled = clk_alpha_pll_is_enabled,
 728         .recalc_rate = alpha_pll_huayra_recalc_rate,
 729         .round_rate = alpha_pll_huayra_round_rate,
 730         .set_rate = alpha_pll_huayra_set_rate,
 731 };
 732 EXPORT_SYMBOL_GPL(clk_alpha_pll_huayra_ops);
 733
 734 const struct clk_ops clk_alpha_pll_hwfsm_ops = {
 735         .enable = clk_alpha_pll_hwfsm_enable,
 736         .disable = clk_alpha_pll_hwfsm_disable,
 737         .is_enabled = clk_alpha_pll_hwfsm_is_enabled,
 738         .recalc_rate = clk_alpha_pll_recalc_rate,
 739         .round_rate = clk_alpha_pll_round_rate,
 740         .set_rate = clk_alpha_pll_hwfsm_set_rate,
 741 };
 742 EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops);
 743
 744 static unsigned long
 745 clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
 746 {
 747         struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
 748         u32 ctl;
 749
 750         regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
 751
 752         ctl >>= PLL_POST_DIV_SHIFT;
 753         ctl &= PLL_POST_DIV_MASK(pll);
 754
 755         return parent_rate >> fls(ctl);
 756 }
 757
 758 static const struct clk_div_table clk_alpha_div_table[] = {
 759         { 0x0, 1 },
 760         { 0x1, 2 },
 761         { 0x3, 4 },
 762         { 0x7, 8 },
 763         { 0xf, 16 },
 764         { }
 765 };
 766
 767 static const struct clk_div_table clk_alpha_2bit_div_table[] = {
 768         { 0x0, 1 },
 769         { 0x1, 2 },
 770         { 0x3, 4 },
 771         { }
 772 };
 773
 774 static long
 775 clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
 776                                  unsigned long *prate)
 777 {
 778         struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
 779         const struct clk_div_table *table;
 780
 781         if (pll->width == 2)
 782                 table = clk_alpha_2bit_div_table;
 783         else
 784                 table = clk_alpha_div_table;
 785
 786         return divider_round_rate(hw, rate, prate, table,
 787                                   pll->width, CLK_DIVIDER_POWER_OF_TWO);
 788 }
 789
 790 static long
 791 clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw *hw, unsigned long rate,
 792                                     unsigned long *prate)
 793 {
 794         struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
 795         u32 ctl, div;
 796
 797         regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
 798
 799         ctl >>= PLL_POST_DIV_SHIFT;
 800         ctl &= BIT(pll->width) - 1;
 801         div = 1 << fls(ctl);
 802
 803         if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)
 804                 *prate = clk_hw_round_rate(clk_hw_get_parent(hw), div * rate);
 805
 806         return DIV_ROUND_UP_ULL((u64)*prate, div);
 807 }
 808
 809 static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
 810                                           unsigned long parent_rate)
 811 {
 812         struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
 813         int div;
 814
 815         /* 16 -> 0xf, 8 -> 0x7, 4 -> 0x3, 2 -> 0x1, 1 -> 0x0 */
 816         div = DIV_ROUND_UP_ULL((u64)parent_rate, rate) - 1;
 817
 818         return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
 819                                   PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT,
 820                                   div << PLL_POST_DIV_SHIFT);
 821 }
 822
 823 const struct clk_ops clk_alpha_pll_postdiv_ops = {
 824         .recalc_rate = clk_alpha_pll_postdiv_recalc_rate,
 825         .round_rate = clk_alpha_pll_postdiv_round_rate,
 826         .set_rate = clk_alpha_pll_postdiv_set_rate,
 827 };
 828 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ops);
 829
 830 const struct clk_ops clk_alpha_pll_postdiv_ro_ops = {
 831         .round_rate = clk_alpha_pll_postdiv_round_ro_rate,
 832         .recalc_rate = clk_alpha_pll_postdiv_recalc_rate,
 833 };
 834 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ro_ops);