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x86/topology: Fix function name in documentation
[cris-mirror.git] / drivers / clk / sunxi-ng / ccu-sun8i-h3.c
blob29bc0566b776e7444f8a07c9a8660073a1ddadb8
1 /*
2 * Copyright (c) 2016 Maxime Ripard. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14 #include <linux/clk-provider.h>
15 #include <linux/of_address.h>
16
17 #include "ccu_common.h"
18 #include "ccu_reset.h"
19
20 #include "ccu_div.h"
21 #include "ccu_gate.h"
22 #include "ccu_mp.h"
23 #include "ccu_mult.h"
24 #include "ccu_nk.h"
25 #include "ccu_nkm.h"
26 #include "ccu_nkmp.h"
27 #include "ccu_nm.h"
28 #include "ccu_phase.h"
29 #include "ccu_sdm.h"
30
31 #include "ccu-sun8i-h3.h"
32
33 static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpux_clk, "pll-cpux",
34 "osc24M", 0x000,
35 8, 5, /* N */
36 4, 2, /* K */
37 0, 2, /* M */
38 16, 2, /* P */
39 BIT(31), /* gate */
40 BIT(28), /* lock */
41 CLK_SET_RATE_UNGATE);
42
43 /*
44 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
45 * the base (2x, 4x and 8x), and one variable divider (the one true
46 * pll audio).
47 *
48 * With sigma-delta modulation for fractional-N on the audio PLL,
49 * we have to use specific dividers. This means the variable divider
50 * can no longer be used, as the audio codec requests the exact clock
51 * rates we support through this mechanism. So we now hard code the
52 * variable divider to 1. This means the clock rates will no longer
53 * match the clock names.
54 */
55 #define SUN8I_H3_PLL_AUDIO_REG 0x008
56
57 static struct ccu_sdm_setting pll_audio_sdm_table[] = {
58 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
59 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
60 };
61
62 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
63 "osc24M", 0x008,
64 8, 7, /* N */
65 0, 5, /* M */
66 pll_audio_sdm_table, BIT(24),
67 0x284, BIT(31),
68 BIT(31), /* gate */
69 BIT(28), /* lock */
70 CLK_SET_RATE_UNGATE);
71
72 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
73 "osc24M", 0x0010,
74 8, 7, /* N */
75 0, 4, /* M */
76 BIT(24), /* frac enable */
77 BIT(25), /* frac select */
78 270000000, /* frac rate 0 */
79 297000000, /* frac rate 1 */
80 BIT(31), /* gate */
81 BIT(28), /* lock */
82 CLK_SET_RATE_UNGATE);
83
84 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
85 "osc24M", 0x0018,
86 8, 7, /* N */
87 0, 4, /* M */
88 BIT(24), /* frac enable */
89 BIT(25), /* frac select */
90 270000000, /* frac rate 0 */
91 297000000, /* frac rate 1 */
92 BIT(31), /* gate */
93 BIT(28), /* lock */
94 CLK_SET_RATE_UNGATE);
95
96 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr",
97 "osc24M", 0x020,
98 8, 5, /* N */
99 4, 2, /* K */
100 0, 2, /* M */
101 BIT(31), /* gate */
102 BIT(28), /* lock */
103 CLK_SET_RATE_UNGATE);
104
105 static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph0_clk, "pll-periph0",
106 "osc24M", 0x028,
107 8, 5, /* N */
108 4, 2, /* K */
109 BIT(31), /* gate */
110 BIT(28), /* lock */
111 2, /* post-div */
112 CLK_SET_RATE_UNGATE);
113
114 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
115 "osc24M", 0x0038,
116 8, 7, /* N */
117 0, 4, /* M */
118 BIT(24), /* frac enable */
119 BIT(25), /* frac select */
120 270000000, /* frac rate 0 */
121 297000000, /* frac rate 1 */
122 BIT(31), /* gate */
123 BIT(28), /* lock */
124 CLK_SET_RATE_UNGATE);
125
126 static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph1_clk, "pll-periph1",
127 "osc24M", 0x044,
128 8, 5, /* N */
129 4, 2, /* K */
130 BIT(31), /* gate */
131 BIT(28), /* lock */
132 2, /* post-div */
133 CLK_SET_RATE_UNGATE);
134
135 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
136 "osc24M", 0x0048,
137 8, 7, /* N */
138 0, 4, /* M */
139 BIT(24), /* frac enable */
140 BIT(25), /* frac select */
141 270000000, /* frac rate 0 */
142 297000000, /* frac rate 1 */
143 BIT(31), /* gate */
144 BIT(28), /* lock */
145 CLK_SET_RATE_UNGATE);
146
147 static const char * const cpux_parents[] = { "osc32k", "osc24M",
148 "pll-cpux" , "pll-cpux" };
149 static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
150 0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT);
151
152 static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
153
154 static const char * const ahb1_parents[] = { "osc32k", "osc24M",
155 "axi" , "pll-periph0" };
156 static const struct ccu_mux_var_prediv ahb1_predivs[] = {
157 { .index = 3, .shift = 6, .width = 2 },
158 };
159 static struct ccu_div ahb1_clk = {
160 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
161
162 .mux = {
163 .shift = 12,
164 .width = 2,
165
166 .var_predivs = ahb1_predivs,
167 .n_var_predivs = ARRAY_SIZE(ahb1_predivs),
168 },
169
170 .common = {
171 .reg = 0x054,
172 .features = CCU_FEATURE_VARIABLE_PREDIV,
173 .hw.init = CLK_HW_INIT_PARENTS("ahb1",
174 ahb1_parents,
175 &ccu_div_ops,
176 0),
177 },
178 };
179
180 static struct clk_div_table apb1_div_table[] = {
181 { .val = 0, .div = 2 },
182 { .val = 1, .div = 2 },
183 { .val = 2, .div = 4 },
184 { .val = 3, .div = 8 },
185 { /* Sentinel */ },
186 };
187 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
188 0x054, 8, 2, apb1_div_table, 0);
189
190 static const char * const apb2_parents[] = { "osc32k", "osc24M",
191 "pll-periph0" , "pll-periph0" };
192 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
193 0, 5, /* M */
194 16, 2, /* P */
195 24, 2, /* mux */
196 0);
197
198 static const char * const ahb2_parents[] = { "ahb1" , "pll-periph0" };
199 static const struct ccu_mux_fixed_prediv ahb2_fixed_predivs[] = {
200 { .index = 1, .div = 2 },
201 };
202 static struct ccu_mux ahb2_clk = {
203 .mux = {
204 .shift = 0,
205 .width = 1,
206 .fixed_predivs = ahb2_fixed_predivs,
207 .n_predivs = ARRAY_SIZE(ahb2_fixed_predivs),
208 },
209
210 .common = {
211 .reg = 0x05c,
212 .features = CCU_FEATURE_FIXED_PREDIV,
213 .hw.init = CLK_HW_INIT_PARENTS("ahb2",
214 ahb2_parents,
215 &ccu_mux_ops,
216 0),
217 },
218 };
219
220 static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "ahb1",
221 0x060, BIT(5), 0);
222 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
223 0x060, BIT(6), 0);
224 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
225 0x060, BIT(8), 0);
226 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
227 0x060, BIT(9), 0);
228 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
229 0x060, BIT(10), 0);
230 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
231 0x060, BIT(13), 0);
232 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
233 0x060, BIT(14), 0);
234 static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb2",
235 0x060, BIT(17), 0);
236 static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb1",
237 0x060, BIT(18), 0);
238 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
239 0x060, BIT(19), 0);
240 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1",
241 0x060, BIT(20), 0);
242 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1",
243 0x060, BIT(21), 0);
244 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1",
245 0x060, BIT(23), 0);
246 static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb1",
247 0x060, BIT(24), 0);
248 static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "ahb2",
249 0x060, BIT(25), 0);
250 static SUNXI_CCU_GATE(bus_ehci2_clk, "bus-ehci2", "ahb2",
251 0x060, BIT(26), 0);
252 static SUNXI_CCU_GATE(bus_ehci3_clk, "bus-ehci3", "ahb2",
253 0x060, BIT(27), 0);
254 static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb1",
255 0x060, BIT(28), 0);
256 static SUNXI_CCU_GATE(bus_ohci1_clk, "bus-ohci1", "ahb2",
257 0x060, BIT(29), 0);
258 static SUNXI_CCU_GATE(bus_ohci2_clk, "bus-ohci2", "ahb2",
259 0x060, BIT(30), 0);
260 static SUNXI_CCU_GATE(bus_ohci3_clk, "bus-ohci3", "ahb2",
261 0x060, BIT(31), 0);
262
263 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1",
264 0x064, BIT(0), 0);
265 static SUNXI_CCU_GATE(bus_tcon0_clk, "bus-tcon0", "ahb1",
266 0x064, BIT(3), 0);
267 static SUNXI_CCU_GATE(bus_tcon1_clk, "bus-tcon1", "ahb1",
268 0x064, BIT(4), 0);
269 static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "ahb1",
270 0x064, BIT(5), 0);
271 static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1",
272 0x064, BIT(8), 0);
273 static SUNXI_CCU_GATE(bus_tve_clk, "bus-tve", "ahb1",
274 0x064, BIT(9), 0);
275 static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb1",
276 0x064, BIT(11), 0);
277 static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb1",
278 0x064, BIT(12), 0);
279 static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1",
280 0x064, BIT(20), 0);
281 static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1",
282 0x064, BIT(21), 0);
283 static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1",
284 0x064, BIT(22), 0);
285
286 static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1",
287 0x068, BIT(0), 0);
288 static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1",
289 0x068, BIT(1), 0);
290 static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1",
291 0x068, BIT(5), 0);
292 static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1",
293 0x068, BIT(8), 0);
294 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1",
295 0x068, BIT(12), 0);
296 static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1",
297 0x068, BIT(13), 0);
298 static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1",
299 0x068, BIT(14), 0);
300
301 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
302 0x06c, BIT(0), 0);
303 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
304 0x06c, BIT(1), 0);
305 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2",
306 0x06c, BIT(2), 0);
307 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2",
308 0x06c, BIT(16), 0);
309 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2",
310 0x06c, BIT(17), 0);
311 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",
312 0x06c, BIT(18), 0);
313 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2",
314 0x06c, BIT(19), 0);
315 static SUNXI_CCU_GATE(bus_scr0_clk, "bus-scr0", "apb2",
316 0x06c, BIT(20), 0);
317 static SUNXI_CCU_GATE(bus_scr1_clk, "bus-scr1", "apb2",
318 0x06c, BIT(21), 0);
319
320 static SUNXI_CCU_GATE(bus_ephy_clk, "bus-ephy", "ahb1",
321 0x070, BIT(0), 0);
322 static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "ahb1",
323 0x070, BIT(7), 0);
324
325 static struct clk_div_table ths_div_table[] = {
326 { .val = 0, .div = 1 },
327 { .val = 1, .div = 2 },
328 { .val = 2, .div = 4 },
329 { .val = 3, .div = 6 },
330 };
331 static SUNXI_CCU_DIV_TABLE_WITH_GATE(ths_clk, "ths", "osc24M",
332 0x074, 0, 2, ths_div_table, BIT(31), 0);
333
334 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0",
335 "pll-periph1" };
336 static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
337 0, 4, /* M */
338 16, 2, /* P */
339 24, 2, /* mux */
340 BIT(31), /* gate */
341 0);
342
343 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
344 0, 4, /* M */
345 16, 2, /* P */
346 24, 2, /* mux */
347 BIT(31), /* gate */
348 0);
349
350 static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0",
351 0x088, 20, 3, 0);
352 static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0",
353 0x088, 8, 3, 0);
354
355 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
356 0, 4, /* M */
357 16, 2, /* P */
358 24, 2, /* mux */
359 BIT(31), /* gate */
360 0);
361
362 static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1",
363 0x08c, 20, 3, 0);
364 static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1",
365 0x08c, 8, 3, 0);
366
367 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
368 0, 4, /* M */
369 16, 2, /* P */
370 24, 2, /* mux */
371 BIT(31), /* gate */
372 0);
373
374 static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample", "mmc2",
375 0x090, 20, 3, 0);
376 static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2",
377 0x090, 8, 3, 0);
378
379 static const char * const ts_parents[] = { "osc24M", "pll-periph0", };
380 static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x098,
381 0, 4, /* M */
382 16, 2, /* P */
383 24, 2, /* mux */
384 BIT(31), /* gate */
385 0);
386
387 static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", mod0_default_parents, 0x09c,
388 0, 4, /* M */
389 16, 2, /* P */
390 24, 2, /* mux */
391 BIT(31), /* gate */
392 0);
393
394 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
395 0, 4, /* M */
396 16, 2, /* P */
397 24, 2, /* mux */
398 BIT(31), /* gate */
399 0);
400
401 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
402 0, 4, /* M */
403 16, 2, /* P */
404 24, 2, /* mux */
405 BIT(31), /* gate */
406 0);
407
408 static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
409 "pll-audio-2x", "pll-audio" };
410 static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents,
411 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
412
413 static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents,
414 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
415
416 static SUNXI_CCU_MUX_WITH_GATE(i2s2_clk, "i2s2", i2s_parents,
417 0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
418
419 static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio",
420 0x0c0, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
421
422 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
423 0x0cc, BIT(8), 0);
424 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
425 0x0cc, BIT(9), 0);
426 static SUNXI_CCU_GATE(usb_phy2_clk, "usb-phy2", "osc24M",
427 0x0cc, BIT(10), 0);
428 static SUNXI_CCU_GATE(usb_phy3_clk, "usb-phy3", "osc24M",
429 0x0cc, BIT(11), 0);
430 static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc24M",
431 0x0cc, BIT(16), 0);
432 static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "osc24M",
433 0x0cc, BIT(17), 0);
434 static SUNXI_CCU_GATE(usb_ohci2_clk, "usb-ohci2", "osc24M",
435 0x0cc, BIT(18), 0);
436 static SUNXI_CCU_GATE(usb_ohci3_clk, "usb-ohci3", "osc24M",
437 0x0cc, BIT(19), 0);
438
439 static const char * const dram_parents[] = { "pll-ddr", "pll-periph0-2x" };
440 static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents,
441 0x0f4, 0, 4, 20, 2, CLK_IS_CRITICAL);
442
443 static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram",
444 0x100, BIT(0), 0);
445 static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "dram",
446 0x100, BIT(1), 0);
447 static SUNXI_CCU_GATE(dram_deinterlace_clk, "dram-deinterlace", "dram",
448 0x100, BIT(2), 0);
449 static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "dram",
450 0x100, BIT(3), 0);
451
452 static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" };
453 static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
454 0x104, 0, 4, 24, 3, BIT(31), 0);
455
456 static const char * const tcon_parents[] = { "pll-video" };
457 static SUNXI_CCU_M_WITH_MUX_GATE(tcon_clk, "tcon", tcon_parents,
458 0x118, 0, 4, 24, 3, BIT(31), 0);
459
460 static const char * const tve_parents[] = { "pll-de", "pll-periph1" };
461 static SUNXI_CCU_M_WITH_MUX_GATE(tve_clk, "tve", tve_parents,
462 0x120, 0, 4, 24, 3, BIT(31), 0);
463
464 static const char * const deinterlace_parents[] = { "pll-periph0", "pll-periph1" };
465 static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace", deinterlace_parents,
466 0x124, 0, 4, 24, 3, BIT(31), 0);
467
468 static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M",
469 0x130, BIT(31), 0);
470
471 static const char * const csi_sclk_parents[] = { "pll-periph0", "pll-periph1" };
472 static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents,
473 0x134, 16, 4, 24, 3, BIT(31), 0);
474
475 static const char * const csi_mclk_parents[] = { "osc24M", "pll-video", "pll-periph0" };
476 static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk", csi_mclk_parents,
477 0x134, 0, 5, 8, 3, BIT(15), 0);
478
479 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
480 0x13c, 16, 3, BIT(31), 0);
481
482 static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio",
483 0x140, BIT(31), CLK_SET_RATE_PARENT);
484 static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M",
485 0x144, BIT(31), 0);
486
487 static const char * const hdmi_parents[] = { "pll-video" };
488 static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,
489 0x150, 0, 4, 24, 2, BIT(31), 0);
490
491 static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M",
492 0x154, BIT(31), 0);
493
494 static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x", "pll-ddr" };
495 static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,
496 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);
497
498 static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
499 0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
500
501 static struct ccu_common *sun8i_h3_ccu_clks[] = {
502 &pll_cpux_clk.common,
503 &pll_audio_base_clk.common,
504 &pll_video_clk.common,
505 &pll_ve_clk.common,
506 &pll_ddr_clk.common,
507 &pll_periph0_clk.common,
508 &pll_gpu_clk.common,
509 &pll_periph1_clk.common,
510 &pll_de_clk.common,
511 &cpux_clk.common,
512 &axi_clk.common,
513 &ahb1_clk.common,
514 &apb1_clk.common,
515 &apb2_clk.common,
516 &ahb2_clk.common,
517 &bus_ce_clk.common,
518 &bus_dma_clk.common,
519 &bus_mmc0_clk.common,
520 &bus_mmc1_clk.common,
521 &bus_mmc2_clk.common,
522 &bus_nand_clk.common,
523 &bus_dram_clk.common,
524 &bus_emac_clk.common,
525 &bus_ts_clk.common,
526 &bus_hstimer_clk.common,
527 &bus_spi0_clk.common,
528 &bus_spi1_clk.common,
529 &bus_otg_clk.common,
530 &bus_ehci0_clk.common,
531 &bus_ehci1_clk.common,
532 &bus_ehci2_clk.common,
533 &bus_ehci3_clk.common,
534 &bus_ohci0_clk.common,
535 &bus_ohci1_clk.common,
536 &bus_ohci2_clk.common,
537 &bus_ohci3_clk.common,
538 &bus_ve_clk.common,
539 &bus_tcon0_clk.common,
540 &bus_tcon1_clk.common,
541 &bus_deinterlace_clk.common,
542 &bus_csi_clk.common,
543 &bus_tve_clk.common,
544 &bus_hdmi_clk.common,
545 &bus_de_clk.common,
546 &bus_gpu_clk.common,
547 &bus_msgbox_clk.common,
548 &bus_spinlock_clk.common,
549 &bus_codec_clk.common,
550 &bus_spdif_clk.common,
551 &bus_pio_clk.common,
552 &bus_ths_clk.common,
553 &bus_i2s0_clk.common,
554 &bus_i2s1_clk.common,
555 &bus_i2s2_clk.common,
556 &bus_i2c0_clk.common,
557 &bus_i2c1_clk.common,
558 &bus_i2c2_clk.common,
559 &bus_uart0_clk.common,
560 &bus_uart1_clk.common,
561 &bus_uart2_clk.common,
562 &bus_uart3_clk.common,
563 &bus_scr0_clk.common,
564 &bus_ephy_clk.common,
565 &bus_dbg_clk.common,
566 &ths_clk.common,
567 &nand_clk.common,
568 &mmc0_clk.common,
569 &mmc0_sample_clk.common,
570 &mmc0_output_clk.common,
571 &mmc1_clk.common,
572 &mmc1_sample_clk.common,
573 &mmc1_output_clk.common,
574 &mmc2_clk.common,
575 &mmc2_sample_clk.common,
576 &mmc2_output_clk.common,
577 &ts_clk.common,
578 &ce_clk.common,
579 &spi0_clk.common,
580 &spi1_clk.common,
581 &i2s0_clk.common,
582 &i2s1_clk.common,
583 &i2s2_clk.common,
584 &spdif_clk.common,
585 &usb_phy0_clk.common,
586 &usb_phy1_clk.common,
587 &usb_phy2_clk.common,
588 &usb_phy3_clk.common,
589 &usb_ohci0_clk.common,
590 &usb_ohci1_clk.common,
591 &usb_ohci2_clk.common,
592 &usb_ohci3_clk.common,
593 &dram_clk.common,
594 &dram_ve_clk.common,
595 &dram_csi_clk.common,
596 &dram_deinterlace_clk.common,
597 &dram_ts_clk.common,
598 &de_clk.common,
599 &tcon_clk.common,
600 &tve_clk.common,
601 &deinterlace_clk.common,
602 &csi_misc_clk.common,
603 &csi_sclk_clk.common,
604 &csi_mclk_clk.common,
605 &ve_clk.common,
606 &ac_dig_clk.common,
607 &avs_clk.common,
608 &hdmi_clk.common,
609 &hdmi_ddc_clk.common,
610 &mbus_clk.common,
611 &gpu_clk.common,
612 };
613
614 static struct ccu_common *sun50i_h5_ccu_clks[] = {
615 &pll_cpux_clk.common,
616 &pll_audio_base_clk.common,
617 &pll_video_clk.common,
618 &pll_ve_clk.common,
619 &pll_ddr_clk.common,
620 &pll_periph0_clk.common,
621 &pll_gpu_clk.common,
622 &pll_periph1_clk.common,
623 &pll_de_clk.common,
624 &cpux_clk.common,
625 &axi_clk.common,
626 &ahb1_clk.common,
627 &apb1_clk.common,
628 &apb2_clk.common,
629 &ahb2_clk.common,
630 &bus_ce_clk.common,
631 &bus_dma_clk.common,
632 &bus_mmc0_clk.common,
633 &bus_mmc1_clk.common,
634 &bus_mmc2_clk.common,
635 &bus_nand_clk.common,
636 &bus_dram_clk.common,
637 &bus_emac_clk.common,
638 &bus_ts_clk.common,
639 &bus_hstimer_clk.common,
640 &bus_spi0_clk.common,
641 &bus_spi1_clk.common,
642 &bus_otg_clk.common,
643 &bus_ehci0_clk.common,
644 &bus_ehci1_clk.common,
645 &bus_ehci2_clk.common,
646 &bus_ehci3_clk.common,
647 &bus_ohci0_clk.common,
648 &bus_ohci1_clk.common,
649 &bus_ohci2_clk.common,
650 &bus_ohci3_clk.common,
651 &bus_ve_clk.common,
652 &bus_tcon0_clk.common,
653 &bus_tcon1_clk.common,
654 &bus_deinterlace_clk.common,
655 &bus_csi_clk.common,
656 &bus_tve_clk.common,
657 &bus_hdmi_clk.common,
658 &bus_de_clk.common,
659 &bus_gpu_clk.common,
660 &bus_msgbox_clk.common,
661 &bus_spinlock_clk.common,
662 &bus_codec_clk.common,
663 &bus_spdif_clk.common,
664 &bus_pio_clk.common,
665 &bus_ths_clk.common,
666 &bus_i2s0_clk.common,
667 &bus_i2s1_clk.common,
668 &bus_i2s2_clk.common,
669 &bus_i2c0_clk.common,
670 &bus_i2c1_clk.common,
671 &bus_i2c2_clk.common,
672 &bus_uart0_clk.common,
673 &bus_uart1_clk.common,
674 &bus_uart2_clk.common,
675 &bus_uart3_clk.common,
676 &bus_scr0_clk.common,
677 &bus_scr1_clk.common,
678 &bus_ephy_clk.common,
679 &bus_dbg_clk.common,
680 &ths_clk.common,
681 &nand_clk.common,
682 &mmc0_clk.common,
683 &mmc1_clk.common,
684 &mmc2_clk.common,
685 &ts_clk.common,
686 &ce_clk.common,
687 &spi0_clk.common,
688 &spi1_clk.common,
689 &i2s0_clk.common,
690 &i2s1_clk.common,
691 &i2s2_clk.common,
692 &spdif_clk.common,
693 &usb_phy0_clk.common,
694 &usb_phy1_clk.common,
695 &usb_phy2_clk.common,
696 &usb_phy3_clk.common,
697 &usb_ohci0_clk.common,
698 &usb_ohci1_clk.common,
699 &usb_ohci2_clk.common,
700 &usb_ohci3_clk.common,
701 &dram_clk.common,
702 &dram_ve_clk.common,
703 &dram_csi_clk.common,
704 &dram_deinterlace_clk.common,
705 &dram_ts_clk.common,
706 &de_clk.common,
707 &tcon_clk.common,
708 &tve_clk.common,
709 &deinterlace_clk.common,
710 &csi_misc_clk.common,
711 &csi_sclk_clk.common,
712 &csi_mclk_clk.common,
713 &ve_clk.common,
714 &ac_dig_clk.common,
715 &avs_clk.common,
716 &hdmi_clk.common,
717 &hdmi_ddc_clk.common,
718 &mbus_clk.common,
719 &gpu_clk.common,
720 };
721
722 /* We hardcode the divider to 1 for now */
723 static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
724 "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
725 static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
726 "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
727 static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
728 "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
729 static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
730 "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
731 static CLK_FIXED_FACTOR(pll_periph0_2x_clk, "pll-periph0-2x",
732 "pll-periph0", 1, 2, 0);
733
734 static struct clk_hw_onecell_data sun8i_h3_hw_clks = {
735 .hws = {
736 [CLK_PLL_CPUX] = &pll_cpux_clk.common.hw,
737 [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
738 [CLK_PLL_AUDIO] = &pll_audio_clk.hw,
739 [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
740 [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
741 [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
742 [CLK_PLL_VIDEO] = &pll_video_clk.common.hw,
743 [CLK_PLL_VE] = &pll_ve_clk.common.hw,
744 [CLK_PLL_DDR] = &pll_ddr_clk.common.hw,
745 [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw,
746 [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw,
747 [CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
748 [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw,
749 [CLK_PLL_DE] = &pll_de_clk.common.hw,
750 [CLK_CPUX] = &cpux_clk.common.hw,
751 [CLK_AXI] = &axi_clk.common.hw,
752 [CLK_AHB1] = &ahb1_clk.common.hw,
753 [CLK_APB1] = &apb1_clk.common.hw,
754 [CLK_APB2] = &apb2_clk.common.hw,
755 [CLK_AHB2] = &ahb2_clk.common.hw,
756 [CLK_BUS_CE] = &bus_ce_clk.common.hw,
757 [CLK_BUS_DMA] = &bus_dma_clk.common.hw,
758 [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
759 [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
760 [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
761 [CLK_BUS_NAND] = &bus_nand_clk.common.hw,
762 [CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
763 [CLK_BUS_EMAC] = &bus_emac_clk.common.hw,
764 [CLK_BUS_TS] = &bus_ts_clk.common.hw,
765 [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
766 [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
767 [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
768 [CLK_BUS_OTG] = &bus_otg_clk.common.hw,
769 [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw,
770 [CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw,
771 [CLK_BUS_EHCI2] = &bus_ehci2_clk.common.hw,
772 [CLK_BUS_EHCI3] = &bus_ehci3_clk.common.hw,
773 [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw,
774 [CLK_BUS_OHCI1] = &bus_ohci1_clk.common.hw,
775 [CLK_BUS_OHCI2] = &bus_ohci2_clk.common.hw,
776 [CLK_BUS_OHCI3] = &bus_ohci3_clk.common.hw,
777 [CLK_BUS_VE] = &bus_ve_clk.common.hw,
778 [CLK_BUS_TCON0] = &bus_tcon0_clk.common.hw,
779 [CLK_BUS_TCON1] = &bus_tcon1_clk.common.hw,
780 [CLK_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw,
781 [CLK_BUS_CSI] = &bus_csi_clk.common.hw,
782 [CLK_BUS_TVE] = &bus_tve_clk.common.hw,
783 [CLK_BUS_HDMI] = &bus_hdmi_clk.common.hw,
784 [CLK_BUS_DE] = &bus_de_clk.common.hw,
785 [CLK_BUS_GPU] = &bus_gpu_clk.common.hw,
786 [CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw,
787 [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw,
788 [CLK_BUS_CODEC] = &bus_codec_clk.common.hw,
789 [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw,
790 [CLK_BUS_PIO] = &bus_pio_clk.common.hw,
791 [CLK_BUS_THS] = &bus_ths_clk.common.hw,
792 [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
793 [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw,
794 [CLK_BUS_I2S2] = &bus_i2s2_clk.common.hw,
795 [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
796 [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
797 [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
798 [CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
799 [CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
800 [CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
801 [CLK_BUS_UART3] = &bus_uart3_clk.common.hw,
802 [CLK_BUS_SCR0] = &bus_scr0_clk.common.hw,
803 [CLK_BUS_EPHY] = &bus_ephy_clk.common.hw,
804 [CLK_BUS_DBG] = &bus_dbg_clk.common.hw,
805 [CLK_THS] = &ths_clk.common.hw,
806 [CLK_NAND] = &nand_clk.common.hw,
807 [CLK_MMC0] = &mmc0_clk.common.hw,
808 [CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw,
809 [CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw,
810 [CLK_MMC1] = &mmc1_clk.common.hw,
811 [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw,
812 [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw,
813 [CLK_MMC2] = &mmc2_clk.common.hw,
814 [CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw,
815 [CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw,
816 [CLK_TS] = &ts_clk.common.hw,
817 [CLK_CE] = &ce_clk.common.hw,
818 [CLK_SPI0] = &spi0_clk.common.hw,
819 [CLK_SPI1] = &spi1_clk.common.hw,
820 [CLK_I2S0] = &i2s0_clk.common.hw,
821 [CLK_I2S1] = &i2s1_clk.common.hw,
822 [CLK_I2S2] = &i2s2_clk.common.hw,
823 [CLK_SPDIF] = &spdif_clk.common.hw,
824 [CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
825 [CLK_USB_PHY1] = &usb_phy1_clk.common.hw,
826 [CLK_USB_PHY2] = &usb_phy2_clk.common.hw,
827 [CLK_USB_PHY3] = &usb_phy3_clk.common.hw,
828 [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
829 [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,
830 [CLK_USB_OHCI2] = &usb_ohci2_clk.common.hw,
831 [CLK_USB_OHCI3] = &usb_ohci3_clk.common.hw,
832 [CLK_DRAM] = &dram_clk.common.hw,
833 [CLK_DRAM_VE] = &dram_ve_clk.common.hw,
834 [CLK_DRAM_CSI] = &dram_csi_clk.common.hw,
835 [CLK_DRAM_DEINTERLACE] = &dram_deinterlace_clk.common.hw,
836 [CLK_DRAM_TS] = &dram_ts_clk.common.hw,
837 [CLK_DE] = &de_clk.common.hw,
838 [CLK_TCON0] = &tcon_clk.common.hw,
839 [CLK_TVE] = &tve_clk.common.hw,
840 [CLK_DEINTERLACE] = &deinterlace_clk.common.hw,
841 [CLK_CSI_MISC] = &csi_misc_clk.common.hw,
842 [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw,
843 [CLK_CSI_MCLK] = &csi_mclk_clk.common.hw,
844 [CLK_VE] = &ve_clk.common.hw,
845 [CLK_AC_DIG] = &ac_dig_clk.common.hw,
846 [CLK_AVS] = &avs_clk.common.hw,
847 [CLK_HDMI] = &hdmi_clk.common.hw,
848 [CLK_HDMI_DDC] = &hdmi_ddc_clk.common.hw,
849 [CLK_MBUS] = &mbus_clk.common.hw,
850 [CLK_GPU] = &gpu_clk.common.hw,
851 },
852 .num = CLK_NUMBER_H3,
853 };
854
855 static struct clk_hw_onecell_data sun50i_h5_hw_clks = {
856 .hws = {
857 [CLK_PLL_CPUX] = &pll_cpux_clk.common.hw,
858 [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
859 [CLK_PLL_AUDIO] = &pll_audio_clk.hw,
860 [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
861 [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
862 [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
863 [CLK_PLL_VIDEO] = &pll_video_clk.common.hw,
864 [CLK_PLL_VE] = &pll_ve_clk.common.hw,
865 [CLK_PLL_DDR] = &pll_ddr_clk.common.hw,
866 [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw,
867 [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw,
868 [CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
869 [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw,
870 [CLK_PLL_DE] = &pll_de_clk.common.hw,
871 [CLK_CPUX] = &cpux_clk.common.hw,
872 [CLK_AXI] = &axi_clk.common.hw,
873 [CLK_AHB1] = &ahb1_clk.common.hw,
874 [CLK_APB1] = &apb1_clk.common.hw,
875 [CLK_APB2] = &apb2_clk.common.hw,
876 [CLK_AHB2] = &ahb2_clk.common.hw,
877 [CLK_BUS_CE] = &bus_ce_clk.common.hw,
878 [CLK_BUS_DMA] = &bus_dma_clk.common.hw,
879 [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
880 [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
881 [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
882 [CLK_BUS_NAND] = &bus_nand_clk.common.hw,
883 [CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
884 [CLK_BUS_EMAC] = &bus_emac_clk.common.hw,
885 [CLK_BUS_TS] = &bus_ts_clk.common.hw,
886 [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
887 [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
888 [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
889 [CLK_BUS_OTG] = &bus_otg_clk.common.hw,
890 [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw,
891 [CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw,
892 [CLK_BUS_EHCI2] = &bus_ehci2_clk.common.hw,
893 [CLK_BUS_EHCI3] = &bus_ehci3_clk.common.hw,
894 [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw,
895 [CLK_BUS_OHCI1] = &bus_ohci1_clk.common.hw,
896 [CLK_BUS_OHCI2] = &bus_ohci2_clk.common.hw,
897 [CLK_BUS_OHCI3] = &bus_ohci3_clk.common.hw,
898 [CLK_BUS_VE] = &bus_ve_clk.common.hw,
899 [CLK_BUS_TCON0] = &bus_tcon0_clk.common.hw,
900 [CLK_BUS_TCON1] = &bus_tcon1_clk.common.hw,
901 [CLK_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw,
902 [CLK_BUS_CSI] = &bus_csi_clk.common.hw,
903 [CLK_BUS_TVE] = &bus_tve_clk.common.hw,
904 [CLK_BUS_HDMI] = &bus_hdmi_clk.common.hw,
905 [CLK_BUS_DE] = &bus_de_clk.common.hw,
906 [CLK_BUS_GPU] = &bus_gpu_clk.common.hw,
907 [CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw,
908 [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw,
909 [CLK_BUS_CODEC] = &bus_codec_clk.common.hw,
910 [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw,
911 [CLK_BUS_PIO] = &bus_pio_clk.common.hw,
912 [CLK_BUS_THS] = &bus_ths_clk.common.hw,
913 [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
914 [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw,
915 [CLK_BUS_I2S2] = &bus_i2s2_clk.common.hw,
916 [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
917 [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
918 [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
919 [CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
920 [CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
921 [CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
922 [CLK_BUS_UART3] = &bus_uart3_clk.common.hw,
923 [CLK_BUS_SCR0] = &bus_scr0_clk.common.hw,
924 [CLK_BUS_SCR1] = &bus_scr1_clk.common.hw,
925 [CLK_BUS_EPHY] = &bus_ephy_clk.common.hw,
926 [CLK_BUS_DBG] = &bus_dbg_clk.common.hw,
927 [CLK_THS] = &ths_clk.common.hw,
928 [CLK_NAND] = &nand_clk.common.hw,
929 [CLK_MMC0] = &mmc0_clk.common.hw,
930 [CLK_MMC1] = &mmc1_clk.common.hw,
931 [CLK_MMC2] = &mmc2_clk.common.hw,
932 [CLK_TS] = &ts_clk.common.hw,
933 [CLK_CE] = &ce_clk.common.hw,
934 [CLK_SPI0] = &spi0_clk.common.hw,
935 [CLK_SPI1] = &spi1_clk.common.hw,
936 [CLK_I2S0] = &i2s0_clk.common.hw,
937 [CLK_I2S1] = &i2s1_clk.common.hw,
938 [CLK_I2S2] = &i2s2_clk.common.hw,
939 [CLK_SPDIF] = &spdif_clk.common.hw,
940 [CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
941 [CLK_USB_PHY1] = &usb_phy1_clk.common.hw,
942 [CLK_USB_PHY2] = &usb_phy2_clk.common.hw,
943 [CLK_USB_PHY3] = &usb_phy3_clk.common.hw,
944 [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
945 [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,
946 [CLK_USB_OHCI2] = &usb_ohci2_clk.common.hw,
947 [CLK_USB_OHCI3] = &usb_ohci3_clk.common.hw,
948 [CLK_DRAM] = &dram_clk.common.hw,
949 [CLK_DRAM_VE] = &dram_ve_clk.common.hw,
950 [CLK_DRAM_CSI] = &dram_csi_clk.common.hw,
951 [CLK_DRAM_DEINTERLACE] = &dram_deinterlace_clk.common.hw,
952 [CLK_DRAM_TS] = &dram_ts_clk.common.hw,
953 [CLK_DE] = &de_clk.common.hw,
954 [CLK_TCON0] = &tcon_clk.common.hw,
955 [CLK_TVE] = &tve_clk.common.hw,
956 [CLK_DEINTERLACE] = &deinterlace_clk.common.hw,
957 [CLK_CSI_MISC] = &csi_misc_clk.common.hw,
958 [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw,
959 [CLK_CSI_MCLK] = &csi_mclk_clk.common.hw,
960 [CLK_VE] = &ve_clk.common.hw,
961 [CLK_AC_DIG] = &ac_dig_clk.common.hw,
962 [CLK_AVS] = &avs_clk.common.hw,
963 [CLK_HDMI] = &hdmi_clk.common.hw,
964 [CLK_HDMI_DDC] = &hdmi_ddc_clk.common.hw,
965 [CLK_MBUS] = &mbus_clk.common.hw,
966 [CLK_GPU] = &gpu_clk.common.hw,
967 },
968 .num = CLK_NUMBER_H5,
969 };
970
971 static struct ccu_reset_map sun8i_h3_ccu_resets[] = {
972 [RST_USB_PHY0] = { 0x0cc, BIT(0) },
973 [RST_USB_PHY1] = { 0x0cc, BIT(1) },
974 [RST_USB_PHY2] = { 0x0cc, BIT(2) },
975 [RST_USB_PHY3] = { 0x0cc, BIT(3) },
976
977 [RST_MBUS] = { 0x0fc, BIT(31) },
978
979 [RST_BUS_CE] = { 0x2c0, BIT(5) },
980 [RST_BUS_DMA] = { 0x2c0, BIT(6) },
981 [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
982 [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
983 [RST_BUS_MMC2] = { 0x2c0, BIT(10) },
984 [RST_BUS_NAND] = { 0x2c0, BIT(13) },
985 [RST_BUS_DRAM] = { 0x2c0, BIT(14) },
986 [RST_BUS_EMAC] = { 0x2c0, BIT(17) },
987 [RST_BUS_TS] = { 0x2c0, BIT(18) },
988 [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
989 [RST_BUS_SPI0] = { 0x2c0, BIT(20) },
990 [RST_BUS_SPI1] = { 0x2c0, BIT(21) },
991 [RST_BUS_OTG] = { 0x2c0, BIT(23) },
992 [RST_BUS_EHCI0] = { 0x2c0, BIT(24) },
993 [RST_BUS_EHCI1] = { 0x2c0, BIT(25) },
994 [RST_BUS_EHCI2] = { 0x2c0, BIT(26) },
995 [RST_BUS_EHCI3] = { 0x2c0, BIT(27) },
996 [RST_BUS_OHCI0] = { 0x2c0, BIT(28) },
997 [RST_BUS_OHCI1] = { 0x2c0, BIT(29) },
998 [RST_BUS_OHCI2] = { 0x2c0, BIT(30) },
999 [RST_BUS_OHCI3] = { 0x2c0, BIT(31) },
1000
1001 [RST_BUS_VE] = { 0x2c4, BIT(0) },
1002 [RST_BUS_TCON0] = { 0x2c4, BIT(3) },
1003 [RST_BUS_TCON1] = { 0x2c4, BIT(4) },
1004 [RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) },
1005 [RST_BUS_CSI] = { 0x2c4, BIT(8) },
1006 [RST_BUS_TVE] = { 0x2c4, BIT(9) },
1007 [RST_BUS_HDMI0] = { 0x2c4, BIT(10) },
1008 [RST_BUS_HDMI1] = { 0x2c4, BIT(11) },
1009 [RST_BUS_DE] = { 0x2c4, BIT(12) },
1010 [RST_BUS_GPU] = { 0x2c4, BIT(20) },
1011 [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) },
1012 [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) },
1013 [RST_BUS_DBG] = { 0x2c4, BIT(31) },
1014
1015 [RST_BUS_EPHY] = { 0x2c8, BIT(2) },
1016
1017 [RST_BUS_CODEC] = { 0x2d0, BIT(0) },
1018 [RST_BUS_SPDIF] = { 0x2d0, BIT(1) },
1019 [RST_BUS_THS] = { 0x2d0, BIT(8) },
1020 [RST_BUS_I2S0] = { 0x2d0, BIT(12) },
1021 [RST_BUS_I2S1] = { 0x2d0, BIT(13) },
1022 [RST_BUS_I2S2] = { 0x2d0, BIT(14) },
1023
1024 [RST_BUS_I2C0] = { 0x2d8, BIT(0) },
1025 [RST_BUS_I2C1] = { 0x2d8, BIT(1) },
1026 [RST_BUS_I2C2] = { 0x2d8, BIT(2) },
1027 [RST_BUS_UART0] = { 0x2d8, BIT(16) },
1028 [RST_BUS_UART1] = { 0x2d8, BIT(17) },
1029 [RST_BUS_UART2] = { 0x2d8, BIT(18) },
1030 [RST_BUS_UART3] = { 0x2d8, BIT(19) },
1031 [RST_BUS_SCR0] = { 0x2d8, BIT(20) },
1032 };
1033
1034 static struct ccu_reset_map sun50i_h5_ccu_resets[] = {
1035 [RST_USB_PHY0] = { 0x0cc, BIT(0) },
1036 [RST_USB_PHY1] = { 0x0cc, BIT(1) },
1037 [RST_USB_PHY2] = { 0x0cc, BIT(2) },
1038 [RST_USB_PHY3] = { 0x0cc, BIT(3) },
1039
1040 [RST_MBUS] = { 0x0fc, BIT(31) },
1041
1042 [RST_BUS_CE] = { 0x2c0, BIT(5) },
1043 [RST_BUS_DMA] = { 0x2c0, BIT(6) },
1044 [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
1045 [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
1046 [RST_BUS_MMC2] = { 0x2c0, BIT(10) },
1047 [RST_BUS_NAND] = { 0x2c0, BIT(13) },
1048 [RST_BUS_DRAM] = { 0x2c0, BIT(14) },
1049 [RST_BUS_EMAC] = { 0x2c0, BIT(17) },
1050 [RST_BUS_TS] = { 0x2c0, BIT(18) },
1051 [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
1052 [RST_BUS_SPI0] = { 0x2c0, BIT(20) },
1053 [RST_BUS_SPI1] = { 0x2c0, BIT(21) },
1054 [RST_BUS_OTG] = { 0x2c0, BIT(23) },
1055 [RST_BUS_EHCI0] = { 0x2c0, BIT(24) },
1056 [RST_BUS_EHCI1] = { 0x2c0, BIT(25) },
1057 [RST_BUS_EHCI2] = { 0x2c0, BIT(26) },
1058 [RST_BUS_EHCI3] = { 0x2c0, BIT(27) },
1059 [RST_BUS_OHCI0] = { 0x2c0, BIT(28) },
1060 [RST_BUS_OHCI1] = { 0x2c0, BIT(29) },
1061 [RST_BUS_OHCI2] = { 0x2c0, BIT(30) },
1062 [RST_BUS_OHCI3] = { 0x2c0, BIT(31) },
1063
1064 [RST_BUS_VE] = { 0x2c4, BIT(0) },
1065 [RST_BUS_TCON0] = { 0x2c4, BIT(3) },
1066 [RST_BUS_TCON1] = { 0x2c4, BIT(4) },
1067 [RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) },
1068 [RST_BUS_CSI] = { 0x2c4, BIT(8) },
1069 [RST_BUS_TVE] = { 0x2c4, BIT(9) },
1070 [RST_BUS_HDMI0] = { 0x2c4, BIT(10) },
1071 [RST_BUS_HDMI1] = { 0x2c4, BIT(11) },
1072 [RST_BUS_DE] = { 0x2c4, BIT(12) },
1073 [RST_BUS_GPU] = { 0x2c4, BIT(20) },
1074 [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) },
1075 [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) },
1076 [RST_BUS_DBG] = { 0x2c4, BIT(31) },
1077
1078 [RST_BUS_EPHY] = { 0x2c8, BIT(2) },
1079
1080 [RST_BUS_CODEC] = { 0x2d0, BIT(0) },
1081 [RST_BUS_SPDIF] = { 0x2d0, BIT(1) },
1082 [RST_BUS_THS] = { 0x2d0, BIT(8) },
1083 [RST_BUS_I2S0] = { 0x2d0, BIT(12) },
1084 [RST_BUS_I2S1] = { 0x2d0, BIT(13) },
1085 [RST_BUS_I2S2] = { 0x2d0, BIT(14) },
1086
1087 [RST_BUS_I2C0] = { 0x2d8, BIT(0) },
1088 [RST_BUS_I2C1] = { 0x2d8, BIT(1) },
1089 [RST_BUS_I2C2] = { 0x2d8, BIT(2) },
1090 [RST_BUS_UART0] = { 0x2d8, BIT(16) },
1091 [RST_BUS_UART1] = { 0x2d8, BIT(17) },
1092 [RST_BUS_UART2] = { 0x2d8, BIT(18) },
1093 [RST_BUS_UART3] = { 0x2d8, BIT(19) },
1094 [RST_BUS_SCR0] = { 0x2d8, BIT(20) },
1095 [RST_BUS_SCR1] = { 0x2d8, BIT(20) },
1096 };
1097
1098 static const struct sunxi_ccu_desc sun8i_h3_ccu_desc = {
1099 .ccu_clks = sun8i_h3_ccu_clks,
1100 .num_ccu_clks = ARRAY_SIZE(sun8i_h3_ccu_clks),
1101
1102 .hw_clks = &sun8i_h3_hw_clks,
1103
1104 .resets = sun8i_h3_ccu_resets,
1105 .num_resets = ARRAY_SIZE(sun8i_h3_ccu_resets),
1106 };
1107
1108 static const struct sunxi_ccu_desc sun50i_h5_ccu_desc = {
1109 .ccu_clks = sun50i_h5_ccu_clks,
1110 .num_ccu_clks = ARRAY_SIZE(sun50i_h5_ccu_clks),
1111
1112 .hw_clks = &sun50i_h5_hw_clks,
1113
1114 .resets = sun50i_h5_ccu_resets,
1115 .num_resets = ARRAY_SIZE(sun50i_h5_ccu_resets),
1116 };
1117
1118 static struct ccu_pll_nb sun8i_h3_pll_cpu_nb = {
1119 .common = &pll_cpux_clk.common,
1120 /* copy from pll_cpux_clk */
1121 .enable = BIT(31),
1122 .lock = BIT(28),
1123 };
1124
1125 static struct ccu_mux_nb sun8i_h3_cpu_nb = {
1126 .common = &cpux_clk.common,
1127 .cm = &cpux_clk.mux,
1128 .delay_us = 1, /* > 8 clock cycles at 24 MHz */
1129 .bypass_index = 1, /* index of 24 MHz oscillator */
1130 };
1131
1132 static void __init sunxi_h3_h5_ccu_init(struct device_node *node,
1133 const struct sunxi_ccu_desc *desc)
1134 {
1135 void __iomem *reg;
1136 u32 val;
1137
1138 reg = of_io_request_and_map(node, 0, of_node_full_name(node));
1139 if (IS_ERR(reg)) {
1140 pr_err("%pOF: Could not map the clock registers\n", node);
1141 return;
1142 }
1143
1144 /* Force the PLL-Audio-1x divider to 1 */
1145 val = readl(reg + SUN8I_H3_PLL_AUDIO_REG);
1146 val &= ~GENMASK(19, 16);
1147 writel(val | (0 << 16), reg + SUN8I_H3_PLL_AUDIO_REG);
1148
1149 sunxi_ccu_probe(node, reg, desc);
1150
1151 /* Gate then ungate PLL CPU after any rate changes */
1152 ccu_pll_notifier_register(&sun8i_h3_pll_cpu_nb);
1153
1154 /* Reparent CPU during PLL CPU rate changes */
1155 ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
1156 &sun8i_h3_cpu_nb);
1157 }
1158
1159 static void __init sun8i_h3_ccu_setup(struct device_node *node)
1160 {
1161 sunxi_h3_h5_ccu_init(node, &sun8i_h3_ccu_desc);
1162 }
1163 CLK_OF_DECLARE(sun8i_h3_ccu, "allwinner,sun8i-h3-ccu",
1164 sun8i_h3_ccu_setup);
1165
1166 static void __init sun50i_h5_ccu_setup(struct device_node *node)
1167 {
1168 sunxi_h3_h5_ccu_init(node, &sun50i_h5_ccu_desc);
1169 }
1170 CLK_OF_DECLARE(sun50i_h5_ccu, "allwinner,sun50i-h5-ccu",
1171 sun50i_h5_ccu_setup);
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