drivers/i2c/busses/i2c-designware-pcidrv.c

   1 /*
   2  * Synopsys DesignWare I2C adapter driver (master only).
   3  *
   4  * Based on the TI DAVINCI I2C adapter driver.
   5  *
   6  * Copyright (C) 2006 Texas Instruments.
   7  * Copyright (C) 2007 MontaVista Software Inc.
   8  * Copyright (C) 2009 Provigent Ltd.
   9  * Copyright (C) 2011, 2015, 2016 Intel Corporation.
  10  *
  11  * ----------------------------------------------------------------------------
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; either version 2 of the License, or
  16  * (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  * ----------------------------------------------------------------------------
  23  *
  24  */
  25
  26 #include <linux/acpi.h>
  27 #include <linux/delay.h>
  28 #include <linux/err.h>
  29 #include <linux/errno.h>
  30 #include <linux/i2c.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/io.h>
  33 #include <linux/kernel.h>
  34 #include <linux/module.h>
  35 #include <linux/pci.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/sched.h>
  38 #include <linux/slab.h>
  39
  40 #include "i2c-designware-core.h"
  41
  42 #define DRIVER_NAME "i2c-designware-pci"
  43
  44 enum dw_pci_ctl_id_t {
  45         medfield,
  46         merrifield,
  47         baytrail,
  48         cherrytrail,
  49         haswell,
  50 };
  51
  52 struct dw_scl_sda_cfg {
  53         u32 ss_hcnt;
  54         u32 fs_hcnt;
  55         u32 ss_lcnt;
  56         u32 fs_lcnt;
  57         u32 sda_hold;
  58 };
  59
  60 struct dw_pci_controller {
  61         u32 bus_num;
  62         u32 bus_cfg;
  63         u32 tx_fifo_depth;
  64         u32 rx_fifo_depth;
  65         u32 clk_khz;
  66         u32 functionality;
  67         u32 flags;
  68         struct dw_scl_sda_cfg *scl_sda_cfg;
  69         int (*setup)(struct pci_dev *pdev, struct dw_pci_controller *c);
  70 };
  71
  72 #define INTEL_MID_STD_CFG  (DW_IC_CON_MASTER |                  \
  73                                 DW_IC_CON_SLAVE_DISABLE |       \
  74                                 DW_IC_CON_RESTART_EN)
  75
  76 /* Merrifield HCNT/LCNT/SDA hold time */
  77 static struct dw_scl_sda_cfg mrfld_config = {
  78         .ss_hcnt = 0x2f8,
  79         .fs_hcnt = 0x87,
  80         .ss_lcnt = 0x37b,
  81         .fs_lcnt = 0x10a,
  82 };
  83
  84 /* BayTrail HCNT/LCNT/SDA hold time */
  85 static struct dw_scl_sda_cfg byt_config = {
  86         .ss_hcnt = 0x200,
  87         .fs_hcnt = 0x55,
  88         .ss_lcnt = 0x200,
  89         .fs_lcnt = 0x99,
  90         .sda_hold = 0x6,
  91 };
  92
  93 /* Haswell HCNT/LCNT/SDA hold time */
  94 static struct dw_scl_sda_cfg hsw_config = {
  95         .ss_hcnt = 0x01b0,
  96         .fs_hcnt = 0x48,
  97         .ss_lcnt = 0x01fb,
  98         .fs_lcnt = 0xa0,
  99         .sda_hold = 0x9,
 100 };
 101
 102 static int mfld_setup(struct pci_dev *pdev, struct dw_pci_controller *c)
 103 {
 104         switch (pdev->device) {
 105         case 0x0817:
 106                 c->bus_cfg &= ~DW_IC_CON_SPEED_MASK;
 107                 c->bus_cfg |= DW_IC_CON_SPEED_STD;
 108         case 0x0818:
 109         case 0x0819:
 110                 c->bus_num = pdev->device - 0x817 + 3;
 111                 return 0;
 112         case 0x082C:
 113         case 0x082D:
 114         case 0x082E:
 115                 c->bus_num = pdev->device - 0x82C + 0;
 116                 return 0;
 117         }
 118         return -ENODEV;
 119 }
 120
 121 static int mrfld_setup(struct pci_dev *pdev, struct dw_pci_controller *c)
 122 {
 123         /*
 124          * On Intel Merrifield the user visible i2c busses are enumerated
 125          * [1..7]. So, we add 1 to shift the default range. Besides that the
 126          * first PCI slot provides 4 functions, that's why we have to add 0 to
 127          * the first slot and 4 to the next one.
 128          */
 129         switch (PCI_SLOT(pdev->devfn)) {
 130         case 8:
 131                 c->bus_num = PCI_FUNC(pdev->devfn) + 0 + 1;
 132                 return 0;
 133         case 9:
 134                 c->bus_num = PCI_FUNC(pdev->devfn) + 4 + 1;
 135                 return 0;
 136         }
 137         return -ENODEV;
 138 }
 139
 140 static struct dw_pci_controller dw_pci_controllers[] = {
 141         [medfield] = {
 142                 .bus_num = -1,
 143                 .bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
 144                 .tx_fifo_depth = 32,
 145                 .rx_fifo_depth = 32,
 146                 .functionality = I2C_FUNC_10BIT_ADDR,
 147                 .clk_khz      = 25000,
 148                 .setup = mfld_setup,
 149         },
 150         [merrifield] = {
 151                 .bus_num = -1,
 152                 .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
 153                 .tx_fifo_depth = 64,
 154                 .rx_fifo_depth = 64,
 155                 .functionality = I2C_FUNC_10BIT_ADDR,
 156                 .scl_sda_cfg = &mrfld_config,
 157                 .setup = mrfld_setup,
 158         },
 159         [baytrail] = {
 160                 .bus_num = -1,
 161                 .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
 162                 .tx_fifo_depth = 32,
 163                 .rx_fifo_depth = 32,
 164                 .functionality = I2C_FUNC_10BIT_ADDR,
 165                 .scl_sda_cfg = &byt_config,
 166         },
 167         [haswell] = {
 168                 .bus_num = -1,
 169                 .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
 170                 .tx_fifo_depth = 32,
 171                 .rx_fifo_depth = 32,
 172                 .functionality = I2C_FUNC_10BIT_ADDR,
 173                 .scl_sda_cfg = &hsw_config,
 174         },
 175         [cherrytrail] = {
 176                 .bus_num = -1,
 177                 .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
 178                 .tx_fifo_depth = 32,
 179                 .rx_fifo_depth = 32,
 180                 .functionality = I2C_FUNC_10BIT_ADDR,
 181                 .flags = MODEL_CHERRYTRAIL,
 182                 .scl_sda_cfg = &byt_config,
 183         },
 184 };
 185
 186 #ifdef CONFIG_PM
 187 static int i2c_dw_pci_suspend(struct device *dev)
 188 {
 189         struct pci_dev *pdev = to_pci_dev(dev);
 190         struct dw_i2c_dev *i_dev = pci_get_drvdata(pdev);
 191
 192         i_dev->disable(i_dev);
 193
 194         return 0;
 195 }
 196
 197 static int i2c_dw_pci_resume(struct device *dev)
 198 {
 199         struct pci_dev *pdev = to_pci_dev(dev);
 200         struct dw_i2c_dev *i_dev = pci_get_drvdata(pdev);
 201
 202         return i_dev->init(i_dev);
 203 }
 204 #endif
 205
 206 static UNIVERSAL_DEV_PM_OPS(i2c_dw_pm_ops, i2c_dw_pci_suspend,
 207                             i2c_dw_pci_resume, NULL);
 208
 209 static u32 i2c_dw_get_clk_rate_khz(struct dw_i2c_dev *dev)
 210 {
 211         return dev->controller->clk_khz;
 212 }
 213
 214 static int i2c_dw_pci_probe(struct pci_dev *pdev,
 215                             const struct pci_device_id *id)
 216 {
 217         struct dw_i2c_dev *dev;
 218         struct i2c_adapter *adap;
 219         int r;
 220         struct dw_pci_controller *controller;
 221         struct dw_scl_sda_cfg *cfg;
 222
 223         if (id->driver_data >= ARRAY_SIZE(dw_pci_controllers)) {
 224                 dev_err(&pdev->dev, "%s: invalid driver data %ld\n", __func__,
 225                         id->driver_data);
 226                 return -EINVAL;
 227         }
 228
 229         controller = &dw_pci_controllers[id->driver_data];
 230
 231         r = pcim_enable_device(pdev);
 232         if (r) {
 233                 dev_err(&pdev->dev, "Failed to enable I2C PCI device (%d)\n",
 234                         r);
 235                 return r;
 236         }
 237
 238         r = pcim_iomap_regions(pdev, 1 << 0, pci_name(pdev));
 239         if (r) {
 240                 dev_err(&pdev->dev, "I/O memory remapping failed\n");
 241                 return r;
 242         }
 243
 244         dev = devm_kzalloc(&pdev->dev, sizeof(struct dw_i2c_dev), GFP_KERNEL);
 245         if (!dev)
 246                 return -ENOMEM;
 247
 248         dev->clk = NULL;
 249         dev->controller = controller;
 250         dev->get_clk_rate_khz = i2c_dw_get_clk_rate_khz;
 251         dev->base = pcim_iomap_table(pdev)[0];
 252         dev->dev = &pdev->dev;
 253         dev->irq = pdev->irq;
 254         dev->flags |= controller->flags;
 255
 256         if (controller->setup) {
 257                 r = controller->setup(pdev, controller);
 258                 if (r)
 259                         return r;
 260         }
 261
 262         dev->functionality = controller->functionality |
 263                                 DW_IC_DEFAULT_FUNCTIONALITY;
 264
 265         dev->master_cfg = controller->bus_cfg;
 266         if (controller->scl_sda_cfg) {
 267                 cfg = controller->scl_sda_cfg;
 268                 dev->ss_hcnt = cfg->ss_hcnt;
 269                 dev->fs_hcnt = cfg->fs_hcnt;
 270                 dev->ss_lcnt = cfg->ss_lcnt;
 271                 dev->fs_lcnt = cfg->fs_lcnt;
 272                 dev->sda_hold_time = cfg->sda_hold;
 273         }
 274
 275         pci_set_drvdata(pdev, dev);
 276
 277         dev->tx_fifo_depth = controller->tx_fifo_depth;
 278         dev->rx_fifo_depth = controller->rx_fifo_depth;
 279
 280         adap = &dev->adapter;
 281         adap->owner = THIS_MODULE;
 282         adap->class = 0;
 283         ACPI_COMPANION_SET(&adap->dev, ACPI_COMPANION(&pdev->dev));
 284         adap->nr = controller->bus_num;
 285
 286         r = i2c_dw_probe(dev);
 287         if (r)
 288                 return r;
 289
 290         pm_runtime_set_autosuspend_delay(&pdev->dev, 1000);
 291         pm_runtime_use_autosuspend(&pdev->dev);
 292         pm_runtime_put_autosuspend(&pdev->dev);
 293         pm_runtime_allow(&pdev->dev);
 294
 295         return 0;
 296 }
 297
 298 static void i2c_dw_pci_remove(struct pci_dev *pdev)
 299 {
 300         struct dw_i2c_dev *dev = pci_get_drvdata(pdev);
 301
 302         dev->disable(dev);
 303         pm_runtime_forbid(&pdev->dev);
 304         pm_runtime_get_noresume(&pdev->dev);
 305
 306         i2c_del_adapter(&dev->adapter);
 307 }
 308
 309 /* work with hotplug and coldplug */
 310 MODULE_ALIAS("i2c_designware-pci");
 311
 312 static const struct pci_device_id i2_designware_pci_ids[] = {
 313         /* Medfield */
 314         { PCI_VDEVICE(INTEL, 0x0817), medfield },
 315         { PCI_VDEVICE(INTEL, 0x0818), medfield },
 316         { PCI_VDEVICE(INTEL, 0x0819), medfield },
 317         { PCI_VDEVICE(INTEL, 0x082C), medfield },
 318         { PCI_VDEVICE(INTEL, 0x082D), medfield },
 319         { PCI_VDEVICE(INTEL, 0x082E), medfield },
 320         /* Merrifield */
 321         { PCI_VDEVICE(INTEL, 0x1195), merrifield },
 322         { PCI_VDEVICE(INTEL, 0x1196), merrifield },
 323         /* Baytrail */
 324         { PCI_VDEVICE(INTEL, 0x0F41), baytrail },
 325         { PCI_VDEVICE(INTEL, 0x0F42), baytrail },
 326         { PCI_VDEVICE(INTEL, 0x0F43), baytrail },
 327         { PCI_VDEVICE(INTEL, 0x0F44), baytrail },
 328         { PCI_VDEVICE(INTEL, 0x0F45), baytrail },
 329         { PCI_VDEVICE(INTEL, 0x0F46), baytrail },
 330         { PCI_VDEVICE(INTEL, 0x0F47), baytrail },
 331         /* Haswell */
 332         { PCI_VDEVICE(INTEL, 0x9c61), haswell },
 333         { PCI_VDEVICE(INTEL, 0x9c62), haswell },
 334         /* Braswell / Cherrytrail */
 335         { PCI_VDEVICE(INTEL, 0x22C1), cherrytrail },
 336         { PCI_VDEVICE(INTEL, 0x22C2), cherrytrail },
 337         { PCI_VDEVICE(INTEL, 0x22C3), cherrytrail },
 338         { PCI_VDEVICE(INTEL, 0x22C4), cherrytrail },
 339         { PCI_VDEVICE(INTEL, 0x22C5), cherrytrail },
 340         { PCI_VDEVICE(INTEL, 0x22C6), cherrytrail },
 341         { PCI_VDEVICE(INTEL, 0x22C7), cherrytrail },
 342         { 0,}
 343 };
 344 MODULE_DEVICE_TABLE(pci, i2_designware_pci_ids);
 345
 346 static struct pci_driver dw_i2c_driver = {
 347         .name           = DRIVER_NAME,
 348         .id_table       = i2_designware_pci_ids,
 349         .probe          = i2c_dw_pci_probe,
 350         .remove         = i2c_dw_pci_remove,
 351         .driver         = {
 352                 .pm     = &i2c_dw_pm_ops,
 353         },
 354 };
 355
 356 module_pci_driver(dw_i2c_driver);
 357
 358 MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
 359 MODULE_DESCRIPTION("Synopsys DesignWare PCI I2C bus adapter");
 360 MODULE_LICENSE("GPL");