drivers/i2c/busses/i2c-designware-slave.c

   1 /*
   2  * Synopsys DesignWare I2C adapter driver (slave only).
   3  *
   4  * Based on the Synopsys DesignWare I2C adapter driver (master).
   5  *
   6  * Copyright (C) 2016 Synopsys Inc.
   7  *
   8  * ----------------------------------------------------------------------------
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  * ----------------------------------------------------------------------------
  20  *
  21  */
  22 #include <linux/delay.h>
  23 #include <linux/err.h>
  24 #include <linux/errno.h>
  25 #include <linux/i2c.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/io.h>
  28 #include <linux/module.h>
  29 #include <linux/pm_runtime.h>
  30
  31 #include "i2c-designware-core.h"
  32
  33 static void i2c_dw_configure_fifo_slave(struct dw_i2c_dev *dev)
  34 {
  35         /* Configure Tx/Rx FIFO threshold levels. */
  36         dw_writel(dev, 0, DW_IC_TX_TL);
  37         dw_writel(dev, 0, DW_IC_RX_TL);
  38
  39         /* Configure the I2C slave. */
  40         dw_writel(dev, dev->slave_cfg, DW_IC_CON);
  41         dw_writel(dev, DW_IC_INTR_SLAVE_MASK, DW_IC_INTR_MASK);
  42 }
  43
  44 /**
  45  * i2c_dw_init_slave() - Initialize the designware i2c slave hardware
  46  * @dev: device private data
  47  *
  48  * This function configures and enables the I2C in slave mode.
  49  * This function is called during I2C init function, and in case of timeout at
  50  * run time.
  51  */
  52 static int i2c_dw_init_slave(struct dw_i2c_dev *dev)
  53 {
  54         u32 reg, comp_param1;
  55         int ret;
  56
  57         ret = i2c_dw_acquire_lock(dev);
  58         if (ret)
  59                 return ret;
  60
  61         reg = dw_readl(dev, DW_IC_COMP_TYPE);
  62         if (reg == ___constant_swab32(DW_IC_COMP_TYPE_VALUE)) {
  63                 /* Configure register endianness access. */
  64                 dev->flags |= ACCESS_SWAP;
  65         } else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) {
  66                 /* Configure register access mode 16bit. */
  67                 dev->flags |= ACCESS_16BIT;
  68         } else if (reg != DW_IC_COMP_TYPE_VALUE) {
  69                 dev_err(dev->dev,
  70                         "Unknown Synopsys component type: 0x%08x\n", reg);
  71                 i2c_dw_release_lock(dev);
  72                 return -ENODEV;
  73         }
  74
  75         comp_param1 = dw_readl(dev, DW_IC_COMP_PARAM_1);
  76
  77         /* Disable the adapter. */
  78         __i2c_dw_enable_and_wait(dev, false);
  79
  80         /* Configure SDA Hold Time if required. */
  81         reg = dw_readl(dev, DW_IC_COMP_VERSION);
  82         if (reg >= DW_IC_SDA_HOLD_MIN_VERS) {
  83                 if (!dev->sda_hold_time) {
  84                         /* Keep previous hold time setting if no one set it. */
  85                         dev->sda_hold_time = dw_readl(dev, DW_IC_SDA_HOLD);
  86                 }
  87                 /*
  88                  * Workaround for avoiding TX arbitration lost in case I2C
  89                  * slave pulls SDA down "too quickly" after falling egde of
  90                  * SCL by enabling non-zero SDA RX hold. Specification says it
  91                  * extends incoming SDA low to high transition while SCL is
  92                  * high but it apprears to help also above issue.
  93                  */
  94                 if (!(dev->sda_hold_time & DW_IC_SDA_HOLD_RX_MASK))
  95                         dev->sda_hold_time |= 1 << DW_IC_SDA_HOLD_RX_SHIFT;
  96                 dw_writel(dev, dev->sda_hold_time, DW_IC_SDA_HOLD);
  97         } else {
  98                 dev_warn(dev->dev,
  99                          "Hardware too old to adjust SDA hold time.\n");
 100         }
 101
 102         i2c_dw_configure_fifo_slave(dev);
 103         i2c_dw_release_lock(dev);
 104
 105         return 0;
 106 }
 107
 108 static int i2c_dw_reg_slave(struct i2c_client *slave)
 109 {
 110         struct dw_i2c_dev *dev = i2c_get_adapdata(slave->adapter);
 111
 112         if (dev->slave)
 113                 return -EBUSY;
 114         if (slave->flags & I2C_CLIENT_TEN)
 115                 return -EAFNOSUPPORT;
 116         pm_runtime_get_sync(dev->dev);
 117
 118         /*
 119          * Set slave address in the IC_SAR register,
 120          * the address to which the DW_apb_i2c responds.
 121          */
 122         __i2c_dw_enable(dev, false);
 123         dw_writel(dev, slave->addr, DW_IC_SAR);
 124         dev->slave = slave;
 125
 126         __i2c_dw_enable(dev, true);
 127
 128         dev->cmd_err = 0;
 129         dev->msg_write_idx = 0;
 130         dev->msg_read_idx = 0;
 131         dev->msg_err = 0;
 132         dev->status = STATUS_IDLE;
 133         dev->abort_source = 0;
 134         dev->rx_outstanding = 0;
 135
 136         return 0;
 137 }
 138
 139 static int i2c_dw_unreg_slave(struct i2c_client *slave)
 140 {
 141         struct dw_i2c_dev *dev = i2c_get_adapdata(slave->adapter);
 142
 143         dev->disable_int(dev);
 144         dev->disable(dev);
 145         dev->slave = NULL;
 146         pm_runtime_put(dev->dev);
 147
 148         return 0;
 149 }
 150
 151 static u32 i2c_dw_read_clear_intrbits_slave(struct dw_i2c_dev *dev)
 152 {
 153         u32 stat;
 154
 155         /*
 156          * The IC_INTR_STAT register just indicates "enabled" interrupts.
 157          * Ths unmasked raw version of interrupt status bits are available
 158          * in the IC_RAW_INTR_STAT register.
 159          *
 160          * That is,
 161          *   stat = dw_readl(IC_INTR_STAT);
 162          * equals to,
 163          *   stat = dw_readl(IC_RAW_INTR_STAT) & dw_readl(IC_INTR_MASK);
 164          *
 165          * The raw version might be useful for debugging purposes.
 166          */
 167         stat = dw_readl(dev, DW_IC_INTR_STAT);
 168
 169         /*
 170          * Do not use the IC_CLR_INTR register to clear interrupts, or
 171          * you'll miss some interrupts, triggered during the period from
 172          * dw_readl(IC_INTR_STAT) to dw_readl(IC_CLR_INTR).
 173          *
 174          * Instead, use the separately-prepared IC_CLR_* registers.
 175          */
 176         if (stat & DW_IC_INTR_TX_ABRT)
 177                 dw_readl(dev, DW_IC_CLR_TX_ABRT);
 178         if (stat & DW_IC_INTR_RX_UNDER)
 179                 dw_readl(dev, DW_IC_CLR_RX_UNDER);
 180         if (stat & DW_IC_INTR_RX_OVER)
 181                 dw_readl(dev, DW_IC_CLR_RX_OVER);
 182         if (stat & DW_IC_INTR_TX_OVER)
 183                 dw_readl(dev, DW_IC_CLR_TX_OVER);
 184         if (stat & DW_IC_INTR_RX_DONE)
 185                 dw_readl(dev, DW_IC_CLR_RX_DONE);
 186         if (stat & DW_IC_INTR_ACTIVITY)
 187                 dw_readl(dev, DW_IC_CLR_ACTIVITY);
 188         if (stat & DW_IC_INTR_STOP_DET)
 189                 dw_readl(dev, DW_IC_CLR_STOP_DET);
 190         if (stat & DW_IC_INTR_START_DET)
 191                 dw_readl(dev, DW_IC_CLR_START_DET);
 192         if (stat & DW_IC_INTR_GEN_CALL)
 193                 dw_readl(dev, DW_IC_CLR_GEN_CALL);
 194
 195         return stat;
 196 }
 197
 198 /*
 199  * Interrupt service routine. This gets called whenever an I2C slave interrupt
 200  * occurs.
 201  */
 202
 203 static int i2c_dw_irq_handler_slave(struct dw_i2c_dev *dev)
 204 {
 205         u32 raw_stat, stat, enabled;
 206         u8 val, slave_activity;
 207
 208         stat = dw_readl(dev, DW_IC_INTR_STAT);
 209         enabled = dw_readl(dev, DW_IC_ENABLE);
 210         raw_stat = dw_readl(dev, DW_IC_RAW_INTR_STAT);
 211         slave_activity = ((dw_readl(dev, DW_IC_STATUS) &
 212                 DW_IC_STATUS_SLAVE_ACTIVITY) >> 6);
 213
 214         if (!enabled || !(raw_stat & ~DW_IC_INTR_ACTIVITY) || !dev->slave)
 215                 return 0;
 216
 217         dev_dbg(dev->dev,
 218                 "%#x STATUS SLAVE_ACTIVITY=%#x : RAW_INTR_STAT=%#x : INTR_STAT=%#x\n",
 219                 enabled, slave_activity, raw_stat, stat);
 220
 221         if ((stat & DW_IC_INTR_RX_FULL) && (stat & DW_IC_INTR_STOP_DET))
 222                 i2c_slave_event(dev->slave, I2C_SLAVE_WRITE_REQUESTED, &val);
 223
 224         if (stat & DW_IC_INTR_RD_REQ) {
 225                 if (slave_activity) {
 226                         if (stat & DW_IC_INTR_RX_FULL) {
 227                                 val = dw_readl(dev, DW_IC_DATA_CMD);
 228
 229                                 if (!i2c_slave_event(dev->slave,
 230                                                      I2C_SLAVE_WRITE_RECEIVED,
 231                                                      &val)) {
 232                                         dev_vdbg(dev->dev, "Byte %X acked!",
 233                                                  val);
 234                                 }
 235                                 dw_readl(dev, DW_IC_CLR_RD_REQ);
 236                                 stat = i2c_dw_read_clear_intrbits_slave(dev);
 237                         } else {
 238                                 dw_readl(dev, DW_IC_CLR_RD_REQ);
 239                                 dw_readl(dev, DW_IC_CLR_RX_UNDER);
 240                                 stat = i2c_dw_read_clear_intrbits_slave(dev);
 241                         }
 242                         if (!i2c_slave_event(dev->slave,
 243                                              I2C_SLAVE_READ_REQUESTED,
 244                                              &val))
 245                                 dw_writel(dev, val, DW_IC_DATA_CMD);
 246                 }
 247         }
 248
 249         if (stat & DW_IC_INTR_RX_DONE) {
 250                 if (!i2c_slave_event(dev->slave, I2C_SLAVE_READ_PROCESSED,
 251                                      &val))
 252                         dw_readl(dev, DW_IC_CLR_RX_DONE);
 253
 254                 i2c_slave_event(dev->slave, I2C_SLAVE_STOP, &val);
 255                 stat = i2c_dw_read_clear_intrbits_slave(dev);
 256                 return 1;
 257         }
 258
 259         if (stat & DW_IC_INTR_RX_FULL) {
 260                 val = dw_readl(dev, DW_IC_DATA_CMD);
 261                 if (!i2c_slave_event(dev->slave, I2C_SLAVE_WRITE_RECEIVED,
 262                                      &val))
 263                         dev_vdbg(dev->dev, "Byte %X acked!", val);
 264         } else {
 265                 i2c_slave_event(dev->slave, I2C_SLAVE_STOP, &val);
 266                 stat = i2c_dw_read_clear_intrbits_slave(dev);
 267         }
 268
 269         return 1;
 270 }
 271
 272 static irqreturn_t i2c_dw_isr_slave(int this_irq, void *dev_id)
 273 {
 274         struct dw_i2c_dev *dev = dev_id;
 275         int ret;
 276
 277         i2c_dw_read_clear_intrbits_slave(dev);
 278         ret = i2c_dw_irq_handler_slave(dev);
 279         if (ret > 0)
 280                 complete(&dev->cmd_complete);
 281
 282         return IRQ_RETVAL(ret);
 283 }
 284
 285 static const struct i2c_algorithm i2c_dw_algo = {
 286         .functionality = i2c_dw_func,
 287         .reg_slave = i2c_dw_reg_slave,
 288         .unreg_slave = i2c_dw_unreg_slave,
 289 };
 290
 291 int i2c_dw_probe_slave(struct dw_i2c_dev *dev)
 292 {
 293         struct i2c_adapter *adap = &dev->adapter;
 294         int ret;
 295
 296         init_completion(&dev->cmd_complete);
 297
 298         dev->init = i2c_dw_init_slave;
 299         dev->disable = i2c_dw_disable;
 300         dev->disable_int = i2c_dw_disable_int;
 301
 302         ret = dev->init(dev);
 303         if (ret)
 304                 return ret;
 305
 306         snprintf(adap->name, sizeof(adap->name),
 307                  "Synopsys DesignWare I2C Slave adapter");
 308         adap->retries = 3;
 309         adap->algo = &i2c_dw_algo;
 310         adap->dev.parent = dev->dev;
 311         i2c_set_adapdata(adap, dev);
 312
 313         ret = devm_request_irq(dev->dev, dev->irq, i2c_dw_isr_slave,
 314                                IRQF_SHARED, dev_name(dev->dev), dev);
 315         if (ret) {
 316                 dev_err(dev->dev, "failure requesting irq %i: %d\n",
 317                         dev->irq, ret);
 318                 return ret;
 319         }
 320
 321         ret = i2c_add_numbered_adapter(adap);
 322         if (ret)
 323                 dev_err(dev->dev, "failure adding adapter: %d\n", ret);
 324
 325         return ret;
 326 }
 327 EXPORT_SYMBOL_GPL(i2c_dw_probe_slave);
 328
 329 MODULE_AUTHOR("Luis Oliveira <lolivei@synopsys.com>");
 330 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus slave adapter");
 331 MODULE_LICENSE("GPL v2");