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x86/topology: Fix function name in documentation
[cris-mirror.git] / drivers / i2c / busses / i2c-imx-lpi2c.c
blobe6da2c7a9a3e60841e7405738f6ea091cc0eea0f
1 /*
2 * This is i.MX low power i2c controller driver.
3 *
4 * Copyright 2016 Freescale Semiconductor, Inc.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18 #include <linux/clk.h>
19 #include <linux/completion.h>
20 #include <linux/delay.h>
21 #include <linux/err.h>
22 #include <linux/errno.h>
23 #include <linux/i2c.h>
24 #include <linux/init.h>
25 #include <linux/interrupt.h>
26 #include <linux/io.h>
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/of.h>
30 #include <linux/of_device.h>
31 #include <linux/pinctrl/consumer.h>
32 #include <linux/platform_device.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/sched.h>
35 #include <linux/slab.h>
36
37 #define DRIVER_NAME "imx-lpi2c"
38
39 #define LPI2C_PARAM 0x04 /* i2c RX/TX FIFO size */
40 #define LPI2C_MCR 0x10 /* i2c contrl register */
41 #define LPI2C_MSR 0x14 /* i2c status register */
42 #define LPI2C_MIER 0x18 /* i2c interrupt enable */
43 #define LPI2C_MCFGR0 0x20 /* i2c master configuration */
44 #define LPI2C_MCFGR1 0x24 /* i2c master configuration */
45 #define LPI2C_MCFGR2 0x28 /* i2c master configuration */
46 #define LPI2C_MCFGR3 0x2C /* i2c master configuration */
47 #define LPI2C_MCCR0 0x48 /* i2c master clk configuration */
48 #define LPI2C_MCCR1 0x50 /* i2c master clk configuration */
49 #define LPI2C_MFCR 0x58 /* i2c master FIFO control */
50 #define LPI2C_MFSR 0x5C /* i2c master FIFO status */
51 #define LPI2C_MTDR 0x60 /* i2c master TX data register */
52 #define LPI2C_MRDR 0x70 /* i2c master RX data register */
53
54 /* i2c command */
55 #define TRAN_DATA 0X00
56 #define RECV_DATA 0X01
57 #define GEN_STOP 0X02
58 #define RECV_DISCARD 0X03
59 #define GEN_START 0X04
60 #define START_NACK 0X05
61 #define START_HIGH 0X06
62 #define START_HIGH_NACK 0X07
63
64 #define MCR_MEN BIT(0)
65 #define MCR_RST BIT(1)
66 #define MCR_DOZEN BIT(2)
67 #define MCR_DBGEN BIT(3)
68 #define MCR_RTF BIT(8)
69 #define MCR_RRF BIT(9)
70 #define MSR_TDF BIT(0)
71 #define MSR_RDF BIT(1)
72 #define MSR_SDF BIT(9)
73 #define MSR_NDF BIT(10)
74 #define MSR_ALF BIT(11)
75 #define MSR_MBF BIT(24)
76 #define MSR_BBF BIT(25)
77 #define MIER_TDIE BIT(0)
78 #define MIER_RDIE BIT(1)
79 #define MIER_SDIE BIT(9)
80 #define MIER_NDIE BIT(10)
81 #define MCFGR1_AUTOSTOP BIT(8)
82 #define MCFGR1_IGNACK BIT(9)
83 #define MRDR_RXEMPTY BIT(14)
84
85 #define I2C_CLK_RATIO 2
86 #define CHUNK_DATA 256
87
88 #define LPI2C_DEFAULT_RATE 100000
89 #define STARDARD_MAX_BITRATE 400000
90 #define FAST_MAX_BITRATE 1000000
91 #define FAST_PLUS_MAX_BITRATE 3400000
92 #define HIGHSPEED_MAX_BITRATE 5000000
93
94 #define I2C_PM_TIMEOUT 10 /* ms */
95
96 enum lpi2c_imx_mode {
97 STANDARD, /* 100+Kbps */
98 FAST, /* 400+Kbps */
99 FAST_PLUS, /* 1.0+Mbps */
100 HS, /* 3.4+Mbps */
101 ULTRA_FAST, /* 5.0+Mbps */
102 };
103
104 enum lpi2c_imx_pincfg {
105 TWO_PIN_OD,
106 TWO_PIN_OO,
107 TWO_PIN_PP,
108 FOUR_PIN_PP,
109 };
110
111 struct lpi2c_imx_struct {
112 struct i2c_adapter adapter;
113 struct clk *clk;
114 void __iomem *base;
115 __u8 *rx_buf;
116 __u8 *tx_buf;
117 struct completion complete;
118 unsigned int msglen;
119 unsigned int delivered;
120 unsigned int block_data;
121 unsigned int bitrate;
122 unsigned int txfifosize;
123 unsigned int rxfifosize;
124 enum lpi2c_imx_mode mode;
125 };
126
127 static void lpi2c_imx_intctrl(struct lpi2c_imx_struct *lpi2c_imx,
128 unsigned int enable)
129 {
130 writel(enable, lpi2c_imx->base + LPI2C_MIER);
131 }
132
133 static int lpi2c_imx_bus_busy(struct lpi2c_imx_struct *lpi2c_imx)
134 {
135 unsigned long orig_jiffies = jiffies;
136 unsigned int temp;
137
138 while (1) {
139 temp = readl(lpi2c_imx->base + LPI2C_MSR);
140
141 /* check for arbitration lost, clear if set */
142 if (temp & MSR_ALF) {
143 writel(temp, lpi2c_imx->base + LPI2C_MSR);
144 return -EAGAIN;
145 }
146
147 if (temp & (MSR_BBF | MSR_MBF))
148 break;
149
150 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
151 dev_dbg(&lpi2c_imx->adapter.dev, "bus not work\n");
152 return -ETIMEDOUT;
153 }
154 schedule();
155 }
156
157 return 0;
158 }
159
160 static void lpi2c_imx_set_mode(struct lpi2c_imx_struct *lpi2c_imx)
161 {
162 unsigned int bitrate = lpi2c_imx->bitrate;
163 enum lpi2c_imx_mode mode;
164
165 if (bitrate < STARDARD_MAX_BITRATE)
166 mode = STANDARD;
167 else if (bitrate < FAST_MAX_BITRATE)
168 mode = FAST;
169 else if (bitrate < FAST_PLUS_MAX_BITRATE)
170 mode = FAST_PLUS;
171 else if (bitrate < HIGHSPEED_MAX_BITRATE)
172 mode = HS;
173 else
174 mode = ULTRA_FAST;
175
176 lpi2c_imx->mode = mode;
177 }
178
179 static int lpi2c_imx_start(struct lpi2c_imx_struct *lpi2c_imx,
180 struct i2c_msg *msgs)
181 {
182 unsigned int temp;
183 u8 read;
184
185 temp = readl(lpi2c_imx->base + LPI2C_MCR);
186 temp |= MCR_RRF | MCR_RTF;
187 writel(temp, lpi2c_imx->base + LPI2C_MCR);
188 writel(0x7f00, lpi2c_imx->base + LPI2C_MSR);
189
190 read = msgs->flags & I2C_M_RD;
191 temp = (msgs->addr << 1 | read) | (GEN_START << 8);
192 writel(temp, lpi2c_imx->base + LPI2C_MTDR);
193
194 return lpi2c_imx_bus_busy(lpi2c_imx);
195 }
196
197 static void lpi2c_imx_stop(struct lpi2c_imx_struct *lpi2c_imx)
198 {
199 unsigned long orig_jiffies = jiffies;
200 unsigned int temp;
201
202 writel(GEN_STOP << 8, lpi2c_imx->base + LPI2C_MTDR);
203
204 do {
205 temp = readl(lpi2c_imx->base + LPI2C_MSR);
206 if (temp & MSR_SDF)
207 break;
208
209 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
210 dev_dbg(&lpi2c_imx->adapter.dev, "stop timeout\n");
211 break;
212 }
213 schedule();
214
215 } while (1);
216 }
217
218 /* CLKLO = I2C_CLK_RATIO * CLKHI, SETHOLD = CLKHI, DATAVD = CLKHI/2 */
219 static int lpi2c_imx_config(struct lpi2c_imx_struct *lpi2c_imx)
220 {
221 u8 prescale, filt, sethold, clkhi, clklo, datavd;
222 unsigned int clk_rate, clk_cycle;
223 enum lpi2c_imx_pincfg pincfg;
224 unsigned int temp;
225
226 lpi2c_imx_set_mode(lpi2c_imx);
227
228 clk_rate = clk_get_rate(lpi2c_imx->clk);
229 if (lpi2c_imx->mode == HS || lpi2c_imx->mode == ULTRA_FAST)
230 filt = 0;
231 else
232 filt = 2;
233
234 for (prescale = 0; prescale <= 7; prescale++) {
235 clk_cycle = clk_rate / ((1 << prescale) * lpi2c_imx->bitrate)
236 - 3 - (filt >> 1);
237 clkhi = (clk_cycle + I2C_CLK_RATIO) / (I2C_CLK_RATIO + 1);
238 clklo = clk_cycle - clkhi;
239 if (clklo < 64)
240 break;
241 }
242
243 if (prescale > 7)
244 return -EINVAL;
245
246 /* set MCFGR1: PINCFG, PRESCALE, IGNACK */
247 if (lpi2c_imx->mode == ULTRA_FAST)
248 pincfg = TWO_PIN_OO;
249 else
250 pincfg = TWO_PIN_OD;
251 temp = prescale | pincfg << 24;
252
253 if (lpi2c_imx->mode == ULTRA_FAST)
254 temp |= MCFGR1_IGNACK;
255
256 writel(temp, lpi2c_imx->base + LPI2C_MCFGR1);
257
258 /* set MCFGR2: FILTSDA, FILTSCL */
259 temp = (filt << 16) | (filt << 24);
260 writel(temp, lpi2c_imx->base + LPI2C_MCFGR2);
261
262 /* set MCCR: DATAVD, SETHOLD, CLKHI, CLKLO */
263 sethold = clkhi;
264 datavd = clkhi >> 1;
265 temp = datavd << 24 | sethold << 16 | clkhi << 8 | clklo;
266
267 if (lpi2c_imx->mode == HS)
268 writel(temp, lpi2c_imx->base + LPI2C_MCCR1);
269 else
270 writel(temp, lpi2c_imx->base + LPI2C_MCCR0);
271
272 return 0;
273 }
274
275 static int lpi2c_imx_master_enable(struct lpi2c_imx_struct *lpi2c_imx)
276 {
277 unsigned int temp;
278 int ret;
279
280 ret = pm_runtime_get_sync(lpi2c_imx->adapter.dev.parent);
281 if (ret < 0)
282 return ret;
283
284 temp = MCR_RST;
285 writel(temp, lpi2c_imx->base + LPI2C_MCR);
286 writel(0, lpi2c_imx->base + LPI2C_MCR);
287
288 ret = lpi2c_imx_config(lpi2c_imx);
289 if (ret)
290 goto rpm_put;
291
292 temp = readl(lpi2c_imx->base + LPI2C_MCR);
293 temp |= MCR_MEN;
294 writel(temp, lpi2c_imx->base + LPI2C_MCR);
295
296 return 0;
297
298 rpm_put:
299 pm_runtime_mark_last_busy(lpi2c_imx->adapter.dev.parent);
300 pm_runtime_put_autosuspend(lpi2c_imx->adapter.dev.parent);
301
302 return ret;
303 }
304
305 static int lpi2c_imx_master_disable(struct lpi2c_imx_struct *lpi2c_imx)
306 {
307 u32 temp;
308
309 temp = readl(lpi2c_imx->base + LPI2C_MCR);
310 temp &= ~MCR_MEN;
311 writel(temp, lpi2c_imx->base + LPI2C_MCR);
312
313 pm_runtime_mark_last_busy(lpi2c_imx->adapter.dev.parent);
314 pm_runtime_put_autosuspend(lpi2c_imx->adapter.dev.parent);
315
316 return 0;
317 }
318
319 static int lpi2c_imx_msg_complete(struct lpi2c_imx_struct *lpi2c_imx)
320 {
321 unsigned long timeout;
322
323 timeout = wait_for_completion_timeout(&lpi2c_imx->complete, HZ);
324
325 return timeout ? 0 : -ETIMEDOUT;
326 }
327
328 static int lpi2c_imx_txfifo_empty(struct lpi2c_imx_struct *lpi2c_imx)
329 {
330 unsigned long orig_jiffies = jiffies;
331 u32 txcnt;
332
333 do {
334 txcnt = readl(lpi2c_imx->base + LPI2C_MFSR) & 0xff;
335
336 if (readl(lpi2c_imx->base + LPI2C_MSR) & MSR_NDF) {
337 dev_dbg(&lpi2c_imx->adapter.dev, "NDF detected\n");
338 return -EIO;
339 }
340
341 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
342 dev_dbg(&lpi2c_imx->adapter.dev, "txfifo empty timeout\n");
343 return -ETIMEDOUT;
344 }
345 schedule();
346
347 } while (txcnt);
348
349 return 0;
350 }
351
352 static void lpi2c_imx_set_tx_watermark(struct lpi2c_imx_struct *lpi2c_imx)
353 {
354 writel(lpi2c_imx->txfifosize >> 1, lpi2c_imx->base + LPI2C_MFCR);
355 }
356
357 static void lpi2c_imx_set_rx_watermark(struct lpi2c_imx_struct *lpi2c_imx)
358 {
359 unsigned int temp, remaining;
360
361 remaining = lpi2c_imx->msglen - lpi2c_imx->delivered;
362
363 if (remaining > (lpi2c_imx->rxfifosize >> 1))
364 temp = lpi2c_imx->rxfifosize >> 1;
365 else
366 temp = 0;
367
368 writel(temp << 16, lpi2c_imx->base + LPI2C_MFCR);
369 }
370
371 static void lpi2c_imx_write_txfifo(struct lpi2c_imx_struct *lpi2c_imx)
372 {
373 unsigned int data, txcnt;
374
375 txcnt = readl(lpi2c_imx->base + LPI2C_MFSR) & 0xff;
376
377 while (txcnt < lpi2c_imx->txfifosize) {
378 if (lpi2c_imx->delivered == lpi2c_imx->msglen)
379 break;
380
381 data = lpi2c_imx->tx_buf[lpi2c_imx->delivered++];
382 writel(data, lpi2c_imx->base + LPI2C_MTDR);
383 txcnt++;
384 }
385
386 if (lpi2c_imx->delivered < lpi2c_imx->msglen)
387 lpi2c_imx_intctrl(lpi2c_imx, MIER_TDIE | MIER_NDIE);
388 else
389 complete(&lpi2c_imx->complete);
390 }
391
392 static void lpi2c_imx_read_rxfifo(struct lpi2c_imx_struct *lpi2c_imx)
393 {
394 unsigned int blocklen, remaining;
395 unsigned int temp, data;
396
397 do {
398 data = readl(lpi2c_imx->base + LPI2C_MRDR);
399 if (data & MRDR_RXEMPTY)
400 break;
401
402 lpi2c_imx->rx_buf[lpi2c_imx->delivered++] = data & 0xff;
403 } while (1);
404
405 /*
406 * First byte is the length of remaining packet in the SMBus block
407 * data read. Add it to msgs->len.
408 */
409 if (lpi2c_imx->block_data) {
410 blocklen = lpi2c_imx->rx_buf[0];
411 lpi2c_imx->msglen += blocklen;
412 }
413
414 remaining = lpi2c_imx->msglen - lpi2c_imx->delivered;
415
416 if (!remaining) {
417 complete(&lpi2c_imx->complete);
418 return;
419 }
420
421 /* not finished, still waiting for rx data */
422 lpi2c_imx_set_rx_watermark(lpi2c_imx);
423
424 /* multiple receive commands */
425 if (lpi2c_imx->block_data) {
426 lpi2c_imx->block_data = 0;
427 temp = remaining;
428 temp |= (RECV_DATA << 8);
429 writel(temp, lpi2c_imx->base + LPI2C_MTDR);
430 } else if (!(lpi2c_imx->delivered & 0xff)) {
431 temp = (remaining > CHUNK_DATA ? CHUNK_DATA : remaining) - 1;
432 temp |= (RECV_DATA << 8);
433 writel(temp, lpi2c_imx->base + LPI2C_MTDR);
434 }
435
436 lpi2c_imx_intctrl(lpi2c_imx, MIER_RDIE);
437 }
438
439 static void lpi2c_imx_write(struct lpi2c_imx_struct *lpi2c_imx,
440 struct i2c_msg *msgs)
441 {
442 lpi2c_imx->tx_buf = msgs->buf;
443 lpi2c_imx_set_tx_watermark(lpi2c_imx);
444 lpi2c_imx_write_txfifo(lpi2c_imx);
445 }
446
447 static void lpi2c_imx_read(struct lpi2c_imx_struct *lpi2c_imx,
448 struct i2c_msg *msgs)
449 {
450 unsigned int temp;
451
452 lpi2c_imx->rx_buf = msgs->buf;
453 lpi2c_imx->block_data = msgs->flags & I2C_M_RECV_LEN;
454
455 lpi2c_imx_set_rx_watermark(lpi2c_imx);
456 temp = msgs->len > CHUNK_DATA ? CHUNK_DATA - 1 : msgs->len - 1;
457 temp |= (RECV_DATA << 8);
458 writel(temp, lpi2c_imx->base + LPI2C_MTDR);
459
460 lpi2c_imx_intctrl(lpi2c_imx, MIER_RDIE | MIER_NDIE);
461 }
462
463 static int lpi2c_imx_xfer(struct i2c_adapter *adapter,
464 struct i2c_msg *msgs, int num)
465 {
466 struct lpi2c_imx_struct *lpi2c_imx = i2c_get_adapdata(adapter);
467 unsigned int temp;
468 int i, result;
469
470 result = lpi2c_imx_master_enable(lpi2c_imx);
471 if (result)
472 return result;
473
474 for (i = 0; i < num; i++) {
475 result = lpi2c_imx_start(lpi2c_imx, &msgs[i]);
476 if (result)
477 goto disable;
478
479 /* quick smbus */
480 if (num == 1 && msgs[0].len == 0)
481 goto stop;
482
483 lpi2c_imx->delivered = 0;
484 lpi2c_imx->msglen = msgs[i].len;
485 init_completion(&lpi2c_imx->complete);
486
487 if (msgs[i].flags & I2C_M_RD)
488 lpi2c_imx_read(lpi2c_imx, &msgs[i]);
489 else
490 lpi2c_imx_write(lpi2c_imx, &msgs[i]);
491
492 result = lpi2c_imx_msg_complete(lpi2c_imx);
493 if (result)
494 goto stop;
495
496 if (!(msgs[i].flags & I2C_M_RD)) {
497 result = lpi2c_imx_txfifo_empty(lpi2c_imx);
498 if (result)
499 goto stop;
500 }
501 }
502
503 stop:
504 lpi2c_imx_stop(lpi2c_imx);
505
506 temp = readl(lpi2c_imx->base + LPI2C_MSR);
507 if ((temp & MSR_NDF) && !result)
508 result = -EIO;
509
510 disable:
511 lpi2c_imx_master_disable(lpi2c_imx);
512
513 dev_dbg(&lpi2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__,
514 (result < 0) ? "error" : "success msg",
515 (result < 0) ? result : num);
516
517 return (result < 0) ? result : num;
518 }
519
520 static irqreturn_t lpi2c_imx_isr(int irq, void *dev_id)
521 {
522 struct lpi2c_imx_struct *lpi2c_imx = dev_id;
523 unsigned int temp;
524
525 lpi2c_imx_intctrl(lpi2c_imx, 0);
526 temp = readl(lpi2c_imx->base + LPI2C_MSR);
527
528 if (temp & MSR_RDF)
529 lpi2c_imx_read_rxfifo(lpi2c_imx);
530
531 if (temp & MSR_TDF)
532 lpi2c_imx_write_txfifo(lpi2c_imx);
533
534 if (temp & MSR_NDF)
535 complete(&lpi2c_imx->complete);
536
537 return IRQ_HANDLED;
538 }
539
540 static u32 lpi2c_imx_func(struct i2c_adapter *adapter)
541 {
542 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
543 I2C_FUNC_SMBUS_READ_BLOCK_DATA;
544 }
545
546 static const struct i2c_algorithm lpi2c_imx_algo = {
547 .master_xfer = lpi2c_imx_xfer,
548 .functionality = lpi2c_imx_func,
549 };
550
551 static const struct of_device_id lpi2c_imx_of_match[] = {
552 { .compatible = "fsl,imx7ulp-lpi2c" },
553 { .compatible = "fsl,imx8dv-lpi2c" },
554 { },
555 };
556 MODULE_DEVICE_TABLE(of, lpi2c_imx_of_match);
557
558 static int lpi2c_imx_probe(struct platform_device *pdev)
559 {
560 struct lpi2c_imx_struct *lpi2c_imx;
561 struct resource *res;
562 unsigned int temp;
563 int irq, ret;
564
565 lpi2c_imx = devm_kzalloc(&pdev->dev, sizeof(*lpi2c_imx), GFP_KERNEL);
566 if (!lpi2c_imx)
567 return -ENOMEM;
568
569 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
570 lpi2c_imx->base = devm_ioremap_resource(&pdev->dev, res);
571 if (IS_ERR(lpi2c_imx->base))
572 return PTR_ERR(lpi2c_imx->base);
573
574 irq = platform_get_irq(pdev, 0);
575 if (irq < 0) {
576 dev_err(&pdev->dev, "can't get irq number\n");
577 return irq;
578 }
579
580 lpi2c_imx->adapter.owner = THIS_MODULE;
581 lpi2c_imx->adapter.algo = &lpi2c_imx_algo;
582 lpi2c_imx->adapter.dev.parent = &pdev->dev;
583 lpi2c_imx->adapter.dev.of_node = pdev->dev.of_node;
584 strlcpy(lpi2c_imx->adapter.name, pdev->name,
585 sizeof(lpi2c_imx->adapter.name));
586
587 lpi2c_imx->clk = devm_clk_get(&pdev->dev, NULL);
588 if (IS_ERR(lpi2c_imx->clk)) {
589 dev_err(&pdev->dev, "can't get I2C peripheral clock\n");
590 return PTR_ERR(lpi2c_imx->clk);
591 }
592
593 ret = of_property_read_u32(pdev->dev.of_node,
594 "clock-frequency", &lpi2c_imx->bitrate);
595 if (ret)
596 lpi2c_imx->bitrate = LPI2C_DEFAULT_RATE;
597
598 ret = devm_request_irq(&pdev->dev, irq, lpi2c_imx_isr, 0,
599 pdev->name, lpi2c_imx);
600 if (ret) {
601 dev_err(&pdev->dev, "can't claim irq %d\n", irq);
602 return ret;
603 }
604
605 i2c_set_adapdata(&lpi2c_imx->adapter, lpi2c_imx);
606 platform_set_drvdata(pdev, lpi2c_imx);
607
608 ret = clk_prepare_enable(lpi2c_imx->clk);
609 if (ret) {
610 dev_err(&pdev->dev, "clk enable failed %d\n", ret);
611 return ret;
612 }
613
614 pm_runtime_set_autosuspend_delay(&pdev->dev, I2C_PM_TIMEOUT);
615 pm_runtime_use_autosuspend(&pdev->dev);
616 pm_runtime_get_noresume(&pdev->dev);
617 pm_runtime_set_active(&pdev->dev);
618 pm_runtime_enable(&pdev->dev);
619
620 temp = readl(lpi2c_imx->base + LPI2C_PARAM);
621 lpi2c_imx->txfifosize = 1 << (temp & 0x0f);
622 lpi2c_imx->rxfifosize = 1 << ((temp >> 8) & 0x0f);
623
624 ret = i2c_add_adapter(&lpi2c_imx->adapter);
625 if (ret)
626 goto rpm_disable;
627
628 pm_runtime_mark_last_busy(&pdev->dev);
629 pm_runtime_put_autosuspend(&pdev->dev);
630
631 dev_info(&lpi2c_imx->adapter.dev, "LPI2C adapter registered\n");
632
633 return 0;
634
635 rpm_disable:
636 pm_runtime_put(&pdev->dev);
637 pm_runtime_disable(&pdev->dev);
638 pm_runtime_dont_use_autosuspend(&pdev->dev);
639
640 return ret;
641 }
642
643 static int lpi2c_imx_remove(struct platform_device *pdev)
644 {
645 struct lpi2c_imx_struct *lpi2c_imx = platform_get_drvdata(pdev);
646
647 i2c_del_adapter(&lpi2c_imx->adapter);
648
649 pm_runtime_disable(&pdev->dev);
650 pm_runtime_dont_use_autosuspend(&pdev->dev);
651
652 return 0;
653 }
654
655 #ifdef CONFIG_PM_SLEEP
656 static int lpi2c_runtime_suspend(struct device *dev)
657 {
658 struct lpi2c_imx_struct *lpi2c_imx = dev_get_drvdata(dev);
659
660 clk_disable_unprepare(lpi2c_imx->clk);
661 pinctrl_pm_select_sleep_state(dev);
662
663 return 0;
664 }
665
666 static int lpi2c_runtime_resume(struct device *dev)
667 {
668 struct lpi2c_imx_struct *lpi2c_imx = dev_get_drvdata(dev);
669 int ret;
670
671 pinctrl_pm_select_default_state(dev);
672 ret = clk_prepare_enable(lpi2c_imx->clk);
673 if (ret) {
674 dev_err(dev, "failed to enable I2C clock, ret=%d\n", ret);
675 return ret;
676 }
677
678 return 0;
679 }
680
681 static const struct dev_pm_ops lpi2c_pm_ops = {
682 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
683 pm_runtime_force_resume)
684 SET_RUNTIME_PM_OPS(lpi2c_runtime_suspend,
685 lpi2c_runtime_resume, NULL)
686 };
687 #define IMX_LPI2C_PM (&lpi2c_pm_ops)
688 #else
689 #define IMX_LPI2C_PM NULL
690 #endif
691
692 static struct platform_driver lpi2c_imx_driver = {
693 .probe = lpi2c_imx_probe,
694 .remove = lpi2c_imx_remove,
695 .driver = {
696 .name = DRIVER_NAME,
697 .of_match_table = lpi2c_imx_of_match,
698 .pm = IMX_LPI2C_PM,
699 },
700 };
701
702 module_platform_driver(lpi2c_imx_driver);
703
704 MODULE_AUTHOR("Gao Pan <pandy.gao@nxp.com>");
705 MODULE_DESCRIPTION("I2C adapter driver for LPI2C bus");
706 MODULE_LICENSE("GPL");
CRIS linux kernel tree