drivers/infiniband/hw/hfi1/pio.h

   1 #ifndef _PIO_H
   2 #define _PIO_H
   3 /*
   4  * Copyright(c) 2015-2017 Intel Corporation.
   5  *
   6  * This file is provided under a dual BSD/GPLv2 license.  When using or
   7  * redistributing this file, you may do so under either license.
   8  *
   9  * GPL LICENSE SUMMARY
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of version 2 of the GNU General Public License as
  13  * published by the Free Software Foundation.
  14  *
  15  * This program is distributed in the hope that it will be useful, but
  16  * WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  18  * General Public License for more details.
  19  *
  20  * BSD LICENSE
  21  *
  22  * Redistribution and use in source and binary forms, with or without
  23  * modification, are permitted provided that the following conditions
  24  * are met:
  25  *
  26  *  - Redistributions of source code must retain the above copyright
  27  *    notice, this list of conditions and the following disclaimer.
  28  *  - Redistributions in binary form must reproduce the above copyright
  29  *    notice, this list of conditions and the following disclaimer in
  30  *    the documentation and/or other materials provided with the
  31  *    distribution.
  32  *  - Neither the name of Intel Corporation nor the names of its
  33  *    contributors may be used to endorse or promote products derived
  34  *    from this software without specific prior written permission.
  35  *
  36  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  37  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  38  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  39  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  40  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  41  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  42  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  43  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  44  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  45  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  46  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  47  *
  48  */
  49
  50 /* send context types */
  51 #define SC_KERNEL 0
  52 #define SC_VL15   1
  53 #define SC_ACK    2
  54 #define SC_USER   3     /* must be the last one: it may take all left */
  55 #define SC_MAX    4     /* count of send context types */
  56
  57 /* invalid send context index */
  58 #define INVALID_SCI 0xff
  59
  60 /* PIO buffer release callback function */
  61 typedef void (*pio_release_cb)(void *arg, int code);
  62
  63 /* PIO release codes - in bits, as there could more than one that apply */
  64 #define PRC_OK          0       /* no known error */
  65 #define PRC_STATUS_ERR  0x01    /* credit return due to status error */
  66 #define PRC_PBC         0x02    /* credit return due to PBC */
  67 #define PRC_THRESHOLD   0x04    /* credit return due to threshold */
  68 #define PRC_FILL_ERR    0x08    /* credit return due fill error */
  69 #define PRC_FORCE       0x10    /* credit return due credit force */
  70 #define PRC_SC_DISABLE  0x20    /* clean-up after a context disable */
  71
  72 /* byte helper */
  73 union mix {
  74         u64 val64;
  75         u32 val32[2];
  76         u8  val8[8];
  77 };
  78
  79 /* an allocated PIO buffer */
  80 struct pio_buf {
  81         struct send_context *sc;/* back pointer to owning send context */
  82         pio_release_cb cb;      /* called when the buffer is released */
  83         void *arg;              /* argument for cb */
  84         void __iomem *start;    /* buffer start address */
  85         void __iomem *end;      /* context end address */
  86         unsigned long sent_at;  /* buffer is sent when <= free */
  87         union mix carry;        /* pending unwritten bytes */
  88         u16 qw_written;         /* QW written so far */
  89         u8 carry_bytes; /* number of valid bytes in carry */
  90 };
  91
  92 /* cache line aligned pio buffer array */
  93 union pio_shadow_ring {
  94         struct pio_buf pbuf;
  95 } ____cacheline_aligned;
  96
  97 /* per-NUMA send context */
  98 struct send_context {
  99         /* read-only after init */
 100         struct hfi1_devdata *dd;                /* device */
 101         union pio_shadow_ring *sr;      /* shadow ring */
 102         void __iomem *base_addr;        /* start of PIO memory */
 103         u32 __percpu *buffers_allocated;/* count of buffers allocated */
 104         u32 size;                       /* context size, in bytes */
 105
 106         int node;                       /* context home node */
 107         u32 sr_size;                    /* size of the shadow ring */
 108         u16 flags;                      /* flags */
 109         u8  type;                       /* context type */
 110         u8  sw_index;                   /* software index number */
 111         u8  hw_context;                 /* hardware context number */
 112         u8  group;                      /* credit return group */
 113
 114         /* allocator fields */
 115         spinlock_t alloc_lock ____cacheline_aligned_in_smp;
 116         u32 sr_head;                    /* shadow ring head */
 117         unsigned long fill;             /* official alloc count */
 118         unsigned long alloc_free;       /* copy of free (less cache thrash) */
 119         u32 fill_wrap;                  /* tracks fill within ring */
 120         u32 credits;                    /* number of blocks in context */
 121         /* adding a new field here would make it part of this cacheline */
 122
 123         /* releaser fields */
 124         spinlock_t release_lock ____cacheline_aligned_in_smp;
 125         u32 sr_tail;                    /* shadow ring tail */
 126         unsigned long free;             /* official free count */
 127         volatile __le64 *hw_free;       /* HW free counter */
 128         /* list for PIO waiters */
 129         struct list_head piowait  ____cacheline_aligned_in_smp;
 130         spinlock_t credit_ctrl_lock ____cacheline_aligned_in_smp;
 131         u32 credit_intr_count;          /* count of credit intr users */
 132         u64 credit_ctrl;                /* cache for credit control */
 133         wait_queue_head_t halt_wait;    /* wait until kernel sees interrupt */
 134         struct work_struct halt_work;   /* halted context work queue entry */
 135 };
 136
 137 /* send context flags */
 138 #define SCF_ENABLED 0x01
 139 #define SCF_IN_FREE 0x02
 140 #define SCF_HALTED  0x04
 141 #define SCF_FROZEN  0x08
 142
 143 struct send_context_info {
 144         struct send_context *sc;        /* allocated working context */
 145         u16 allocated;                  /* has this been allocated? */
 146         u16 type;                       /* context type */
 147         u16 base;                       /* base in PIO array */
 148         u16 credits;                    /* size in PIO array */
 149 };
 150
 151 /* DMA credit return, index is always (context & 0x7) */
 152 struct credit_return {
 153         volatile __le64 cr[8];
 154 };
 155
 156 /* NUMA indexed credit return array */
 157 struct credit_return_base {
 158         struct credit_return *va;
 159         dma_addr_t dma;
 160 };
 161
 162 /* send context configuration sizes (one per type) */
 163 struct sc_config_sizes {
 164         short int size;
 165         short int count;
 166 };
 167
 168 /*
 169  * The diagram below details the relationship of the mapping structures
 170  *
 171  * Since the mapping now allows for non-uniform send contexts per vl, the
 172  * number of send contexts for a vl is either the vl_scontexts[vl] or
 173  * a computation based on num_kernel_send_contexts/num_vls:
 174  *
 175  * For example:
 176  * nactual = vl_scontexts ? vl_scontexts[vl] : num_kernel_send_contexts/num_vls
 177  *
 178  * n = roundup to next highest power of 2 using nactual
 179  *
 180  * In the case where there are num_kernel_send_contexts/num_vls doesn't divide
 181  * evenly, the extras are added from the last vl downward.
 182  *
 183  * For the case where n > nactual, the send contexts are assigned
 184  * in a round robin fashion wrapping back to the first send context
 185  * for a particular vl.
 186  *
 187  *               dd->pio_map
 188  *                    |                                   pio_map_elem[0]
 189  *                    |                                +--------------------+
 190  *                    v                                |       mask         |
 191  *               pio_vl_map                            |--------------------|
 192  *      +--------------------------+                   | ksc[0] -> sc 1     |
 193  *      |    list (RCU)            |                   |--------------------|
 194  *      |--------------------------|                 ->| ksc[1] -> sc 2     |
 195  *      |    mask                  |              --/  |--------------------|
 196  *      |--------------------------|            -/     |        *           |
 197  *      |    actual_vls (max 8)    |          -/       |--------------------|
 198  *      |--------------------------|       --/         | ksc[n-1] -> sc n   |
 199  *      |    vls (max 8)           |     -/            +--------------------+
 200  *      |--------------------------|  --/
 201  *      |    map[0]                |-/
 202  *      |--------------------------|                   +--------------------+
 203  *      |    map[1]                |---                |       mask         |
 204  *      |--------------------------|   \----           |--------------------|
 205  *      |           *              |        \--        | ksc[0] -> sc 1+n   |
 206  *      |           *              |           \----   |--------------------|
 207  *      |           *              |                \->| ksc[1] -> sc 2+n   |
 208  *      |--------------------------|                   |--------------------|
 209  *      |   map[vls - 1]           |-                  |         *          |
 210  *      +--------------------------+ \-                |--------------------|
 211  *                                     \-              | ksc[m-1] -> sc m+n |
 212  *                                       \             +--------------------+
 213  *                                        \-
 214  *                                          \
 215  *                                           \-        +----------------------+
 216  *                                             \-      |       mask           |
 217  *                                               \     |----------------------|
 218  *                                                \-   | ksc[0] -> sc 1+m+n   |
 219  *                                                  \- |----------------------|
 220  *                                                    >| ksc[1] -> sc 2+m+n   |
 221  *                                                     |----------------------|
 222  *                                                     |         *            |
 223  *                                                     |----------------------|
 224  *                                                     | ksc[o-1] -> sc o+m+n |
 225  *                                                     +----------------------+
 226  *
 227  */
 228
 229 /* Initial number of send contexts per VL */
 230 #define INIT_SC_PER_VL 2
 231
 232 /*
 233  * struct pio_map_elem - mapping for a vl
 234  * @mask - selector mask
 235  * @ksc - array of kernel send contexts for this vl
 236  *
 237  * The mask is used to "mod" the selector to
 238  * produce index into the trailing array of
 239  * kscs
 240  */
 241 struct pio_map_elem {
 242         u32 mask;
 243         struct send_context *ksc[0];
 244 };
 245
 246 /*
 247  * struct pio_vl_map - mapping for a vl
 248  * @list - rcu head for free callback
 249  * @mask - vl mask to "mod" the vl to produce an index to map array
 250  * @actual_vls - number of vls
 251  * @vls - numbers of vls rounded to next power of 2
 252  * @map - array of pio_map_elem entries
 253  *
 254  * This is the parent mapping structure. The trailing members of the
 255  * struct point to pio_map_elem entries, which in turn point to an
 256  * array of kscs for that vl.
 257  */
 258 struct pio_vl_map {
 259         struct rcu_head list;
 260         u32 mask;
 261         u8 actual_vls;
 262         u8 vls;
 263         struct pio_map_elem *map[0];
 264 };
 265
 266 int pio_map_init(struct hfi1_devdata *dd, u8 port, u8 num_vls,
 267                  u8 *vl_scontexts);
 268 void free_pio_map(struct hfi1_devdata *dd);
 269 struct send_context *pio_select_send_context_vl(struct hfi1_devdata *dd,
 270                                                 u32 selector, u8 vl);
 271 struct send_context *pio_select_send_context_sc(struct hfi1_devdata *dd,
 272                                                 u32 selector, u8 sc5);
 273
 274 /* send context functions */
 275 int init_credit_return(struct hfi1_devdata *dd);
 276 void free_credit_return(struct hfi1_devdata *dd);
 277 int init_sc_pools_and_sizes(struct hfi1_devdata *dd);
 278 int init_send_contexts(struct hfi1_devdata *dd);
 279 int init_credit_return(struct hfi1_devdata *dd);
 280 int init_pervl_scs(struct hfi1_devdata *dd);
 281 struct send_context *sc_alloc(struct hfi1_devdata *dd, int type,
 282                               uint hdrqentsize, int numa);
 283 void sc_free(struct send_context *sc);
 284 int sc_enable(struct send_context *sc);
 285 void sc_disable(struct send_context *sc);
 286 int sc_restart(struct send_context *sc);
 287 void sc_return_credits(struct send_context *sc);
 288 void sc_flush(struct send_context *sc);
 289 void sc_drop(struct send_context *sc);
 290 void sc_stop(struct send_context *sc, int bit);
 291 struct pio_buf *sc_buffer_alloc(struct send_context *sc, u32 dw_len,
 292                                 pio_release_cb cb, void *arg);
 293 void sc_release_update(struct send_context *sc);
 294 void sc_return_credits(struct send_context *sc);
 295 void sc_group_release_update(struct hfi1_devdata *dd, u32 hw_context);
 296 void sc_add_credit_return_intr(struct send_context *sc);
 297 void sc_del_credit_return_intr(struct send_context *sc);
 298 void sc_set_cr_threshold(struct send_context *sc, u32 new_threshold);
 299 u32 sc_percent_to_threshold(struct send_context *sc, u32 percent);
 300 u32 sc_mtu_to_threshold(struct send_context *sc, u32 mtu, u32 hdrqentsize);
 301 void hfi1_sc_wantpiobuf_intr(struct send_context *sc, u32 needint);
 302 void sc_wait(struct hfi1_devdata *dd);
 303 void set_pio_integrity(struct send_context *sc);
 304
 305 /* support functions */
 306 void pio_reset_all(struct hfi1_devdata *dd);
 307 void pio_freeze(struct hfi1_devdata *dd);
 308 void pio_kernel_unfreeze(struct hfi1_devdata *dd);
 309
 310 /* global PIO send control operations */
 311 #define PSC_GLOBAL_ENABLE 0
 312 #define PSC_GLOBAL_DISABLE 1
 313 #define PSC_GLOBAL_VLARB_ENABLE 2
 314 #define PSC_GLOBAL_VLARB_DISABLE 3
 315 #define PSC_CM_RESET 4
 316 #define PSC_DATA_VL_ENABLE 5
 317 #define PSC_DATA_VL_DISABLE 6
 318
 319 void __cm_reset(struct hfi1_devdata *dd, u64 sendctrl);
 320 void pio_send_control(struct hfi1_devdata *dd, int op);
 321
 322 /* PIO copy routines */
 323 void pio_copy(struct hfi1_devdata *dd, struct pio_buf *pbuf, u64 pbc,
 324               const void *from, size_t count);
 325 void seg_pio_copy_start(struct pio_buf *pbuf, u64 pbc,
 326                         const void *from, size_t nbytes);
 327 void seg_pio_copy_mid(struct pio_buf *pbuf, const void *from, size_t nbytes);
 328 void seg_pio_copy_end(struct pio_buf *pbuf);
 329
 330 #endif /* _PIO_H */