?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
x86/topology: Fix function name in documentation
[cris-mirror.git] / drivers / infiniband / hw / mlx4 / qp.c
blobf045491f2c1490260693a3577e5679196998b462
1 /*
2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
34 #include <linux/log2.h>
35 #include <linux/etherdevice.h>
36 #include <net/ip.h>
37 #include <linux/slab.h>
38 #include <linux/netdevice.h>
39
40 #include <rdma/ib_cache.h>
41 #include <rdma/ib_pack.h>
42 #include <rdma/ib_addr.h>
43 #include <rdma/ib_mad.h>
44
45 #include <linux/mlx4/driver.h>
46 #include <linux/mlx4/qp.h>
47
48 #include "mlx4_ib.h"
49 #include <rdma/mlx4-abi.h>
50
51 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq,
52 struct mlx4_ib_cq *recv_cq);
53 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq,
54 struct mlx4_ib_cq *recv_cq);
55 static int _mlx4_ib_modify_wq(struct ib_wq *ibwq, enum ib_wq_state new_state);
56
57 enum {
58 MLX4_IB_ACK_REQ_FREQ = 8,
59 };
60
61 enum {
62 MLX4_IB_DEFAULT_SCHED_QUEUE = 0x83,
63 MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
64 MLX4_IB_LINK_TYPE_IB = 0,
65 MLX4_IB_LINK_TYPE_ETH = 1
66 };
67
68 enum {
69 /*
70 * Largest possible UD header: send with GRH and immediate
71 * data plus 18 bytes for an Ethernet header with VLAN/802.1Q
72 * tag. (LRH would only use 8 bytes, so Ethernet is the
73 * biggest case)
74 */
75 MLX4_IB_UD_HEADER_SIZE = 82,
76 MLX4_IB_LSO_HEADER_SPARE = 128,
77 };
78
79 struct mlx4_ib_sqp {
80 struct mlx4_ib_qp qp;
81 int pkey_index;
82 u32 qkey;
83 u32 send_psn;
84 struct ib_ud_header ud_header;
85 u8 header_buf[MLX4_IB_UD_HEADER_SIZE];
86 struct ib_qp *roce_v2_gsi;
87 };
88
89 enum {
90 MLX4_IB_MIN_SQ_STRIDE = 6,
91 MLX4_IB_CACHE_LINE_SIZE = 64,
92 };
93
94 enum {
95 MLX4_RAW_QP_MTU = 7,
96 MLX4_RAW_QP_MSGMAX = 31,
97 };
98
99 #ifndef ETH_ALEN
100 #define ETH_ALEN 6
101 #endif
102
103 static const __be32 mlx4_ib_opcode[] = {
104 [IB_WR_SEND] = cpu_to_be32(MLX4_OPCODE_SEND),
105 [IB_WR_LSO] = cpu_to_be32(MLX4_OPCODE_LSO),
106 [IB_WR_SEND_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_SEND_IMM),
107 [IB_WR_RDMA_WRITE] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
108 [IB_WR_RDMA_WRITE_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
109 [IB_WR_RDMA_READ] = cpu_to_be32(MLX4_OPCODE_RDMA_READ),
110 [IB_WR_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
111 [IB_WR_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
112 [IB_WR_SEND_WITH_INV] = cpu_to_be32(MLX4_OPCODE_SEND_INVAL),
113 [IB_WR_LOCAL_INV] = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL),
114 [IB_WR_REG_MR] = cpu_to_be32(MLX4_OPCODE_FMR),
115 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS),
116 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA),
117 };
118
119 enum mlx4_ib_source_type {
120 MLX4_IB_QP_SRC = 0,
121 MLX4_IB_RWQ_SRC = 1,
122 };
123
124 static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
125 {
126 return container_of(mqp, struct mlx4_ib_sqp, qp);
127 }
128
129 static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
130 {
131 if (!mlx4_is_master(dev->dev))
132 return 0;
133
134 return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn &&
135 qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn +
136 8 * MLX4_MFUNC_MAX;
137 }
138
139 static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
140 {
141 int proxy_sqp = 0;
142 int real_sqp = 0;
143 int i;
144 /* PPF or Native -- real SQP */
145 real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
146 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
147 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3);
148 if (real_sqp)
149 return 1;
150 /* VF or PF -- proxy SQP */
151 if (mlx4_is_mfunc(dev->dev)) {
152 for (i = 0; i < dev->dev->caps.num_ports; i++) {
153 if (qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp0_proxy ||
154 qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp1_proxy) {
155 proxy_sqp = 1;
156 break;
157 }
158 }
159 }
160 if (proxy_sqp)
161 return 1;
162
163 return !!(qp->flags & MLX4_IB_ROCE_V2_GSI_QP);
164 }
165
166 /* used for INIT/CLOSE port logic */
167 static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
168 {
169 int proxy_qp0 = 0;
170 int real_qp0 = 0;
171 int i;
172 /* PPF or Native -- real QP0 */
173 real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
174 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
175 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1);
176 if (real_qp0)
177 return 1;
178 /* VF or PF -- proxy QP0 */
179 if (mlx4_is_mfunc(dev->dev)) {
180 for (i = 0; i < dev->dev->caps.num_ports; i++) {
181 if (qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp0_proxy) {
182 proxy_qp0 = 1;
183 break;
184 }
185 }
186 }
187 return proxy_qp0;
188 }
189
190 static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
191 {
192 return mlx4_buf_offset(&qp->buf, offset);
193 }
194
195 static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
196 {
197 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
198 }
199
200 static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
201 {
202 return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
203 }
204
205 /*
206 * Stamp a SQ WQE so that it is invalid if prefetched by marking the
207 * first four bytes of every 64 byte chunk with
208 * 0x7FFFFFF | (invalid_ownership_value << 31).
209 *
210 * When the max work request size is less than or equal to the WQE
211 * basic block size, as an optimization, we can stamp all WQEs with
212 * 0xffffffff, and skip the very first chunk of each WQE.
213 */
214 static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size)
215 {
216 __be32 *wqe;
217 int i;
218 int s;
219 int ind;
220 void *buf;
221 __be32 stamp;
222 struct mlx4_wqe_ctrl_seg *ctrl;
223
224 if (qp->sq_max_wqes_per_wr > 1) {
225 s = roundup(size, 1U << qp->sq.wqe_shift);
226 for (i = 0; i < s; i += 64) {
227 ind = (i >> qp->sq.wqe_shift) + n;
228 stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) :
229 cpu_to_be32(0xffffffff);
230 buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
231 wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1));
232 *wqe = stamp;
233 }
234 } else {
235 ctrl = buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
236 s = (ctrl->qpn_vlan.fence_size & 0x3f) << 4;
237 for (i = 64; i < s; i += 64) {
238 wqe = buf + i;
239 *wqe = cpu_to_be32(0xffffffff);
240 }
241 }
242 }
243
244 static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size)
245 {
246 struct mlx4_wqe_ctrl_seg *ctrl;
247 struct mlx4_wqe_inline_seg *inl;
248 void *wqe;
249 int s;
250
251 ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
252 s = sizeof(struct mlx4_wqe_ctrl_seg);
253
254 if (qp->ibqp.qp_type == IB_QPT_UD) {
255 struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl;
256 struct mlx4_av *av = (struct mlx4_av *)dgram->av;
257 memset(dgram, 0, sizeof *dgram);
258 av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn);
259 s += sizeof(struct mlx4_wqe_datagram_seg);
260 }
261
262 /* Pad the remainder of the WQE with an inline data segment. */
263 if (size > s) {
264 inl = wqe + s;
265 inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl));
266 }
267 ctrl->srcrb_flags = 0;
268 ctrl->qpn_vlan.fence_size = size / 16;
269 /*
270 * Make sure descriptor is fully written before setting ownership bit
271 * (because HW can start executing as soon as we do).
272 */
273 wmb();
274
275 ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) |
276 (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
277
278 stamp_send_wqe(qp, n + qp->sq_spare_wqes, size);
279 }
280
281 /* Post NOP WQE to prevent wrap-around in the middle of WR */
282 static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind)
283 {
284 unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1));
285 if (unlikely(s < qp->sq_max_wqes_per_wr)) {
286 post_nop_wqe(qp, ind, s << qp->sq.wqe_shift);
287 ind += s;
288 }
289 return ind;
290 }
291
292 static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
293 {
294 struct ib_event event;
295 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
296
297 if (type == MLX4_EVENT_TYPE_PATH_MIG)
298 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
299
300 if (ibqp->event_handler) {
301 event.device = ibqp->device;
302 event.element.qp = ibqp;
303 switch (type) {
304 case MLX4_EVENT_TYPE_PATH_MIG:
305 event.event = IB_EVENT_PATH_MIG;
306 break;
307 case MLX4_EVENT_TYPE_COMM_EST:
308 event.event = IB_EVENT_COMM_EST;
309 break;
310 case MLX4_EVENT_TYPE_SQ_DRAINED:
311 event.event = IB_EVENT_SQ_DRAINED;
312 break;
313 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
314 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
315 break;
316 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
317 event.event = IB_EVENT_QP_FATAL;
318 break;
319 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
320 event.event = IB_EVENT_PATH_MIG_ERR;
321 break;
322 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
323 event.event = IB_EVENT_QP_REQ_ERR;
324 break;
325 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
326 event.event = IB_EVENT_QP_ACCESS_ERR;
327 break;
328 default:
329 pr_warn("Unexpected event type %d "
330 "on QP %06x\n", type, qp->qpn);
331 return;
332 }
333
334 ibqp->event_handler(&event, ibqp->qp_context);
335 }
336 }
337
338 static void mlx4_ib_wq_event(struct mlx4_qp *qp, enum mlx4_event type)
339 {
340 pr_warn_ratelimited("Unexpected event type %d on WQ 0x%06x. Events are not supported for WQs\n",
341 type, qp->qpn);
342 }
343
344 static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags)
345 {
346 /*
347 * UD WQEs must have a datagram segment.
348 * RC and UC WQEs might have a remote address segment.
349 * MLX WQEs need two extra inline data segments (for the UD
350 * header and space for the ICRC).
351 */
352 switch (type) {
353 case MLX4_IB_QPT_UD:
354 return sizeof (struct mlx4_wqe_ctrl_seg) +
355 sizeof (struct mlx4_wqe_datagram_seg) +
356 ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0);
357 case MLX4_IB_QPT_PROXY_SMI_OWNER:
358 case MLX4_IB_QPT_PROXY_SMI:
359 case MLX4_IB_QPT_PROXY_GSI:
360 return sizeof (struct mlx4_wqe_ctrl_seg) +
361 sizeof (struct mlx4_wqe_datagram_seg) + 64;
362 case MLX4_IB_QPT_TUN_SMI_OWNER:
363 case MLX4_IB_QPT_TUN_GSI:
364 return sizeof (struct mlx4_wqe_ctrl_seg) +
365 sizeof (struct mlx4_wqe_datagram_seg);
366
367 case MLX4_IB_QPT_UC:
368 return sizeof (struct mlx4_wqe_ctrl_seg) +
369 sizeof (struct mlx4_wqe_raddr_seg);
370 case MLX4_IB_QPT_RC:
371 return sizeof (struct mlx4_wqe_ctrl_seg) +
372 sizeof (struct mlx4_wqe_masked_atomic_seg) +
373 sizeof (struct mlx4_wqe_raddr_seg);
374 case MLX4_IB_QPT_SMI:
375 case MLX4_IB_QPT_GSI:
376 return sizeof (struct mlx4_wqe_ctrl_seg) +
377 ALIGN(MLX4_IB_UD_HEADER_SIZE +
378 DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
379 MLX4_INLINE_ALIGN) *
380 sizeof (struct mlx4_wqe_inline_seg),
381 sizeof (struct mlx4_wqe_data_seg)) +
382 ALIGN(4 +
383 sizeof (struct mlx4_wqe_inline_seg),
384 sizeof (struct mlx4_wqe_data_seg));
385 default:
386 return sizeof (struct mlx4_wqe_ctrl_seg);
387 }
388 }
389
390 static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
391 int is_user, int has_rq, struct mlx4_ib_qp *qp,
392 u32 inl_recv_sz)
393 {
394 /* Sanity check RQ size before proceeding */
395 if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE ||
396 cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg))
397 return -EINVAL;
398
399 if (!has_rq) {
400 if (cap->max_recv_wr || inl_recv_sz)
401 return -EINVAL;
402
403 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
404 } else {
405 u32 max_inl_recv_sz = dev->dev->caps.max_rq_sg *
406 sizeof(struct mlx4_wqe_data_seg);
407 u32 wqe_size;
408
409 /* HW requires >= 1 RQ entry with >= 1 gather entry */
410 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge ||
411 inl_recv_sz > max_inl_recv_sz))
412 return -EINVAL;
413
414 qp->rq.wqe_cnt = roundup_pow_of_two(max(1U, cap->max_recv_wr));
415 qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge));
416 wqe_size = qp->rq.max_gs * sizeof(struct mlx4_wqe_data_seg);
417 qp->rq.wqe_shift = ilog2(max_t(u32, wqe_size, inl_recv_sz));
418 }
419
420 /* leave userspace return values as they were, so as not to break ABI */
421 if (is_user) {
422 cap->max_recv_wr = qp->rq.max_post = qp->rq.wqe_cnt;
423 cap->max_recv_sge = qp->rq.max_gs;
424 } else {
425 cap->max_recv_wr = qp->rq.max_post =
426 min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt);
427 cap->max_recv_sge = min(qp->rq.max_gs,
428 min(dev->dev->caps.max_sq_sg,
429 dev->dev->caps.max_rq_sg));
430 }
431
432 return 0;
433 }
434
435 static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
436 enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp,
437 bool shrink_wqe)
438 {
439 int s;
440
441 /* Sanity check SQ size before proceeding */
442 if (cap->max_send_wr > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) ||
443 cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) ||
444 cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
445 sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
446 return -EINVAL;
447
448 /*
449 * For MLX transport we need 2 extra S/G entries:
450 * one for the header and one for the checksum at the end
451 */
452 if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI ||
453 type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) &&
454 cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
455 return -EINVAL;
456
457 s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
458 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
459 send_wqe_overhead(type, qp->flags);
460
461 if (s > dev->dev->caps.max_sq_desc_sz)
462 return -EINVAL;
463
464 /*
465 * Hermon supports shrinking WQEs, such that a single work
466 * request can include multiple units of 1 << wqe_shift. This
467 * way, work requests can differ in size, and do not have to
468 * be a power of 2 in size, saving memory and speeding up send
469 * WR posting. Unfortunately, if we do this then the
470 * wqe_index field in CQEs can't be used to look up the WR ID
471 * anymore, so we do this only if selective signaling is off.
472 *
473 * Further, on 32-bit platforms, we can't use vmap() to make
474 * the QP buffer virtually contiguous. Thus we have to use
475 * constant-sized WRs to make sure a WR is always fully within
476 * a single page-sized chunk.
477 *
478 * Finally, we use NOP work requests to pad the end of the
479 * work queue, to avoid wrap-around in the middle of WR. We
480 * set NEC bit to avoid getting completions with error for
481 * these NOP WRs, but since NEC is only supported starting
482 * with firmware 2.2.232, we use constant-sized WRs for older
483 * firmware.
484 *
485 * And, since MLX QPs only support SEND, we use constant-sized
486 * WRs in this case.
487 *
488 * We look for the smallest value of wqe_shift such that the
489 * resulting number of wqes does not exceed device
490 * capabilities.
491 *
492 * We set WQE size to at least 64 bytes, this way stamping
493 * invalidates each WQE.
494 */
495 if (shrink_wqe && dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC &&
496 qp->sq_signal_bits && BITS_PER_LONG == 64 &&
497 type != MLX4_IB_QPT_SMI && type != MLX4_IB_QPT_GSI &&
498 !(type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_PROXY_SMI |
499 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER)))
500 qp->sq.wqe_shift = ilog2(64);
501 else
502 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
503
504 for (;;) {
505 qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift);
506
507 /*
508 * We need to leave 2 KB + 1 WR of headroom in the SQ to
509 * allow HW to prefetch.
510 */
511 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr;
512 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr *
513 qp->sq_max_wqes_per_wr +
514 qp->sq_spare_wqes);
515
516 if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes)
517 break;
518
519 if (qp->sq_max_wqes_per_wr <= 1)
520 return -EINVAL;
521
522 ++qp->sq.wqe_shift;
523 }
524
525 qp->sq.max_gs = (min(dev->dev->caps.max_sq_desc_sz,
526 (qp->sq_max_wqes_per_wr << qp->sq.wqe_shift)) -
527 send_wqe_overhead(type, qp->flags)) /
528 sizeof (struct mlx4_wqe_data_seg);
529
530 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
531 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
532 if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
533 qp->rq.offset = 0;
534 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
535 } else {
536 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
537 qp->sq.offset = 0;
538 }
539
540 cap->max_send_wr = qp->sq.max_post =
541 (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr;
542 cap->max_send_sge = min(qp->sq.max_gs,
543 min(dev->dev->caps.max_sq_sg,
544 dev->dev->caps.max_rq_sg));
545 /* We don't support inline sends for kernel QPs (yet) */
546 cap->max_inline_data = 0;
547
548 return 0;
549 }
550
551 static int set_user_sq_size(struct mlx4_ib_dev *dev,
552 struct mlx4_ib_qp *qp,
553 struct mlx4_ib_create_qp *ucmd)
554 {
555 /* Sanity check SQ size before proceeding */
556 if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes ||
557 ucmd->log_sq_stride >
558 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
559 ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
560 return -EINVAL;
561
562 qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count;
563 qp->sq.wqe_shift = ucmd->log_sq_stride;
564
565 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
566 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
567
568 return 0;
569 }
570
571 static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
572 {
573 int i;
574
575 qp->sqp_proxy_rcv =
576 kmalloc(sizeof (struct mlx4_ib_buf) * qp->rq.wqe_cnt,
577 GFP_KERNEL);
578 if (!qp->sqp_proxy_rcv)
579 return -ENOMEM;
580 for (i = 0; i < qp->rq.wqe_cnt; i++) {
581 qp->sqp_proxy_rcv[i].addr =
582 kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr),
583 GFP_KERNEL);
584 if (!qp->sqp_proxy_rcv[i].addr)
585 goto err;
586 qp->sqp_proxy_rcv[i].map =
587 ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr,
588 sizeof (struct mlx4_ib_proxy_sqp_hdr),
589 DMA_FROM_DEVICE);
590 if (ib_dma_mapping_error(dev, qp->sqp_proxy_rcv[i].map)) {
591 kfree(qp->sqp_proxy_rcv[i].addr);
592 goto err;
593 }
594 }
595 return 0;
596
597 err:
598 while (i > 0) {
599 --i;
600 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
601 sizeof (struct mlx4_ib_proxy_sqp_hdr),
602 DMA_FROM_DEVICE);
603 kfree(qp->sqp_proxy_rcv[i].addr);
604 }
605 kfree(qp->sqp_proxy_rcv);
606 qp->sqp_proxy_rcv = NULL;
607 return -ENOMEM;
608 }
609
610 static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
611 {
612 int i;
613
614 for (i = 0; i < qp->rq.wqe_cnt; i++) {
615 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
616 sizeof (struct mlx4_ib_proxy_sqp_hdr),
617 DMA_FROM_DEVICE);
618 kfree(qp->sqp_proxy_rcv[i].addr);
619 }
620 kfree(qp->sqp_proxy_rcv);
621 }
622
623 static int qp_has_rq(struct ib_qp_init_attr *attr)
624 {
625 if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT)
626 return 0;
627
628 return !attr->srq;
629 }
630
631 static int qp0_enabled_vf(struct mlx4_dev *dev, int qpn)
632 {
633 int i;
634 for (i = 0; i < dev->caps.num_ports; i++) {
635 if (qpn == dev->caps.spec_qps[i].qp0_proxy)
636 return !!dev->caps.spec_qps[i].qp0_qkey;
637 }
638 return 0;
639 }
640
641 static void mlx4_ib_free_qp_counter(struct mlx4_ib_dev *dev,
642 struct mlx4_ib_qp *qp)
643 {
644 mutex_lock(&dev->counters_table[qp->port - 1].mutex);
645 mlx4_counter_free(dev->dev, qp->counter_index->index);
646 list_del(&qp->counter_index->list);
647 mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
648
649 kfree(qp->counter_index);
650 qp->counter_index = NULL;
651 }
652
653 static int set_qp_rss(struct mlx4_ib_dev *dev, struct mlx4_ib_rss *rss_ctx,
654 struct ib_qp_init_attr *init_attr,
655 struct mlx4_ib_create_qp_rss *ucmd)
656 {
657 rss_ctx->base_qpn_tbl_sz = init_attr->rwq_ind_tbl->ind_tbl[0]->wq_num |
658 (init_attr->rwq_ind_tbl->log_ind_tbl_size << 24);
659
660 if ((ucmd->rx_hash_function == MLX4_IB_RX_HASH_FUNC_TOEPLITZ) &&
661 (dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_TOP)) {
662 memcpy(rss_ctx->rss_key, ucmd->rx_hash_key,
663 MLX4_EN_RSS_KEY_SIZE);
664 } else {
665 pr_debug("RX Hash function is not supported\n");
666 return (-EOPNOTSUPP);
667 }
668
669 if (ucmd->rx_hash_fields_mask & ~(MLX4_IB_RX_HASH_SRC_IPV4 |
670 MLX4_IB_RX_HASH_DST_IPV4 |
671 MLX4_IB_RX_HASH_SRC_IPV6 |
672 MLX4_IB_RX_HASH_DST_IPV6 |
673 MLX4_IB_RX_HASH_SRC_PORT_TCP |
674 MLX4_IB_RX_HASH_DST_PORT_TCP |
675 MLX4_IB_RX_HASH_SRC_PORT_UDP |
676 MLX4_IB_RX_HASH_DST_PORT_UDP)) {
677 pr_debug("RX Hash fields_mask has unsupported mask (0x%llx)\n",
678 ucmd->rx_hash_fields_mask);
679 return (-EOPNOTSUPP);
680 }
681
682 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV4) &&
683 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV4)) {
684 rss_ctx->flags = MLX4_RSS_IPV4;
685 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV4) ||
686 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV4)) {
687 pr_debug("RX Hash fields_mask is not supported - both IPv4 SRC and DST must be set\n");
688 return (-EOPNOTSUPP);
689 }
690
691 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV6) &&
692 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV6)) {
693 rss_ctx->flags |= MLX4_RSS_IPV6;
694 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV6) ||
695 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV6)) {
696 pr_debug("RX Hash fields_mask is not supported - both IPv6 SRC and DST must be set\n");
697 return (-EOPNOTSUPP);
698 }
699
700 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_UDP) &&
701 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_UDP)) {
702 if (!(dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UDP_RSS)) {
703 pr_debug("RX Hash fields_mask for UDP is not supported\n");
704 return (-EOPNOTSUPP);
705 }
706
707 if (rss_ctx->flags & MLX4_RSS_IPV4)
708 rss_ctx->flags |= MLX4_RSS_UDP_IPV4;
709 if (rss_ctx->flags & MLX4_RSS_IPV6)
710 rss_ctx->flags |= MLX4_RSS_UDP_IPV6;
711 if (!(rss_ctx->flags & (MLX4_RSS_IPV6 | MLX4_RSS_IPV4))) {
712 pr_debug("RX Hash fields_mask is not supported - UDP must be set with IPv4 or IPv6\n");
713 return (-EOPNOTSUPP);
714 }
715 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_UDP) ||
716 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_UDP)) {
717 pr_debug("RX Hash fields_mask is not supported - both UDP SRC and DST must be set\n");
718 return (-EOPNOTSUPP);
719 }
720
721 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_TCP) &&
722 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_TCP)) {
723 if (rss_ctx->flags & MLX4_RSS_IPV4)
724 rss_ctx->flags |= MLX4_RSS_TCP_IPV4;
725 if (rss_ctx->flags & MLX4_RSS_IPV6)
726 rss_ctx->flags |= MLX4_RSS_TCP_IPV6;
727 if (!(rss_ctx->flags & (MLX4_RSS_IPV6 | MLX4_RSS_IPV4))) {
728 pr_debug("RX Hash fields_mask is not supported - TCP must be set with IPv4 or IPv6\n");
729 return (-EOPNOTSUPP);
730 }
731 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_TCP) ||
732 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_TCP)) {
733 pr_debug("RX Hash fields_mask is not supported - both TCP SRC and DST must be set\n");
734 return (-EOPNOTSUPP);
735 }
736
737 if (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_INNER) {
738 if (dev->dev->caps.tunnel_offload_mode ==
739 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
740 /*
741 * Hash according to inner headers if exist, otherwise
742 * according to outer headers.
743 */
744 rss_ctx->flags |= MLX4_RSS_BY_INNER_HEADERS_IPONLY;
745 } else {
746 pr_debug("RSS Hash for inner headers isn't supported\n");
747 return (-EOPNOTSUPP);
748 }
749 }
750
751 return 0;
752 }
753
754 static int create_qp_rss(struct mlx4_ib_dev *dev,
755 struct ib_qp_init_attr *init_attr,
756 struct mlx4_ib_create_qp_rss *ucmd,
757 struct mlx4_ib_qp *qp)
758 {
759 int qpn;
760 int err;
761
762 qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS;
763
764 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn, 0, qp->mqp.usage);
765 if (err)
766 return err;
767
768 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp);
769 if (err)
770 goto err_qpn;
771
772 mutex_init(&qp->mutex);
773
774 INIT_LIST_HEAD(&qp->gid_list);
775 INIT_LIST_HEAD(&qp->steering_rules);
776
777 qp->mlx4_ib_qp_type = MLX4_IB_QPT_RAW_PACKET;
778 qp->state = IB_QPS_RESET;
779
780 /* Set dummy send resources to be compatible with HV and PRM */
781 qp->sq_no_prefetch = 1;
782 qp->sq.wqe_cnt = 1;
783 qp->sq.wqe_shift = MLX4_IB_MIN_SQ_STRIDE;
784 qp->buf_size = qp->sq.wqe_cnt << MLX4_IB_MIN_SQ_STRIDE;
785 qp->mtt = (to_mqp(
786 (struct ib_qp *)init_attr->rwq_ind_tbl->ind_tbl[0]))->mtt;
787
788 qp->rss_ctx = kzalloc(sizeof(*qp->rss_ctx), GFP_KERNEL);
789 if (!qp->rss_ctx) {
790 err = -ENOMEM;
791 goto err_qp_alloc;
792 }
793
794 err = set_qp_rss(dev, qp->rss_ctx, init_attr, ucmd);
795 if (err)
796 goto err;
797
798 return 0;
799
800 err:
801 kfree(qp->rss_ctx);
802
803 err_qp_alloc:
804 mlx4_qp_remove(dev->dev, &qp->mqp);
805 mlx4_qp_free(dev->dev, &qp->mqp);
806
807 err_qpn:
808 mlx4_qp_release_range(dev->dev, qpn, 1);
809 return err;
810 }
811
812 static struct ib_qp *_mlx4_ib_create_qp_rss(struct ib_pd *pd,
813 struct ib_qp_init_attr *init_attr,
814 struct ib_udata *udata)
815 {
816 struct mlx4_ib_qp *qp;
817 struct mlx4_ib_create_qp_rss ucmd = {};
818 size_t required_cmd_sz;
819 int err;
820
821 if (!udata) {
822 pr_debug("RSS QP with NULL udata\n");
823 return ERR_PTR(-EINVAL);
824 }
825
826 if (udata->outlen)
827 return ERR_PTR(-EOPNOTSUPP);
828
829 required_cmd_sz = offsetof(typeof(ucmd), reserved1) +
830 sizeof(ucmd.reserved1);
831 if (udata->inlen < required_cmd_sz) {
832 pr_debug("invalid inlen\n");
833 return ERR_PTR(-EINVAL);
834 }
835
836 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
837 pr_debug("copy failed\n");
838 return ERR_PTR(-EFAULT);
839 }
840
841 if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved)))
842 return ERR_PTR(-EOPNOTSUPP);
843
844 if (ucmd.comp_mask || ucmd.reserved1)
845 return ERR_PTR(-EOPNOTSUPP);
846
847 if (udata->inlen > sizeof(ucmd) &&
848 !ib_is_udata_cleared(udata, sizeof(ucmd),
849 udata->inlen - sizeof(ucmd))) {
850 pr_debug("inlen is not supported\n");
851 return ERR_PTR(-EOPNOTSUPP);
852 }
853
854 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
855 pr_debug("RSS QP with unsupported QP type %d\n",
856 init_attr->qp_type);
857 return ERR_PTR(-EOPNOTSUPP);
858 }
859
860 if (init_attr->create_flags) {
861 pr_debug("RSS QP doesn't support create flags\n");
862 return ERR_PTR(-EOPNOTSUPP);
863 }
864
865 if (init_attr->send_cq || init_attr->cap.max_send_wr) {
866 pr_debug("RSS QP with unsupported send attributes\n");
867 return ERR_PTR(-EOPNOTSUPP);
868 }
869
870 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
871 if (!qp)
872 return ERR_PTR(-ENOMEM);
873
874 qp->pri.vid = 0xFFFF;
875 qp->alt.vid = 0xFFFF;
876
877 err = create_qp_rss(to_mdev(pd->device), init_attr, &ucmd, qp);
878 if (err) {
879 kfree(qp);
880 return ERR_PTR(err);
881 }
882
883 qp->ibqp.qp_num = qp->mqp.qpn;
884
885 return &qp->ibqp;
886 }
887
888 /*
889 * This function allocates a WQN from a range which is consecutive and aligned
890 * to its size. In case the range is full, then it creates a new range and
891 * allocates WQN from it. The new range will be used for following allocations.
892 */
893 static int mlx4_ib_alloc_wqn(struct mlx4_ib_ucontext *context,
894 struct mlx4_ib_qp *qp, int range_size, int *wqn)
895 {
896 struct mlx4_ib_dev *dev = to_mdev(context->ibucontext.device);
897 struct mlx4_wqn_range *range;
898 int err = 0;
899
900 mutex_lock(&context->wqn_ranges_mutex);
901
902 range = list_first_entry_or_null(&context->wqn_ranges_list,
903 struct mlx4_wqn_range, list);
904
905 if (!range || (range->refcount == range->size) || range->dirty) {
906 range = kzalloc(sizeof(*range), GFP_KERNEL);
907 if (!range) {
908 err = -ENOMEM;
909 goto out;
910 }
911
912 err = mlx4_qp_reserve_range(dev->dev, range_size,
913 range_size, &range->base_wqn, 0,
914 qp->mqp.usage);
915 if (err) {
916 kfree(range);
917 goto out;
918 }
919
920 range->size = range_size;
921 list_add(&range->list, &context->wqn_ranges_list);
922 } else if (range_size != 1) {
923 /*
924 * Requesting a new range (>1) when last range is still open, is
925 * not valid.
926 */
927 err = -EINVAL;
928 goto out;
929 }
930
931 qp->wqn_range = range;
932
933 *wqn = range->base_wqn + range->refcount;
934
935 range->refcount++;
936
937 out:
938 mutex_unlock(&context->wqn_ranges_mutex);
939
940 return err;
941 }
942
943 static void mlx4_ib_release_wqn(struct mlx4_ib_ucontext *context,
944 struct mlx4_ib_qp *qp, bool dirty_release)
945 {
946 struct mlx4_ib_dev *dev = to_mdev(context->ibucontext.device);
947 struct mlx4_wqn_range *range;
948
949 mutex_lock(&context->wqn_ranges_mutex);
950
951 range = qp->wqn_range;
952
953 range->refcount--;
954 if (!range->refcount) {
955 mlx4_qp_release_range(dev->dev, range->base_wqn,
956 range->size);
957 list_del(&range->list);
958 kfree(range);
959 } else if (dirty_release) {
960 /*
961 * A range which one of its WQNs is destroyed, won't be able to be
962 * reused for further WQN allocations.
963 * The next created WQ will allocate a new range.
964 */
965 range->dirty = 1;
966 }
967
968 mutex_unlock(&context->wqn_ranges_mutex);
969 }
970
971 static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
972 enum mlx4_ib_source_type src,
973 struct ib_qp_init_attr *init_attr,
974 struct ib_udata *udata, int sqpn,
975 struct mlx4_ib_qp **caller_qp)
976 {
977 int qpn;
978 int err;
979 struct ib_qp_cap backup_cap;
980 struct mlx4_ib_sqp *sqp = NULL;
981 struct mlx4_ib_qp *qp;
982 enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type;
983 struct mlx4_ib_cq *mcq;
984 unsigned long flags;
985 int range_size = 0;
986
987 /* When tunneling special qps, we use a plain UD qp */
988 if (sqpn) {
989 if (mlx4_is_mfunc(dev->dev) &&
990 (!mlx4_is_master(dev->dev) ||
991 !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) {
992 if (init_attr->qp_type == IB_QPT_GSI)
993 qp_type = MLX4_IB_QPT_PROXY_GSI;
994 else {
995 if (mlx4_is_master(dev->dev) ||
996 qp0_enabled_vf(dev->dev, sqpn))
997 qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER;
998 else
999 qp_type = MLX4_IB_QPT_PROXY_SMI;
1000 }
1001 }
1002 qpn = sqpn;
1003 /* add extra sg entry for tunneling */
1004 init_attr->cap.max_recv_sge++;
1005 } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) {
1006 struct mlx4_ib_qp_tunnel_init_attr *tnl_init =
1007 container_of(init_attr,
1008 struct mlx4_ib_qp_tunnel_init_attr, init_attr);
1009 if ((tnl_init->proxy_qp_type != IB_QPT_SMI &&
1010 tnl_init->proxy_qp_type != IB_QPT_GSI) ||
1011 !mlx4_is_master(dev->dev))
1012 return -EINVAL;
1013 if (tnl_init->proxy_qp_type == IB_QPT_GSI)
1014 qp_type = MLX4_IB_QPT_TUN_GSI;
1015 else if (tnl_init->slave == mlx4_master_func_num(dev->dev) ||
1016 mlx4_vf_smi_enabled(dev->dev, tnl_init->slave,
1017 tnl_init->port))
1018 qp_type = MLX4_IB_QPT_TUN_SMI_OWNER;
1019 else
1020 qp_type = MLX4_IB_QPT_TUN_SMI;
1021 /* we are definitely in the PPF here, since we are creating
1022 * tunnel QPs. base_tunnel_sqpn is therefore valid. */
1023 qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave
1024 + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1;
1025 sqpn = qpn;
1026 }
1027
1028 if (!*caller_qp) {
1029 if (qp_type == MLX4_IB_QPT_SMI || qp_type == MLX4_IB_QPT_GSI ||
1030 (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER |
1031 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) {
1032 sqp = kzalloc(sizeof(struct mlx4_ib_sqp), GFP_KERNEL);
1033 if (!sqp)
1034 return -ENOMEM;
1035 qp = &sqp->qp;
1036 qp->pri.vid = 0xFFFF;
1037 qp->alt.vid = 0xFFFF;
1038 } else {
1039 qp = kzalloc(sizeof(struct mlx4_ib_qp), GFP_KERNEL);
1040 if (!qp)
1041 return -ENOMEM;
1042 qp->pri.vid = 0xFFFF;
1043 qp->alt.vid = 0xFFFF;
1044 }
1045 } else
1046 qp = *caller_qp;
1047
1048 qp->mlx4_ib_qp_type = qp_type;
1049
1050 mutex_init(&qp->mutex);
1051 spin_lock_init(&qp->sq.lock);
1052 spin_lock_init(&qp->rq.lock);
1053 INIT_LIST_HEAD(&qp->gid_list);
1054 INIT_LIST_HEAD(&qp->steering_rules);
1055
1056 qp->state = IB_QPS_RESET;
1057 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1058 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
1059
1060
1061 if (pd->uobject) {
1062 union {
1063 struct mlx4_ib_create_qp qp;
1064 struct mlx4_ib_create_wq wq;
1065 } ucmd;
1066 size_t copy_len;
1067 int shift;
1068 int n;
1069
1070 copy_len = (src == MLX4_IB_QP_SRC) ?
1071 sizeof(struct mlx4_ib_create_qp) :
1072 min(sizeof(struct mlx4_ib_create_wq), udata->inlen);
1073
1074 if (ib_copy_from_udata(&ucmd, udata, copy_len)) {
1075 err = -EFAULT;
1076 goto err;
1077 }
1078
1079 if (src == MLX4_IB_RWQ_SRC) {
1080 if (ucmd.wq.comp_mask || ucmd.wq.reserved[0] ||
1081 ucmd.wq.reserved[1] || ucmd.wq.reserved[2]) {
1082 pr_debug("user command isn't supported\n");
1083 err = -EOPNOTSUPP;
1084 goto err;
1085 }
1086
1087 if (ucmd.wq.log_range_size >
1088 ilog2(dev->dev->caps.max_rss_tbl_sz)) {
1089 pr_debug("WQN range size must be equal or smaller than %d\n",
1090 dev->dev->caps.max_rss_tbl_sz);
1091 err = -EOPNOTSUPP;
1092 goto err;
1093 }
1094 range_size = 1 << ucmd.wq.log_range_size;
1095 } else {
1096 qp->inl_recv_sz = ucmd.qp.inl_recv_sz;
1097 }
1098
1099 err = set_rq_size(dev, &init_attr->cap, !!pd->uobject,
1100 qp_has_rq(init_attr), qp, qp->inl_recv_sz);
1101 if (err)
1102 goto err;
1103
1104 if (src == MLX4_IB_QP_SRC) {
1105 qp->sq_no_prefetch = ucmd.qp.sq_no_prefetch;
1106
1107 err = set_user_sq_size(dev, qp,
1108 (struct mlx4_ib_create_qp *)
1109 &ucmd);
1110 if (err)
1111 goto err;
1112 } else {
1113 qp->sq_no_prefetch = 1;
1114 qp->sq.wqe_cnt = 1;
1115 qp->sq.wqe_shift = MLX4_IB_MIN_SQ_STRIDE;
1116 /* Allocated buffer expects to have at least that SQ
1117 * size.
1118 */
1119 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
1120 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
1121 }
1122
1123 qp->umem = ib_umem_get(pd->uobject->context,
1124 (src == MLX4_IB_QP_SRC) ? ucmd.qp.buf_addr :
1125 ucmd.wq.buf_addr, qp->buf_size, 0, 0);
1126 if (IS_ERR(qp->umem)) {
1127 err = PTR_ERR(qp->umem);
1128 goto err;
1129 }
1130
1131 n = ib_umem_page_count(qp->umem);
1132 shift = mlx4_ib_umem_calc_optimal_mtt_size(qp->umem, 0, &n);
1133 err = mlx4_mtt_init(dev->dev, n, shift, &qp->mtt);
1134
1135 if (err)
1136 goto err_buf;
1137
1138 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
1139 if (err)
1140 goto err_mtt;
1141
1142 if (qp_has_rq(init_attr)) {
1143 err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
1144 (src == MLX4_IB_QP_SRC) ? ucmd.qp.db_addr :
1145 ucmd.wq.db_addr, &qp->db);
1146 if (err)
1147 goto err_mtt;
1148 }
1149 qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS;
1150 } else {
1151 err = set_rq_size(dev, &init_attr->cap, !!pd->uobject,
1152 qp_has_rq(init_attr), qp, 0);
1153 if (err)
1154 goto err;
1155
1156 qp->sq_no_prefetch = 0;
1157
1158 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
1159 qp->flags |= MLX4_IB_QP_LSO;
1160
1161 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1162 if (dev->steering_support ==
1163 MLX4_STEERING_MODE_DEVICE_MANAGED)
1164 qp->flags |= MLX4_IB_QP_NETIF;
1165 else
1166 goto err;
1167 }
1168
1169 memcpy(&backup_cap, &init_attr->cap, sizeof(backup_cap));
1170 err = set_kernel_sq_size(dev, &init_attr->cap,
1171 qp_type, qp, true);
1172 if (err)
1173 goto err;
1174
1175 if (qp_has_rq(init_attr)) {
1176 err = mlx4_db_alloc(dev->dev, &qp->db, 0);
1177 if (err)
1178 goto err;
1179
1180 *qp->db.db = 0;
1181 }
1182
1183 if (mlx4_buf_alloc(dev->dev, qp->buf_size, qp->buf_size,
1184 &qp->buf)) {
1185 memcpy(&init_attr->cap, &backup_cap,
1186 sizeof(backup_cap));
1187 err = set_kernel_sq_size(dev, &init_attr->cap, qp_type,
1188 qp, false);
1189 if (err)
1190 goto err_db;
1191
1192 if (mlx4_buf_alloc(dev->dev, qp->buf_size,
1193 PAGE_SIZE * 2, &qp->buf)) {
1194 err = -ENOMEM;
1195 goto err_db;
1196 }
1197 }
1198
1199 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
1200 &qp->mtt);
1201 if (err)
1202 goto err_buf;
1203
1204 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf);
1205 if (err)
1206 goto err_mtt;
1207
1208 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
1209 sizeof(u64), GFP_KERNEL);
1210 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
1211 sizeof(u64), GFP_KERNEL);
1212 if (!qp->sq.wrid || !qp->rq.wrid) {
1213 err = -ENOMEM;
1214 goto err_wrid;
1215 }
1216 qp->mqp.usage = MLX4_RES_USAGE_DRIVER;
1217 }
1218
1219 if (sqpn) {
1220 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1221 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
1222 if (alloc_proxy_bufs(pd->device, qp)) {
1223 err = -ENOMEM;
1224 goto err_wrid;
1225 }
1226 }
1227 } else if (src == MLX4_IB_RWQ_SRC) {
1228 err = mlx4_ib_alloc_wqn(to_mucontext(pd->uobject->context), qp,
1229 range_size, &qpn);
1230 if (err)
1231 goto err_wrid;
1232 } else {
1233 /* Raw packet QPNs may not have bits 6,7 set in their qp_num;
1234 * otherwise, the WQE BlueFlame setup flow wrongly causes
1235 * VLAN insertion. */
1236 if (init_attr->qp_type == IB_QPT_RAW_PACKET)
1237 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn,
1238 (init_attr->cap.max_send_wr ?
1239 MLX4_RESERVE_ETH_BF_QP : 0) |
1240 (init_attr->cap.max_recv_wr ?
1241 MLX4_RESERVE_A0_QP : 0),
1242 qp->mqp.usage);
1243 else
1244 if (qp->flags & MLX4_IB_QP_NETIF)
1245 err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn);
1246 else
1247 err = mlx4_qp_reserve_range(dev->dev, 1, 1,
1248 &qpn, 0, qp->mqp.usage);
1249 if (err)
1250 goto err_proxy;
1251 }
1252
1253 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
1254 qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1255
1256 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp);
1257 if (err)
1258 goto err_qpn;
1259
1260 if (init_attr->qp_type == IB_QPT_XRC_TGT)
1261 qp->mqp.qpn |= (1 << 23);
1262
1263 /*
1264 * Hardware wants QPN written in big-endian order (after
1265 * shifting) for send doorbell. Precompute this value to save
1266 * a little bit when posting sends.
1267 */
1268 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
1269
1270 qp->mqp.event = (src == MLX4_IB_QP_SRC) ? mlx4_ib_qp_event :
1271 mlx4_ib_wq_event;
1272
1273 if (!*caller_qp)
1274 *caller_qp = qp;
1275
1276 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1277 mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq),
1278 to_mcq(init_attr->recv_cq));
1279 /* Maintain device to QPs access, needed for further handling
1280 * via reset flow
1281 */
1282 list_add_tail(&qp->qps_list, &dev->qp_list);
1283 /* Maintain CQ to QPs access, needed for further handling
1284 * via reset flow
1285 */
1286 mcq = to_mcq(init_attr->send_cq);
1287 list_add_tail(&qp->cq_send_list, &mcq->send_qp_list);
1288 mcq = to_mcq(init_attr->recv_cq);
1289 list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list);
1290 mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq),
1291 to_mcq(init_attr->recv_cq));
1292 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1293 return 0;
1294
1295 err_qpn:
1296 if (!sqpn) {
1297 if (qp->flags & MLX4_IB_QP_NETIF)
1298 mlx4_ib_steer_qp_free(dev, qpn, 1);
1299 else if (src == MLX4_IB_RWQ_SRC)
1300 mlx4_ib_release_wqn(to_mucontext(pd->uobject->context),
1301 qp, 0);
1302 else
1303 mlx4_qp_release_range(dev->dev, qpn, 1);
1304 }
1305 err_proxy:
1306 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
1307 free_proxy_bufs(pd->device, qp);
1308 err_wrid:
1309 if (pd->uobject) {
1310 if (qp_has_rq(init_attr))
1311 mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db);
1312 } else {
1313 kvfree(qp->sq.wrid);
1314 kvfree(qp->rq.wrid);
1315 }
1316
1317 err_mtt:
1318 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1319
1320 err_buf:
1321 if (pd->uobject)
1322 ib_umem_release(qp->umem);
1323 else
1324 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
1325
1326 err_db:
1327 if (!pd->uobject && qp_has_rq(init_attr))
1328 mlx4_db_free(dev->dev, &qp->db);
1329
1330 err:
1331 if (sqp)
1332 kfree(sqp);
1333 else if (!*caller_qp)
1334 kfree(qp);
1335 return err;
1336 }
1337
1338 static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
1339 {
1340 switch (state) {
1341 case IB_QPS_RESET: return MLX4_QP_STATE_RST;
1342 case IB_QPS_INIT: return MLX4_QP_STATE_INIT;
1343 case IB_QPS_RTR: return MLX4_QP_STATE_RTR;
1344 case IB_QPS_RTS: return MLX4_QP_STATE_RTS;
1345 case IB_QPS_SQD: return MLX4_QP_STATE_SQD;
1346 case IB_QPS_SQE: return MLX4_QP_STATE_SQER;
1347 case IB_QPS_ERR: return MLX4_QP_STATE_ERR;
1348 default: return -1;
1349 }
1350 }
1351
1352 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
1353 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1354 {
1355 if (send_cq == recv_cq) {
1356 spin_lock(&send_cq->lock);
1357 __acquire(&recv_cq->lock);
1358 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1359 spin_lock(&send_cq->lock);
1360 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
1361 } else {
1362 spin_lock(&recv_cq->lock);
1363 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
1364 }
1365 }
1366
1367 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
1368 __releases(&send_cq->lock) __releases(&recv_cq->lock)
1369 {
1370 if (send_cq == recv_cq) {
1371 __release(&recv_cq->lock);
1372 spin_unlock(&send_cq->lock);
1373 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1374 spin_unlock(&recv_cq->lock);
1375 spin_unlock(&send_cq->lock);
1376 } else {
1377 spin_unlock(&send_cq->lock);
1378 spin_unlock(&recv_cq->lock);
1379 }
1380 }
1381
1382 static void del_gid_entries(struct mlx4_ib_qp *qp)
1383 {
1384 struct mlx4_ib_gid_entry *ge, *tmp;
1385
1386 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1387 list_del(&ge->list);
1388 kfree(ge);
1389 }
1390 }
1391
1392 static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp)
1393 {
1394 if (qp->ibqp.qp_type == IB_QPT_XRC_TGT)
1395 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd);
1396 else
1397 return to_mpd(qp->ibqp.pd);
1398 }
1399
1400 static void get_cqs(struct mlx4_ib_qp *qp, enum mlx4_ib_source_type src,
1401 struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq)
1402 {
1403 switch (qp->ibqp.qp_type) {
1404 case IB_QPT_XRC_TGT:
1405 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq);
1406 *recv_cq = *send_cq;
1407 break;
1408 case IB_QPT_XRC_INI:
1409 *send_cq = to_mcq(qp->ibqp.send_cq);
1410 *recv_cq = *send_cq;
1411 break;
1412 default:
1413 *recv_cq = (src == MLX4_IB_QP_SRC) ? to_mcq(qp->ibqp.recv_cq) :
1414 to_mcq(qp->ibwq.cq);
1415 *send_cq = (src == MLX4_IB_QP_SRC) ? to_mcq(qp->ibqp.send_cq) :
1416 *recv_cq;
1417 break;
1418 }
1419 }
1420
1421 static void destroy_qp_rss(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1422 {
1423 if (qp->state != IB_QPS_RESET) {
1424 int i;
1425
1426 for (i = 0; i < (1 << qp->ibqp.rwq_ind_tbl->log_ind_tbl_size);
1427 i++) {
1428 struct ib_wq *ibwq = qp->ibqp.rwq_ind_tbl->ind_tbl[i];
1429 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
1430
1431 mutex_lock(&wq->mutex);
1432
1433 wq->rss_usecnt--;
1434
1435 mutex_unlock(&wq->mutex);
1436 }
1437
1438 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
1439 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
1440 pr_warn("modify QP %06x to RESET failed.\n",
1441 qp->mqp.qpn);
1442 }
1443
1444 mlx4_qp_remove(dev->dev, &qp->mqp);
1445 mlx4_qp_free(dev->dev, &qp->mqp);
1446 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1447 del_gid_entries(qp);
1448 kfree(qp->rss_ctx);
1449 }
1450
1451 static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
1452 enum mlx4_ib_source_type src, int is_user)
1453 {
1454 struct mlx4_ib_cq *send_cq, *recv_cq;
1455 unsigned long flags;
1456
1457 if (qp->state != IB_QPS_RESET) {
1458 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
1459 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
1460 pr_warn("modify QP %06x to RESET failed.\n",
1461 qp->mqp.qpn);
1462 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
1463 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1464 qp->pri.smac = 0;
1465 qp->pri.smac_port = 0;
1466 }
1467 if (qp->alt.smac) {
1468 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1469 qp->alt.smac = 0;
1470 }
1471 if (qp->pri.vid < 0x1000) {
1472 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1473 qp->pri.vid = 0xFFFF;
1474 qp->pri.candidate_vid = 0xFFFF;
1475 qp->pri.update_vid = 0;
1476 }
1477 if (qp->alt.vid < 0x1000) {
1478 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1479 qp->alt.vid = 0xFFFF;
1480 qp->alt.candidate_vid = 0xFFFF;
1481 qp->alt.update_vid = 0;
1482 }
1483 }
1484
1485 get_cqs(qp, src, &send_cq, &recv_cq);
1486
1487 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1488 mlx4_ib_lock_cqs(send_cq, recv_cq);
1489
1490 /* del from lists under both locks above to protect reset flow paths */
1491 list_del(&qp->qps_list);
1492 list_del(&qp->cq_send_list);
1493 list_del(&qp->cq_recv_list);
1494 if (!is_user) {
1495 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1496 qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
1497 if (send_cq != recv_cq)
1498 __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1499 }
1500
1501 mlx4_qp_remove(dev->dev, &qp->mqp);
1502
1503 mlx4_ib_unlock_cqs(send_cq, recv_cq);
1504 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1505
1506 mlx4_qp_free(dev->dev, &qp->mqp);
1507
1508 if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) {
1509 if (qp->flags & MLX4_IB_QP_NETIF)
1510 mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1);
1511 else if (src == MLX4_IB_RWQ_SRC)
1512 mlx4_ib_release_wqn(to_mucontext(
1513 qp->ibwq.uobject->context), qp, 1);
1514 else
1515 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1516 }
1517
1518 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1519
1520 if (is_user) {
1521 if (qp->rq.wqe_cnt) {
1522 struct mlx4_ib_ucontext *mcontext = !src ?
1523 to_mucontext(qp->ibqp.uobject->context) :
1524 to_mucontext(qp->ibwq.uobject->context);
1525 mlx4_ib_db_unmap_user(mcontext, &qp->db);
1526 }
1527 ib_umem_release(qp->umem);
1528 } else {
1529 kvfree(qp->sq.wrid);
1530 kvfree(qp->rq.wrid);
1531 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1532 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI))
1533 free_proxy_bufs(&dev->ib_dev, qp);
1534 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
1535 if (qp->rq.wqe_cnt)
1536 mlx4_db_free(dev->dev, &qp->db);
1537 }
1538
1539 del_gid_entries(qp);
1540 }
1541
1542 static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr)
1543 {
1544 /* Native or PPF */
1545 if (!mlx4_is_mfunc(dev->dev) ||
1546 (mlx4_is_master(dev->dev) &&
1547 attr->create_flags & MLX4_IB_SRIOV_SQP)) {
1548 return dev->dev->phys_caps.base_sqpn +
1549 (attr->qp_type == IB_QPT_SMI ? 0 : 2) +
1550 attr->port_num - 1;
1551 }
1552 /* PF or VF -- creating proxies */
1553 if (attr->qp_type == IB_QPT_SMI)
1554 return dev->dev->caps.spec_qps[attr->port_num - 1].qp0_proxy;
1555 else
1556 return dev->dev->caps.spec_qps[attr->port_num - 1].qp1_proxy;
1557 }
1558
1559 static struct ib_qp *_mlx4_ib_create_qp(struct ib_pd *pd,
1560 struct ib_qp_init_attr *init_attr,
1561 struct ib_udata *udata)
1562 {
1563 struct mlx4_ib_qp *qp = NULL;
1564 int err;
1565 int sup_u_create_flags = MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1566 u16 xrcdn = 0;
1567
1568 if (init_attr->rwq_ind_tbl)
1569 return _mlx4_ib_create_qp_rss(pd, init_attr, udata);
1570
1571 /*
1572 * We only support LSO, vendor flag1, and multicast loopback blocking,
1573 * and only for kernel UD QPs.
1574 */
1575 if (init_attr->create_flags & ~(MLX4_IB_QP_LSO |
1576 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK |
1577 MLX4_IB_SRIOV_TUNNEL_QP |
1578 MLX4_IB_SRIOV_SQP |
1579 MLX4_IB_QP_NETIF |
1580 MLX4_IB_QP_CREATE_ROCE_V2_GSI))
1581 return ERR_PTR(-EINVAL);
1582
1583 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1584 if (init_attr->qp_type != IB_QPT_UD)
1585 return ERR_PTR(-EINVAL);
1586 }
1587
1588 if (init_attr->create_flags) {
1589 if (udata && init_attr->create_flags & ~(sup_u_create_flags))
1590 return ERR_PTR(-EINVAL);
1591
1592 if ((init_attr->create_flags & ~(MLX4_IB_SRIOV_SQP |
1593 MLX4_IB_QP_CREATE_ROCE_V2_GSI |
1594 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) &&
1595 init_attr->qp_type != IB_QPT_UD) ||
1596 (init_attr->create_flags & MLX4_IB_SRIOV_SQP &&
1597 init_attr->qp_type > IB_QPT_GSI) ||
1598 (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI &&
1599 init_attr->qp_type != IB_QPT_GSI))
1600 return ERR_PTR(-EINVAL);
1601 }
1602
1603 switch (init_attr->qp_type) {
1604 case IB_QPT_XRC_TGT:
1605 pd = to_mxrcd(init_attr->xrcd)->pd;
1606 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1607 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq;
1608 /* fall through */
1609 case IB_QPT_XRC_INI:
1610 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1611 return ERR_PTR(-ENOSYS);
1612 init_attr->recv_cq = init_attr->send_cq;
1613 /* fall through */
1614 case IB_QPT_RC:
1615 case IB_QPT_UC:
1616 case IB_QPT_RAW_PACKET:
1617 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
1618 if (!qp)
1619 return ERR_PTR(-ENOMEM);
1620 qp->pri.vid = 0xFFFF;
1621 qp->alt.vid = 0xFFFF;
1622 /* fall through */
1623 case IB_QPT_UD:
1624 {
1625 err = create_qp_common(to_mdev(pd->device), pd, MLX4_IB_QP_SRC,
1626 init_attr, udata, 0, &qp);
1627 if (err) {
1628 kfree(qp);
1629 return ERR_PTR(err);
1630 }
1631
1632 qp->ibqp.qp_num = qp->mqp.qpn;
1633 qp->xrcdn = xrcdn;
1634
1635 break;
1636 }
1637 case IB_QPT_SMI:
1638 case IB_QPT_GSI:
1639 {
1640 int sqpn;
1641
1642 /* Userspace is not allowed to create special QPs: */
1643 if (udata)
1644 return ERR_PTR(-EINVAL);
1645 if (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI) {
1646 int res = mlx4_qp_reserve_range(to_mdev(pd->device)->dev,
1647 1, 1, &sqpn, 0,
1648 MLX4_RES_USAGE_DRIVER);
1649
1650 if (res)
1651 return ERR_PTR(res);
1652 } else {
1653 sqpn = get_sqp_num(to_mdev(pd->device), init_attr);
1654 }
1655
1656 err = create_qp_common(to_mdev(pd->device), pd, MLX4_IB_QP_SRC,
1657 init_attr, udata, sqpn, &qp);
1658 if (err)
1659 return ERR_PTR(err);
1660
1661 qp->port = init_attr->port_num;
1662 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 :
1663 init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI ? sqpn : 1;
1664 break;
1665 }
1666 default:
1667 /* Don't support raw QPs */
1668 return ERR_PTR(-EINVAL);
1669 }
1670
1671 return &qp->ibqp;
1672 }
1673
1674 struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
1675 struct ib_qp_init_attr *init_attr,
1676 struct ib_udata *udata) {
1677 struct ib_device *device = pd ? pd->device : init_attr->xrcd->device;
1678 struct ib_qp *ibqp;
1679 struct mlx4_ib_dev *dev = to_mdev(device);
1680
1681 ibqp = _mlx4_ib_create_qp(pd, init_attr, udata);
1682
1683 if (!IS_ERR(ibqp) &&
1684 (init_attr->qp_type == IB_QPT_GSI) &&
1685 !(init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI)) {
1686 struct mlx4_ib_sqp *sqp = to_msqp((to_mqp(ibqp)));
1687 int is_eth = rdma_cap_eth_ah(&dev->ib_dev, init_attr->port_num);
1688
1689 if (is_eth &&
1690 dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) {
1691 init_attr->create_flags |= MLX4_IB_QP_CREATE_ROCE_V2_GSI;
1692 sqp->roce_v2_gsi = ib_create_qp(pd, init_attr);
1693
1694 if (IS_ERR(sqp->roce_v2_gsi)) {
1695 pr_err("Failed to create GSI QP for RoCEv2 (%ld)\n", PTR_ERR(sqp->roce_v2_gsi));
1696 sqp->roce_v2_gsi = NULL;
1697 } else {
1698 sqp = to_msqp(to_mqp(sqp->roce_v2_gsi));
1699 sqp->qp.flags |= MLX4_IB_ROCE_V2_GSI_QP;
1700 }
1701
1702 init_attr->create_flags &= ~MLX4_IB_QP_CREATE_ROCE_V2_GSI;
1703 }
1704 }
1705 return ibqp;
1706 }
1707
1708 static int _mlx4_ib_destroy_qp(struct ib_qp *qp)
1709 {
1710 struct mlx4_ib_dev *dev = to_mdev(qp->device);
1711 struct mlx4_ib_qp *mqp = to_mqp(qp);
1712
1713 if (is_qp0(dev, mqp))
1714 mlx4_CLOSE_PORT(dev->dev, mqp->port);
1715
1716 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI &&
1717 dev->qp1_proxy[mqp->port - 1] == mqp) {
1718 mutex_lock(&dev->qp1_proxy_lock[mqp->port - 1]);
1719 dev->qp1_proxy[mqp->port - 1] = NULL;
1720 mutex_unlock(&dev->qp1_proxy_lock[mqp->port - 1]);
1721 }
1722
1723 if (mqp->counter_index)
1724 mlx4_ib_free_qp_counter(dev, mqp);
1725
1726 if (qp->rwq_ind_tbl) {
1727 destroy_qp_rss(dev, mqp);
1728 } else {
1729 struct mlx4_ib_pd *pd;
1730
1731 pd = get_pd(mqp);
1732 destroy_qp_common(dev, mqp, MLX4_IB_QP_SRC, !!pd->ibpd.uobject);
1733 }
1734
1735 if (is_sqp(dev, mqp))
1736 kfree(to_msqp(mqp));
1737 else
1738 kfree(mqp);
1739
1740 return 0;
1741 }
1742
1743 int mlx4_ib_destroy_qp(struct ib_qp *qp)
1744 {
1745 struct mlx4_ib_qp *mqp = to_mqp(qp);
1746
1747 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
1748 struct mlx4_ib_sqp *sqp = to_msqp(mqp);
1749
1750 if (sqp->roce_v2_gsi)
1751 ib_destroy_qp(sqp->roce_v2_gsi);
1752 }
1753
1754 return _mlx4_ib_destroy_qp(qp);
1755 }
1756
1757 static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type)
1758 {
1759 switch (type) {
1760 case MLX4_IB_QPT_RC: return MLX4_QP_ST_RC;
1761 case MLX4_IB_QPT_UC: return MLX4_QP_ST_UC;
1762 case MLX4_IB_QPT_UD: return MLX4_QP_ST_UD;
1763 case MLX4_IB_QPT_XRC_INI:
1764 case MLX4_IB_QPT_XRC_TGT: return MLX4_QP_ST_XRC;
1765 case MLX4_IB_QPT_SMI:
1766 case MLX4_IB_QPT_GSI:
1767 case MLX4_IB_QPT_RAW_PACKET: return MLX4_QP_ST_MLX;
1768
1769 case MLX4_IB_QPT_PROXY_SMI_OWNER:
1770 case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ?
1771 MLX4_QP_ST_MLX : -1);
1772 case MLX4_IB_QPT_PROXY_SMI:
1773 case MLX4_IB_QPT_TUN_SMI:
1774 case MLX4_IB_QPT_PROXY_GSI:
1775 case MLX4_IB_QPT_TUN_GSI: return (mlx4_is_mfunc(dev->dev) ?
1776 MLX4_QP_ST_UD : -1);
1777 default: return -1;
1778 }
1779 }
1780
1781 static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
1782 int attr_mask)
1783 {
1784 u8 dest_rd_atomic;
1785 u32 access_flags;
1786 u32 hw_access_flags = 0;
1787
1788 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1789 dest_rd_atomic = attr->max_dest_rd_atomic;
1790 else
1791 dest_rd_atomic = qp->resp_depth;
1792
1793 if (attr_mask & IB_QP_ACCESS_FLAGS)
1794 access_flags = attr->qp_access_flags;
1795 else
1796 access_flags = qp->atomic_rd_en;
1797
1798 if (!dest_rd_atomic)
1799 access_flags &= IB_ACCESS_REMOTE_WRITE;
1800
1801 if (access_flags & IB_ACCESS_REMOTE_READ)
1802 hw_access_flags |= MLX4_QP_BIT_RRE;
1803 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1804 hw_access_flags |= MLX4_QP_BIT_RAE;
1805 if (access_flags & IB_ACCESS_REMOTE_WRITE)
1806 hw_access_flags |= MLX4_QP_BIT_RWE;
1807
1808 return cpu_to_be32(hw_access_flags);
1809 }
1810
1811 static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
1812 int attr_mask)
1813 {
1814 if (attr_mask & IB_QP_PKEY_INDEX)
1815 sqp->pkey_index = attr->pkey_index;
1816 if (attr_mask & IB_QP_QKEY)
1817 sqp->qkey = attr->qkey;
1818 if (attr_mask & IB_QP_SQ_PSN)
1819 sqp->send_psn = attr->sq_psn;
1820 }
1821
1822 static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
1823 {
1824 path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
1825 }
1826
1827 static int _mlx4_set_path(struct mlx4_ib_dev *dev,
1828 const struct rdma_ah_attr *ah,
1829 u64 smac, u16 vlan_tag, struct mlx4_qp_path *path,
1830 struct mlx4_roce_smac_vlan_info *smac_info, u8 port)
1831 {
1832 int vidx;
1833 int smac_index;
1834 int err;
1835
1836 path->grh_mylmc = rdma_ah_get_path_bits(ah) & 0x7f;
1837 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
1838 if (rdma_ah_get_static_rate(ah)) {
1839 path->static_rate = rdma_ah_get_static_rate(ah) +
1840 MLX4_STAT_RATE_OFFSET;
1841 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
1842 !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
1843 --path->static_rate;
1844 } else
1845 path->static_rate = 0;
1846
1847 if (rdma_ah_get_ah_flags(ah) & IB_AH_GRH) {
1848 const struct ib_global_route *grh = rdma_ah_read_grh(ah);
1849 int real_sgid_index =
1850 mlx4_ib_gid_index_to_real_index(dev, port,
1851 grh->sgid_index);
1852
1853 if (real_sgid_index < 0)
1854 return real_sgid_index;
1855 if (real_sgid_index >= dev->dev->caps.gid_table_len[port]) {
1856 pr_err("sgid_index (%u) too large. max is %d\n",
1857 real_sgid_index, dev->dev->caps.gid_table_len[port] - 1);
1858 return -1;
1859 }
1860
1861 path->grh_mylmc |= 1 << 7;
1862 path->mgid_index = real_sgid_index;
1863 path->hop_limit = grh->hop_limit;
1864 path->tclass_flowlabel =
1865 cpu_to_be32((grh->traffic_class << 20) |
1866 (grh->flow_label));
1867 memcpy(path->rgid, grh->dgid.raw, 16);
1868 }
1869
1870 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
1871 if (!(rdma_ah_get_ah_flags(ah) & IB_AH_GRH))
1872 return -1;
1873
1874 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1875 ((port - 1) << 6) | ((rdma_ah_get_sl(ah) & 7) << 3);
1876
1877 path->feup |= MLX4_FEUP_FORCE_ETH_UP;
1878 if (vlan_tag < 0x1000) {
1879 if (smac_info->vid < 0x1000) {
1880 /* both valid vlan ids */
1881 if (smac_info->vid != vlan_tag) {
1882 /* different VIDs. unreg old and reg new */
1883 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1884 if (err)
1885 return err;
1886 smac_info->candidate_vid = vlan_tag;
1887 smac_info->candidate_vlan_index = vidx;
1888 smac_info->candidate_vlan_port = port;
1889 smac_info->update_vid = 1;
1890 path->vlan_index = vidx;
1891 } else {
1892 path->vlan_index = smac_info->vlan_index;
1893 }
1894 } else {
1895 /* no current vlan tag in qp */
1896 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1897 if (err)
1898 return err;
1899 smac_info->candidate_vid = vlan_tag;
1900 smac_info->candidate_vlan_index = vidx;
1901 smac_info->candidate_vlan_port = port;
1902 smac_info->update_vid = 1;
1903 path->vlan_index = vidx;
1904 }
1905 path->feup |= MLX4_FVL_FORCE_ETH_VLAN;
1906 path->fl = 1 << 6;
1907 } else {
1908 /* have current vlan tag. unregister it at modify-qp success */
1909 if (smac_info->vid < 0x1000) {
1910 smac_info->candidate_vid = 0xFFFF;
1911 smac_info->update_vid = 1;
1912 }
1913 }
1914
1915 /* get smac_index for RoCE use.
1916 * If no smac was yet assigned, register one.
1917 * If one was already assigned, but the new mac differs,
1918 * unregister the old one and register the new one.
1919 */
1920 if ((!smac_info->smac && !smac_info->smac_port) ||
1921 smac_info->smac != smac) {
1922 /* register candidate now, unreg if needed, after success */
1923 smac_index = mlx4_register_mac(dev->dev, port, smac);
1924 if (smac_index >= 0) {
1925 smac_info->candidate_smac_index = smac_index;
1926 smac_info->candidate_smac = smac;
1927 smac_info->candidate_smac_port = port;
1928 } else {
1929 return -EINVAL;
1930 }
1931 } else {
1932 smac_index = smac_info->smac_index;
1933 }
1934 memcpy(path->dmac, ah->roce.dmac, 6);
1935 path->ackto = MLX4_IB_LINK_TYPE_ETH;
1936 /* put MAC table smac index for IBoE */
1937 path->grh_mylmc = (u8) (smac_index) | 0x80;
1938 } else {
1939 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1940 ((port - 1) << 6) | ((rdma_ah_get_sl(ah) & 0xf) << 2);
1941 }
1942
1943 return 0;
1944 }
1945
1946 static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_qp_attr *qp,
1947 enum ib_qp_attr_mask qp_attr_mask,
1948 struct mlx4_ib_qp *mqp,
1949 struct mlx4_qp_path *path, u8 port,
1950 u16 vlan_id, u8 *smac)
1951 {
1952 return _mlx4_set_path(dev, &qp->ah_attr,
1953 mlx4_mac_to_u64(smac),
1954 vlan_id,
1955 path, &mqp->pri, port);
1956 }
1957
1958 static int mlx4_set_alt_path(struct mlx4_ib_dev *dev,
1959 const struct ib_qp_attr *qp,
1960 enum ib_qp_attr_mask qp_attr_mask,
1961 struct mlx4_ib_qp *mqp,
1962 struct mlx4_qp_path *path, u8 port)
1963 {
1964 return _mlx4_set_path(dev, &qp->alt_ah_attr,
1965 0,
1966 0xffff,
1967 path, &mqp->alt, port);
1968 }
1969
1970 static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1971 {
1972 struct mlx4_ib_gid_entry *ge, *tmp;
1973
1974 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1975 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) {
1976 ge->added = 1;
1977 ge->port = qp->port;
1978 }
1979 }
1980 }
1981
1982 static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev,
1983 struct mlx4_ib_qp *qp,
1984 struct mlx4_qp_context *context)
1985 {
1986 u64 u64_mac;
1987 int smac_index;
1988
1989 u64_mac = atomic64_read(&dev->iboe.mac[qp->port - 1]);
1990
1991 context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6);
1992 if (!qp->pri.smac && !qp->pri.smac_port) {
1993 smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac);
1994 if (smac_index >= 0) {
1995 qp->pri.candidate_smac_index = smac_index;
1996 qp->pri.candidate_smac = u64_mac;
1997 qp->pri.candidate_smac_port = qp->port;
1998 context->pri_path.grh_mylmc = 0x80 | (u8) smac_index;
1999 } else {
2000 return -ENOENT;
2001 }
2002 }
2003 return 0;
2004 }
2005
2006 static int create_qp_lb_counter(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
2007 {
2008 struct counter_index *new_counter_index;
2009 int err;
2010 u32 tmp_idx;
2011
2012 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) !=
2013 IB_LINK_LAYER_ETHERNET ||
2014 !(qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) ||
2015 !(dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_LB_SRC_CHK))
2016 return 0;
2017
2018 err = mlx4_counter_alloc(dev->dev, &tmp_idx, MLX4_RES_USAGE_DRIVER);
2019 if (err)
2020 return err;
2021
2022 new_counter_index = kmalloc(sizeof(*new_counter_index), GFP_KERNEL);
2023 if (!new_counter_index) {
2024 mlx4_counter_free(dev->dev, tmp_idx);
2025 return -ENOMEM;
2026 }
2027
2028 new_counter_index->index = tmp_idx;
2029 new_counter_index->allocated = 1;
2030 qp->counter_index = new_counter_index;
2031
2032 mutex_lock(&dev->counters_table[qp->port - 1].mutex);
2033 list_add_tail(&new_counter_index->list,
2034 &dev->counters_table[qp->port - 1].counters_list);
2035 mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
2036
2037 return 0;
2038 }
2039
2040 enum {
2041 MLX4_QPC_ROCE_MODE_1 = 0,
2042 MLX4_QPC_ROCE_MODE_2 = 2,
2043 MLX4_QPC_ROCE_MODE_UNDEFINED = 0xff
2044 };
2045
2046 static u8 gid_type_to_qpc(enum ib_gid_type gid_type)
2047 {
2048 switch (gid_type) {
2049 case IB_GID_TYPE_ROCE:
2050 return MLX4_QPC_ROCE_MODE_1;
2051 case IB_GID_TYPE_ROCE_UDP_ENCAP:
2052 return MLX4_QPC_ROCE_MODE_2;
2053 default:
2054 return MLX4_QPC_ROCE_MODE_UNDEFINED;
2055 }
2056 }
2057
2058 /*
2059 * Go over all RSS QP's childes (WQs) and apply their HW state according to
2060 * their logic state if the RSS QP is the first RSS QP associated for the WQ.
2061 */
2062 static int bringup_rss_rwqs(struct ib_rwq_ind_table *ind_tbl, u8 port_num)
2063 {
2064 int err = 0;
2065 int i;
2066
2067 for (i = 0; i < (1 << ind_tbl->log_ind_tbl_size); i++) {
2068 struct ib_wq *ibwq = ind_tbl->ind_tbl[i];
2069 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
2070
2071 mutex_lock(&wq->mutex);
2072
2073 /* Mlx4_ib restrictions:
2074 * WQ's is associated to a port according to the RSS QP it is
2075 * associates to.
2076 * In case the WQ is associated to a different port by another
2077 * RSS QP, return a failure.
2078 */
2079 if ((wq->rss_usecnt > 0) && (wq->port != port_num)) {
2080 err = -EINVAL;
2081 mutex_unlock(&wq->mutex);
2082 break;
2083 }
2084 wq->port = port_num;
2085 if ((wq->rss_usecnt == 0) && (ibwq->state == IB_WQS_RDY)) {
2086 err = _mlx4_ib_modify_wq(ibwq, IB_WQS_RDY);
2087 if (err) {
2088 mutex_unlock(&wq->mutex);
2089 break;
2090 }
2091 }
2092 wq->rss_usecnt++;
2093
2094 mutex_unlock(&wq->mutex);
2095 }
2096
2097 if (i && err) {
2098 int j;
2099
2100 for (j = (i - 1); j >= 0; j--) {
2101 struct ib_wq *ibwq = ind_tbl->ind_tbl[j];
2102 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
2103
2104 mutex_lock(&wq->mutex);
2105
2106 if ((wq->rss_usecnt == 1) &&
2107 (ibwq->state == IB_WQS_RDY))
2108 if (_mlx4_ib_modify_wq(ibwq, IB_WQS_RESET))
2109 pr_warn("failed to reverse WQN=0x%06x\n",
2110 ibwq->wq_num);
2111 wq->rss_usecnt--;
2112
2113 mutex_unlock(&wq->mutex);
2114 }
2115 }
2116
2117 return err;
2118 }
2119
2120 static void bring_down_rss_rwqs(struct ib_rwq_ind_table *ind_tbl)
2121 {
2122 int i;
2123
2124 for (i = 0; i < (1 << ind_tbl->log_ind_tbl_size); i++) {
2125 struct ib_wq *ibwq = ind_tbl->ind_tbl[i];
2126 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
2127
2128 mutex_lock(&wq->mutex);
2129
2130 if ((wq->rss_usecnt == 1) && (ibwq->state == IB_WQS_RDY))
2131 if (_mlx4_ib_modify_wq(ibwq, IB_WQS_RESET))
2132 pr_warn("failed to reverse WQN=%x\n",
2133 ibwq->wq_num);
2134 wq->rss_usecnt--;
2135
2136 mutex_unlock(&wq->mutex);
2137 }
2138 }
2139
2140 static void fill_qp_rss_context(struct mlx4_qp_context *context,
2141 struct mlx4_ib_qp *qp)
2142 {
2143 struct mlx4_rss_context *rss_context;
2144
2145 rss_context = (void *)context + offsetof(struct mlx4_qp_context,
2146 pri_path) + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH;
2147
2148 rss_context->base_qpn = cpu_to_be32(qp->rss_ctx->base_qpn_tbl_sz);
2149 rss_context->default_qpn =
2150 cpu_to_be32(qp->rss_ctx->base_qpn_tbl_sz & 0xffffff);
2151 if (qp->rss_ctx->flags & (MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6))
2152 rss_context->base_qpn_udp = rss_context->default_qpn;
2153 rss_context->flags = qp->rss_ctx->flags;
2154 /* Currently support just toeplitz */
2155 rss_context->hash_fn = MLX4_RSS_HASH_TOP;
2156
2157 memcpy(rss_context->rss_key, qp->rss_ctx->rss_key,
2158 MLX4_EN_RSS_KEY_SIZE);
2159 }
2160
2161 static int __mlx4_ib_modify_qp(void *src, enum mlx4_ib_source_type src_type,
2162 const struct ib_qp_attr *attr, int attr_mask,
2163 enum ib_qp_state cur_state, enum ib_qp_state new_state)
2164 {
2165 struct ib_uobject *ibuobject;
2166 struct ib_srq *ibsrq;
2167 struct ib_rwq_ind_table *rwq_ind_tbl;
2168 enum ib_qp_type qp_type;
2169 struct mlx4_ib_dev *dev;
2170 struct mlx4_ib_qp *qp;
2171 struct mlx4_ib_pd *pd;
2172 struct mlx4_ib_cq *send_cq, *recv_cq;
2173 struct mlx4_qp_context *context;
2174 enum mlx4_qp_optpar optpar = 0;
2175 int sqd_event;
2176 int steer_qp = 0;
2177 int err = -EINVAL;
2178 int counter_index;
2179
2180 if (src_type == MLX4_IB_RWQ_SRC) {
2181 struct ib_wq *ibwq;
2182
2183 ibwq = (struct ib_wq *)src;
2184 ibuobject = ibwq->uobject;
2185 ibsrq = NULL;
2186 rwq_ind_tbl = NULL;
2187 qp_type = IB_QPT_RAW_PACKET;
2188 qp = to_mqp((struct ib_qp *)ibwq);
2189 dev = to_mdev(ibwq->device);
2190 pd = to_mpd(ibwq->pd);
2191 } else {
2192 struct ib_qp *ibqp;
2193
2194 ibqp = (struct ib_qp *)src;
2195 ibuobject = ibqp->uobject;
2196 ibsrq = ibqp->srq;
2197 rwq_ind_tbl = ibqp->rwq_ind_tbl;
2198 qp_type = ibqp->qp_type;
2199 qp = to_mqp(ibqp);
2200 dev = to_mdev(ibqp->device);
2201 pd = get_pd(qp);
2202 }
2203
2204 /* APM is not supported under RoCE */
2205 if (attr_mask & IB_QP_ALT_PATH &&
2206 rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
2207 IB_LINK_LAYER_ETHERNET)
2208 return -ENOTSUPP;
2209
2210 context = kzalloc(sizeof *context, GFP_KERNEL);
2211 if (!context)
2212 return -ENOMEM;
2213
2214 context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
2215 (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16));
2216
2217 if (!(attr_mask & IB_QP_PATH_MIG_STATE))
2218 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
2219 else {
2220 optpar |= MLX4_QP_OPTPAR_PM_STATE;
2221 switch (attr->path_mig_state) {
2222 case IB_MIG_MIGRATED:
2223 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
2224 break;
2225 case IB_MIG_REARM:
2226 context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
2227 break;
2228 case IB_MIG_ARMED:
2229 context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
2230 break;
2231 }
2232 }
2233
2234 if (qp->inl_recv_sz)
2235 context->param3 |= cpu_to_be32(1 << 25);
2236
2237 if (qp_type == IB_QPT_GSI || qp_type == IB_QPT_SMI)
2238 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
2239 else if (qp_type == IB_QPT_RAW_PACKET)
2240 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX;
2241 else if (qp_type == IB_QPT_UD) {
2242 if (qp->flags & MLX4_IB_QP_LSO)
2243 context->mtu_msgmax = (IB_MTU_4096 << 5) |
2244 ilog2(dev->dev->caps.max_gso_sz);
2245 else
2246 context->mtu_msgmax = (IB_MTU_4096 << 5) | 13;
2247 } else if (attr_mask & IB_QP_PATH_MTU) {
2248 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
2249 pr_err("path MTU (%u) is invalid\n",
2250 attr->path_mtu);
2251 goto out;
2252 }
2253 context->mtu_msgmax = (attr->path_mtu << 5) |
2254 ilog2(dev->dev->caps.max_msg_sz);
2255 }
2256
2257 if (!rwq_ind_tbl) { /* PRM RSS receive side should be left zeros */
2258 if (qp->rq.wqe_cnt)
2259 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
2260 context->rq_size_stride |= qp->rq.wqe_shift - 4;
2261 }
2262
2263 if (qp->sq.wqe_cnt)
2264 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
2265 context->sq_size_stride |= qp->sq.wqe_shift - 4;
2266
2267 if (new_state == IB_QPS_RESET && qp->counter_index)
2268 mlx4_ib_free_qp_counter(dev, qp);
2269
2270 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2271 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
2272 context->xrcd = cpu_to_be32((u32) qp->xrcdn);
2273 if (qp_type == IB_QPT_RAW_PACKET)
2274 context->param3 |= cpu_to_be32(1 << 30);
2275 }
2276
2277 if (ibuobject)
2278 context->usr_page = cpu_to_be32(
2279 mlx4_to_hw_uar_index(dev->dev,
2280 to_mucontext(ibuobject->context)
2281 ->uar.index));
2282 else
2283 context->usr_page = cpu_to_be32(
2284 mlx4_to_hw_uar_index(dev->dev, dev->priv_uar.index));
2285
2286 if (attr_mask & IB_QP_DEST_QPN)
2287 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
2288
2289 if (attr_mask & IB_QP_PORT) {
2290 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
2291 !(attr_mask & IB_QP_AV)) {
2292 mlx4_set_sched(&context->pri_path, attr->port_num);
2293 optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
2294 }
2295 }
2296
2297 if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
2298 err = create_qp_lb_counter(dev, qp);
2299 if (err)
2300 goto out;
2301
2302 counter_index =
2303 dev->counters_table[qp->port - 1].default_counter;
2304 if (qp->counter_index)
2305 counter_index = qp->counter_index->index;
2306
2307 if (counter_index != -1) {
2308 context->pri_path.counter_index = counter_index;
2309 optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX;
2310 if (qp->counter_index) {
2311 context->pri_path.fl |=
2312 MLX4_FL_ETH_SRC_CHECK_MC_LB;
2313 context->pri_path.vlan_control |=
2314 MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER;
2315 }
2316 } else
2317 context->pri_path.counter_index =
2318 MLX4_SINK_COUNTER_INDEX(dev->dev);
2319
2320 if (qp->flags & MLX4_IB_QP_NETIF) {
2321 mlx4_ib_steer_qp_reg(dev, qp, 1);
2322 steer_qp = 1;
2323 }
2324
2325 if (qp_type == IB_QPT_GSI) {
2326 enum ib_gid_type gid_type = qp->flags & MLX4_IB_ROCE_V2_GSI_QP ?
2327 IB_GID_TYPE_ROCE_UDP_ENCAP : IB_GID_TYPE_ROCE;
2328 u8 qpc_roce_mode = gid_type_to_qpc(gid_type);
2329
2330 context->rlkey_roce_mode |= (qpc_roce_mode << 6);
2331 }
2332 }
2333
2334 if (attr_mask & IB_QP_PKEY_INDEX) {
2335 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
2336 context->pri_path.disable_pkey_check = 0x40;
2337 context->pri_path.pkey_index = attr->pkey_index;
2338 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
2339 }
2340
2341 if (attr_mask & IB_QP_AV) {
2342 u8 port_num = mlx4_is_bonded(dev->dev) ? 1 :
2343 attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2344 union ib_gid gid;
2345 struct ib_gid_attr gid_attr = {.gid_type = IB_GID_TYPE_IB};
2346 u16 vlan = 0xffff;
2347 u8 smac[ETH_ALEN];
2348 int status = 0;
2349 int is_eth =
2350 rdma_cap_eth_ah(&dev->ib_dev, port_num) &&
2351 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH;
2352
2353 if (is_eth) {
2354 int index =
2355 rdma_ah_read_grh(&attr->ah_attr)->sgid_index;
2356
2357 status = ib_get_cached_gid(&dev->ib_dev, port_num,
2358 index, &gid, &gid_attr);
2359 if (!status && !memcmp(&gid, &zgid, sizeof(gid)))
2360 status = -ENOENT;
2361 if (!status && gid_attr.ndev) {
2362 vlan = rdma_vlan_dev_vlan_id(gid_attr.ndev);
2363 memcpy(smac, gid_attr.ndev->dev_addr, ETH_ALEN);
2364 dev_put(gid_attr.ndev);
2365 }
2366 }
2367 if (status)
2368 goto out;
2369
2370 if (mlx4_set_path(dev, attr, attr_mask, qp, &context->pri_path,
2371 port_num, vlan, smac))
2372 goto out;
2373
2374 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
2375 MLX4_QP_OPTPAR_SCHED_QUEUE);
2376
2377 if (is_eth &&
2378 (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR)) {
2379 u8 qpc_roce_mode = gid_type_to_qpc(gid_attr.gid_type);
2380
2381 if (qpc_roce_mode == MLX4_QPC_ROCE_MODE_UNDEFINED) {
2382 err = -EINVAL;
2383 goto out;
2384 }
2385 context->rlkey_roce_mode |= (qpc_roce_mode << 6);
2386 }
2387
2388 }
2389
2390 if (attr_mask & IB_QP_TIMEOUT) {
2391 context->pri_path.ackto |= attr->timeout << 3;
2392 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
2393 }
2394
2395 if (attr_mask & IB_QP_ALT_PATH) {
2396 if (attr->alt_port_num == 0 ||
2397 attr->alt_port_num > dev->dev->caps.num_ports)
2398 goto out;
2399
2400 if (attr->alt_pkey_index >=
2401 dev->dev->caps.pkey_table_len[attr->alt_port_num])
2402 goto out;
2403
2404 if (mlx4_set_alt_path(dev, attr, attr_mask, qp,
2405 &context->alt_path,
2406 attr->alt_port_num))
2407 goto out;
2408
2409 context->alt_path.pkey_index = attr->alt_pkey_index;
2410 context->alt_path.ackto = attr->alt_timeout << 3;
2411 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
2412 }
2413
2414 context->pd = cpu_to_be32(pd->pdn);
2415
2416 if (!rwq_ind_tbl) {
2417 context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
2418 get_cqs(qp, src_type, &send_cq, &recv_cq);
2419 } else { /* Set dummy CQs to be compatible with HV and PRM */
2420 send_cq = to_mcq(rwq_ind_tbl->ind_tbl[0]->cq);
2421 recv_cq = send_cq;
2422 }
2423 context->cqn_send = cpu_to_be32(send_cq->mcq.cqn);
2424 context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn);
2425
2426 /* Set "fast registration enabled" for all kernel QPs */
2427 if (!ibuobject)
2428 context->params1 |= cpu_to_be32(1 << 11);
2429
2430 if (attr_mask & IB_QP_RNR_RETRY) {
2431 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
2432 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
2433 }
2434
2435 if (attr_mask & IB_QP_RETRY_CNT) {
2436 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
2437 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
2438 }
2439
2440 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2441 if (attr->max_rd_atomic)
2442 context->params1 |=
2443 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
2444 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
2445 }
2446
2447 if (attr_mask & IB_QP_SQ_PSN)
2448 context->next_send_psn = cpu_to_be32(attr->sq_psn);
2449
2450 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2451 if (attr->max_dest_rd_atomic)
2452 context->params2 |=
2453 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
2454 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
2455 }
2456
2457 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
2458 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
2459 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
2460 }
2461
2462 if (ibsrq)
2463 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
2464
2465 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
2466 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
2467 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
2468 }
2469 if (attr_mask & IB_QP_RQ_PSN)
2470 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
2471
2472 /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */
2473 if (attr_mask & IB_QP_QKEY) {
2474 if (qp->mlx4_ib_qp_type &
2475 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))
2476 context->qkey = cpu_to_be32(IB_QP_SET_QKEY);
2477 else {
2478 if (mlx4_is_mfunc(dev->dev) &&
2479 !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) &&
2480 (attr->qkey & MLX4_RESERVED_QKEY_MASK) ==
2481 MLX4_RESERVED_QKEY_BASE) {
2482 pr_err("Cannot use reserved QKEY"
2483 " 0x%x (range 0xffff0000..0xffffffff"
2484 " is reserved)\n", attr->qkey);
2485 err = -EINVAL;
2486 goto out;
2487 }
2488 context->qkey = cpu_to_be32(attr->qkey);
2489 }
2490 optpar |= MLX4_QP_OPTPAR_Q_KEY;
2491 }
2492
2493 if (ibsrq)
2494 context->srqn = cpu_to_be32(1 << 24 |
2495 to_msrq(ibsrq)->msrq.srqn);
2496
2497 if (qp->rq.wqe_cnt &&
2498 cur_state == IB_QPS_RESET &&
2499 new_state == IB_QPS_INIT)
2500 context->db_rec_addr = cpu_to_be64(qp->db.dma);
2501
2502 if (cur_state == IB_QPS_INIT &&
2503 new_state == IB_QPS_RTR &&
2504 (qp_type == IB_QPT_GSI || qp_type == IB_QPT_SMI ||
2505 qp_type == IB_QPT_UD || qp_type == IB_QPT_RAW_PACKET)) {
2506 context->pri_path.sched_queue = (qp->port - 1) << 6;
2507 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
2508 qp->mlx4_ib_qp_type &
2509 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) {
2510 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
2511 if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI)
2512 context->pri_path.fl = 0x80;
2513 } else {
2514 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
2515 context->pri_path.fl = 0x80;
2516 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
2517 }
2518 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
2519 IB_LINK_LAYER_ETHERNET) {
2520 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI ||
2521 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI)
2522 context->pri_path.feup = 1 << 7; /* don't fsm */
2523 /* handle smac_index */
2524 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD ||
2525 qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI ||
2526 qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) {
2527 err = handle_eth_ud_smac_index(dev, qp, context);
2528 if (err) {
2529 err = -EINVAL;
2530 goto out;
2531 }
2532 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
2533 dev->qp1_proxy[qp->port - 1] = qp;
2534 }
2535 }
2536 }
2537
2538 if (qp_type == IB_QPT_RAW_PACKET) {
2539 context->pri_path.ackto = (context->pri_path.ackto & 0xf8) |
2540 MLX4_IB_LINK_TYPE_ETH;
2541 if (dev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
2542 /* set QP to receive both tunneled & non-tunneled packets */
2543 if (!rwq_ind_tbl)
2544 context->srqn = cpu_to_be32(7 << 28);
2545 }
2546 }
2547
2548 if (qp_type == IB_QPT_UD && (new_state == IB_QPS_RTR)) {
2549 int is_eth = rdma_port_get_link_layer(
2550 &dev->ib_dev, qp->port) ==
2551 IB_LINK_LAYER_ETHERNET;
2552 if (is_eth) {
2553 context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH;
2554 optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH;
2555 }
2556 }
2557
2558 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
2559 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
2560 sqd_event = 1;
2561 else
2562 sqd_event = 0;
2563
2564 if (!ibuobject &&
2565 cur_state == IB_QPS_RESET &&
2566 new_state == IB_QPS_INIT)
2567 context->rlkey_roce_mode |= (1 << 4);
2568
2569 /*
2570 * Before passing a kernel QP to the HW, make sure that the
2571 * ownership bits of the send queue are set and the SQ
2572 * headroom is stamped so that the hardware doesn't start
2573 * processing stale work requests.
2574 */
2575 if (!ibuobject &&
2576 cur_state == IB_QPS_RESET &&
2577 new_state == IB_QPS_INIT) {
2578 struct mlx4_wqe_ctrl_seg *ctrl;
2579 int i;
2580
2581 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
2582 ctrl = get_send_wqe(qp, i);
2583 ctrl->owner_opcode = cpu_to_be32(1 << 31);
2584 if (qp->sq_max_wqes_per_wr == 1)
2585 ctrl->qpn_vlan.fence_size =
2586 1 << (qp->sq.wqe_shift - 4);
2587
2588 stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift);
2589 }
2590 }
2591
2592 if (rwq_ind_tbl &&
2593 cur_state == IB_QPS_RESET &&
2594 new_state == IB_QPS_INIT) {
2595 fill_qp_rss_context(context, qp);
2596 context->flags |= cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET);
2597 }
2598
2599 err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
2600 to_mlx4_state(new_state), context, optpar,
2601 sqd_event, &qp->mqp);
2602 if (err)
2603 goto out;
2604
2605 qp->state = new_state;
2606
2607 if (attr_mask & IB_QP_ACCESS_FLAGS)
2608 qp->atomic_rd_en = attr->qp_access_flags;
2609 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2610 qp->resp_depth = attr->max_dest_rd_atomic;
2611 if (attr_mask & IB_QP_PORT) {
2612 qp->port = attr->port_num;
2613 update_mcg_macs(dev, qp);
2614 }
2615 if (attr_mask & IB_QP_ALT_PATH)
2616 qp->alt_port = attr->alt_port_num;
2617
2618 if (is_sqp(dev, qp))
2619 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
2620
2621 /*
2622 * If we moved QP0 to RTR, bring the IB link up; if we moved
2623 * QP0 to RESET or ERROR, bring the link back down.
2624 */
2625 if (is_qp0(dev, qp)) {
2626 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
2627 if (mlx4_INIT_PORT(dev->dev, qp->port))
2628 pr_warn("INIT_PORT failed for port %d\n",
2629 qp->port);
2630
2631 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
2632 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
2633 mlx4_CLOSE_PORT(dev->dev, qp->port);
2634 }
2635
2636 /*
2637 * If we moved a kernel QP to RESET, clean up all old CQ
2638 * entries and reinitialize the QP.
2639 */
2640 if (new_state == IB_QPS_RESET) {
2641 if (!ibuobject) {
2642 mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
2643 ibsrq ? to_msrq(ibsrq) : NULL);
2644 if (send_cq != recv_cq)
2645 mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
2646
2647 qp->rq.head = 0;
2648 qp->rq.tail = 0;
2649 qp->sq.head = 0;
2650 qp->sq.tail = 0;
2651 qp->sq_next_wqe = 0;
2652 if (qp->rq.wqe_cnt)
2653 *qp->db.db = 0;
2654
2655 if (qp->flags & MLX4_IB_QP_NETIF)
2656 mlx4_ib_steer_qp_reg(dev, qp, 0);
2657 }
2658 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
2659 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
2660 qp->pri.smac = 0;
2661 qp->pri.smac_port = 0;
2662 }
2663 if (qp->alt.smac) {
2664 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
2665 qp->alt.smac = 0;
2666 }
2667 if (qp->pri.vid < 0x1000) {
2668 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
2669 qp->pri.vid = 0xFFFF;
2670 qp->pri.candidate_vid = 0xFFFF;
2671 qp->pri.update_vid = 0;
2672 }
2673
2674 if (qp->alt.vid < 0x1000) {
2675 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
2676 qp->alt.vid = 0xFFFF;
2677 qp->alt.candidate_vid = 0xFFFF;
2678 qp->alt.update_vid = 0;
2679 }
2680 }
2681 out:
2682 if (err && qp->counter_index)
2683 mlx4_ib_free_qp_counter(dev, qp);
2684 if (err && steer_qp)
2685 mlx4_ib_steer_qp_reg(dev, qp, 0);
2686 kfree(context);
2687 if (qp->pri.candidate_smac ||
2688 (!qp->pri.candidate_smac && qp->pri.candidate_smac_port)) {
2689 if (err) {
2690 mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac);
2691 } else {
2692 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port))
2693 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
2694 qp->pri.smac = qp->pri.candidate_smac;
2695 qp->pri.smac_index = qp->pri.candidate_smac_index;
2696 qp->pri.smac_port = qp->pri.candidate_smac_port;
2697 }
2698 qp->pri.candidate_smac = 0;
2699 qp->pri.candidate_smac_index = 0;
2700 qp->pri.candidate_smac_port = 0;
2701 }
2702 if (qp->alt.candidate_smac) {
2703 if (err) {
2704 mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->alt.candidate_smac);
2705 } else {
2706 if (qp->alt.smac)
2707 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
2708 qp->alt.smac = qp->alt.candidate_smac;
2709 qp->alt.smac_index = qp->alt.candidate_smac_index;
2710 qp->alt.smac_port = qp->alt.candidate_smac_port;
2711 }
2712 qp->alt.candidate_smac = 0;
2713 qp->alt.candidate_smac_index = 0;
2714 qp->alt.candidate_smac_port = 0;
2715 }
2716
2717 if (qp->pri.update_vid) {
2718 if (err) {
2719 if (qp->pri.candidate_vid < 0x1000)
2720 mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port,
2721 qp->pri.candidate_vid);
2722 } else {
2723 if (qp->pri.vid < 0x1000)
2724 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port,
2725 qp->pri.vid);
2726 qp->pri.vid = qp->pri.candidate_vid;
2727 qp->pri.vlan_port = qp->pri.candidate_vlan_port;
2728 qp->pri.vlan_index = qp->pri.candidate_vlan_index;
2729 }
2730 qp->pri.candidate_vid = 0xFFFF;
2731 qp->pri.update_vid = 0;
2732 }
2733
2734 if (qp->alt.update_vid) {
2735 if (err) {
2736 if (qp->alt.candidate_vid < 0x1000)
2737 mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port,
2738 qp->alt.candidate_vid);
2739 } else {
2740 if (qp->alt.vid < 0x1000)
2741 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port,
2742 qp->alt.vid);
2743 qp->alt.vid = qp->alt.candidate_vid;
2744 qp->alt.vlan_port = qp->alt.candidate_vlan_port;
2745 qp->alt.vlan_index = qp->alt.candidate_vlan_index;
2746 }
2747 qp->alt.candidate_vid = 0xFFFF;
2748 qp->alt.update_vid = 0;
2749 }
2750
2751 return err;
2752 }
2753
2754 enum {
2755 MLX4_IB_MODIFY_QP_RSS_SUP_ATTR_MSK = (IB_QP_STATE |
2756 IB_QP_PORT),
2757 };
2758
2759 static int _mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2760 int attr_mask, struct ib_udata *udata)
2761 {
2762 enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED;
2763 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
2764 struct mlx4_ib_qp *qp = to_mqp(ibqp);
2765 enum ib_qp_state cur_state, new_state;
2766 int err = -EINVAL;
2767 mutex_lock(&qp->mutex);
2768
2769 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2770 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2771
2772 if (cur_state != new_state || cur_state != IB_QPS_RESET) {
2773 int port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2774 ll = rdma_port_get_link_layer(&dev->ib_dev, port);
2775 }
2776
2777 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type,
2778 attr_mask, ll)) {
2779 pr_debug("qpn 0x%x: invalid attribute mask specified "
2780 "for transition %d to %d. qp_type %d,"
2781 " attr_mask 0x%x\n",
2782 ibqp->qp_num, cur_state, new_state,
2783 ibqp->qp_type, attr_mask);
2784 goto out;
2785 }
2786
2787 if (ibqp->rwq_ind_tbl) {
2788 if (!(((cur_state == IB_QPS_RESET) &&
2789 (new_state == IB_QPS_INIT)) ||
2790 ((cur_state == IB_QPS_INIT) &&
2791 (new_state == IB_QPS_RTR)))) {
2792 pr_debug("qpn 0x%x: RSS QP unsupported transition %d to %d\n",
2793 ibqp->qp_num, cur_state, new_state);
2794
2795 err = -EOPNOTSUPP;
2796 goto out;
2797 }
2798
2799 if (attr_mask & ~MLX4_IB_MODIFY_QP_RSS_SUP_ATTR_MSK) {
2800 pr_debug("qpn 0x%x: RSS QP unsupported attribute mask 0x%x for transition %d to %d\n",
2801 ibqp->qp_num, attr_mask, cur_state, new_state);
2802
2803 err = -EOPNOTSUPP;
2804 goto out;
2805 }
2806 }
2807
2808 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) {
2809 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2810 if ((ibqp->qp_type == IB_QPT_RC) ||
2811 (ibqp->qp_type == IB_QPT_UD) ||
2812 (ibqp->qp_type == IB_QPT_UC) ||
2813 (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
2814 (ibqp->qp_type == IB_QPT_XRC_INI)) {
2815 attr->port_num = mlx4_ib_bond_next_port(dev);
2816 }
2817 } else {
2818 /* no sense in changing port_num
2819 * when ports are bonded */
2820 attr_mask &= ~IB_QP_PORT;
2821 }
2822 }
2823
2824 if ((attr_mask & IB_QP_PORT) &&
2825 (attr->port_num == 0 || attr->port_num > dev->num_ports)) {
2826 pr_debug("qpn 0x%x: invalid port number (%d) specified "
2827 "for transition %d to %d. qp_type %d\n",
2828 ibqp->qp_num, attr->port_num, cur_state,
2829 new_state, ibqp->qp_type);
2830 goto out;
2831 }
2832
2833 if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) &&
2834 (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) !=
2835 IB_LINK_LAYER_ETHERNET))
2836 goto out;
2837
2838 if (attr_mask & IB_QP_PKEY_INDEX) {
2839 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2840 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) {
2841 pr_debug("qpn 0x%x: invalid pkey index (%d) specified "
2842 "for transition %d to %d. qp_type %d\n",
2843 ibqp->qp_num, attr->pkey_index, cur_state,
2844 new_state, ibqp->qp_type);
2845 goto out;
2846 }
2847 }
2848
2849 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
2850 attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
2851 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. "
2852 "Transition %d to %d. qp_type %d\n",
2853 ibqp->qp_num, attr->max_rd_atomic, cur_state,
2854 new_state, ibqp->qp_type);
2855 goto out;
2856 }
2857
2858 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
2859 attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
2860 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. "
2861 "Transition %d to %d. qp_type %d\n",
2862 ibqp->qp_num, attr->max_dest_rd_atomic, cur_state,
2863 new_state, ibqp->qp_type);
2864 goto out;
2865 }
2866
2867 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2868 err = 0;
2869 goto out;
2870 }
2871
2872 if (ibqp->rwq_ind_tbl && (new_state == IB_QPS_INIT)) {
2873 err = bringup_rss_rwqs(ibqp->rwq_ind_tbl, attr->port_num);
2874 if (err)
2875 goto out;
2876 }
2877
2878 err = __mlx4_ib_modify_qp(ibqp, MLX4_IB_QP_SRC, attr, attr_mask,
2879 cur_state, new_state);
2880
2881 if (ibqp->rwq_ind_tbl && err)
2882 bring_down_rss_rwqs(ibqp->rwq_ind_tbl);
2883
2884 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT))
2885 attr->port_num = 1;
2886
2887 out:
2888 mutex_unlock(&qp->mutex);
2889 return err;
2890 }
2891
2892 int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2893 int attr_mask, struct ib_udata *udata)
2894 {
2895 struct mlx4_ib_qp *mqp = to_mqp(ibqp);
2896 int ret;
2897
2898 ret = _mlx4_ib_modify_qp(ibqp, attr, attr_mask, udata);
2899
2900 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
2901 struct mlx4_ib_sqp *sqp = to_msqp(mqp);
2902 int err = 0;
2903
2904 if (sqp->roce_v2_gsi)
2905 err = ib_modify_qp(sqp->roce_v2_gsi, attr, attr_mask);
2906 if (err)
2907 pr_err("Failed to modify GSI QP for RoCEv2 (%d)\n",
2908 err);
2909 }
2910 return ret;
2911 }
2912
2913 static int vf_get_qp0_qkey(struct mlx4_dev *dev, int qpn, u32 *qkey)
2914 {
2915 int i;
2916 for (i = 0; i < dev->caps.num_ports; i++) {
2917 if (qpn == dev->caps.spec_qps[i].qp0_proxy ||
2918 qpn == dev->caps.spec_qps[i].qp0_tunnel) {
2919 *qkey = dev->caps.spec_qps[i].qp0_qkey;
2920 return 0;
2921 }
2922 }
2923 return -EINVAL;
2924 }
2925
2926 static int build_sriov_qp0_header(struct mlx4_ib_sqp *sqp,
2927 struct ib_ud_wr *wr,
2928 void *wqe, unsigned *mlx_seg_len)
2929 {
2930 struct mlx4_ib_dev *mdev = to_mdev(sqp->qp.ibqp.device);
2931 struct ib_device *ib_dev = &mdev->ib_dev;
2932 struct mlx4_wqe_mlx_seg *mlx = wqe;
2933 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
2934 struct mlx4_ib_ah *ah = to_mah(wr->ah);
2935 u16 pkey;
2936 u32 qkey;
2937 int send_size;
2938 int header_size;
2939 int spc;
2940 int i;
2941
2942 if (wr->wr.opcode != IB_WR_SEND)
2943 return -EINVAL;
2944
2945 send_size = 0;
2946
2947 for (i = 0; i < wr->wr.num_sge; ++i)
2948 send_size += wr->wr.sg_list[i].length;
2949
2950 /* for proxy-qp0 sends, need to add in size of tunnel header */
2951 /* for tunnel-qp0 sends, tunnel header is already in s/g list */
2952 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER)
2953 send_size += sizeof (struct mlx4_ib_tunnel_header);
2954
2955 ib_ud_header_init(send_size, 1, 0, 0, 0, 0, 0, 0, &sqp->ud_header);
2956
2957 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) {
2958 sqp->ud_header.lrh.service_level =
2959 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2960 sqp->ud_header.lrh.destination_lid =
2961 cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2962 sqp->ud_header.lrh.source_lid =
2963 cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2964 }
2965
2966 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
2967
2968 /* force loopback */
2969 mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR);
2970 mlx->rlid = sqp->ud_header.lrh.destination_lid;
2971
2972 sqp->ud_header.lrh.virtual_lane = 0;
2973 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
2974 ib_get_cached_pkey(ib_dev, sqp->qp.port, 0, &pkey);
2975 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2976 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER)
2977 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
2978 else
2979 sqp->ud_header.bth.destination_qpn =
2980 cpu_to_be32(mdev->dev->caps.spec_qps[sqp->qp.port - 1].qp0_tunnel);
2981
2982 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
2983 if (mlx4_is_master(mdev->dev)) {
2984 if (mlx4_get_parav_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2985 return -EINVAL;
2986 } else {
2987 if (vf_get_qp0_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2988 return -EINVAL;
2989 }
2990 sqp->ud_header.deth.qkey = cpu_to_be32(qkey);
2991 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.mqp.qpn);
2992
2993 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
2994 sqp->ud_header.immediate_present = 0;
2995
2996 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2997
2998 /*
2999 * Inline data segments may not cross a 64 byte boundary. If
3000 * our UD header is bigger than the space available up to the
3001 * next 64 byte boundary in the WQE, use two inline data
3002 * segments to hold the UD header.
3003 */
3004 spc = MLX4_INLINE_ALIGN -
3005 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
3006 if (header_size <= spc) {
3007 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
3008 memcpy(inl + 1, sqp->header_buf, header_size);
3009 i = 1;
3010 } else {
3011 inl->byte_count = cpu_to_be32(1 << 31 | spc);
3012 memcpy(inl + 1, sqp->header_buf, spc);
3013
3014 inl = (void *) (inl + 1) + spc;
3015 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
3016 /*
3017 * Need a barrier here to make sure all the data is
3018 * visible before the byte_count field is set.
3019 * Otherwise the HCA prefetcher could grab the 64-byte
3020 * chunk with this inline segment and get a valid (!=
3021 * 0xffffffff) byte count but stale data, and end up
3022 * generating a packet with bad headers.
3023 *
3024 * The first inline segment's byte_count field doesn't
3025 * need a barrier, because it comes after a
3026 * control/MLX segment and therefore is at an offset
3027 * of 16 mod 64.
3028 */
3029 wmb();
3030 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
3031 i = 2;
3032 }
3033
3034 *mlx_seg_len =
3035 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
3036 return 0;
3037 }
3038
3039 static u8 sl_to_vl(struct mlx4_ib_dev *dev, u8 sl, int port_num)
3040 {
3041 union sl2vl_tbl_to_u64 tmp_vltab;
3042 u8 vl;
3043
3044 if (sl > 15)
3045 return 0xf;
3046 tmp_vltab.sl64 = atomic64_read(&dev->sl2vl[port_num - 1]);
3047 vl = tmp_vltab.sl8[sl >> 1];
3048 if (sl & 1)
3049 vl &= 0x0f;
3050 else
3051 vl >>= 4;
3052 return vl;
3053 }
3054
3055 static int fill_gid_by_hw_index(struct mlx4_ib_dev *ibdev, u8 port_num,
3056 int index, union ib_gid *gid,
3057 enum ib_gid_type *gid_type)
3058 {
3059 struct mlx4_ib_iboe *iboe = &ibdev->iboe;
3060 struct mlx4_port_gid_table *port_gid_table;
3061 unsigned long flags;
3062
3063 port_gid_table = &iboe->gids[port_num - 1];
3064 spin_lock_irqsave(&iboe->lock, flags);
3065 memcpy(gid, &port_gid_table->gids[index].gid, sizeof(*gid));
3066 *gid_type = port_gid_table->gids[index].gid_type;
3067 spin_unlock_irqrestore(&iboe->lock, flags);
3068 if (!memcmp(gid, &zgid, sizeof(*gid)))
3069 return -ENOENT;
3070
3071 return 0;
3072 }
3073
3074 #define MLX4_ROCEV2_QP1_SPORT 0xC000
3075 static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_ud_wr *wr,
3076 void *wqe, unsigned *mlx_seg_len)
3077 {
3078 struct ib_device *ib_dev = sqp->qp.ibqp.device;
3079 struct mlx4_ib_dev *ibdev = to_mdev(ib_dev);
3080 struct mlx4_wqe_mlx_seg *mlx = wqe;
3081 struct mlx4_wqe_ctrl_seg *ctrl = wqe;
3082 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
3083 struct mlx4_ib_ah *ah = to_mah(wr->ah);
3084 union ib_gid sgid;
3085 u16 pkey;
3086 int send_size;
3087 int header_size;
3088 int spc;
3089 int i;
3090 int err = 0;
3091 u16 vlan = 0xffff;
3092 bool is_eth;
3093 bool is_vlan = false;
3094 bool is_grh;
3095 bool is_udp = false;
3096 int ip_version = 0;
3097
3098 send_size = 0;
3099 for (i = 0; i < wr->wr.num_sge; ++i)
3100 send_size += wr->wr.sg_list[i].length;
3101
3102 is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET;
3103 is_grh = mlx4_ib_ah_grh_present(ah);
3104 if (is_eth) {
3105 enum ib_gid_type gid_type;
3106 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
3107 /* When multi-function is enabled, the ib_core gid
3108 * indexes don't necessarily match the hw ones, so
3109 * we must use our own cache */
3110 err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev,
3111 be32_to_cpu(ah->av.ib.port_pd) >> 24,
3112 ah->av.ib.gid_index, &sgid.raw[0]);
3113 if (err)
3114 return err;
3115 } else {
3116 err = fill_gid_by_hw_index(ibdev, sqp->qp.port,
3117 ah->av.ib.gid_index,
3118 &sgid, &gid_type);
3119 if (!err) {
3120 is_udp = gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP;
3121 if (is_udp) {
3122 if (ipv6_addr_v4mapped((struct in6_addr *)&sgid))
3123 ip_version = 4;
3124 else
3125 ip_version = 6;
3126 is_grh = false;
3127 }
3128 } else {
3129 return err;
3130 }
3131 }
3132 if (ah->av.eth.vlan != cpu_to_be16(0xffff)) {
3133 vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff;
3134 is_vlan = 1;
3135 }
3136 }
3137 err = ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh,
3138 ip_version, is_udp, 0, &sqp->ud_header);
3139 if (err)
3140 return err;
3141
3142 if (!is_eth) {
3143 sqp->ud_header.lrh.service_level =
3144 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
3145 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid;
3146 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f);
3147 }
3148
3149 if (is_grh || (ip_version == 6)) {
3150 sqp->ud_header.grh.traffic_class =
3151 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
3152 sqp->ud_header.grh.flow_label =
3153 ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
3154 sqp->ud_header.grh.hop_limit = ah->av.ib.hop_limit;
3155 if (is_eth) {
3156 memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16);
3157 } else {
3158 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
3159 /* When multi-function is enabled, the ib_core gid
3160 * indexes don't necessarily match the hw ones, so
3161 * we must use our own cache
3162 */
3163 sqp->ud_header.grh.source_gid.global.subnet_prefix =
3164 cpu_to_be64(atomic64_read(&(to_mdev(ib_dev)->sriov.
3165 demux[sqp->qp.port - 1].
3166 subnet_prefix)));
3167 sqp->ud_header.grh.source_gid.global.interface_id =
3168 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
3169 guid_cache[ah->av.ib.gid_index];
3170 } else {
3171 ib_get_cached_gid(ib_dev,
3172 be32_to_cpu(ah->av.ib.port_pd) >> 24,
3173 ah->av.ib.gid_index,
3174 &sqp->ud_header.grh.source_gid, NULL);
3175 }
3176 }
3177 memcpy(sqp->ud_header.grh.destination_gid.raw,
3178 ah->av.ib.dgid, 16);
3179 }
3180
3181 if (ip_version == 4) {
3182 sqp->ud_header.ip4.tos =
3183 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
3184 sqp->ud_header.ip4.id = 0;
3185 sqp->ud_header.ip4.frag_off = htons(IP_DF);
3186 sqp->ud_header.ip4.ttl = ah->av.eth.hop_limit;
3187
3188 memcpy(&sqp->ud_header.ip4.saddr,
3189 sgid.raw + 12, 4);
3190 memcpy(&sqp->ud_header.ip4.daddr, ah->av.ib.dgid + 12, 4);
3191 sqp->ud_header.ip4.check = ib_ud_ip4_csum(&sqp->ud_header);
3192 }
3193
3194 if (is_udp) {
3195 sqp->ud_header.udp.dport = htons(ROCE_V2_UDP_DPORT);
3196 sqp->ud_header.udp.sport = htons(MLX4_ROCEV2_QP1_SPORT);
3197 sqp->ud_header.udp.csum = 0;
3198 }
3199
3200 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
3201
3202 if (!is_eth) {
3203 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
3204 (sqp->ud_header.lrh.destination_lid ==
3205 IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
3206 (sqp->ud_header.lrh.service_level << 8));
3207 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000))
3208 mlx->flags |= cpu_to_be32(0x1); /* force loopback */
3209 mlx->rlid = sqp->ud_header.lrh.destination_lid;
3210 }
3211
3212 switch (wr->wr.opcode) {
3213 case IB_WR_SEND:
3214 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
3215 sqp->ud_header.immediate_present = 0;
3216 break;
3217 case IB_WR_SEND_WITH_IMM:
3218 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
3219 sqp->ud_header.immediate_present = 1;
3220 sqp->ud_header.immediate_data = wr->wr.ex.imm_data;
3221 break;
3222 default:
3223 return -EINVAL;
3224 }
3225
3226 if (is_eth) {
3227 struct in6_addr in6;
3228 u16 ether_type;
3229 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13;
3230
3231 ether_type = (!is_udp) ? ETH_P_IBOE:
3232 (ip_version == 4 ? ETH_P_IP : ETH_P_IPV6);
3233
3234 mlx->sched_prio = cpu_to_be16(pcp);
3235
3236 ether_addr_copy(sqp->ud_header.eth.smac_h, ah->av.eth.s_mac);
3237 memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6);
3238 memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2);
3239 memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4);
3240 memcpy(&in6, sgid.raw, sizeof(in6));
3241
3242
3243 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6))
3244 mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
3245 if (!is_vlan) {
3246 sqp->ud_header.eth.type = cpu_to_be16(ether_type);
3247 } else {
3248 sqp->ud_header.vlan.type = cpu_to_be16(ether_type);
3249 sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp);
3250 }
3251 } else {
3252 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 :
3253 sl_to_vl(to_mdev(ib_dev),
3254 sqp->ud_header.lrh.service_level,
3255 sqp->qp.port);
3256 if (sqp->qp.ibqp.qp_num && sqp->ud_header.lrh.virtual_lane == 15)
3257 return -EINVAL;
3258 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
3259 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
3260 }
3261 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
3262 if (!sqp->qp.ibqp.qp_num)
3263 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey);
3264 else
3265 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->pkey_index, &pkey);
3266 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
3267 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
3268 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
3269 sqp->ud_header.deth.qkey = cpu_to_be32(wr->remote_qkey & 0x80000000 ?
3270 sqp->qkey : wr->remote_qkey);
3271 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
3272
3273 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
3274
3275 if (0) {
3276 pr_err("built UD header of size %d:\n", header_size);
3277 for (i = 0; i < header_size / 4; ++i) {
3278 if (i % 8 == 0)
3279 pr_err(" [%02x] ", i * 4);
3280 pr_cont(" %08x",
3281 be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
3282 if ((i + 1) % 8 == 0)
3283 pr_cont("\n");
3284 }
3285 pr_err("\n");
3286 }
3287
3288 /*
3289 * Inline data segments may not cross a 64 byte boundary. If
3290 * our UD header is bigger than the space available up to the
3291 * next 64 byte boundary in the WQE, use two inline data
3292 * segments to hold the UD header.
3293 */
3294 spc = MLX4_INLINE_ALIGN -
3295 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
3296 if (header_size <= spc) {
3297 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
3298 memcpy(inl + 1, sqp->header_buf, header_size);
3299 i = 1;
3300 } else {
3301 inl->byte_count = cpu_to_be32(1 << 31 | spc);
3302 memcpy(inl + 1, sqp->header_buf, spc);
3303
3304 inl = (void *) (inl + 1) + spc;
3305 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
3306 /*
3307 * Need a barrier here to make sure all the data is
3308 * visible before the byte_count field is set.
3309 * Otherwise the HCA prefetcher could grab the 64-byte
3310 * chunk with this inline segment and get a valid (!=
3311 * 0xffffffff) byte count but stale data, and end up
3312 * generating a packet with bad headers.
3313 *
3314 * The first inline segment's byte_count field doesn't
3315 * need a barrier, because it comes after a
3316 * control/MLX segment and therefore is at an offset
3317 * of 16 mod 64.
3318 */
3319 wmb();
3320 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
3321 i = 2;
3322 }
3323
3324 *mlx_seg_len =
3325 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
3326 return 0;
3327 }
3328
3329 static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
3330 {
3331 unsigned cur;
3332 struct mlx4_ib_cq *cq;
3333
3334 cur = wq->head - wq->tail;
3335 if (likely(cur + nreq < wq->max_post))
3336 return 0;
3337
3338 cq = to_mcq(ib_cq);
3339 spin_lock(&cq->lock);
3340 cur = wq->head - wq->tail;
3341 spin_unlock(&cq->lock);
3342
3343 return cur + nreq >= wq->max_post;
3344 }
3345
3346 static __be32 convert_access(int acc)
3347 {
3348 return (acc & IB_ACCESS_REMOTE_ATOMIC ?
3349 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC) : 0) |
3350 (acc & IB_ACCESS_REMOTE_WRITE ?
3351 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) |
3352 (acc & IB_ACCESS_REMOTE_READ ?
3353 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ) : 0) |
3354 (acc & IB_ACCESS_LOCAL_WRITE ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE) : 0) |
3355 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ);
3356 }
3357
3358 static void set_reg_seg(struct mlx4_wqe_fmr_seg *fseg,
3359 struct ib_reg_wr *wr)
3360 {
3361 struct mlx4_ib_mr *mr = to_mmr(wr->mr);
3362
3363 fseg->flags = convert_access(wr->access);
3364 fseg->mem_key = cpu_to_be32(wr->key);
3365 fseg->buf_list = cpu_to_be64(mr->page_map);
3366 fseg->start_addr = cpu_to_be64(mr->ibmr.iova);
3367 fseg->reg_len = cpu_to_be64(mr->ibmr.length);
3368 fseg->offset = 0; /* XXX -- is this just for ZBVA? */
3369 fseg->page_size = cpu_to_be32(ilog2(mr->ibmr.page_size));
3370 fseg->reserved[0] = 0;
3371 fseg->reserved[1] = 0;
3372 }
3373
3374 static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey)
3375 {
3376 memset(iseg, 0, sizeof(*iseg));
3377 iseg->mem_key = cpu_to_be32(rkey);
3378 }
3379
3380 static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
3381 u64 remote_addr, u32 rkey)
3382 {
3383 rseg->raddr = cpu_to_be64(remote_addr);
3384 rseg->rkey = cpu_to_be32(rkey);
3385 rseg->reserved = 0;
3386 }
3387
3388 static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg,
3389 struct ib_atomic_wr *wr)
3390 {
3391 if (wr->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
3392 aseg->swap_add = cpu_to_be64(wr->swap);
3393 aseg->compare = cpu_to_be64(wr->compare_add);
3394 } else if (wr->wr.opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) {
3395 aseg->swap_add = cpu_to_be64(wr->compare_add);
3396 aseg->compare = cpu_to_be64(wr->compare_add_mask);
3397 } else {
3398 aseg->swap_add = cpu_to_be64(wr->compare_add);
3399 aseg->compare = 0;
3400 }
3401
3402 }
3403
3404 static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg,
3405 struct ib_atomic_wr *wr)
3406 {
3407 aseg->swap_add = cpu_to_be64(wr->swap);
3408 aseg->swap_add_mask = cpu_to_be64(wr->swap_mask);
3409 aseg->compare = cpu_to_be64(wr->compare_add);
3410 aseg->compare_mask = cpu_to_be64(wr->compare_add_mask);
3411 }
3412
3413 static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
3414 struct ib_ud_wr *wr)
3415 {
3416 memcpy(dseg->av, &to_mah(wr->ah)->av, sizeof (struct mlx4_av));
3417 dseg->dqpn = cpu_to_be32(wr->remote_qpn);
3418 dseg->qkey = cpu_to_be32(wr->remote_qkey);
3419 dseg->vlan = to_mah(wr->ah)->av.eth.vlan;
3420 memcpy(dseg->mac, to_mah(wr->ah)->av.eth.mac, 6);
3421 }
3422
3423 static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev,
3424 struct mlx4_wqe_datagram_seg *dseg,
3425 struct ib_ud_wr *wr,
3426 enum mlx4_ib_qp_type qpt)
3427 {
3428 union mlx4_ext_av *av = &to_mah(wr->ah)->av;
3429 struct mlx4_av sqp_av = {0};
3430 int port = *((u8 *) &av->ib.port_pd) & 0x3;
3431
3432 /* force loopback */
3433 sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000);
3434 sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */
3435 sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel &
3436 cpu_to_be32(0xf0000000);
3437
3438 memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av));
3439 if (qpt == MLX4_IB_QPT_PROXY_GSI)
3440 dseg->dqpn = cpu_to_be32(dev->dev->caps.spec_qps[port - 1].qp1_tunnel);
3441 else
3442 dseg->dqpn = cpu_to_be32(dev->dev->caps.spec_qps[port - 1].qp0_tunnel);
3443 /* Use QKEY from the QP context, which is set by master */
3444 dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY);
3445 }
3446
3447 static void build_tunnel_header(struct ib_ud_wr *wr, void *wqe, unsigned *mlx_seg_len)
3448 {
3449 struct mlx4_wqe_inline_seg *inl = wqe;
3450 struct mlx4_ib_tunnel_header hdr;
3451 struct mlx4_ib_ah *ah = to_mah(wr->ah);
3452 int spc;
3453 int i;
3454
3455 memcpy(&hdr.av, &ah->av, sizeof hdr.av);
3456 hdr.remote_qpn = cpu_to_be32(wr->remote_qpn);
3457 hdr.pkey_index = cpu_to_be16(wr->pkey_index);
3458 hdr.qkey = cpu_to_be32(wr->remote_qkey);
3459 memcpy(hdr.mac, ah->av.eth.mac, 6);
3460 hdr.vlan = ah->av.eth.vlan;
3461
3462 spc = MLX4_INLINE_ALIGN -
3463 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
3464 if (sizeof (hdr) <= spc) {
3465 memcpy(inl + 1, &hdr, sizeof (hdr));
3466 wmb();
3467 inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr));
3468 i = 1;
3469 } else {
3470 memcpy(inl + 1, &hdr, spc);
3471 wmb();
3472 inl->byte_count = cpu_to_be32(1 << 31 | spc);
3473
3474 inl = (void *) (inl + 1) + spc;
3475 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc);
3476 wmb();
3477 inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc));
3478 i = 2;
3479 }
3480
3481 *mlx_seg_len =
3482 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16);
3483 }
3484
3485 static void set_mlx_icrc_seg(void *dseg)
3486 {
3487 u32 *t = dseg;
3488 struct mlx4_wqe_inline_seg *iseg = dseg;
3489
3490 t[1] = 0;
3491
3492 /*
3493 * Need a barrier here before writing the byte_count field to
3494 * make sure that all the data is visible before the
3495 * byte_count field is set. Otherwise, if the segment begins
3496 * a new cacheline, the HCA prefetcher could grab the 64-byte
3497 * chunk and get a valid (!= * 0xffffffff) byte count but
3498 * stale data, and end up sending the wrong data.
3499 */
3500 wmb();
3501
3502 iseg->byte_count = cpu_to_be32((1 << 31) | 4);
3503 }
3504
3505 static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
3506 {
3507 dseg->lkey = cpu_to_be32(sg->lkey);
3508 dseg->addr = cpu_to_be64(sg->addr);
3509
3510 /*
3511 * Need a barrier here before writing the byte_count field to
3512 * make sure that all the data is visible before the
3513 * byte_count field is set. Otherwise, if the segment begins
3514 * a new cacheline, the HCA prefetcher could grab the 64-byte
3515 * chunk and get a valid (!= * 0xffffffff) byte count but
3516 * stale data, and end up sending the wrong data.
3517 */
3518 wmb();
3519
3520 dseg->byte_count = cpu_to_be32(sg->length);
3521 }
3522
3523 static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
3524 {
3525 dseg->byte_count = cpu_to_be32(sg->length);
3526 dseg->lkey = cpu_to_be32(sg->lkey);
3527 dseg->addr = cpu_to_be64(sg->addr);
3528 }
3529
3530 static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, struct ib_ud_wr *wr,
3531 struct mlx4_ib_qp *qp, unsigned *lso_seg_len,
3532 __be32 *lso_hdr_sz, __be32 *blh)
3533 {
3534 unsigned halign = ALIGN(sizeof *wqe + wr->hlen, 16);
3535
3536 if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE))
3537 *blh = cpu_to_be32(1 << 6);
3538
3539 if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
3540 wr->wr.num_sge > qp->sq.max_gs - (halign >> 4)))
3541 return -EINVAL;
3542
3543 memcpy(wqe->header, wr->header, wr->hlen);
3544
3545 *lso_hdr_sz = cpu_to_be32(wr->mss << 16 | wr->hlen);
3546 *lso_seg_len = halign;
3547 return 0;
3548 }
3549
3550 static __be32 send_ieth(struct ib_send_wr *wr)
3551 {
3552 switch (wr->opcode) {
3553 case IB_WR_SEND_WITH_IMM:
3554 case IB_WR_RDMA_WRITE_WITH_IMM:
3555 return wr->ex.imm_data;
3556
3557 case IB_WR_SEND_WITH_INV:
3558 return cpu_to_be32(wr->ex.invalidate_rkey);
3559
3560 default:
3561 return 0;
3562 }
3563 }
3564
3565 static void add_zero_len_inline(void *wqe)
3566 {
3567 struct mlx4_wqe_inline_seg *inl = wqe;
3568 memset(wqe, 0, 16);
3569 inl->byte_count = cpu_to_be32(1 << 31);
3570 }
3571
3572 int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
3573 struct ib_send_wr **bad_wr)
3574 {
3575 struct mlx4_ib_qp *qp = to_mqp(ibqp);
3576 void *wqe;
3577 struct mlx4_wqe_ctrl_seg *ctrl;
3578 struct mlx4_wqe_data_seg *dseg;
3579 unsigned long flags;
3580 int nreq;
3581 int err = 0;
3582 unsigned ind;
3583 int uninitialized_var(stamp);
3584 int uninitialized_var(size);
3585 unsigned uninitialized_var(seglen);
3586 __be32 dummy;
3587 __be32 *lso_wqe;
3588 __be32 uninitialized_var(lso_hdr_sz);
3589 __be32 blh;
3590 int i;
3591 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
3592
3593 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
3594 struct mlx4_ib_sqp *sqp = to_msqp(qp);
3595
3596 if (sqp->roce_v2_gsi) {
3597 struct mlx4_ib_ah *ah = to_mah(ud_wr(wr)->ah);
3598 enum ib_gid_type gid_type;
3599 union ib_gid gid;
3600
3601 if (!fill_gid_by_hw_index(mdev, sqp->qp.port,
3602 ah->av.ib.gid_index,
3603 &gid, &gid_type))
3604 qp = (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) ?
3605 to_mqp(sqp->roce_v2_gsi) : qp;
3606 else
3607 pr_err("Failed to get gid at index %d. RoCEv2 will not work properly\n",
3608 ah->av.ib.gid_index);
3609 }
3610 }
3611
3612 spin_lock_irqsave(&qp->sq.lock, flags);
3613 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
3614 err = -EIO;
3615 *bad_wr = wr;
3616 nreq = 0;
3617 goto out;
3618 }
3619
3620 ind = qp->sq_next_wqe;
3621
3622 for (nreq = 0; wr; ++nreq, wr = wr->next) {
3623 lso_wqe = &dummy;
3624 blh = 0;
3625
3626 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
3627 err = -ENOMEM;
3628 *bad_wr = wr;
3629 goto out;
3630 }
3631
3632 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
3633 err = -EINVAL;
3634 *bad_wr = wr;
3635 goto out;
3636 }
3637
3638 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
3639 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
3640
3641 ctrl->srcrb_flags =
3642 (wr->send_flags & IB_SEND_SIGNALED ?
3643 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
3644 (wr->send_flags & IB_SEND_SOLICITED ?
3645 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
3646 ((wr->send_flags & IB_SEND_IP_CSUM) ?
3647 cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
3648 MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
3649 qp->sq_signal_bits;
3650
3651 ctrl->imm = send_ieth(wr);
3652
3653 wqe += sizeof *ctrl;
3654 size = sizeof *ctrl / 16;
3655
3656 switch (qp->mlx4_ib_qp_type) {
3657 case MLX4_IB_QPT_RC:
3658 case MLX4_IB_QPT_UC:
3659 switch (wr->opcode) {
3660 case IB_WR_ATOMIC_CMP_AND_SWP:
3661 case IB_WR_ATOMIC_FETCH_AND_ADD:
3662 case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
3663 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
3664 atomic_wr(wr)->rkey);
3665 wqe += sizeof (struct mlx4_wqe_raddr_seg);
3666
3667 set_atomic_seg(wqe, atomic_wr(wr));
3668 wqe += sizeof (struct mlx4_wqe_atomic_seg);
3669
3670 size += (sizeof (struct mlx4_wqe_raddr_seg) +
3671 sizeof (struct mlx4_wqe_atomic_seg)) / 16;
3672
3673 break;
3674
3675 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
3676 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
3677 atomic_wr(wr)->rkey);
3678 wqe += sizeof (struct mlx4_wqe_raddr_seg);
3679
3680 set_masked_atomic_seg(wqe, atomic_wr(wr));
3681 wqe += sizeof (struct mlx4_wqe_masked_atomic_seg);
3682
3683 size += (sizeof (struct mlx4_wqe_raddr_seg) +
3684 sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16;
3685
3686 break;
3687
3688 case IB_WR_RDMA_READ:
3689 case IB_WR_RDMA_WRITE:
3690 case IB_WR_RDMA_WRITE_WITH_IMM:
3691 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
3692 rdma_wr(wr)->rkey);
3693 wqe += sizeof (struct mlx4_wqe_raddr_seg);
3694 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
3695 break;
3696
3697 case IB_WR_LOCAL_INV:
3698 ctrl->srcrb_flags |=
3699 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
3700 set_local_inv_seg(wqe, wr->ex.invalidate_rkey);
3701 wqe += sizeof (struct mlx4_wqe_local_inval_seg);
3702 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16;
3703 break;
3704
3705 case IB_WR_REG_MR:
3706 ctrl->srcrb_flags |=
3707 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
3708 set_reg_seg(wqe, reg_wr(wr));
3709 wqe += sizeof(struct mlx4_wqe_fmr_seg);
3710 size += sizeof(struct mlx4_wqe_fmr_seg) / 16;
3711 break;
3712
3713 default:
3714 /* No extra segments required for sends */
3715 break;
3716 }
3717 break;
3718
3719 case MLX4_IB_QPT_TUN_SMI_OWNER:
3720 err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr),
3721 ctrl, &seglen);
3722 if (unlikely(err)) {
3723 *bad_wr = wr;
3724 goto out;
3725 }
3726 wqe += seglen;
3727 size += seglen / 16;
3728 break;
3729 case MLX4_IB_QPT_TUN_SMI:
3730 case MLX4_IB_QPT_TUN_GSI:
3731 /* this is a UD qp used in MAD responses to slaves. */
3732 set_datagram_seg(wqe, ud_wr(wr));
3733 /* set the forced-loopback bit in the data seg av */
3734 *(__be32 *) wqe |= cpu_to_be32(0x80000000);
3735 wqe += sizeof (struct mlx4_wqe_datagram_seg);
3736 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
3737 break;
3738 case MLX4_IB_QPT_UD:
3739 set_datagram_seg(wqe, ud_wr(wr));
3740 wqe += sizeof (struct mlx4_wqe_datagram_seg);
3741 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
3742
3743 if (wr->opcode == IB_WR_LSO) {
3744 err = build_lso_seg(wqe, ud_wr(wr), qp, &seglen,
3745 &lso_hdr_sz, &blh);
3746 if (unlikely(err)) {
3747 *bad_wr = wr;
3748 goto out;
3749 }
3750 lso_wqe = (__be32 *) wqe;
3751 wqe += seglen;
3752 size += seglen / 16;
3753 }
3754 break;
3755
3756 case MLX4_IB_QPT_PROXY_SMI_OWNER:
3757 err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr),
3758 ctrl, &seglen);
3759 if (unlikely(err)) {
3760 *bad_wr = wr;
3761 goto out;
3762 }
3763 wqe += seglen;
3764 size += seglen / 16;
3765 /* to start tunnel header on a cache-line boundary */
3766 add_zero_len_inline(wqe);
3767 wqe += 16;
3768 size++;
3769 build_tunnel_header(ud_wr(wr), wqe, &seglen);
3770 wqe += seglen;
3771 size += seglen / 16;
3772 break;
3773 case MLX4_IB_QPT_PROXY_SMI:
3774 case MLX4_IB_QPT_PROXY_GSI:
3775 /* If we are tunneling special qps, this is a UD qp.
3776 * In this case we first add a UD segment targeting
3777 * the tunnel qp, and then add a header with address
3778 * information */
3779 set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe,
3780 ud_wr(wr),
3781 qp->mlx4_ib_qp_type);
3782 wqe += sizeof (struct mlx4_wqe_datagram_seg);
3783 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
3784 build_tunnel_header(ud_wr(wr), wqe, &seglen);
3785 wqe += seglen;
3786 size += seglen / 16;
3787 break;
3788
3789 case MLX4_IB_QPT_SMI:
3790 case MLX4_IB_QPT_GSI:
3791 err = build_mlx_header(to_msqp(qp), ud_wr(wr), ctrl,
3792 &seglen);
3793 if (unlikely(err)) {
3794 *bad_wr = wr;
3795 goto out;
3796 }
3797 wqe += seglen;
3798 size += seglen / 16;
3799 break;
3800
3801 default:
3802 break;
3803 }
3804
3805 /*
3806 * Write data segments in reverse order, so as to
3807 * overwrite cacheline stamp last within each
3808 * cacheline. This avoids issues with WQE
3809 * prefetching.
3810 */
3811
3812 dseg = wqe;
3813 dseg += wr->num_sge - 1;
3814 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
3815
3816 /* Add one more inline data segment for ICRC for MLX sends */
3817 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
3818 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI ||
3819 qp->mlx4_ib_qp_type &
3820 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) {
3821 set_mlx_icrc_seg(dseg + 1);
3822 size += sizeof (struct mlx4_wqe_data_seg) / 16;
3823 }
3824
3825 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
3826 set_data_seg(dseg, wr->sg_list + i);
3827
3828 /*
3829 * Possibly overwrite stamping in cacheline with LSO
3830 * segment only after making sure all data segments
3831 * are written.
3832 */
3833 wmb();
3834 *lso_wqe = lso_hdr_sz;
3835
3836 ctrl->qpn_vlan.fence_size = (wr->send_flags & IB_SEND_FENCE ?
3837 MLX4_WQE_CTRL_FENCE : 0) | size;
3838
3839 /*
3840 * Make sure descriptor is fully written before
3841 * setting ownership bit (because HW can start
3842 * executing as soon as we do).
3843 */
3844 wmb();
3845
3846 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
3847 *bad_wr = wr;
3848 err = -EINVAL;
3849 goto out;
3850 }
3851
3852 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
3853 (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh;
3854
3855 stamp = ind + qp->sq_spare_wqes;
3856 ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift);
3857
3858 /*
3859 * We can improve latency by not stamping the last
3860 * send queue WQE until after ringing the doorbell, so
3861 * only stamp here if there are still more WQEs to post.
3862 *
3863 * Same optimization applies to padding with NOP wqe
3864 * in case of WQE shrinking (used to prevent wrap-around
3865 * in the middle of WR).
3866 */
3867 if (wr->next) {
3868 stamp_send_wqe(qp, stamp, size * 16);
3869 ind = pad_wraparound(qp, ind);
3870 }
3871 }
3872
3873 out:
3874 if (likely(nreq)) {
3875 qp->sq.head += nreq;
3876
3877 /*
3878 * Make sure that descriptors are written before
3879 * doorbell record.
3880 */
3881 wmb();
3882
3883 writel(qp->doorbell_qpn,
3884 to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
3885
3886 /*
3887 * Make sure doorbells don't leak out of SQ spinlock
3888 * and reach the HCA out of order.
3889 */
3890 mmiowb();
3891
3892 stamp_send_wqe(qp, stamp, size * 16);
3893
3894 ind = pad_wraparound(qp, ind);
3895 qp->sq_next_wqe = ind;
3896 }
3897
3898 spin_unlock_irqrestore(&qp->sq.lock, flags);
3899
3900 return err;
3901 }
3902
3903 int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
3904 struct ib_recv_wr **bad_wr)
3905 {
3906 struct mlx4_ib_qp *qp = to_mqp(ibqp);
3907 struct mlx4_wqe_data_seg *scat;
3908 unsigned long flags;
3909 int err = 0;
3910 int nreq;
3911 int ind;
3912 int max_gs;
3913 int i;
3914 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
3915
3916 max_gs = qp->rq.max_gs;
3917 spin_lock_irqsave(&qp->rq.lock, flags);
3918
3919 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
3920 err = -EIO;
3921 *bad_wr = wr;
3922 nreq = 0;
3923 goto out;
3924 }
3925
3926 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
3927
3928 for (nreq = 0; wr; ++nreq, wr = wr->next) {
3929 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
3930 err = -ENOMEM;
3931 *bad_wr = wr;
3932 goto out;
3933 }
3934
3935 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
3936 err = -EINVAL;
3937 *bad_wr = wr;
3938 goto out;
3939 }
3940
3941 scat = get_recv_wqe(qp, ind);
3942
3943 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
3944 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
3945 ib_dma_sync_single_for_device(ibqp->device,
3946 qp->sqp_proxy_rcv[ind].map,
3947 sizeof (struct mlx4_ib_proxy_sqp_hdr),
3948 DMA_FROM_DEVICE);
3949 scat->byte_count =
3950 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr));
3951 /* use dma lkey from upper layer entry */
3952 scat->lkey = cpu_to_be32(wr->sg_list->lkey);
3953 scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map);
3954 scat++;
3955 max_gs--;
3956 }
3957
3958 for (i = 0; i < wr->num_sge; ++i)
3959 __set_data_seg(scat + i, wr->sg_list + i);
3960
3961 if (i < max_gs) {
3962 scat[i].byte_count = 0;
3963 scat[i].lkey = cpu_to_be32(MLX4_INVALID_LKEY);
3964 scat[i].addr = 0;
3965 }
3966
3967 qp->rq.wrid[ind] = wr->wr_id;
3968
3969 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
3970 }
3971
3972 out:
3973 if (likely(nreq)) {
3974 qp->rq.head += nreq;
3975
3976 /*
3977 * Make sure that descriptors are written before
3978 * doorbell record.
3979 */
3980 wmb();
3981
3982 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
3983 }
3984
3985 spin_unlock_irqrestore(&qp->rq.lock, flags);
3986
3987 return err;
3988 }
3989
3990 static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
3991 {
3992 switch (mlx4_state) {
3993 case MLX4_QP_STATE_RST: return IB_QPS_RESET;
3994 case MLX4_QP_STATE_INIT: return IB_QPS_INIT;
3995 case MLX4_QP_STATE_RTR: return IB_QPS_RTR;
3996 case MLX4_QP_STATE_RTS: return IB_QPS_RTS;
3997 case MLX4_QP_STATE_SQ_DRAINING:
3998 case MLX4_QP_STATE_SQD: return IB_QPS_SQD;
3999 case MLX4_QP_STATE_SQER: return IB_QPS_SQE;
4000 case MLX4_QP_STATE_ERR: return IB_QPS_ERR;
4001 default: return -1;
4002 }
4003 }
4004
4005 static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
4006 {
4007 switch (mlx4_mig_state) {
4008 case MLX4_QP_PM_ARMED: return IB_MIG_ARMED;
4009 case MLX4_QP_PM_REARM: return IB_MIG_REARM;
4010 case MLX4_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
4011 default: return -1;
4012 }
4013 }
4014
4015 static int to_ib_qp_access_flags(int mlx4_flags)
4016 {
4017 int ib_flags = 0;
4018
4019 if (mlx4_flags & MLX4_QP_BIT_RRE)
4020 ib_flags |= IB_ACCESS_REMOTE_READ;
4021 if (mlx4_flags & MLX4_QP_BIT_RWE)
4022 ib_flags |= IB_ACCESS_REMOTE_WRITE;
4023 if (mlx4_flags & MLX4_QP_BIT_RAE)
4024 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
4025
4026 return ib_flags;
4027 }
4028
4029 static void to_rdma_ah_attr(struct mlx4_ib_dev *ibdev,
4030 struct rdma_ah_attr *ah_attr,
4031 struct mlx4_qp_path *path)
4032 {
4033 struct mlx4_dev *dev = ibdev->dev;
4034 u8 port_num = path->sched_queue & 0x40 ? 2 : 1;
4035
4036 memset(ah_attr, 0, sizeof(*ah_attr));
4037 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, port_num);
4038 if (port_num == 0 || port_num > dev->caps.num_ports)
4039 return;
4040
4041 if (ah_attr->type == RDMA_AH_ATTR_TYPE_ROCE)
4042 rdma_ah_set_sl(ah_attr, ((path->sched_queue >> 3) & 0x7) |
4043 ((path->sched_queue & 4) << 1));
4044 else
4045 rdma_ah_set_sl(ah_attr, (path->sched_queue >> 2) & 0xf);
4046 rdma_ah_set_port_num(ah_attr, port_num);
4047
4048 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
4049 rdma_ah_set_path_bits(ah_attr, path->grh_mylmc & 0x7f);
4050 rdma_ah_set_static_rate(ah_attr,
4051 path->static_rate ? path->static_rate - 5 : 0);
4052 if (path->grh_mylmc & (1 << 7)) {
4053 rdma_ah_set_grh(ah_attr, NULL,
4054 be32_to_cpu(path->tclass_flowlabel) & 0xfffff,
4055 path->mgid_index,
4056 path->hop_limit,
4057 (be32_to_cpu(path->tclass_flowlabel)
4058 >> 20) & 0xff);
4059 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
4060 }
4061 }
4062
4063 int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
4064 struct ib_qp_init_attr *qp_init_attr)
4065 {
4066 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
4067 struct mlx4_ib_qp *qp = to_mqp(ibqp);
4068 struct mlx4_qp_context context;
4069 int mlx4_state;
4070 int err = 0;
4071
4072 if (ibqp->rwq_ind_tbl)
4073 return -EOPNOTSUPP;
4074
4075 mutex_lock(&qp->mutex);
4076
4077 if (qp->state == IB_QPS_RESET) {
4078 qp_attr->qp_state = IB_QPS_RESET;
4079 goto done;
4080 }
4081
4082 err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
4083 if (err) {
4084 err = -EINVAL;
4085 goto out;
4086 }
4087
4088 mlx4_state = be32_to_cpu(context.flags) >> 28;
4089
4090 qp->state = to_ib_qp_state(mlx4_state);
4091 qp_attr->qp_state = qp->state;
4092 qp_attr->path_mtu = context.mtu_msgmax >> 5;
4093 qp_attr->path_mig_state =
4094 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
4095 qp_attr->qkey = be32_to_cpu(context.qkey);
4096 qp_attr->rq_psn = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
4097 qp_attr->sq_psn = be32_to_cpu(context.next_send_psn) & 0xffffff;
4098 qp_attr->dest_qp_num = be32_to_cpu(context.remote_qpn) & 0xffffff;
4099 qp_attr->qp_access_flags =
4100 to_ib_qp_access_flags(be32_to_cpu(context.params2));
4101
4102 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
4103 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path);
4104 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path);
4105 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
4106 qp_attr->alt_port_num =
4107 rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
4108 }
4109
4110 qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
4111 if (qp_attr->qp_state == IB_QPS_INIT)
4112 qp_attr->port_num = qp->port;
4113 else
4114 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
4115
4116 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
4117 qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
4118
4119 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
4120
4121 qp_attr->max_dest_rd_atomic =
4122 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
4123 qp_attr->min_rnr_timer =
4124 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
4125 qp_attr->timeout = context.pri_path.ackto >> 3;
4126 qp_attr->retry_cnt = (be32_to_cpu(context.params1) >> 16) & 0x7;
4127 qp_attr->rnr_retry = (be32_to_cpu(context.params1) >> 13) & 0x7;
4128 qp_attr->alt_timeout = context.alt_path.ackto >> 3;
4129
4130 done:
4131 qp_attr->cur_qp_state = qp_attr->qp_state;
4132 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
4133 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
4134
4135 if (!ibqp->uobject) {
4136 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt;
4137 qp_attr->cap.max_send_sge = qp->sq.max_gs;
4138 } else {
4139 qp_attr->cap.max_send_wr = 0;
4140 qp_attr->cap.max_send_sge = 0;
4141 }
4142
4143 /*
4144 * We don't support inline sends for kernel QPs (yet), and we
4145 * don't know what userspace's value should be.
4146 */
4147 qp_attr->cap.max_inline_data = 0;
4148
4149 qp_init_attr->cap = qp_attr->cap;
4150
4151 qp_init_attr->create_flags = 0;
4152 if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)
4153 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
4154
4155 if (qp->flags & MLX4_IB_QP_LSO)
4156 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO;
4157
4158 if (qp->flags & MLX4_IB_QP_NETIF)
4159 qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP;
4160
4161 qp_init_attr->sq_sig_type =
4162 qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ?
4163 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
4164
4165 out:
4166 mutex_unlock(&qp->mutex);
4167 return err;
4168 }
4169
4170 struct ib_wq *mlx4_ib_create_wq(struct ib_pd *pd,
4171 struct ib_wq_init_attr *init_attr,
4172 struct ib_udata *udata)
4173 {
4174 struct mlx4_ib_dev *dev;
4175 struct ib_qp_init_attr ib_qp_init_attr;
4176 struct mlx4_ib_qp *qp;
4177 struct mlx4_ib_create_wq ucmd;
4178 int err, required_cmd_sz;
4179
4180 if (!(udata && pd->uobject))
4181 return ERR_PTR(-EINVAL);
4182
4183 required_cmd_sz = offsetof(typeof(ucmd), comp_mask) +
4184 sizeof(ucmd.comp_mask);
4185 if (udata->inlen < required_cmd_sz) {
4186 pr_debug("invalid inlen\n");
4187 return ERR_PTR(-EINVAL);
4188 }
4189
4190 if (udata->inlen > sizeof(ucmd) &&
4191 !ib_is_udata_cleared(udata, sizeof(ucmd),
4192 udata->inlen - sizeof(ucmd))) {
4193 pr_debug("inlen is not supported\n");
4194 return ERR_PTR(-EOPNOTSUPP);
4195 }
4196
4197 if (udata->outlen)
4198 return ERR_PTR(-EOPNOTSUPP);
4199
4200 dev = to_mdev(pd->device);
4201
4202 if (init_attr->wq_type != IB_WQT_RQ) {
4203 pr_debug("unsupported wq type %d\n", init_attr->wq_type);
4204 return ERR_PTR(-EOPNOTSUPP);
4205 }
4206
4207 if (init_attr->create_flags) {
4208 pr_debug("unsupported create_flags %u\n",
4209 init_attr->create_flags);
4210 return ERR_PTR(-EOPNOTSUPP);
4211 }
4212
4213 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
4214 if (!qp)
4215 return ERR_PTR(-ENOMEM);
4216
4217 qp->pri.vid = 0xFFFF;
4218 qp->alt.vid = 0xFFFF;
4219
4220 memset(&ib_qp_init_attr, 0, sizeof(ib_qp_init_attr));
4221 ib_qp_init_attr.qp_context = init_attr->wq_context;
4222 ib_qp_init_attr.qp_type = IB_QPT_RAW_PACKET;
4223 ib_qp_init_attr.cap.max_recv_wr = init_attr->max_wr;
4224 ib_qp_init_attr.cap.max_recv_sge = init_attr->max_sge;
4225 ib_qp_init_attr.recv_cq = init_attr->cq;
4226 ib_qp_init_attr.send_cq = ib_qp_init_attr.recv_cq; /* Dummy CQ */
4227
4228 err = create_qp_common(dev, pd, MLX4_IB_RWQ_SRC, &ib_qp_init_attr,
4229 udata, 0, &qp);
4230 if (err) {
4231 kfree(qp);
4232 return ERR_PTR(err);
4233 }
4234
4235 qp->ibwq.event_handler = init_attr->event_handler;
4236 qp->ibwq.wq_num = qp->mqp.qpn;
4237 qp->ibwq.state = IB_WQS_RESET;
4238
4239 return &qp->ibwq;
4240 }
4241
4242 static int ib_wq2qp_state(enum ib_wq_state state)
4243 {
4244 switch (state) {
4245 case IB_WQS_RESET:
4246 return IB_QPS_RESET;
4247 case IB_WQS_RDY:
4248 return IB_QPS_RTR;
4249 default:
4250 return IB_QPS_ERR;
4251 }
4252 }
4253
4254 static int _mlx4_ib_modify_wq(struct ib_wq *ibwq, enum ib_wq_state new_state)
4255 {
4256 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq);
4257 enum ib_qp_state qp_cur_state;
4258 enum ib_qp_state qp_new_state;
4259 int attr_mask;
4260 int err;
4261
4262 /* ib_qp.state represents the WQ HW state while ib_wq.state represents
4263 * the WQ logic state.
4264 */
4265 qp_cur_state = qp->state;
4266 qp_new_state = ib_wq2qp_state(new_state);
4267
4268 if (ib_wq2qp_state(new_state) == qp_cur_state)
4269 return 0;
4270
4271 if (new_state == IB_WQS_RDY) {
4272 struct ib_qp_attr attr = {};
4273
4274 attr.port_num = qp->port;
4275 attr_mask = IB_QP_PORT;
4276
4277 err = __mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, &attr,
4278 attr_mask, IB_QPS_RESET, IB_QPS_INIT);
4279 if (err) {
4280 pr_debug("WQN=0x%06x failed to apply RST->INIT on the HW QP\n",
4281 ibwq->wq_num);
4282 return err;
4283 }
4284
4285 qp_cur_state = IB_QPS_INIT;
4286 }
4287
4288 attr_mask = 0;
4289 err = __mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, NULL, attr_mask,
4290 qp_cur_state, qp_new_state);
4291
4292 if (err && (qp_cur_state == IB_QPS_INIT)) {
4293 qp_new_state = IB_QPS_RESET;
4294 if (__mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, NULL,
4295 attr_mask, IB_QPS_INIT, IB_QPS_RESET)) {
4296 pr_warn("WQN=0x%06x failed with reverting HW's resources failure\n",
4297 ibwq->wq_num);
4298 qp_new_state = IB_QPS_INIT;
4299 }
4300 }
4301
4302 qp->state = qp_new_state;
4303
4304 return err;
4305 }
4306
4307 int mlx4_ib_modify_wq(struct ib_wq *ibwq, struct ib_wq_attr *wq_attr,
4308 u32 wq_attr_mask, struct ib_udata *udata)
4309 {
4310 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq);
4311 struct mlx4_ib_modify_wq ucmd = {};
4312 size_t required_cmd_sz;
4313 enum ib_wq_state cur_state, new_state;
4314 int err = 0;
4315
4316 required_cmd_sz = offsetof(typeof(ucmd), reserved) +
4317 sizeof(ucmd.reserved);
4318 if (udata->inlen < required_cmd_sz)
4319 return -EINVAL;
4320
4321 if (udata->inlen > sizeof(ucmd) &&
4322 !ib_is_udata_cleared(udata, sizeof(ucmd),
4323 udata->inlen - sizeof(ucmd)))
4324 return -EOPNOTSUPP;
4325
4326 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
4327 return -EFAULT;
4328
4329 if (ucmd.comp_mask || ucmd.reserved)
4330 return -EOPNOTSUPP;
4331
4332 if (wq_attr_mask & IB_WQ_FLAGS)
4333 return -EOPNOTSUPP;
4334
4335 cur_state = wq_attr_mask & IB_WQ_CUR_STATE ? wq_attr->curr_wq_state :
4336 ibwq->state;
4337 new_state = wq_attr_mask & IB_WQ_STATE ? wq_attr->wq_state : cur_state;
4338
4339 if (cur_state < IB_WQS_RESET || cur_state > IB_WQS_ERR ||
4340 new_state < IB_WQS_RESET || new_state > IB_WQS_ERR)
4341 return -EINVAL;
4342
4343 if ((new_state == IB_WQS_RDY) && (cur_state == IB_WQS_ERR))
4344 return -EINVAL;
4345
4346 if ((new_state == IB_WQS_ERR) && (cur_state == IB_WQS_RESET))
4347 return -EINVAL;
4348
4349 /* Need to protect against the parent RSS which also may modify WQ
4350 * state.
4351 */
4352 mutex_lock(&qp->mutex);
4353
4354 /* Can update HW state only if a RSS QP has already associated to this
4355 * WQ, so we can apply its port on the WQ.
4356 */
4357 if (qp->rss_usecnt)
4358 err = _mlx4_ib_modify_wq(ibwq, new_state);
4359
4360 if (!err)
4361 ibwq->state = new_state;
4362
4363 mutex_unlock(&qp->mutex);
4364
4365 return err;
4366 }
4367
4368 int mlx4_ib_destroy_wq(struct ib_wq *ibwq)
4369 {
4370 struct mlx4_ib_dev *dev = to_mdev(ibwq->device);
4371 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq);
4372
4373 if (qp->counter_index)
4374 mlx4_ib_free_qp_counter(dev, qp);
4375
4376 destroy_qp_common(dev, qp, MLX4_IB_RWQ_SRC, 1);
4377
4378 kfree(qp);
4379
4380 return 0;
4381 }
4382
4383 struct ib_rwq_ind_table
4384 *mlx4_ib_create_rwq_ind_table(struct ib_device *device,
4385 struct ib_rwq_ind_table_init_attr *init_attr,
4386 struct ib_udata *udata)
4387 {
4388 struct ib_rwq_ind_table *rwq_ind_table;
4389 struct mlx4_ib_create_rwq_ind_tbl_resp resp = {};
4390 unsigned int ind_tbl_size = 1 << init_attr->log_ind_tbl_size;
4391 unsigned int base_wqn;
4392 size_t min_resp_len;
4393 int i;
4394 int err;
4395
4396 if (udata->inlen > 0 &&
4397 !ib_is_udata_cleared(udata, 0,
4398 udata->inlen))
4399 return ERR_PTR(-EOPNOTSUPP);
4400
4401 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4402 if (udata->outlen && udata->outlen < min_resp_len)
4403 return ERR_PTR(-EINVAL);
4404
4405 if (ind_tbl_size >
4406 device->attrs.rss_caps.max_rwq_indirection_table_size) {
4407 pr_debug("log_ind_tbl_size = %d is bigger than supported = %d\n",
4408 ind_tbl_size,
4409 device->attrs.rss_caps.max_rwq_indirection_table_size);
4410 return ERR_PTR(-EINVAL);
4411 }
4412
4413 base_wqn = init_attr->ind_tbl[0]->wq_num;
4414
4415 if (base_wqn % ind_tbl_size) {
4416 pr_debug("WQN=0x%x isn't aligned with indirection table size\n",
4417 base_wqn);
4418 return ERR_PTR(-EINVAL);
4419 }
4420
4421 for (i = 1; i < ind_tbl_size; i++) {
4422 if (++base_wqn != init_attr->ind_tbl[i]->wq_num) {
4423 pr_debug("indirection table's WQNs aren't consecutive\n");
4424 return ERR_PTR(-EINVAL);
4425 }
4426 }
4427
4428 rwq_ind_table = kzalloc(sizeof(*rwq_ind_table), GFP_KERNEL);
4429 if (!rwq_ind_table)
4430 return ERR_PTR(-ENOMEM);
4431
4432 if (udata->outlen) {
4433 resp.response_length = offsetof(typeof(resp), response_length) +
4434 sizeof(resp.response_length);
4435 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4436 if (err)
4437 goto err;
4438 }
4439
4440 return rwq_ind_table;
4441
4442 err:
4443 kfree(rwq_ind_table);
4444 return ERR_PTR(err);
4445 }
4446
4447 int mlx4_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
4448 {
4449 kfree(ib_rwq_ind_tbl);
4450 return 0;
4451 }
CRIS linux kernel tree