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x86/topology: Fix function name in documentation
[cris-mirror.git] / drivers / net / ethernet / broadcom / genet / bcmgenet.c
blobb1e35a9accf1e2727a8749ba00801e58608181db
1 /*
2 * Broadcom GENET (Gigabit Ethernet) controller driver
3 *
4 * Copyright (c) 2014-2017 Broadcom
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #define pr_fmt(fmt) "bcmgenet: " fmt
12
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/sched.h>
16 #include <linux/types.h>
17 #include <linux/fcntl.h>
18 #include <linux/interrupt.h>
19 #include <linux/string.h>
20 #include <linux/if_ether.h>
21 #include <linux/init.h>
22 #include <linux/errno.h>
23 #include <linux/delay.h>
24 #include <linux/platform_device.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/pm.h>
27 #include <linux/clk.h>
28 #include <linux/of.h>
29 #include <linux/of_address.h>
30 #include <linux/of_irq.h>
31 #include <linux/of_net.h>
32 #include <linux/of_platform.h>
33 #include <net/arp.h>
34
35 #include <linux/mii.h>
36 #include <linux/ethtool.h>
37 #include <linux/netdevice.h>
38 #include <linux/inetdevice.h>
39 #include <linux/etherdevice.h>
40 #include <linux/skbuff.h>
41 #include <linux/in.h>
42 #include <linux/ip.h>
43 #include <linux/ipv6.h>
44 #include <linux/phy.h>
45 #include <linux/platform_data/bcmgenet.h>
46
47 #include <asm/unaligned.h>
48
49 #include "bcmgenet.h"
50
51 /* Maximum number of hardware queues, downsized if needed */
52 #define GENET_MAX_MQ_CNT 4
53
54 /* Default highest priority queue for multi queue support */
55 #define GENET_Q0_PRIORITY 0
56
57 #define GENET_Q16_RX_BD_CNT \
58 (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q)
59 #define GENET_Q16_TX_BD_CNT \
60 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q)
61
62 #define RX_BUF_LENGTH 2048
63 #define SKB_ALIGNMENT 32
64
65 /* Tx/Rx DMA register offset, skip 256 descriptors */
66 #define WORDS_PER_BD(p) (p->hw_params->words_per_bd)
67 #define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32))
68
69 #define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \
70 TOTAL_DESC * DMA_DESC_SIZE)
71
72 #define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \
73 TOTAL_DESC * DMA_DESC_SIZE)
74
75 static inline void bcmgenet_writel(u32 value, void __iomem *offset)
76 {
77 /* MIPS chips strapped for BE will automagically configure the
78 * peripheral registers for CPU-native byte order.
79 */
80 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
81 __raw_writel(value, offset);
82 else
83 writel_relaxed(value, offset);
84 }
85
86 static inline u32 bcmgenet_readl(void __iomem *offset)
87 {
88 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
89 return __raw_readl(offset);
90 else
91 return readl_relaxed(offset);
92 }
93
94 static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
95 void __iomem *d, u32 value)
96 {
97 bcmgenet_writel(value, d + DMA_DESC_LENGTH_STATUS);
98 }
99
100 static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv,
101 void __iomem *d)
102 {
103 return bcmgenet_readl(d + DMA_DESC_LENGTH_STATUS);
104 }
105
106 static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
107 void __iomem *d,
108 dma_addr_t addr)
109 {
110 bcmgenet_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
111
112 /* Register writes to GISB bus can take couple hundred nanoseconds
113 * and are done for each packet, save these expensive writes unless
114 * the platform is explicitly configured for 64-bits/LPAE.
115 */
116 #ifdef CONFIG_PHYS_ADDR_T_64BIT
117 if (priv->hw_params->flags & GENET_HAS_40BITS)
118 bcmgenet_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
119 #endif
120 }
121
122 /* Combined address + length/status setter */
123 static inline void dmadesc_set(struct bcmgenet_priv *priv,
124 void __iomem *d, dma_addr_t addr, u32 val)
125 {
126 dmadesc_set_addr(priv, d, addr);
127 dmadesc_set_length_status(priv, d, val);
128 }
129
130 static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,
131 void __iomem *d)
132 {
133 dma_addr_t addr;
134
135 addr = bcmgenet_readl(d + DMA_DESC_ADDRESS_LO);
136
137 /* Register writes to GISB bus can take couple hundred nanoseconds
138 * and are done for each packet, save these expensive writes unless
139 * the platform is explicitly configured for 64-bits/LPAE.
140 */
141 #ifdef CONFIG_PHYS_ADDR_T_64BIT
142 if (priv->hw_params->flags & GENET_HAS_40BITS)
143 addr |= (u64)bcmgenet_readl(d + DMA_DESC_ADDRESS_HI) << 32;
144 #endif
145 return addr;
146 }
147
148 #define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x"
149
150 #define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
151 NETIF_MSG_LINK)
152
153 static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
154 {
155 if (GENET_IS_V1(priv))
156 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
157 else
158 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
159 }
160
161 static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
162 {
163 if (GENET_IS_V1(priv))
164 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
165 else
166 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
167 }
168
169 /* These macros are defined to deal with register map change
170 * between GENET1.1 and GENET2. Only those currently being used
171 * by driver are defined.
172 */
173 static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
174 {
175 if (GENET_IS_V1(priv))
176 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
177 else
178 return bcmgenet_readl(priv->base +
179 priv->hw_params->tbuf_offset + TBUF_CTRL);
180 }
181
182 static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
183 {
184 if (GENET_IS_V1(priv))
185 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
186 else
187 bcmgenet_writel(val, priv->base +
188 priv->hw_params->tbuf_offset + TBUF_CTRL);
189 }
190
191 static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
192 {
193 if (GENET_IS_V1(priv))
194 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
195 else
196 return bcmgenet_readl(priv->base +
197 priv->hw_params->tbuf_offset + TBUF_BP_MC);
198 }
199
200 static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
201 {
202 if (GENET_IS_V1(priv))
203 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
204 else
205 bcmgenet_writel(val, priv->base +
206 priv->hw_params->tbuf_offset + TBUF_BP_MC);
207 }
208
209 /* RX/TX DMA register accessors */
210 enum dma_reg {
211 DMA_RING_CFG = 0,
212 DMA_CTRL,
213 DMA_STATUS,
214 DMA_SCB_BURST_SIZE,
215 DMA_ARB_CTRL,
216 DMA_PRIORITY_0,
217 DMA_PRIORITY_1,
218 DMA_PRIORITY_2,
219 DMA_INDEX2RING_0,
220 DMA_INDEX2RING_1,
221 DMA_INDEX2RING_2,
222 DMA_INDEX2RING_3,
223 DMA_INDEX2RING_4,
224 DMA_INDEX2RING_5,
225 DMA_INDEX2RING_6,
226 DMA_INDEX2RING_7,
227 DMA_RING0_TIMEOUT,
228 DMA_RING1_TIMEOUT,
229 DMA_RING2_TIMEOUT,
230 DMA_RING3_TIMEOUT,
231 DMA_RING4_TIMEOUT,
232 DMA_RING5_TIMEOUT,
233 DMA_RING6_TIMEOUT,
234 DMA_RING7_TIMEOUT,
235 DMA_RING8_TIMEOUT,
236 DMA_RING9_TIMEOUT,
237 DMA_RING10_TIMEOUT,
238 DMA_RING11_TIMEOUT,
239 DMA_RING12_TIMEOUT,
240 DMA_RING13_TIMEOUT,
241 DMA_RING14_TIMEOUT,
242 DMA_RING15_TIMEOUT,
243 DMA_RING16_TIMEOUT,
244 };
245
246 static const u8 bcmgenet_dma_regs_v3plus[] = {
247 [DMA_RING_CFG] = 0x00,
248 [DMA_CTRL] = 0x04,
249 [DMA_STATUS] = 0x08,
250 [DMA_SCB_BURST_SIZE] = 0x0C,
251 [DMA_ARB_CTRL] = 0x2C,
252 [DMA_PRIORITY_0] = 0x30,
253 [DMA_PRIORITY_1] = 0x34,
254 [DMA_PRIORITY_2] = 0x38,
255 [DMA_RING0_TIMEOUT] = 0x2C,
256 [DMA_RING1_TIMEOUT] = 0x30,
257 [DMA_RING2_TIMEOUT] = 0x34,
258 [DMA_RING3_TIMEOUT] = 0x38,
259 [DMA_RING4_TIMEOUT] = 0x3c,
260 [DMA_RING5_TIMEOUT] = 0x40,
261 [DMA_RING6_TIMEOUT] = 0x44,
262 [DMA_RING7_TIMEOUT] = 0x48,
263 [DMA_RING8_TIMEOUT] = 0x4c,
264 [DMA_RING9_TIMEOUT] = 0x50,
265 [DMA_RING10_TIMEOUT] = 0x54,
266 [DMA_RING11_TIMEOUT] = 0x58,
267 [DMA_RING12_TIMEOUT] = 0x5c,
268 [DMA_RING13_TIMEOUT] = 0x60,
269 [DMA_RING14_TIMEOUT] = 0x64,
270 [DMA_RING15_TIMEOUT] = 0x68,
271 [DMA_RING16_TIMEOUT] = 0x6C,
272 [DMA_INDEX2RING_0] = 0x70,
273 [DMA_INDEX2RING_1] = 0x74,
274 [DMA_INDEX2RING_2] = 0x78,
275 [DMA_INDEX2RING_3] = 0x7C,
276 [DMA_INDEX2RING_4] = 0x80,
277 [DMA_INDEX2RING_5] = 0x84,
278 [DMA_INDEX2RING_6] = 0x88,
279 [DMA_INDEX2RING_7] = 0x8C,
280 };
281
282 static const u8 bcmgenet_dma_regs_v2[] = {
283 [DMA_RING_CFG] = 0x00,
284 [DMA_CTRL] = 0x04,
285 [DMA_STATUS] = 0x08,
286 [DMA_SCB_BURST_SIZE] = 0x0C,
287 [DMA_ARB_CTRL] = 0x30,
288 [DMA_PRIORITY_0] = 0x34,
289 [DMA_PRIORITY_1] = 0x38,
290 [DMA_PRIORITY_2] = 0x3C,
291 [DMA_RING0_TIMEOUT] = 0x2C,
292 [DMA_RING1_TIMEOUT] = 0x30,
293 [DMA_RING2_TIMEOUT] = 0x34,
294 [DMA_RING3_TIMEOUT] = 0x38,
295 [DMA_RING4_TIMEOUT] = 0x3c,
296 [DMA_RING5_TIMEOUT] = 0x40,
297 [DMA_RING6_TIMEOUT] = 0x44,
298 [DMA_RING7_TIMEOUT] = 0x48,
299 [DMA_RING8_TIMEOUT] = 0x4c,
300 [DMA_RING9_TIMEOUT] = 0x50,
301 [DMA_RING10_TIMEOUT] = 0x54,
302 [DMA_RING11_TIMEOUT] = 0x58,
303 [DMA_RING12_TIMEOUT] = 0x5c,
304 [DMA_RING13_TIMEOUT] = 0x60,
305 [DMA_RING14_TIMEOUT] = 0x64,
306 [DMA_RING15_TIMEOUT] = 0x68,
307 [DMA_RING16_TIMEOUT] = 0x6C,
308 };
309
310 static const u8 bcmgenet_dma_regs_v1[] = {
311 [DMA_CTRL] = 0x00,
312 [DMA_STATUS] = 0x04,
313 [DMA_SCB_BURST_SIZE] = 0x0C,
314 [DMA_ARB_CTRL] = 0x30,
315 [DMA_PRIORITY_0] = 0x34,
316 [DMA_PRIORITY_1] = 0x38,
317 [DMA_PRIORITY_2] = 0x3C,
318 [DMA_RING0_TIMEOUT] = 0x2C,
319 [DMA_RING1_TIMEOUT] = 0x30,
320 [DMA_RING2_TIMEOUT] = 0x34,
321 [DMA_RING3_TIMEOUT] = 0x38,
322 [DMA_RING4_TIMEOUT] = 0x3c,
323 [DMA_RING5_TIMEOUT] = 0x40,
324 [DMA_RING6_TIMEOUT] = 0x44,
325 [DMA_RING7_TIMEOUT] = 0x48,
326 [DMA_RING8_TIMEOUT] = 0x4c,
327 [DMA_RING9_TIMEOUT] = 0x50,
328 [DMA_RING10_TIMEOUT] = 0x54,
329 [DMA_RING11_TIMEOUT] = 0x58,
330 [DMA_RING12_TIMEOUT] = 0x5c,
331 [DMA_RING13_TIMEOUT] = 0x60,
332 [DMA_RING14_TIMEOUT] = 0x64,
333 [DMA_RING15_TIMEOUT] = 0x68,
334 [DMA_RING16_TIMEOUT] = 0x6C,
335 };
336
337 /* Set at runtime once bcmgenet version is known */
338 static const u8 *bcmgenet_dma_regs;
339
340 static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
341 {
342 return netdev_priv(dev_get_drvdata(dev));
343 }
344
345 static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
346 enum dma_reg r)
347 {
348 return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF +
349 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
350 }
351
352 static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
353 u32 val, enum dma_reg r)
354 {
355 bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF +
356 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
357 }
358
359 static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
360 enum dma_reg r)
361 {
362 return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF +
363 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
364 }
365
366 static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
367 u32 val, enum dma_reg r)
368 {
369 bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF +
370 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
371 }
372
373 /* RDMA/TDMA ring registers and accessors
374 * we merge the common fields and just prefix with T/D the registers
375 * having different meaning depending on the direction
376 */
377 enum dma_ring_reg {
378 TDMA_READ_PTR = 0,
379 RDMA_WRITE_PTR = TDMA_READ_PTR,
380 TDMA_READ_PTR_HI,
381 RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
382 TDMA_CONS_INDEX,
383 RDMA_PROD_INDEX = TDMA_CONS_INDEX,
384 TDMA_PROD_INDEX,
385 RDMA_CONS_INDEX = TDMA_PROD_INDEX,
386 DMA_RING_BUF_SIZE,
387 DMA_START_ADDR,
388 DMA_START_ADDR_HI,
389 DMA_END_ADDR,
390 DMA_END_ADDR_HI,
391 DMA_MBUF_DONE_THRESH,
392 TDMA_FLOW_PERIOD,
393 RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
394 TDMA_WRITE_PTR,
395 RDMA_READ_PTR = TDMA_WRITE_PTR,
396 TDMA_WRITE_PTR_HI,
397 RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
398 };
399
400 /* GENET v4 supports 40-bits pointer addressing
401 * for obvious reasons the LO and HI word parts
402 * are contiguous, but this offsets the other
403 * registers.
404 */
405 static const u8 genet_dma_ring_regs_v4[] = {
406 [TDMA_READ_PTR] = 0x00,
407 [TDMA_READ_PTR_HI] = 0x04,
408 [TDMA_CONS_INDEX] = 0x08,
409 [TDMA_PROD_INDEX] = 0x0C,
410 [DMA_RING_BUF_SIZE] = 0x10,
411 [DMA_START_ADDR] = 0x14,
412 [DMA_START_ADDR_HI] = 0x18,
413 [DMA_END_ADDR] = 0x1C,
414 [DMA_END_ADDR_HI] = 0x20,
415 [DMA_MBUF_DONE_THRESH] = 0x24,
416 [TDMA_FLOW_PERIOD] = 0x28,
417 [TDMA_WRITE_PTR] = 0x2C,
418 [TDMA_WRITE_PTR_HI] = 0x30,
419 };
420
421 static const u8 genet_dma_ring_regs_v123[] = {
422 [TDMA_READ_PTR] = 0x00,
423 [TDMA_CONS_INDEX] = 0x04,
424 [TDMA_PROD_INDEX] = 0x08,
425 [DMA_RING_BUF_SIZE] = 0x0C,
426 [DMA_START_ADDR] = 0x10,
427 [DMA_END_ADDR] = 0x14,
428 [DMA_MBUF_DONE_THRESH] = 0x18,
429 [TDMA_FLOW_PERIOD] = 0x1C,
430 [TDMA_WRITE_PTR] = 0x20,
431 };
432
433 /* Set at runtime once GENET version is known */
434 static const u8 *genet_dma_ring_regs;
435
436 static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
437 unsigned int ring,
438 enum dma_ring_reg r)
439 {
440 return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF +
441 (DMA_RING_SIZE * ring) +
442 genet_dma_ring_regs[r]);
443 }
444
445 static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
446 unsigned int ring, u32 val,
447 enum dma_ring_reg r)
448 {
449 bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF +
450 (DMA_RING_SIZE * ring) +
451 genet_dma_ring_regs[r]);
452 }
453
454 static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
455 unsigned int ring,
456 enum dma_ring_reg r)
457 {
458 return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF +
459 (DMA_RING_SIZE * ring) +
460 genet_dma_ring_regs[r]);
461 }
462
463 static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
464 unsigned int ring, u32 val,
465 enum dma_ring_reg r)
466 {
467 bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF +
468 (DMA_RING_SIZE * ring) +
469 genet_dma_ring_regs[r]);
470 }
471
472 static int bcmgenet_begin(struct net_device *dev)
473 {
474 struct bcmgenet_priv *priv = netdev_priv(dev);
475
476 /* Turn on the clock */
477 return clk_prepare_enable(priv->clk);
478 }
479
480 static void bcmgenet_complete(struct net_device *dev)
481 {
482 struct bcmgenet_priv *priv = netdev_priv(dev);
483
484 /* Turn off the clock */
485 clk_disable_unprepare(priv->clk);
486 }
487
488 static int bcmgenet_get_link_ksettings(struct net_device *dev,
489 struct ethtool_link_ksettings *cmd)
490 {
491 if (!netif_running(dev))
492 return -EINVAL;
493
494 if (!dev->phydev)
495 return -ENODEV;
496
497 phy_ethtool_ksettings_get(dev->phydev, cmd);
498
499 return 0;
500 }
501
502 static int bcmgenet_set_link_ksettings(struct net_device *dev,
503 const struct ethtool_link_ksettings *cmd)
504 {
505 if (!netif_running(dev))
506 return -EINVAL;
507
508 if (!dev->phydev)
509 return -ENODEV;
510
511 return phy_ethtool_ksettings_set(dev->phydev, cmd);
512 }
513
514 static int bcmgenet_set_rx_csum(struct net_device *dev,
515 netdev_features_t wanted)
516 {
517 struct bcmgenet_priv *priv = netdev_priv(dev);
518 u32 rbuf_chk_ctrl;
519 bool rx_csum_en;
520
521 rx_csum_en = !!(wanted & NETIF_F_RXCSUM);
522
523 rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
524
525 /* enable rx checksumming */
526 if (rx_csum_en)
527 rbuf_chk_ctrl |= RBUF_RXCHK_EN;
528 else
529 rbuf_chk_ctrl &= ~RBUF_RXCHK_EN;
530 priv->desc_rxchk_en = rx_csum_en;
531
532 /* If UniMAC forwards CRC, we need to skip over it to get
533 * a valid CHK bit to be set in the per-packet status word
534 */
535 if (rx_csum_en && priv->crc_fwd_en)
536 rbuf_chk_ctrl |= RBUF_SKIP_FCS;
537 else
538 rbuf_chk_ctrl &= ~RBUF_SKIP_FCS;
539
540 bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL);
541
542 return 0;
543 }
544
545 static int bcmgenet_set_tx_csum(struct net_device *dev,
546 netdev_features_t wanted)
547 {
548 struct bcmgenet_priv *priv = netdev_priv(dev);
549 bool desc_64b_en;
550 u32 tbuf_ctrl, rbuf_ctrl;
551
552 tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv);
553 rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
554
555 desc_64b_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
556
557 /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */
558 if (desc_64b_en) {
559 tbuf_ctrl |= RBUF_64B_EN;
560 rbuf_ctrl |= RBUF_64B_EN;
561 } else {
562 tbuf_ctrl &= ~RBUF_64B_EN;
563 rbuf_ctrl &= ~RBUF_64B_EN;
564 }
565 priv->desc_64b_en = desc_64b_en;
566
567 bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl);
568 bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL);
569
570 return 0;
571 }
572
573 static int bcmgenet_set_features(struct net_device *dev,
574 netdev_features_t features)
575 {
576 netdev_features_t changed = features ^ dev->features;
577 netdev_features_t wanted = dev->wanted_features;
578 int ret = 0;
579
580 if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))
581 ret = bcmgenet_set_tx_csum(dev, wanted);
582 if (changed & (NETIF_F_RXCSUM))
583 ret = bcmgenet_set_rx_csum(dev, wanted);
584
585 return ret;
586 }
587
588 static u32 bcmgenet_get_msglevel(struct net_device *dev)
589 {
590 struct bcmgenet_priv *priv = netdev_priv(dev);
591
592 return priv->msg_enable;
593 }
594
595 static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
596 {
597 struct bcmgenet_priv *priv = netdev_priv(dev);
598
599 priv->msg_enable = level;
600 }
601
602 static int bcmgenet_get_coalesce(struct net_device *dev,
603 struct ethtool_coalesce *ec)
604 {
605 struct bcmgenet_priv *priv = netdev_priv(dev);
606
607 ec->tx_max_coalesced_frames =
608 bcmgenet_tdma_ring_readl(priv, DESC_INDEX,
609 DMA_MBUF_DONE_THRESH);
610 ec->rx_max_coalesced_frames =
611 bcmgenet_rdma_ring_readl(priv, DESC_INDEX,
612 DMA_MBUF_DONE_THRESH);
613 ec->rx_coalesce_usecs =
614 bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT) * 8192 / 1000;
615
616 return 0;
617 }
618
619 static int bcmgenet_set_coalesce(struct net_device *dev,
620 struct ethtool_coalesce *ec)
621 {
622 struct bcmgenet_priv *priv = netdev_priv(dev);
623 unsigned int i;
624 u32 reg;
625
626 /* Base system clock is 125Mhz, DMA timeout is this reference clock
627 * divided by 1024, which yields roughly 8.192us, our maximum value
628 * has to fit in the DMA_TIMEOUT_MASK (16 bits)
629 */
630 if (ec->tx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
631 ec->tx_max_coalesced_frames == 0 ||
632 ec->rx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
633 ec->rx_coalesce_usecs > (DMA_TIMEOUT_MASK * 8) + 1)
634 return -EINVAL;
635
636 if (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0)
637 return -EINVAL;
638
639 /* GENET TDMA hardware does not support a configurable timeout, but will
640 * always generate an interrupt either after MBDONE packets have been
641 * transmitted, or when the ring is empty.
642 */
643 if (ec->tx_coalesce_usecs || ec->tx_coalesce_usecs_high ||
644 ec->tx_coalesce_usecs_irq || ec->tx_coalesce_usecs_low)
645 return -EOPNOTSUPP;
646
647 /* Program all TX queues with the same values, as there is no
648 * ethtool knob to do coalescing on a per-queue basis
649 */
650 for (i = 0; i < priv->hw_params->tx_queues; i++)
651 bcmgenet_tdma_ring_writel(priv, i,
652 ec->tx_max_coalesced_frames,
653 DMA_MBUF_DONE_THRESH);
654 bcmgenet_tdma_ring_writel(priv, DESC_INDEX,
655 ec->tx_max_coalesced_frames,
656 DMA_MBUF_DONE_THRESH);
657
658 for (i = 0; i < priv->hw_params->rx_queues; i++) {
659 bcmgenet_rdma_ring_writel(priv, i,
660 ec->rx_max_coalesced_frames,
661 DMA_MBUF_DONE_THRESH);
662
663 reg = bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT + i);
664 reg &= ~DMA_TIMEOUT_MASK;
665 reg |= DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000, 8192);
666 bcmgenet_rdma_writel(priv, reg, DMA_RING0_TIMEOUT + i);
667 }
668
669 bcmgenet_rdma_ring_writel(priv, DESC_INDEX,
670 ec->rx_max_coalesced_frames,
671 DMA_MBUF_DONE_THRESH);
672
673 reg = bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT);
674 reg &= ~DMA_TIMEOUT_MASK;
675 reg |= DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000, 8192);
676 bcmgenet_rdma_writel(priv, reg, DMA_RING16_TIMEOUT);
677
678 return 0;
679 }
680
681 /* standard ethtool support functions. */
682 enum bcmgenet_stat_type {
683 BCMGENET_STAT_NETDEV = -1,
684 BCMGENET_STAT_MIB_RX,
685 BCMGENET_STAT_MIB_TX,
686 BCMGENET_STAT_RUNT,
687 BCMGENET_STAT_MISC,
688 BCMGENET_STAT_SOFT,
689 };
690
691 struct bcmgenet_stats {
692 char stat_string[ETH_GSTRING_LEN];
693 int stat_sizeof;
694 int stat_offset;
695 enum bcmgenet_stat_type type;
696 /* reg offset from UMAC base for misc counters */
697 u16 reg_offset;
698 };
699
700 #define STAT_NETDEV(m) { \
701 .stat_string = __stringify(m), \
702 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
703 .stat_offset = offsetof(struct net_device_stats, m), \
704 .type = BCMGENET_STAT_NETDEV, \
705 }
706
707 #define STAT_GENET_MIB(str, m, _type) { \
708 .stat_string = str, \
709 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
710 .stat_offset = offsetof(struct bcmgenet_priv, m), \
711 .type = _type, \
712 }
713
714 #define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
715 #define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
716 #define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
717 #define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT)
718
719 #define STAT_GENET_MISC(str, m, offset) { \
720 .stat_string = str, \
721 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
722 .stat_offset = offsetof(struct bcmgenet_priv, m), \
723 .type = BCMGENET_STAT_MISC, \
724 .reg_offset = offset, \
725 }
726
727 #define STAT_GENET_Q(num) \
728 STAT_GENET_SOFT_MIB("txq" __stringify(num) "_packets", \
729 tx_rings[num].packets), \
730 STAT_GENET_SOFT_MIB("txq" __stringify(num) "_bytes", \
731 tx_rings[num].bytes), \
732 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_bytes", \
733 rx_rings[num].bytes), \
734 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_packets", \
735 rx_rings[num].packets), \
736 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_errors", \
737 rx_rings[num].errors), \
738 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_dropped", \
739 rx_rings[num].dropped)
740
741 /* There is a 0xC gap between the end of RX and beginning of TX stats and then
742 * between the end of TX stats and the beginning of the RX RUNT
743 */
744 #define BCMGENET_STAT_OFFSET 0xc
745
746 /* Hardware counters must be kept in sync because the order/offset
747 * is important here (order in structure declaration = order in hardware)
748 */
749 static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
750 /* general stats */
751 STAT_NETDEV(rx_packets),
752 STAT_NETDEV(tx_packets),
753 STAT_NETDEV(rx_bytes),
754 STAT_NETDEV(tx_bytes),
755 STAT_NETDEV(rx_errors),
756 STAT_NETDEV(tx_errors),
757 STAT_NETDEV(rx_dropped),
758 STAT_NETDEV(tx_dropped),
759 STAT_NETDEV(multicast),
760 /* UniMAC RSV counters */
761 STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
762 STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
763 STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
764 STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
765 STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
766 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
767 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
768 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
769 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
770 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
771 STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
772 STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
773 STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
774 STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
775 STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
776 STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
777 STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
778 STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
779 STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
780 STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
781 STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
782 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
783 STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
784 STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
785 STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
786 STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
787 STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
788 STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
789 STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
790 /* UniMAC TSV counters */
791 STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
792 STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
793 STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
794 STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
795 STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
796 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
797 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
798 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
799 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
800 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
801 STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
802 STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
803 STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
804 STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
805 STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
806 STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
807 STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
808 STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
809 STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
810 STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
811 STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
812 STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
813 STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
814 STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
815 STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
816 STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
817 STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
818 STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
819 STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
820 /* UniMAC RUNT counters */
821 STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
822 STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
823 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
824 STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
825 /* Misc UniMAC counters */
826 STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
827 UMAC_RBUF_OVFL_CNT_V1),
828 STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt,
829 UMAC_RBUF_ERR_CNT_V1),
830 STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
831 STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
832 STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed),
833 STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed),
834 /* Per TX queues */
835 STAT_GENET_Q(0),
836 STAT_GENET_Q(1),
837 STAT_GENET_Q(2),
838 STAT_GENET_Q(3),
839 STAT_GENET_Q(16),
840 };
841
842 #define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats)
843
844 static void bcmgenet_get_drvinfo(struct net_device *dev,
845 struct ethtool_drvinfo *info)
846 {
847 strlcpy(info->driver, "bcmgenet", sizeof(info->driver));
848 strlcpy(info->version, "v2.0", sizeof(info->version));
849 }
850
851 static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
852 {
853 switch (string_set) {
854 case ETH_SS_STATS:
855 return BCMGENET_STATS_LEN;
856 default:
857 return -EOPNOTSUPP;
858 }
859 }
860
861 static void bcmgenet_get_strings(struct net_device *dev, u32 stringset,
862 u8 *data)
863 {
864 int i;
865
866 switch (stringset) {
867 case ETH_SS_STATS:
868 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
869 memcpy(data + i * ETH_GSTRING_LEN,
870 bcmgenet_gstrings_stats[i].stat_string,
871 ETH_GSTRING_LEN);
872 }
873 break;
874 }
875 }
876
877 static u32 bcmgenet_update_stat_misc(struct bcmgenet_priv *priv, u16 offset)
878 {
879 u16 new_offset;
880 u32 val;
881
882 switch (offset) {
883 case UMAC_RBUF_OVFL_CNT_V1:
884 if (GENET_IS_V2(priv))
885 new_offset = RBUF_OVFL_CNT_V2;
886 else
887 new_offset = RBUF_OVFL_CNT_V3PLUS;
888
889 val = bcmgenet_rbuf_readl(priv, new_offset);
890 /* clear if overflowed */
891 if (val == ~0)
892 bcmgenet_rbuf_writel(priv, 0, new_offset);
893 break;
894 case UMAC_RBUF_ERR_CNT_V1:
895 if (GENET_IS_V2(priv))
896 new_offset = RBUF_ERR_CNT_V2;
897 else
898 new_offset = RBUF_ERR_CNT_V3PLUS;
899
900 val = bcmgenet_rbuf_readl(priv, new_offset);
901 /* clear if overflowed */
902 if (val == ~0)
903 bcmgenet_rbuf_writel(priv, 0, new_offset);
904 break;
905 default:
906 val = bcmgenet_umac_readl(priv, offset);
907 /* clear if overflowed */
908 if (val == ~0)
909 bcmgenet_umac_writel(priv, 0, offset);
910 break;
911 }
912
913 return val;
914 }
915
916 static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
917 {
918 int i, j = 0;
919
920 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
921 const struct bcmgenet_stats *s;
922 u8 offset = 0;
923 u32 val = 0;
924 char *p;
925
926 s = &bcmgenet_gstrings_stats[i];
927 switch (s->type) {
928 case BCMGENET_STAT_NETDEV:
929 case BCMGENET_STAT_SOFT:
930 continue;
931 case BCMGENET_STAT_RUNT:
932 offset += BCMGENET_STAT_OFFSET;
933 /* fall through */
934 case BCMGENET_STAT_MIB_TX:
935 offset += BCMGENET_STAT_OFFSET;
936 /* fall through */
937 case BCMGENET_STAT_MIB_RX:
938 val = bcmgenet_umac_readl(priv,
939 UMAC_MIB_START + j + offset);
940 offset = 0; /* Reset Offset */
941 break;
942 case BCMGENET_STAT_MISC:
943 if (GENET_IS_V1(priv)) {
944 val = bcmgenet_umac_readl(priv, s->reg_offset);
945 /* clear if overflowed */
946 if (val == ~0)
947 bcmgenet_umac_writel(priv, 0,
948 s->reg_offset);
949 } else {
950 val = bcmgenet_update_stat_misc(priv,
951 s->reg_offset);
952 }
953 break;
954 }
955
956 j += s->stat_sizeof;
957 p = (char *)priv + s->stat_offset;
958 *(u32 *)p = val;
959 }
960 }
961
962 static void bcmgenet_get_ethtool_stats(struct net_device *dev,
963 struct ethtool_stats *stats,
964 u64 *data)
965 {
966 struct bcmgenet_priv *priv = netdev_priv(dev);
967 int i;
968
969 if (netif_running(dev))
970 bcmgenet_update_mib_counters(priv);
971
972 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
973 const struct bcmgenet_stats *s;
974 char *p;
975
976 s = &bcmgenet_gstrings_stats[i];
977 if (s->type == BCMGENET_STAT_NETDEV)
978 p = (char *)&dev->stats;
979 else
980 p = (char *)priv;
981 p += s->stat_offset;
982 if (sizeof(unsigned long) != sizeof(u32) &&
983 s->stat_sizeof == sizeof(unsigned long))
984 data[i] = *(unsigned long *)p;
985 else
986 data[i] = *(u32 *)p;
987 }
988 }
989
990 static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable)
991 {
992 struct bcmgenet_priv *priv = netdev_priv(dev);
993 u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL;
994 u32 reg;
995
996 if (enable && !priv->clk_eee_enabled) {
997 clk_prepare_enable(priv->clk_eee);
998 priv->clk_eee_enabled = true;
999 }
1000
1001 reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL);
1002 if (enable)
1003 reg |= EEE_EN;
1004 else
1005 reg &= ~EEE_EN;
1006 bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL);
1007
1008 /* Enable EEE and switch to a 27Mhz clock automatically */
1009 reg = bcmgenet_readl(priv->base + off);
1010 if (enable)
1011 reg |= TBUF_EEE_EN | TBUF_PM_EN;
1012 else
1013 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN);
1014 bcmgenet_writel(reg, priv->base + off);
1015
1016 /* Do the same for thing for RBUF */
1017 reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL);
1018 if (enable)
1019 reg |= RBUF_EEE_EN | RBUF_PM_EN;
1020 else
1021 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN);
1022 bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL);
1023
1024 if (!enable && priv->clk_eee_enabled) {
1025 clk_disable_unprepare(priv->clk_eee);
1026 priv->clk_eee_enabled = false;
1027 }
1028
1029 priv->eee.eee_enabled = enable;
1030 priv->eee.eee_active = enable;
1031 }
1032
1033 static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e)
1034 {
1035 struct bcmgenet_priv *priv = netdev_priv(dev);
1036 struct ethtool_eee *p = &priv->eee;
1037
1038 if (GENET_IS_V1(priv))
1039 return -EOPNOTSUPP;
1040
1041 if (!dev->phydev)
1042 return -ENODEV;
1043
1044 e->eee_enabled = p->eee_enabled;
1045 e->eee_active = p->eee_active;
1046 e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER);
1047
1048 return phy_ethtool_get_eee(dev->phydev, e);
1049 }
1050
1051 static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e)
1052 {
1053 struct bcmgenet_priv *priv = netdev_priv(dev);
1054 struct ethtool_eee *p = &priv->eee;
1055 int ret = 0;
1056
1057 if (GENET_IS_V1(priv))
1058 return -EOPNOTSUPP;
1059
1060 if (!dev->phydev)
1061 return -ENODEV;
1062
1063 p->eee_enabled = e->eee_enabled;
1064
1065 if (!p->eee_enabled) {
1066 bcmgenet_eee_enable_set(dev, false);
1067 } else {
1068 ret = phy_init_eee(dev->phydev, 0);
1069 if (ret) {
1070 netif_err(priv, hw, dev, "EEE initialization failed\n");
1071 return ret;
1072 }
1073
1074 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER);
1075 bcmgenet_eee_enable_set(dev, true);
1076 }
1077
1078 return phy_ethtool_set_eee(dev->phydev, e);
1079 }
1080
1081 /* standard ethtool support functions. */
1082 static const struct ethtool_ops bcmgenet_ethtool_ops = {
1083 .begin = bcmgenet_begin,
1084 .complete = bcmgenet_complete,
1085 .get_strings = bcmgenet_get_strings,
1086 .get_sset_count = bcmgenet_get_sset_count,
1087 .get_ethtool_stats = bcmgenet_get_ethtool_stats,
1088 .get_drvinfo = bcmgenet_get_drvinfo,
1089 .get_link = ethtool_op_get_link,
1090 .get_msglevel = bcmgenet_get_msglevel,
1091 .set_msglevel = bcmgenet_set_msglevel,
1092 .get_wol = bcmgenet_get_wol,
1093 .set_wol = bcmgenet_set_wol,
1094 .get_eee = bcmgenet_get_eee,
1095 .set_eee = bcmgenet_set_eee,
1096 .nway_reset = phy_ethtool_nway_reset,
1097 .get_coalesce = bcmgenet_get_coalesce,
1098 .set_coalesce = bcmgenet_set_coalesce,
1099 .get_link_ksettings = bcmgenet_get_link_ksettings,
1100 .set_link_ksettings = bcmgenet_set_link_ksettings,
1101 };
1102
1103 /* Power down the unimac, based on mode. */
1104 static int bcmgenet_power_down(struct bcmgenet_priv *priv,
1105 enum bcmgenet_power_mode mode)
1106 {
1107 int ret = 0;
1108 u32 reg;
1109
1110 switch (mode) {
1111 case GENET_POWER_CABLE_SENSE:
1112 phy_detach(priv->dev->phydev);
1113 break;
1114
1115 case GENET_POWER_WOL_MAGIC:
1116 ret = bcmgenet_wol_power_down_cfg(priv, mode);
1117 break;
1118
1119 case GENET_POWER_PASSIVE:
1120 /* Power down LED */
1121 if (priv->hw_params->flags & GENET_HAS_EXT) {
1122 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1123 if (GENET_IS_V5(priv))
1124 reg |= EXT_PWR_DOWN_PHY_EN |
1125 EXT_PWR_DOWN_PHY_RD |
1126 EXT_PWR_DOWN_PHY_SD |
1127 EXT_PWR_DOWN_PHY_RX |
1128 EXT_PWR_DOWN_PHY_TX |
1129 EXT_IDDQ_GLBL_PWR;
1130 else
1131 reg |= EXT_PWR_DOWN_PHY;
1132
1133 reg |= (EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
1134 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1135
1136 bcmgenet_phy_power_set(priv->dev, false);
1137 }
1138 break;
1139 default:
1140 break;
1141 }
1142
1143 return 0;
1144 }
1145
1146 static void bcmgenet_power_up(struct bcmgenet_priv *priv,
1147 enum bcmgenet_power_mode mode)
1148 {
1149 u32 reg;
1150
1151 if (!(priv->hw_params->flags & GENET_HAS_EXT))
1152 return;
1153
1154 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1155
1156 switch (mode) {
1157 case GENET_POWER_PASSIVE:
1158 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
1159 if (GENET_IS_V5(priv)) {
1160 reg &= ~(EXT_PWR_DOWN_PHY_EN |
1161 EXT_PWR_DOWN_PHY_RD |
1162 EXT_PWR_DOWN_PHY_SD |
1163 EXT_PWR_DOWN_PHY_RX |
1164 EXT_PWR_DOWN_PHY_TX |
1165 EXT_IDDQ_GLBL_PWR);
1166 reg |= EXT_PHY_RESET;
1167 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1168 mdelay(1);
1169
1170 reg &= ~EXT_PHY_RESET;
1171 } else {
1172 reg &= ~EXT_PWR_DOWN_PHY;
1173 reg |= EXT_PWR_DN_EN_LD;
1174 }
1175 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1176 bcmgenet_phy_power_set(priv->dev, true);
1177 break;
1178
1179 case GENET_POWER_CABLE_SENSE:
1180 /* enable APD */
1181 if (!GENET_IS_V5(priv)) {
1182 reg |= EXT_PWR_DN_EN_LD;
1183 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1184 }
1185 break;
1186 case GENET_POWER_WOL_MAGIC:
1187 bcmgenet_wol_power_up_cfg(priv, mode);
1188 return;
1189 default:
1190 break;
1191 }
1192 }
1193
1194 /* ioctl handle special commands that are not present in ethtool. */
1195 static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1196 {
1197 if (!netif_running(dev))
1198 return -EINVAL;
1199
1200 if (!dev->phydev)
1201 return -ENODEV;
1202
1203 return phy_mii_ioctl(dev->phydev, rq, cmd);
1204 }
1205
1206 static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
1207 struct bcmgenet_tx_ring *ring)
1208 {
1209 struct enet_cb *tx_cb_ptr;
1210
1211 tx_cb_ptr = ring->cbs;
1212 tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
1213
1214 /* Advancing local write pointer */
1215 if (ring->write_ptr == ring->end_ptr)
1216 ring->write_ptr = ring->cb_ptr;
1217 else
1218 ring->write_ptr++;
1219
1220 return tx_cb_ptr;
1221 }
1222
1223 static struct enet_cb *bcmgenet_put_txcb(struct bcmgenet_priv *priv,
1224 struct bcmgenet_tx_ring *ring)
1225 {
1226 struct enet_cb *tx_cb_ptr;
1227
1228 tx_cb_ptr = ring->cbs;
1229 tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
1230
1231 /* Rewinding local write pointer */
1232 if (ring->write_ptr == ring->cb_ptr)
1233 ring->write_ptr = ring->end_ptr;
1234 else
1235 ring->write_ptr--;
1236
1237 return tx_cb_ptr;
1238 }
1239
1240 static inline void bcmgenet_rx_ring16_int_disable(struct bcmgenet_rx_ring *ring)
1241 {
1242 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
1243 INTRL2_CPU_MASK_SET);
1244 }
1245
1246 static inline void bcmgenet_rx_ring16_int_enable(struct bcmgenet_rx_ring *ring)
1247 {
1248 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
1249 INTRL2_CPU_MASK_CLEAR);
1250 }
1251
1252 static inline void bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring *ring)
1253 {
1254 bcmgenet_intrl2_1_writel(ring->priv,
1255 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1256 INTRL2_CPU_MASK_SET);
1257 }
1258
1259 static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring)
1260 {
1261 bcmgenet_intrl2_1_writel(ring->priv,
1262 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1263 INTRL2_CPU_MASK_CLEAR);
1264 }
1265
1266 static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_tx_ring *ring)
1267 {
1268 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
1269 INTRL2_CPU_MASK_SET);
1270 }
1271
1272 static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_tx_ring *ring)
1273 {
1274 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
1275 INTRL2_CPU_MASK_CLEAR);
1276 }
1277
1278 static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring *ring)
1279 {
1280 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
1281 INTRL2_CPU_MASK_CLEAR);
1282 }
1283
1284 static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring *ring)
1285 {
1286 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
1287 INTRL2_CPU_MASK_SET);
1288 }
1289
1290 /* Simple helper to free a transmit control block's resources
1291 * Returns an skb when the last transmit control block associated with the
1292 * skb is freed. The skb should be freed by the caller if necessary.
1293 */
1294 static struct sk_buff *bcmgenet_free_tx_cb(struct device *dev,
1295 struct enet_cb *cb)
1296 {
1297 struct sk_buff *skb;
1298
1299 skb = cb->skb;
1300
1301 if (skb) {
1302 cb->skb = NULL;
1303 if (cb == GENET_CB(skb)->first_cb)
1304 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr),
1305 dma_unmap_len(cb, dma_len),
1306 DMA_TO_DEVICE);
1307 else
1308 dma_unmap_page(dev, dma_unmap_addr(cb, dma_addr),
1309 dma_unmap_len(cb, dma_len),
1310 DMA_TO_DEVICE);
1311 dma_unmap_addr_set(cb, dma_addr, 0);
1312
1313 if (cb == GENET_CB(skb)->last_cb)
1314 return skb;
1315
1316 } else if (dma_unmap_addr(cb, dma_addr)) {
1317 dma_unmap_page(dev,
1318 dma_unmap_addr(cb, dma_addr),
1319 dma_unmap_len(cb, dma_len),
1320 DMA_TO_DEVICE);
1321 dma_unmap_addr_set(cb, dma_addr, 0);
1322 }
1323
1324 return 0;
1325 }
1326
1327 /* Simple helper to free a receive control block's resources */
1328 static struct sk_buff *bcmgenet_free_rx_cb(struct device *dev,
1329 struct enet_cb *cb)
1330 {
1331 struct sk_buff *skb;
1332
1333 skb = cb->skb;
1334 cb->skb = NULL;
1335
1336 if (dma_unmap_addr(cb, dma_addr)) {
1337 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr),
1338 dma_unmap_len(cb, dma_len), DMA_FROM_DEVICE);
1339 dma_unmap_addr_set(cb, dma_addr, 0);
1340 }
1341
1342 return skb;
1343 }
1344
1345 /* Unlocked version of the reclaim routine */
1346 static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev,
1347 struct bcmgenet_tx_ring *ring)
1348 {
1349 struct bcmgenet_priv *priv = netdev_priv(dev);
1350 unsigned int txbds_processed = 0;
1351 unsigned int bytes_compl = 0;
1352 unsigned int pkts_compl = 0;
1353 unsigned int txbds_ready;
1354 unsigned int c_index;
1355 struct sk_buff *skb;
1356
1357 /* Clear status before servicing to reduce spurious interrupts */
1358 if (ring->index == DESC_INDEX)
1359 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_TXDMA_DONE,
1360 INTRL2_CPU_CLEAR);
1361 else
1362 bcmgenet_intrl2_1_writel(priv, (1 << ring->index),
1363 INTRL2_CPU_CLEAR);
1364
1365 /* Compute how many buffers are transmitted since last xmit call */
1366 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX)
1367 & DMA_C_INDEX_MASK;
1368 txbds_ready = (c_index - ring->c_index) & DMA_C_INDEX_MASK;
1369
1370 netif_dbg(priv, tx_done, dev,
1371 "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n",
1372 __func__, ring->index, ring->c_index, c_index, txbds_ready);
1373
1374 /* Reclaim transmitted buffers */
1375 while (txbds_processed < txbds_ready) {
1376 skb = bcmgenet_free_tx_cb(&priv->pdev->dev,
1377 &priv->tx_cbs[ring->clean_ptr]);
1378 if (skb) {
1379 pkts_compl++;
1380 bytes_compl += GENET_CB(skb)->bytes_sent;
1381 dev_consume_skb_any(skb);
1382 }
1383
1384 txbds_processed++;
1385 if (likely(ring->clean_ptr < ring->end_ptr))
1386 ring->clean_ptr++;
1387 else
1388 ring->clean_ptr = ring->cb_ptr;
1389 }
1390
1391 ring->free_bds += txbds_processed;
1392 ring->c_index = c_index;
1393
1394 ring->packets += pkts_compl;
1395 ring->bytes += bytes_compl;
1396
1397 netdev_tx_completed_queue(netdev_get_tx_queue(dev, ring->queue),
1398 pkts_compl, bytes_compl);
1399
1400 return txbds_processed;
1401 }
1402
1403 static unsigned int bcmgenet_tx_reclaim(struct net_device *dev,
1404 struct bcmgenet_tx_ring *ring)
1405 {
1406 unsigned int released;
1407
1408 spin_lock_bh(&ring->lock);
1409 released = __bcmgenet_tx_reclaim(dev, ring);
1410 spin_unlock_bh(&ring->lock);
1411
1412 return released;
1413 }
1414
1415 static int bcmgenet_tx_poll(struct napi_struct *napi, int budget)
1416 {
1417 struct bcmgenet_tx_ring *ring =
1418 container_of(napi, struct bcmgenet_tx_ring, napi);
1419 unsigned int work_done = 0;
1420 struct netdev_queue *txq;
1421
1422 spin_lock(&ring->lock);
1423 work_done = __bcmgenet_tx_reclaim(ring->priv->dev, ring);
1424 if (ring->free_bds > (MAX_SKB_FRAGS + 1)) {
1425 txq = netdev_get_tx_queue(ring->priv->dev, ring->queue);
1426 netif_tx_wake_queue(txq);
1427 }
1428 spin_unlock(&ring->lock);
1429
1430 if (work_done == 0) {
1431 napi_complete(napi);
1432 ring->int_enable(ring);
1433
1434 return 0;
1435 }
1436
1437 return budget;
1438 }
1439
1440 static void bcmgenet_tx_reclaim_all(struct net_device *dev)
1441 {
1442 struct bcmgenet_priv *priv = netdev_priv(dev);
1443 int i;
1444
1445 if (netif_is_multiqueue(dev)) {
1446 for (i = 0; i < priv->hw_params->tx_queues; i++)
1447 bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]);
1448 }
1449
1450 bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]);
1451 }
1452
1453 /* Reallocate the SKB to put enough headroom in front of it and insert
1454 * the transmit checksum offsets in the descriptors
1455 */
1456 static struct sk_buff *bcmgenet_put_tx_csum(struct net_device *dev,
1457 struct sk_buff *skb)
1458 {
1459 struct status_64 *status = NULL;
1460 struct sk_buff *new_skb;
1461 u16 offset;
1462 u8 ip_proto;
1463 u16 ip_ver;
1464 u32 tx_csum_info;
1465
1466 if (unlikely(skb_headroom(skb) < sizeof(*status))) {
1467 /* If 64 byte status block enabled, must make sure skb has
1468 * enough headroom for us to insert 64B status block.
1469 */
1470 new_skb = skb_realloc_headroom(skb, sizeof(*status));
1471 dev_kfree_skb(skb);
1472 if (!new_skb) {
1473 dev->stats.tx_dropped++;
1474 return NULL;
1475 }
1476 skb = new_skb;
1477 }
1478
1479 skb_push(skb, sizeof(*status));
1480 status = (struct status_64 *)skb->data;
1481
1482 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1483 ip_ver = htons(skb->protocol);
1484 switch (ip_ver) {
1485 case ETH_P_IP:
1486 ip_proto = ip_hdr(skb)->protocol;
1487 break;
1488 case ETH_P_IPV6:
1489 ip_proto = ipv6_hdr(skb)->nexthdr;
1490 break;
1491 default:
1492 return skb;
1493 }
1494
1495 offset = skb_checksum_start_offset(skb) - sizeof(*status);
1496 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
1497 (offset + skb->csum_offset);
1498
1499 /* Set the length valid bit for TCP and UDP and just set
1500 * the special UDP flag for IPv4, else just set to 0.
1501 */
1502 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) {
1503 tx_csum_info |= STATUS_TX_CSUM_LV;
1504 if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP)
1505 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
1506 } else {
1507 tx_csum_info = 0;
1508 }
1509
1510 status->tx_csum_info = tx_csum_info;
1511 }
1512
1513 return skb;
1514 }
1515
1516 static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
1517 {
1518 struct bcmgenet_priv *priv = netdev_priv(dev);
1519 struct device *kdev = &priv->pdev->dev;
1520 struct bcmgenet_tx_ring *ring = NULL;
1521 struct enet_cb *tx_cb_ptr;
1522 struct netdev_queue *txq;
1523 int nr_frags, index;
1524 dma_addr_t mapping;
1525 unsigned int size;
1526 skb_frag_t *frag;
1527 u32 len_stat;
1528 int ret;
1529 int i;
1530
1531 index = skb_get_queue_mapping(skb);
1532 /* Mapping strategy:
1533 * queue_mapping = 0, unclassified, packet xmited through ring16
1534 * queue_mapping = 1, goes to ring 0. (highest priority queue
1535 * queue_mapping = 2, goes to ring 1.
1536 * queue_mapping = 3, goes to ring 2.
1537 * queue_mapping = 4, goes to ring 3.
1538 */
1539 if (index == 0)
1540 index = DESC_INDEX;
1541 else
1542 index -= 1;
1543
1544 ring = &priv->tx_rings[index];
1545 txq = netdev_get_tx_queue(dev, ring->queue);
1546
1547 nr_frags = skb_shinfo(skb)->nr_frags;
1548
1549 spin_lock(&ring->lock);
1550 if (ring->free_bds <= (nr_frags + 1)) {
1551 if (!netif_tx_queue_stopped(txq)) {
1552 netif_tx_stop_queue(txq);
1553 netdev_err(dev,
1554 "%s: tx ring %d full when queue %d awake\n",
1555 __func__, index, ring->queue);
1556 }
1557 ret = NETDEV_TX_BUSY;
1558 goto out;
1559 }
1560
1561 if (skb_padto(skb, ETH_ZLEN)) {
1562 ret = NETDEV_TX_OK;
1563 goto out;
1564 }
1565
1566 /* Retain how many bytes will be sent on the wire, without TSB inserted
1567 * by transmit checksum offload
1568 */
1569 GENET_CB(skb)->bytes_sent = skb->len;
1570
1571 /* set the SKB transmit checksum */
1572 if (priv->desc_64b_en) {
1573 skb = bcmgenet_put_tx_csum(dev, skb);
1574 if (!skb) {
1575 ret = NETDEV_TX_OK;
1576 goto out;
1577 }
1578 }
1579
1580 for (i = 0; i <= nr_frags; i++) {
1581 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1582
1583 BUG_ON(!tx_cb_ptr);
1584
1585 if (!i) {
1586 /* Transmit single SKB or head of fragment list */
1587 GENET_CB(skb)->first_cb = tx_cb_ptr;
1588 size = skb_headlen(skb);
1589 mapping = dma_map_single(kdev, skb->data, size,
1590 DMA_TO_DEVICE);
1591 } else {
1592 /* xmit fragment */
1593 frag = &skb_shinfo(skb)->frags[i - 1];
1594 size = skb_frag_size(frag);
1595 mapping = skb_frag_dma_map(kdev, frag, 0, size,
1596 DMA_TO_DEVICE);
1597 }
1598
1599 ret = dma_mapping_error(kdev, mapping);
1600 if (ret) {
1601 priv->mib.tx_dma_failed++;
1602 netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
1603 ret = NETDEV_TX_OK;
1604 goto out_unmap_frags;
1605 }
1606 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1607 dma_unmap_len_set(tx_cb_ptr, dma_len, size);
1608
1609 tx_cb_ptr->skb = skb;
1610
1611 len_stat = (size << DMA_BUFLENGTH_SHIFT) |
1612 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT);
1613
1614 if (!i) {
1615 len_stat |= DMA_TX_APPEND_CRC | DMA_SOP;
1616 if (skb->ip_summed == CHECKSUM_PARTIAL)
1617 len_stat |= DMA_TX_DO_CSUM;
1618 }
1619 if (i == nr_frags)
1620 len_stat |= DMA_EOP;
1621
1622 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, len_stat);
1623 }
1624
1625 GENET_CB(skb)->last_cb = tx_cb_ptr;
1626 skb_tx_timestamp(skb);
1627
1628 /* Decrement total BD count and advance our write pointer */
1629 ring->free_bds -= nr_frags + 1;
1630 ring->prod_index += nr_frags + 1;
1631 ring->prod_index &= DMA_P_INDEX_MASK;
1632
1633 netdev_tx_sent_queue(txq, GENET_CB(skb)->bytes_sent);
1634
1635 if (ring->free_bds <= (MAX_SKB_FRAGS + 1))
1636 netif_tx_stop_queue(txq);
1637
1638 if (!skb->xmit_more || netif_xmit_stopped(txq))
1639 /* Packets are ready, update producer index */
1640 bcmgenet_tdma_ring_writel(priv, ring->index,
1641 ring->prod_index, TDMA_PROD_INDEX);
1642 out:
1643 spin_unlock(&ring->lock);
1644
1645 return ret;
1646
1647 out_unmap_frags:
1648 /* Back up for failed control block mapping */
1649 bcmgenet_put_txcb(priv, ring);
1650
1651 /* Unmap successfully mapped control blocks */
1652 while (i-- > 0) {
1653 tx_cb_ptr = bcmgenet_put_txcb(priv, ring);
1654 bcmgenet_free_tx_cb(kdev, tx_cb_ptr);
1655 }
1656
1657 dev_kfree_skb(skb);
1658 goto out;
1659 }
1660
1661 static struct sk_buff *bcmgenet_rx_refill(struct bcmgenet_priv *priv,
1662 struct enet_cb *cb)
1663 {
1664 struct device *kdev = &priv->pdev->dev;
1665 struct sk_buff *skb;
1666 struct sk_buff *rx_skb;
1667 dma_addr_t mapping;
1668
1669 /* Allocate a new Rx skb */
1670 skb = netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT);
1671 if (!skb) {
1672 priv->mib.alloc_rx_buff_failed++;
1673 netif_err(priv, rx_err, priv->dev,
1674 "%s: Rx skb allocation failed\n", __func__);
1675 return NULL;
1676 }
1677
1678 /* DMA-map the new Rx skb */
1679 mapping = dma_map_single(kdev, skb->data, priv->rx_buf_len,
1680 DMA_FROM_DEVICE);
1681 if (dma_mapping_error(kdev, mapping)) {
1682 priv->mib.rx_dma_failed++;
1683 dev_kfree_skb_any(skb);
1684 netif_err(priv, rx_err, priv->dev,
1685 "%s: Rx skb DMA mapping failed\n", __func__);
1686 return NULL;
1687 }
1688
1689 /* Grab the current Rx skb from the ring and DMA-unmap it */
1690 rx_skb = bcmgenet_free_rx_cb(kdev, cb);
1691
1692 /* Put the new Rx skb on the ring */
1693 cb->skb = skb;
1694 dma_unmap_addr_set(cb, dma_addr, mapping);
1695 dma_unmap_len_set(cb, dma_len, priv->rx_buf_len);
1696 dmadesc_set_addr(priv, cb->bd_addr, mapping);
1697
1698 /* Return the current Rx skb to caller */
1699 return rx_skb;
1700 }
1701
1702 /* bcmgenet_desc_rx - descriptor based rx process.
1703 * this could be called from bottom half, or from NAPI polling method.
1704 */
1705 static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring,
1706 unsigned int budget)
1707 {
1708 struct bcmgenet_priv *priv = ring->priv;
1709 struct net_device *dev = priv->dev;
1710 struct enet_cb *cb;
1711 struct sk_buff *skb;
1712 u32 dma_length_status;
1713 unsigned long dma_flag;
1714 int len;
1715 unsigned int rxpktprocessed = 0, rxpkttoprocess;
1716 unsigned int p_index, mask;
1717 unsigned int discards;
1718 unsigned int chksum_ok = 0;
1719
1720 /* Clear status before servicing to reduce spurious interrupts */
1721 if (ring->index == DESC_INDEX) {
1722 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_DONE,
1723 INTRL2_CPU_CLEAR);
1724 } else {
1725 mask = 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index);
1726 bcmgenet_intrl2_1_writel(priv,
1727 mask,
1728 INTRL2_CPU_CLEAR);
1729 }
1730
1731 p_index = bcmgenet_rdma_ring_readl(priv, ring->index, RDMA_PROD_INDEX);
1732
1733 discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) &
1734 DMA_P_INDEX_DISCARD_CNT_MASK;
1735 if (discards > ring->old_discards) {
1736 discards = discards - ring->old_discards;
1737 ring->errors += discards;
1738 ring->old_discards += discards;
1739
1740 /* Clear HW register when we reach 75% of maximum 0xFFFF */
1741 if (ring->old_discards >= 0xC000) {
1742 ring->old_discards = 0;
1743 bcmgenet_rdma_ring_writel(priv, ring->index, 0,
1744 RDMA_PROD_INDEX);
1745 }
1746 }
1747
1748 p_index &= DMA_P_INDEX_MASK;
1749 rxpkttoprocess = (p_index - ring->c_index) & DMA_C_INDEX_MASK;
1750
1751 netif_dbg(priv, rx_status, dev,
1752 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
1753
1754 while ((rxpktprocessed < rxpkttoprocess) &&
1755 (rxpktprocessed < budget)) {
1756 cb = &priv->rx_cbs[ring->read_ptr];
1757 skb = bcmgenet_rx_refill(priv, cb);
1758
1759 if (unlikely(!skb)) {
1760 ring->dropped++;
1761 goto next;
1762 }
1763
1764 if (!priv->desc_64b_en) {
1765 dma_length_status =
1766 dmadesc_get_length_status(priv, cb->bd_addr);
1767 } else {
1768 struct status_64 *status;
1769
1770 status = (struct status_64 *)skb->data;
1771 dma_length_status = status->length_status;
1772 }
1773
1774 /* DMA flags and length are still valid no matter how
1775 * we got the Receive Status Vector (64B RSB or register)
1776 */
1777 dma_flag = dma_length_status & 0xffff;
1778 len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
1779
1780 netif_dbg(priv, rx_status, dev,
1781 "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
1782 __func__, p_index, ring->c_index,
1783 ring->read_ptr, dma_length_status);
1784
1785 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
1786 netif_err(priv, rx_status, dev,
1787 "dropping fragmented packet!\n");
1788 ring->errors++;
1789 dev_kfree_skb_any(skb);
1790 goto next;
1791 }
1792
1793 /* report errors */
1794 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
1795 DMA_RX_OV |
1796 DMA_RX_NO |
1797 DMA_RX_LG |
1798 DMA_RX_RXER))) {
1799 netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
1800 (unsigned int)dma_flag);
1801 if (dma_flag & DMA_RX_CRC_ERROR)
1802 dev->stats.rx_crc_errors++;
1803 if (dma_flag & DMA_RX_OV)
1804 dev->stats.rx_over_errors++;
1805 if (dma_flag & DMA_RX_NO)
1806 dev->stats.rx_frame_errors++;
1807 if (dma_flag & DMA_RX_LG)
1808 dev->stats.rx_length_errors++;
1809 dev->stats.rx_errors++;
1810 dev_kfree_skb_any(skb);
1811 goto next;
1812 } /* error packet */
1813
1814 chksum_ok = (dma_flag & priv->dma_rx_chk_bit) &&
1815 priv->desc_rxchk_en;
1816
1817 skb_put(skb, len);
1818 if (priv->desc_64b_en) {
1819 skb_pull(skb, 64);
1820 len -= 64;
1821 }
1822
1823 if (likely(chksum_ok))
1824 skb->ip_summed = CHECKSUM_UNNECESSARY;
1825
1826 /* remove hardware 2bytes added for IP alignment */
1827 skb_pull(skb, 2);
1828 len -= 2;
1829
1830 if (priv->crc_fwd_en) {
1831 skb_trim(skb, len - ETH_FCS_LEN);
1832 len -= ETH_FCS_LEN;
1833 }
1834
1835 /*Finish setting up the received SKB and send it to the kernel*/
1836 skb->protocol = eth_type_trans(skb, priv->dev);
1837 ring->packets++;
1838 ring->bytes += len;
1839 if (dma_flag & DMA_RX_MULT)
1840 dev->stats.multicast++;
1841
1842 /* Notify kernel */
1843 napi_gro_receive(&ring->napi, skb);
1844 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
1845
1846 next:
1847 rxpktprocessed++;
1848 if (likely(ring->read_ptr < ring->end_ptr))
1849 ring->read_ptr++;
1850 else
1851 ring->read_ptr = ring->cb_ptr;
1852
1853 ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK;
1854 bcmgenet_rdma_ring_writel(priv, ring->index, ring->c_index, RDMA_CONS_INDEX);
1855 }
1856
1857 return rxpktprocessed;
1858 }
1859
1860 /* Rx NAPI polling method */
1861 static int bcmgenet_rx_poll(struct napi_struct *napi, int budget)
1862 {
1863 struct bcmgenet_rx_ring *ring = container_of(napi,
1864 struct bcmgenet_rx_ring, napi);
1865 unsigned int work_done;
1866
1867 work_done = bcmgenet_desc_rx(ring, budget);
1868
1869 if (work_done < budget) {
1870 napi_complete_done(napi, work_done);
1871 ring->int_enable(ring);
1872 }
1873
1874 return work_done;
1875 }
1876
1877 /* Assign skb to RX DMA descriptor. */
1878 static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv,
1879 struct bcmgenet_rx_ring *ring)
1880 {
1881 struct enet_cb *cb;
1882 struct sk_buff *skb;
1883 int i;
1884
1885 netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
1886
1887 /* loop here for each buffer needing assign */
1888 for (i = 0; i < ring->size; i++) {
1889 cb = ring->cbs + i;
1890 skb = bcmgenet_rx_refill(priv, cb);
1891 if (skb)
1892 dev_consume_skb_any(skb);
1893 if (!cb->skb)
1894 return -ENOMEM;
1895 }
1896
1897 return 0;
1898 }
1899
1900 static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
1901 {
1902 struct sk_buff *skb;
1903 struct enet_cb *cb;
1904 int i;
1905
1906 for (i = 0; i < priv->num_rx_bds; i++) {
1907 cb = &priv->rx_cbs[i];
1908
1909 skb = bcmgenet_free_rx_cb(&priv->pdev->dev, cb);
1910 if (skb)
1911 dev_consume_skb_any(skb);
1912 }
1913 }
1914
1915 static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable)
1916 {
1917 u32 reg;
1918
1919 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1920 if (enable)
1921 reg |= mask;
1922 else
1923 reg &= ~mask;
1924 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
1925
1926 /* UniMAC stops on a packet boundary, wait for a full-size packet
1927 * to be processed
1928 */
1929 if (enable == 0)
1930 usleep_range(1000, 2000);
1931 }
1932
1933 static void reset_umac(struct bcmgenet_priv *priv)
1934 {
1935 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
1936 bcmgenet_rbuf_ctrl_set(priv, 0);
1937 udelay(10);
1938
1939 /* disable MAC while updating its registers */
1940 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1941
1942 /* issue soft reset with (rg)mii loopback to ensure a stable rxclk */
1943 bcmgenet_umac_writel(priv, CMD_SW_RESET | CMD_LCL_LOOP_EN, UMAC_CMD);
1944 udelay(2);
1945 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1946 }
1947
1948 static void bcmgenet_intr_disable(struct bcmgenet_priv *priv)
1949 {
1950 /* Mask all interrupts.*/
1951 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1952 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1953 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1954 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1955 }
1956
1957 static void bcmgenet_link_intr_enable(struct bcmgenet_priv *priv)
1958 {
1959 u32 int0_enable = 0;
1960
1961 /* Monitor cable plug/unplugged event for internal PHY, external PHY
1962 * and MoCA PHY
1963 */
1964 if (priv->internal_phy) {
1965 int0_enable |= UMAC_IRQ_LINK_EVENT;
1966 } else if (priv->ext_phy) {
1967 int0_enable |= UMAC_IRQ_LINK_EVENT;
1968 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
1969 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET)
1970 int0_enable |= UMAC_IRQ_LINK_EVENT;
1971 }
1972 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
1973 }
1974
1975 static void init_umac(struct bcmgenet_priv *priv)
1976 {
1977 struct device *kdev = &priv->pdev->dev;
1978 u32 reg;
1979 u32 int0_enable = 0;
1980
1981 dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
1982
1983 reset_umac(priv);
1984
1985 /* clear tx/rx counter */
1986 bcmgenet_umac_writel(priv,
1987 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT,
1988 UMAC_MIB_CTRL);
1989 bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
1990
1991 bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
1992
1993 /* init rx registers, enable ip header optimization */
1994 reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
1995 reg |= RBUF_ALIGN_2B;
1996 bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
1997
1998 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
1999 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
2000
2001 bcmgenet_intr_disable(priv);
2002
2003 /* Configure backpressure vectors for MoCA */
2004 if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
2005 reg = bcmgenet_bp_mc_get(priv);
2006 reg |= BIT(priv->hw_params->bp_in_en_shift);
2007
2008 /* bp_mask: back pressure mask */
2009 if (netif_is_multiqueue(priv->dev))
2010 reg |= priv->hw_params->bp_in_mask;
2011 else
2012 reg &= ~priv->hw_params->bp_in_mask;
2013 bcmgenet_bp_mc_set(priv, reg);
2014 }
2015
2016 /* Enable MDIO interrupts on GENET v3+ */
2017 if (priv->hw_params->flags & GENET_HAS_MDIO_INTR)
2018 int0_enable |= (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
2019
2020 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
2021
2022 dev_dbg(kdev, "done init umac\n");
2023 }
2024
2025 /* Initialize a Tx ring along with corresponding hardware registers */
2026 static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
2027 unsigned int index, unsigned int size,
2028 unsigned int start_ptr, unsigned int end_ptr)
2029 {
2030 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
2031 u32 words_per_bd = WORDS_PER_BD(priv);
2032 u32 flow_period_val = 0;
2033
2034 spin_lock_init(&ring->lock);
2035 ring->priv = priv;
2036 ring->index = index;
2037 if (index == DESC_INDEX) {
2038 ring->queue = 0;
2039 ring->int_enable = bcmgenet_tx_ring16_int_enable;
2040 ring->int_disable = bcmgenet_tx_ring16_int_disable;
2041 } else {
2042 ring->queue = index + 1;
2043 ring->int_enable = bcmgenet_tx_ring_int_enable;
2044 ring->int_disable = bcmgenet_tx_ring_int_disable;
2045 }
2046 ring->cbs = priv->tx_cbs + start_ptr;
2047 ring->size = size;
2048 ring->clean_ptr = start_ptr;
2049 ring->c_index = 0;
2050 ring->free_bds = size;
2051 ring->write_ptr = start_ptr;
2052 ring->cb_ptr = start_ptr;
2053 ring->end_ptr = end_ptr - 1;
2054 ring->prod_index = 0;
2055
2056 /* Set flow period for ring != 16 */
2057 if (index != DESC_INDEX)
2058 flow_period_val = ENET_MAX_MTU_SIZE << 16;
2059
2060 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
2061 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
2062 bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
2063 /* Disable rate control for now */
2064 bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
2065 TDMA_FLOW_PERIOD);
2066 bcmgenet_tdma_ring_writel(priv, index,
2067 ((size << DMA_RING_SIZE_SHIFT) |
2068 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
2069
2070 /* Set start and end address, read and write pointers */
2071 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2072 DMA_START_ADDR);
2073 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2074 TDMA_READ_PTR);
2075 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2076 TDMA_WRITE_PTR);
2077 bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
2078 DMA_END_ADDR);
2079
2080 /* Initialize Tx NAPI */
2081 netif_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll,
2082 NAPI_POLL_WEIGHT);
2083 }
2084
2085 /* Initialize a RDMA ring */
2086 static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
2087 unsigned int index, unsigned int size,
2088 unsigned int start_ptr, unsigned int end_ptr)
2089 {
2090 struct bcmgenet_rx_ring *ring = &priv->rx_rings[index];
2091 u32 words_per_bd = WORDS_PER_BD(priv);
2092 int ret;
2093
2094 ring->priv = priv;
2095 ring->index = index;
2096 if (index == DESC_INDEX) {
2097 ring->int_enable = bcmgenet_rx_ring16_int_enable;
2098 ring->int_disable = bcmgenet_rx_ring16_int_disable;
2099 } else {
2100 ring->int_enable = bcmgenet_rx_ring_int_enable;
2101 ring->int_disable = bcmgenet_rx_ring_int_disable;
2102 }
2103 ring->cbs = priv->rx_cbs + start_ptr;
2104 ring->size = size;
2105 ring->c_index = 0;
2106 ring->read_ptr = start_ptr;
2107 ring->cb_ptr = start_ptr;
2108 ring->end_ptr = end_ptr - 1;
2109
2110 ret = bcmgenet_alloc_rx_buffers(priv, ring);
2111 if (ret)
2112 return ret;
2113
2114 /* Initialize Rx NAPI */
2115 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll,
2116 NAPI_POLL_WEIGHT);
2117
2118 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
2119 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
2120 bcmgenet_rdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
2121 bcmgenet_rdma_ring_writel(priv, index,
2122 ((size << DMA_RING_SIZE_SHIFT) |
2123 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
2124 bcmgenet_rdma_ring_writel(priv, index,
2125 (DMA_FC_THRESH_LO <<
2126 DMA_XOFF_THRESHOLD_SHIFT) |
2127 DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
2128
2129 /* Set start and end address, read and write pointers */
2130 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2131 DMA_START_ADDR);
2132 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2133 RDMA_READ_PTR);
2134 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2135 RDMA_WRITE_PTR);
2136 bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
2137 DMA_END_ADDR);
2138
2139 return ret;
2140 }
2141
2142 static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv)
2143 {
2144 unsigned int i;
2145 struct bcmgenet_tx_ring *ring;
2146
2147 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2148 ring = &priv->tx_rings[i];
2149 napi_enable(&ring->napi);
2150 ring->int_enable(ring);
2151 }
2152
2153 ring = &priv->tx_rings[DESC_INDEX];
2154 napi_enable(&ring->napi);
2155 ring->int_enable(ring);
2156 }
2157
2158 static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv)
2159 {
2160 unsigned int i;
2161 struct bcmgenet_tx_ring *ring;
2162
2163 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2164 ring = &priv->tx_rings[i];
2165 napi_disable(&ring->napi);
2166 }
2167
2168 ring = &priv->tx_rings[DESC_INDEX];
2169 napi_disable(&ring->napi);
2170 }
2171
2172 static void bcmgenet_fini_tx_napi(struct bcmgenet_priv *priv)
2173 {
2174 unsigned int i;
2175 struct bcmgenet_tx_ring *ring;
2176
2177 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2178 ring = &priv->tx_rings[i];
2179 netif_napi_del(&ring->napi);
2180 }
2181
2182 ring = &priv->tx_rings[DESC_INDEX];
2183 netif_napi_del(&ring->napi);
2184 }
2185
2186 /* Initialize Tx queues
2187 *
2188 * Queues 0-3 are priority-based, each one has 32 descriptors,
2189 * with queue 0 being the highest priority queue.
2190 *
2191 * Queue 16 is the default Tx queue with
2192 * GENET_Q16_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors.
2193 *
2194 * The transmit control block pool is then partitioned as follows:
2195 * - Tx queue 0 uses tx_cbs[0..31]
2196 * - Tx queue 1 uses tx_cbs[32..63]
2197 * - Tx queue 2 uses tx_cbs[64..95]
2198 * - Tx queue 3 uses tx_cbs[96..127]
2199 * - Tx queue 16 uses tx_cbs[128..255]
2200 */
2201 static void bcmgenet_init_tx_queues(struct net_device *dev)
2202 {
2203 struct bcmgenet_priv *priv = netdev_priv(dev);
2204 u32 i, dma_enable;
2205 u32 dma_ctrl, ring_cfg;
2206 u32 dma_priority[3] = {0, 0, 0};
2207
2208 dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL);
2209 dma_enable = dma_ctrl & DMA_EN;
2210 dma_ctrl &= ~DMA_EN;
2211 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
2212
2213 dma_ctrl = 0;
2214 ring_cfg = 0;
2215
2216 /* Enable strict priority arbiter mode */
2217 bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
2218
2219 /* Initialize Tx priority queues */
2220 for (i = 0; i < priv->hw_params->tx_queues; i++) {
2221 bcmgenet_init_tx_ring(priv, i, priv->hw_params->tx_bds_per_q,
2222 i * priv->hw_params->tx_bds_per_q,
2223 (i + 1) * priv->hw_params->tx_bds_per_q);
2224 ring_cfg |= (1 << i);
2225 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2226 dma_priority[DMA_PRIO_REG_INDEX(i)] |=
2227 ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i));
2228 }
2229
2230 /* Initialize Tx default queue 16 */
2231 bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_Q16_TX_BD_CNT,
2232 priv->hw_params->tx_queues *
2233 priv->hw_params->tx_bds_per_q,
2234 TOTAL_DESC);
2235 ring_cfg |= (1 << DESC_INDEX);
2236 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2237 dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |=
2238 ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) <<
2239 DMA_PRIO_REG_SHIFT(DESC_INDEX));
2240
2241 /* Set Tx queue priorities */
2242 bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0);
2243 bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1);
2244 bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2);
2245
2246 /* Enable Tx queues */
2247 bcmgenet_tdma_writel(priv, ring_cfg, DMA_RING_CFG);
2248
2249 /* Enable Tx DMA */
2250 if (dma_enable)
2251 dma_ctrl |= DMA_EN;
2252 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
2253 }
2254
2255 static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv)
2256 {
2257 unsigned int i;
2258 struct bcmgenet_rx_ring *ring;
2259
2260 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2261 ring = &priv->rx_rings[i];
2262 napi_enable(&ring->napi);
2263 ring->int_enable(ring);
2264 }
2265
2266 ring = &priv->rx_rings[DESC_INDEX];
2267 napi_enable(&ring->napi);
2268 ring->int_enable(ring);
2269 }
2270
2271 static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv)
2272 {
2273 unsigned int i;
2274 struct bcmgenet_rx_ring *ring;
2275
2276 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2277 ring = &priv->rx_rings[i];
2278 napi_disable(&ring->napi);
2279 }
2280
2281 ring = &priv->rx_rings[DESC_INDEX];
2282 napi_disable(&ring->napi);
2283 }
2284
2285 static void bcmgenet_fini_rx_napi(struct bcmgenet_priv *priv)
2286 {
2287 unsigned int i;
2288 struct bcmgenet_rx_ring *ring;
2289
2290 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2291 ring = &priv->rx_rings[i];
2292 netif_napi_del(&ring->napi);
2293 }
2294
2295 ring = &priv->rx_rings[DESC_INDEX];
2296 netif_napi_del(&ring->napi);
2297 }
2298
2299 /* Initialize Rx queues
2300 *
2301 * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be
2302 * used to direct traffic to these queues.
2303 *
2304 * Queue 16 is the default Rx queue with GENET_Q16_RX_BD_CNT descriptors.
2305 */
2306 static int bcmgenet_init_rx_queues(struct net_device *dev)
2307 {
2308 struct bcmgenet_priv *priv = netdev_priv(dev);
2309 u32 i;
2310 u32 dma_enable;
2311 u32 dma_ctrl;
2312 u32 ring_cfg;
2313 int ret;
2314
2315 dma_ctrl = bcmgenet_rdma_readl(priv, DMA_CTRL);
2316 dma_enable = dma_ctrl & DMA_EN;
2317 dma_ctrl &= ~DMA_EN;
2318 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2319
2320 dma_ctrl = 0;
2321 ring_cfg = 0;
2322
2323 /* Initialize Rx priority queues */
2324 for (i = 0; i < priv->hw_params->rx_queues; i++) {
2325 ret = bcmgenet_init_rx_ring(priv, i,
2326 priv->hw_params->rx_bds_per_q,
2327 i * priv->hw_params->rx_bds_per_q,
2328 (i + 1) *
2329 priv->hw_params->rx_bds_per_q);
2330 if (ret)
2331 return ret;
2332
2333 ring_cfg |= (1 << i);
2334 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2335 }
2336
2337 /* Initialize Rx default queue 16 */
2338 ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, GENET_Q16_RX_BD_CNT,
2339 priv->hw_params->rx_queues *
2340 priv->hw_params->rx_bds_per_q,
2341 TOTAL_DESC);
2342 if (ret)
2343 return ret;
2344
2345 ring_cfg |= (1 << DESC_INDEX);
2346 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2347
2348 /* Enable rings */
2349 bcmgenet_rdma_writel(priv, ring_cfg, DMA_RING_CFG);
2350
2351 /* Configure ring as descriptor ring and re-enable DMA if enabled */
2352 if (dma_enable)
2353 dma_ctrl |= DMA_EN;
2354 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2355
2356 return 0;
2357 }
2358
2359 static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
2360 {
2361 int ret = 0;
2362 int timeout = 0;
2363 u32 reg;
2364 u32 dma_ctrl;
2365 int i;
2366
2367 /* Disable TDMA to stop add more frames in TX DMA */
2368 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2369 reg &= ~DMA_EN;
2370 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2371
2372 /* Check TDMA status register to confirm TDMA is disabled */
2373 while (timeout++ < DMA_TIMEOUT_VAL) {
2374 reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
2375 if (reg & DMA_DISABLED)
2376 break;
2377
2378 udelay(1);
2379 }
2380
2381 if (timeout == DMA_TIMEOUT_VAL) {
2382 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n");
2383 ret = -ETIMEDOUT;
2384 }
2385
2386 /* Wait 10ms for packet drain in both tx and rx dma */
2387 usleep_range(10000, 20000);
2388
2389 /* Disable RDMA */
2390 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2391 reg &= ~DMA_EN;
2392 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2393
2394 timeout = 0;
2395 /* Check RDMA status register to confirm RDMA is disabled */
2396 while (timeout++ < DMA_TIMEOUT_VAL) {
2397 reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
2398 if (reg & DMA_DISABLED)
2399 break;
2400
2401 udelay(1);
2402 }
2403
2404 if (timeout == DMA_TIMEOUT_VAL) {
2405 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n");
2406 ret = -ETIMEDOUT;
2407 }
2408
2409 dma_ctrl = 0;
2410 for (i = 0; i < priv->hw_params->rx_queues; i++)
2411 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2412 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2413 reg &= ~dma_ctrl;
2414 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2415
2416 dma_ctrl = 0;
2417 for (i = 0; i < priv->hw_params->tx_queues; i++)
2418 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2419 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2420 reg &= ~dma_ctrl;
2421 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2422
2423 return ret;
2424 }
2425
2426 static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
2427 {
2428 struct netdev_queue *txq;
2429 struct sk_buff *skb;
2430 struct enet_cb *cb;
2431 int i;
2432
2433 bcmgenet_fini_rx_napi(priv);
2434 bcmgenet_fini_tx_napi(priv);
2435
2436 for (i = 0; i < priv->num_tx_bds; i++) {
2437 cb = priv->tx_cbs + i;
2438 skb = bcmgenet_free_tx_cb(&priv->pdev->dev, cb);
2439 if (skb)
2440 dev_kfree_skb(skb);
2441 }
2442
2443 for (i = 0; i < priv->hw_params->tx_queues; i++) {
2444 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[i].queue);
2445 netdev_tx_reset_queue(txq);
2446 }
2447
2448 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[DESC_INDEX].queue);
2449 netdev_tx_reset_queue(txq);
2450
2451 bcmgenet_free_rx_buffers(priv);
2452 kfree(priv->rx_cbs);
2453 kfree(priv->tx_cbs);
2454 }
2455
2456 /* init_edma: Initialize DMA control register */
2457 static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
2458 {
2459 int ret;
2460 unsigned int i;
2461 struct enet_cb *cb;
2462
2463 netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
2464
2465 /* Initialize common Rx ring structures */
2466 priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
2467 priv->num_rx_bds = TOTAL_DESC;
2468 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb),
2469 GFP_KERNEL);
2470 if (!priv->rx_cbs)
2471 return -ENOMEM;
2472
2473 for (i = 0; i < priv->num_rx_bds; i++) {
2474 cb = priv->rx_cbs + i;
2475 cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE;
2476 }
2477
2478 /* Initialize common TX ring structures */
2479 priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
2480 priv->num_tx_bds = TOTAL_DESC;
2481 priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb),
2482 GFP_KERNEL);
2483 if (!priv->tx_cbs) {
2484 kfree(priv->rx_cbs);
2485 return -ENOMEM;
2486 }
2487
2488 for (i = 0; i < priv->num_tx_bds; i++) {
2489 cb = priv->tx_cbs + i;
2490 cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE;
2491 }
2492
2493 /* Init rDma */
2494 bcmgenet_rdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2495
2496 /* Initialize Rx queues */
2497 ret = bcmgenet_init_rx_queues(priv->dev);
2498 if (ret) {
2499 netdev_err(priv->dev, "failed to initialize Rx queues\n");
2500 bcmgenet_free_rx_buffers(priv);
2501 kfree(priv->rx_cbs);
2502 kfree(priv->tx_cbs);
2503 return ret;
2504 }
2505
2506 /* Init tDma */
2507 bcmgenet_tdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2508
2509 /* Initialize Tx queues */
2510 bcmgenet_init_tx_queues(priv->dev);
2511
2512 return 0;
2513 }
2514
2515 /* Interrupt bottom half */
2516 static void bcmgenet_irq_task(struct work_struct *work)
2517 {
2518 unsigned int status;
2519 struct bcmgenet_priv *priv = container_of(
2520 work, struct bcmgenet_priv, bcmgenet_irq_work);
2521
2522 netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
2523
2524 spin_lock_irq(&priv->lock);
2525 status = priv->irq0_stat;
2526 priv->irq0_stat = 0;
2527 spin_unlock_irq(&priv->lock);
2528
2529 /* Link UP/DOWN event */
2530 if (status & UMAC_IRQ_LINK_EVENT) {
2531 priv->dev->phydev->link = !!(status & UMAC_IRQ_LINK_UP);
2532 phy_mac_interrupt(priv->dev->phydev);
2533 }
2534 }
2535
2536 /* bcmgenet_isr1: handle Rx and Tx priority queues */
2537 static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
2538 {
2539 struct bcmgenet_priv *priv = dev_id;
2540 struct bcmgenet_rx_ring *rx_ring;
2541 struct bcmgenet_tx_ring *tx_ring;
2542 unsigned int index, status;
2543
2544 /* Read irq status */
2545 status = bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
2546 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
2547
2548 /* clear interrupts */
2549 bcmgenet_intrl2_1_writel(priv, status, INTRL2_CPU_CLEAR);
2550
2551 netif_dbg(priv, intr, priv->dev,
2552 "%s: IRQ=0x%x\n", __func__, status);
2553
2554 /* Check Rx priority queue interrupts */
2555 for (index = 0; index < priv->hw_params->rx_queues; index++) {
2556 if (!(status & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index)))
2557 continue;
2558
2559 rx_ring = &priv->rx_rings[index];
2560
2561 if (likely(napi_schedule_prep(&rx_ring->napi))) {
2562 rx_ring->int_disable(rx_ring);
2563 __napi_schedule_irqoff(&rx_ring->napi);
2564 }
2565 }
2566
2567 /* Check Tx priority queue interrupts */
2568 for (index = 0; index < priv->hw_params->tx_queues; index++) {
2569 if (!(status & BIT(index)))
2570 continue;
2571
2572 tx_ring = &priv->tx_rings[index];
2573
2574 if (likely(napi_schedule_prep(&tx_ring->napi))) {
2575 tx_ring->int_disable(tx_ring);
2576 __napi_schedule_irqoff(&tx_ring->napi);
2577 }
2578 }
2579
2580 return IRQ_HANDLED;
2581 }
2582
2583 /* bcmgenet_isr0: handle Rx and Tx default queues + other stuff */
2584 static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
2585 {
2586 struct bcmgenet_priv *priv = dev_id;
2587 struct bcmgenet_rx_ring *rx_ring;
2588 struct bcmgenet_tx_ring *tx_ring;
2589 unsigned int status;
2590 unsigned long flags;
2591
2592 /* Read irq status */
2593 status = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
2594 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
2595
2596 /* clear interrupts */
2597 bcmgenet_intrl2_0_writel(priv, status, INTRL2_CPU_CLEAR);
2598
2599 netif_dbg(priv, intr, priv->dev,
2600 "IRQ=0x%x\n", status);
2601
2602 if (status & UMAC_IRQ_RXDMA_DONE) {
2603 rx_ring = &priv->rx_rings[DESC_INDEX];
2604
2605 if (likely(napi_schedule_prep(&rx_ring->napi))) {
2606 rx_ring->int_disable(rx_ring);
2607 __napi_schedule_irqoff(&rx_ring->napi);
2608 }
2609 }
2610
2611 if (status & UMAC_IRQ_TXDMA_DONE) {
2612 tx_ring = &priv->tx_rings[DESC_INDEX];
2613
2614 if (likely(napi_schedule_prep(&tx_ring->napi))) {
2615 tx_ring->int_disable(tx_ring);
2616 __napi_schedule_irqoff(&tx_ring->napi);
2617 }
2618 }
2619
2620 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
2621 status & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
2622 wake_up(&priv->wq);
2623 }
2624
2625 /* all other interested interrupts handled in bottom half */
2626 status &= UMAC_IRQ_LINK_EVENT;
2627 if (status) {
2628 /* Save irq status for bottom-half processing. */
2629 spin_lock_irqsave(&priv->lock, flags);
2630 priv->irq0_stat |= status;
2631 spin_unlock_irqrestore(&priv->lock, flags);
2632
2633 schedule_work(&priv->bcmgenet_irq_work);
2634 }
2635
2636 return IRQ_HANDLED;
2637 }
2638
2639 static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id)
2640 {
2641 struct bcmgenet_priv *priv = dev_id;
2642
2643 pm_wakeup_event(&priv->pdev->dev, 0);
2644
2645 return IRQ_HANDLED;
2646 }
2647
2648 #ifdef CONFIG_NET_POLL_CONTROLLER
2649 static void bcmgenet_poll_controller(struct net_device *dev)
2650 {
2651 struct bcmgenet_priv *priv = netdev_priv(dev);
2652
2653 /* Invoke the main RX/TX interrupt handler */
2654 disable_irq(priv->irq0);
2655 bcmgenet_isr0(priv->irq0, priv);
2656 enable_irq(priv->irq0);
2657
2658 /* And the interrupt handler for RX/TX priority queues */
2659 disable_irq(priv->irq1);
2660 bcmgenet_isr1(priv->irq1, priv);
2661 enable_irq(priv->irq1);
2662 }
2663 #endif
2664
2665 static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
2666 {
2667 u32 reg;
2668
2669 reg = bcmgenet_rbuf_ctrl_get(priv);
2670 reg |= BIT(1);
2671 bcmgenet_rbuf_ctrl_set(priv, reg);
2672 udelay(10);
2673
2674 reg &= ~BIT(1);
2675 bcmgenet_rbuf_ctrl_set(priv, reg);
2676 udelay(10);
2677 }
2678
2679 static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
2680 unsigned char *addr)
2681 {
2682 bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) |
2683 (addr[2] << 8) | addr[3], UMAC_MAC0);
2684 bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1);
2685 }
2686
2687 /* Returns a reusable dma control register value */
2688 static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
2689 {
2690 u32 reg;
2691 u32 dma_ctrl;
2692
2693 /* disable DMA */
2694 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
2695 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2696 reg &= ~dma_ctrl;
2697 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2698
2699 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2700 reg &= ~dma_ctrl;
2701 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2702
2703 bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
2704 udelay(10);
2705 bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
2706
2707 return dma_ctrl;
2708 }
2709
2710 static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
2711 {
2712 u32 reg;
2713
2714 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2715 reg |= dma_ctrl;
2716 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2717
2718 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2719 reg |= dma_ctrl;
2720 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2721 }
2722
2723 /* bcmgenet_hfb_clear
2724 *
2725 * Clear Hardware Filter Block and disable all filtering.
2726 */
2727 static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv)
2728 {
2729 u32 i;
2730
2731 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_CTRL);
2732 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS);
2733 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS + 4);
2734
2735 for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++)
2736 bcmgenet_rdma_writel(priv, 0x0, i);
2737
2738 for (i = 0; i < (priv->hw_params->hfb_filter_cnt / 4); i++)
2739 bcmgenet_hfb_reg_writel(priv, 0x0,
2740 HFB_FLT_LEN_V3PLUS + i * sizeof(u32));
2741
2742 for (i = 0; i < priv->hw_params->hfb_filter_cnt *
2743 priv->hw_params->hfb_filter_size; i++)
2744 bcmgenet_hfb_writel(priv, 0x0, i * sizeof(u32));
2745 }
2746
2747 static void bcmgenet_hfb_init(struct bcmgenet_priv *priv)
2748 {
2749 if (GENET_IS_V1(priv) || GENET_IS_V2(priv))
2750 return;
2751
2752 bcmgenet_hfb_clear(priv);
2753 }
2754
2755 static void bcmgenet_netif_start(struct net_device *dev)
2756 {
2757 struct bcmgenet_priv *priv = netdev_priv(dev);
2758
2759 /* Start the network engine */
2760 bcmgenet_enable_rx_napi(priv);
2761
2762 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
2763
2764 netif_tx_start_all_queues(dev);
2765 bcmgenet_enable_tx_napi(priv);
2766
2767 /* Monitor link interrupts now */
2768 bcmgenet_link_intr_enable(priv);
2769
2770 phy_start(dev->phydev);
2771 }
2772
2773 static int bcmgenet_open(struct net_device *dev)
2774 {
2775 struct bcmgenet_priv *priv = netdev_priv(dev);
2776 unsigned long dma_ctrl;
2777 u32 reg;
2778 int ret;
2779
2780 netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
2781
2782 /* Turn on the clock */
2783 clk_prepare_enable(priv->clk);
2784
2785 /* If this is an internal GPHY, power it back on now, before UniMAC is
2786 * brought out of reset as absolutely no UniMAC activity is allowed
2787 */
2788 if (priv->internal_phy)
2789 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
2790
2791 /* take MAC out of reset */
2792 bcmgenet_umac_reset(priv);
2793
2794 init_umac(priv);
2795
2796 /* Make sure we reflect the value of CRC_CMD_FWD */
2797 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2798 priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
2799
2800 bcmgenet_set_hw_addr(priv, dev->dev_addr);
2801
2802 if (priv->internal_phy) {
2803 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2804 reg |= EXT_ENERGY_DET_MASK;
2805 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2806 }
2807
2808 /* Disable RX/TX DMA and flush TX queues */
2809 dma_ctrl = bcmgenet_dma_disable(priv);
2810
2811 /* Reinitialize TDMA and RDMA and SW housekeeping */
2812 ret = bcmgenet_init_dma(priv);
2813 if (ret) {
2814 netdev_err(dev, "failed to initialize DMA\n");
2815 goto err_clk_disable;
2816 }
2817
2818 /* Always enable ring 16 - descriptor ring */
2819 bcmgenet_enable_dma(priv, dma_ctrl);
2820
2821 /* HFB init */
2822 bcmgenet_hfb_init(priv);
2823
2824 ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
2825 dev->name, priv);
2826 if (ret < 0) {
2827 netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
2828 goto err_fini_dma;
2829 }
2830
2831 ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
2832 dev->name, priv);
2833 if (ret < 0) {
2834 netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
2835 goto err_irq0;
2836 }
2837
2838 ret = bcmgenet_mii_probe(dev);
2839 if (ret) {
2840 netdev_err(dev, "failed to connect to PHY\n");
2841 goto err_irq1;
2842 }
2843
2844 bcmgenet_netif_start(dev);
2845
2846 return 0;
2847
2848 err_irq1:
2849 free_irq(priv->irq1, priv);
2850 err_irq0:
2851 free_irq(priv->irq0, priv);
2852 err_fini_dma:
2853 bcmgenet_dma_teardown(priv);
2854 bcmgenet_fini_dma(priv);
2855 err_clk_disable:
2856 if (priv->internal_phy)
2857 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
2858 clk_disable_unprepare(priv->clk);
2859 return ret;
2860 }
2861
2862 static void bcmgenet_netif_stop(struct net_device *dev)
2863 {
2864 struct bcmgenet_priv *priv = netdev_priv(dev);
2865
2866 bcmgenet_disable_tx_napi(priv);
2867 netif_tx_stop_all_queues(dev);
2868
2869 /* Disable MAC receive */
2870 umac_enable_set(priv, CMD_RX_EN, false);
2871
2872 bcmgenet_dma_teardown(priv);
2873
2874 /* Disable MAC transmit. TX DMA disabled must be done before this */
2875 umac_enable_set(priv, CMD_TX_EN, false);
2876
2877 phy_stop(dev->phydev);
2878 bcmgenet_disable_rx_napi(priv);
2879 bcmgenet_intr_disable(priv);
2880
2881 /* Wait for pending work items to complete. Since interrupts are
2882 * disabled no new work will be scheduled.
2883 */
2884 cancel_work_sync(&priv->bcmgenet_irq_work);
2885
2886 priv->old_link = -1;
2887 priv->old_speed = -1;
2888 priv->old_duplex = -1;
2889 priv->old_pause = -1;
2890
2891 /* tx reclaim */
2892 bcmgenet_tx_reclaim_all(dev);
2893 bcmgenet_fini_dma(priv);
2894 }
2895
2896 static int bcmgenet_close(struct net_device *dev)
2897 {
2898 struct bcmgenet_priv *priv = netdev_priv(dev);
2899 int ret = 0;
2900
2901 netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
2902
2903 bcmgenet_netif_stop(dev);
2904
2905 /* Really kill the PHY state machine and disconnect from it */
2906 phy_disconnect(dev->phydev);
2907
2908 free_irq(priv->irq0, priv);
2909 free_irq(priv->irq1, priv);
2910
2911 if (priv->internal_phy)
2912 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
2913
2914 clk_disable_unprepare(priv->clk);
2915
2916 return ret;
2917 }
2918
2919 static void bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring *ring)
2920 {
2921 struct bcmgenet_priv *priv = ring->priv;
2922 u32 p_index, c_index, intsts, intmsk;
2923 struct netdev_queue *txq;
2924 unsigned int free_bds;
2925 bool txq_stopped;
2926
2927 if (!netif_msg_tx_err(priv))
2928 return;
2929
2930 txq = netdev_get_tx_queue(priv->dev, ring->queue);
2931
2932 spin_lock(&ring->lock);
2933 if (ring->index == DESC_INDEX) {
2934 intsts = ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
2935 intmsk = UMAC_IRQ_TXDMA_DONE | UMAC_IRQ_TXDMA_MBDONE;
2936 } else {
2937 intsts = ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
2938 intmsk = 1 << ring->index;
2939 }
2940 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
2941 p_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_PROD_INDEX);
2942 txq_stopped = netif_tx_queue_stopped(txq);
2943 free_bds = ring->free_bds;
2944 spin_unlock(&ring->lock);
2945
2946 netif_err(priv, tx_err, priv->dev, "Ring %d queue %d status summary\n"
2947 "TX queue status: %s, interrupts: %s\n"
2948 "(sw)free_bds: %d (sw)size: %d\n"
2949 "(sw)p_index: %d (hw)p_index: %d\n"
2950 "(sw)c_index: %d (hw)c_index: %d\n"
2951 "(sw)clean_p: %d (sw)write_p: %d\n"
2952 "(sw)cb_ptr: %d (sw)end_ptr: %d\n",
2953 ring->index, ring->queue,
2954 txq_stopped ? "stopped" : "active",
2955 intsts & intmsk ? "enabled" : "disabled",
2956 free_bds, ring->size,
2957 ring->prod_index, p_index & DMA_P_INDEX_MASK,
2958 ring->c_index, c_index & DMA_C_INDEX_MASK,
2959 ring->clean_ptr, ring->write_ptr,
2960 ring->cb_ptr, ring->end_ptr);
2961 }
2962
2963 static void bcmgenet_timeout(struct net_device *dev)
2964 {
2965 struct bcmgenet_priv *priv = netdev_priv(dev);
2966 u32 int0_enable = 0;
2967 u32 int1_enable = 0;
2968 unsigned int q;
2969
2970 netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
2971
2972 for (q = 0; q < priv->hw_params->tx_queues; q++)
2973 bcmgenet_dump_tx_queue(&priv->tx_rings[q]);
2974 bcmgenet_dump_tx_queue(&priv->tx_rings[DESC_INDEX]);
2975
2976 bcmgenet_tx_reclaim_all(dev);
2977
2978 for (q = 0; q < priv->hw_params->tx_queues; q++)
2979 int1_enable |= (1 << q);
2980
2981 int0_enable = UMAC_IRQ_TXDMA_DONE;
2982
2983 /* Re-enable TX interrupts if disabled */
2984 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
2985 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
2986
2987 netif_trans_update(dev);
2988
2989 dev->stats.tx_errors++;
2990
2991 netif_tx_wake_all_queues(dev);
2992 }
2993
2994 #define MAX_MC_COUNT 16
2995
2996 static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
2997 unsigned char *addr,
2998 int *i,
2999 int *mc)
3000 {
3001 u32 reg;
3002
3003 bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1],
3004 UMAC_MDF_ADDR + (*i * 4));
3005 bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 |
3006 addr[4] << 8 | addr[5],
3007 UMAC_MDF_ADDR + ((*i + 1) * 4));
3008 reg = bcmgenet_umac_readl(priv, UMAC_MDF_CTRL);
3009 reg |= (1 << (MAX_MC_COUNT - *mc));
3010 bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
3011 *i += 2;
3012 (*mc)++;
3013 }
3014
3015 static void bcmgenet_set_rx_mode(struct net_device *dev)
3016 {
3017 struct bcmgenet_priv *priv = netdev_priv(dev);
3018 struct netdev_hw_addr *ha;
3019 int i, mc;
3020 u32 reg;
3021
3022 netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
3023
3024 /* Promiscuous mode */
3025 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
3026 if (dev->flags & IFF_PROMISC) {
3027 reg |= CMD_PROMISC;
3028 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3029 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
3030 return;
3031 } else {
3032 reg &= ~CMD_PROMISC;
3033 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3034 }
3035
3036 /* UniMac doesn't support ALLMULTI */
3037 if (dev->flags & IFF_ALLMULTI) {
3038 netdev_warn(dev, "ALLMULTI is not supported\n");
3039 return;
3040 }
3041
3042 /* update MDF filter */
3043 i = 0;
3044 mc = 0;
3045 /* Broadcast */
3046 bcmgenet_set_mdf_addr(priv, dev->broadcast, &i, &mc);
3047 /* my own address.*/
3048 bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i, &mc);
3049 /* Unicast list*/
3050 if (netdev_uc_count(dev) > (MAX_MC_COUNT - mc))
3051 return;
3052
3053 if (!netdev_uc_empty(dev))
3054 netdev_for_each_uc_addr(ha, dev)
3055 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
3056 /* Multicast */
3057 if (netdev_mc_empty(dev) || netdev_mc_count(dev) >= (MAX_MC_COUNT - mc))
3058 return;
3059
3060 netdev_for_each_mc_addr(ha, dev)
3061 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
3062 }
3063
3064 /* Set the hardware MAC address. */
3065 static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
3066 {
3067 struct sockaddr *addr = p;
3068
3069 /* Setting the MAC address at the hardware level is not possible
3070 * without disabling the UniMAC RX/TX enable bits.
3071 */
3072 if (netif_running(dev))
3073 return -EBUSY;
3074
3075 ether_addr_copy(dev->dev_addr, addr->sa_data);
3076
3077 return 0;
3078 }
3079
3080 static struct net_device_stats *bcmgenet_get_stats(struct net_device *dev)
3081 {
3082 struct bcmgenet_priv *priv = netdev_priv(dev);
3083 unsigned long tx_bytes = 0, tx_packets = 0;
3084 unsigned long rx_bytes = 0, rx_packets = 0;
3085 unsigned long rx_errors = 0, rx_dropped = 0;
3086 struct bcmgenet_tx_ring *tx_ring;
3087 struct bcmgenet_rx_ring *rx_ring;
3088 unsigned int q;
3089
3090 for (q = 0; q < priv->hw_params->tx_queues; q++) {
3091 tx_ring = &priv->tx_rings[q];
3092 tx_bytes += tx_ring->bytes;
3093 tx_packets += tx_ring->packets;
3094 }
3095 tx_ring = &priv->tx_rings[DESC_INDEX];
3096 tx_bytes += tx_ring->bytes;
3097 tx_packets += tx_ring->packets;
3098
3099 for (q = 0; q < priv->hw_params->rx_queues; q++) {
3100 rx_ring = &priv->rx_rings[q];
3101
3102 rx_bytes += rx_ring->bytes;
3103 rx_packets += rx_ring->packets;
3104 rx_errors += rx_ring->errors;
3105 rx_dropped += rx_ring->dropped;
3106 }
3107 rx_ring = &priv->rx_rings[DESC_INDEX];
3108 rx_bytes += rx_ring->bytes;
3109 rx_packets += rx_ring->packets;
3110 rx_errors += rx_ring->errors;
3111 rx_dropped += rx_ring->dropped;
3112
3113 dev->stats.tx_bytes = tx_bytes;
3114 dev->stats.tx_packets = tx_packets;
3115 dev->stats.rx_bytes = rx_bytes;
3116 dev->stats.rx_packets = rx_packets;
3117 dev->stats.rx_errors = rx_errors;
3118 dev->stats.rx_missed_errors = rx_errors;
3119 return &dev->stats;
3120 }
3121
3122 static const struct net_device_ops bcmgenet_netdev_ops = {
3123 .ndo_open = bcmgenet_open,
3124 .ndo_stop = bcmgenet_close,
3125 .ndo_start_xmit = bcmgenet_xmit,
3126 .ndo_tx_timeout = bcmgenet_timeout,
3127 .ndo_set_rx_mode = bcmgenet_set_rx_mode,
3128 .ndo_set_mac_address = bcmgenet_set_mac_addr,
3129 .ndo_do_ioctl = bcmgenet_ioctl,
3130 .ndo_set_features = bcmgenet_set_features,
3131 #ifdef CONFIG_NET_POLL_CONTROLLER
3132 .ndo_poll_controller = bcmgenet_poll_controller,
3133 #endif
3134 .ndo_get_stats = bcmgenet_get_stats,
3135 };
3136
3137 /* Array of GENET hardware parameters/characteristics */
3138 static struct bcmgenet_hw_params bcmgenet_hw_params[] = {
3139 [GENET_V1] = {
3140 .tx_queues = 0,
3141 .tx_bds_per_q = 0,
3142 .rx_queues = 0,
3143 .rx_bds_per_q = 0,
3144 .bp_in_en_shift = 16,
3145 .bp_in_mask = 0xffff,
3146 .hfb_filter_cnt = 16,
3147 .qtag_mask = 0x1F,
3148 .hfb_offset = 0x1000,
3149 .rdma_offset = 0x2000,
3150 .tdma_offset = 0x3000,
3151 .words_per_bd = 2,
3152 },
3153 [GENET_V2] = {
3154 .tx_queues = 4,
3155 .tx_bds_per_q = 32,
3156 .rx_queues = 0,
3157 .rx_bds_per_q = 0,
3158 .bp_in_en_shift = 16,
3159 .bp_in_mask = 0xffff,
3160 .hfb_filter_cnt = 16,
3161 .qtag_mask = 0x1F,
3162 .tbuf_offset = 0x0600,
3163 .hfb_offset = 0x1000,
3164 .hfb_reg_offset = 0x2000,
3165 .rdma_offset = 0x3000,
3166 .tdma_offset = 0x4000,
3167 .words_per_bd = 2,
3168 .flags = GENET_HAS_EXT,
3169 },
3170 [GENET_V3] = {
3171 .tx_queues = 4,
3172 .tx_bds_per_q = 32,
3173 .rx_queues = 0,
3174 .rx_bds_per_q = 0,
3175 .bp_in_en_shift = 17,
3176 .bp_in_mask = 0x1ffff,
3177 .hfb_filter_cnt = 48,
3178 .hfb_filter_size = 128,
3179 .qtag_mask = 0x3F,
3180 .tbuf_offset = 0x0600,
3181 .hfb_offset = 0x8000,
3182 .hfb_reg_offset = 0xfc00,
3183 .rdma_offset = 0x10000,
3184 .tdma_offset = 0x11000,
3185 .words_per_bd = 2,
3186 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR |
3187 GENET_HAS_MOCA_LINK_DET,
3188 },
3189 [GENET_V4] = {
3190 .tx_queues = 4,
3191 .tx_bds_per_q = 32,
3192 .rx_queues = 0,
3193 .rx_bds_per_q = 0,
3194 .bp_in_en_shift = 17,
3195 .bp_in_mask = 0x1ffff,
3196 .hfb_filter_cnt = 48,
3197 .hfb_filter_size = 128,
3198 .qtag_mask = 0x3F,
3199 .tbuf_offset = 0x0600,
3200 .hfb_offset = 0x8000,
3201 .hfb_reg_offset = 0xfc00,
3202 .rdma_offset = 0x2000,
3203 .tdma_offset = 0x4000,
3204 .words_per_bd = 3,
3205 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3206 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
3207 },
3208 [GENET_V5] = {
3209 .tx_queues = 4,
3210 .tx_bds_per_q = 32,
3211 .rx_queues = 0,
3212 .rx_bds_per_q = 0,
3213 .bp_in_en_shift = 17,
3214 .bp_in_mask = 0x1ffff,
3215 .hfb_filter_cnt = 48,
3216 .hfb_filter_size = 128,
3217 .qtag_mask = 0x3F,
3218 .tbuf_offset = 0x0600,
3219 .hfb_offset = 0x8000,
3220 .hfb_reg_offset = 0xfc00,
3221 .rdma_offset = 0x2000,
3222 .tdma_offset = 0x4000,
3223 .words_per_bd = 3,
3224 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3225 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
3226 },
3227 };
3228
3229 /* Infer hardware parameters from the detected GENET version */
3230 static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
3231 {
3232 struct bcmgenet_hw_params *params;
3233 u32 reg;
3234 u8 major;
3235 u16 gphy_rev;
3236
3237 if (GENET_IS_V5(priv) || GENET_IS_V4(priv)) {
3238 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3239 genet_dma_ring_regs = genet_dma_ring_regs_v4;
3240 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
3241 } else if (GENET_IS_V3(priv)) {
3242 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3243 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3244 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
3245 } else if (GENET_IS_V2(priv)) {
3246 bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
3247 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3248 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
3249 } else if (GENET_IS_V1(priv)) {
3250 bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
3251 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3252 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
3253 }
3254
3255 /* enum genet_version starts at 1 */
3256 priv->hw_params = &bcmgenet_hw_params[priv->version];
3257 params = priv->hw_params;
3258
3259 /* Read GENET HW version */
3260 reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
3261 major = (reg >> 24 & 0x0f);
3262 if (major == 6)
3263 major = 5;
3264 else if (major == 5)
3265 major = 4;
3266 else if (major == 0)
3267 major = 1;
3268 if (major != priv->version) {
3269 dev_err(&priv->pdev->dev,
3270 "GENET version mismatch, got: %d, configured for: %d\n",
3271 major, priv->version);
3272 }
3273
3274 /* Print the GENET core version */
3275 dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
3276 major, (reg >> 16) & 0x0f, reg & 0xffff);
3277
3278 /* Store the integrated PHY revision for the MDIO probing function
3279 * to pass this information to the PHY driver. The PHY driver expects
3280 * to find the PHY major revision in bits 15:8 while the GENET register
3281 * stores that information in bits 7:0, account for that.
3282 *
3283 * On newer chips, starting with PHY revision G0, a new scheme is
3284 * deployed similar to the Starfighter 2 switch with GPHY major
3285 * revision in bits 15:8 and patch level in bits 7:0. Major revision 0
3286 * is reserved as well as special value 0x01ff, we have a small
3287 * heuristic to check for the new GPHY revision and re-arrange things
3288 * so the GPHY driver is happy.
3289 */
3290 gphy_rev = reg & 0xffff;
3291
3292 if (GENET_IS_V5(priv)) {
3293 /* The EPHY revision should come from the MDIO registers of
3294 * the PHY not from GENET.
3295 */
3296 if (gphy_rev != 0) {
3297 pr_warn("GENET is reporting EPHY revision: 0x%04x\n",
3298 gphy_rev);
3299 }
3300 /* This is reserved so should require special treatment */
3301 } else if (gphy_rev == 0 || gphy_rev == 0x01ff) {
3302 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev);
3303 return;
3304 /* This is the good old scheme, just GPHY major, no minor nor patch */
3305 } else if ((gphy_rev & 0xf0) != 0) {
3306 priv->gphy_rev = gphy_rev << 8;
3307 /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */
3308 } else if ((gphy_rev & 0xff00) != 0) {
3309 priv->gphy_rev = gphy_rev;
3310 }
3311
3312 #ifdef CONFIG_PHYS_ADDR_T_64BIT
3313 if (!(params->flags & GENET_HAS_40BITS))
3314 pr_warn("GENET does not support 40-bits PA\n");
3315 #endif
3316
3317 pr_debug("Configuration for version: %d\n"
3318 "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n"
3319 "BP << en: %2d, BP msk: 0x%05x\n"
3320 "HFB count: %2d, QTAQ msk: 0x%05x\n"
3321 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
3322 "RDMA: 0x%05x, TDMA: 0x%05x\n"
3323 "Words/BD: %d\n",
3324 priv->version,
3325 params->tx_queues, params->tx_bds_per_q,
3326 params->rx_queues, params->rx_bds_per_q,
3327 params->bp_in_en_shift, params->bp_in_mask,
3328 params->hfb_filter_cnt, params->qtag_mask,
3329 params->tbuf_offset, params->hfb_offset,
3330 params->hfb_reg_offset,
3331 params->rdma_offset, params->tdma_offset,
3332 params->words_per_bd);
3333 }
3334
3335 static const struct of_device_id bcmgenet_match[] = {
3336 { .compatible = "brcm,genet-v1", .data = (void *)GENET_V1 },
3337 { .compatible = "brcm,genet-v2", .data = (void *)GENET_V2 },
3338 { .compatible = "brcm,genet-v3", .data = (void *)GENET_V3 },
3339 { .compatible = "brcm,genet-v4", .data = (void *)GENET_V4 },
3340 { .compatible = "brcm,genet-v5", .data = (void *)GENET_V5 },
3341 { },
3342 };
3343 MODULE_DEVICE_TABLE(of, bcmgenet_match);
3344
3345 static int bcmgenet_probe(struct platform_device *pdev)
3346 {
3347 struct bcmgenet_platform_data *pd = pdev->dev.platform_data;
3348 struct device_node *dn = pdev->dev.of_node;
3349 const struct of_device_id *of_id = NULL;
3350 struct bcmgenet_priv *priv;
3351 struct net_device *dev;
3352 const void *macaddr;
3353 struct resource *r;
3354 int err = -EIO;
3355 const char *phy_mode_str;
3356
3357 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */
3358 dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1,
3359 GENET_MAX_MQ_CNT + 1);
3360 if (!dev) {
3361 dev_err(&pdev->dev, "can't allocate net device\n");
3362 return -ENOMEM;
3363 }
3364
3365 if (dn) {
3366 of_id = of_match_node(bcmgenet_match, dn);
3367 if (!of_id)
3368 return -EINVAL;
3369 }
3370
3371 priv = netdev_priv(dev);
3372 priv->irq0 = platform_get_irq(pdev, 0);
3373 priv->irq1 = platform_get_irq(pdev, 1);
3374 priv->wol_irq = platform_get_irq(pdev, 2);
3375 if (!priv->irq0 || !priv->irq1) {
3376 dev_err(&pdev->dev, "can't find IRQs\n");
3377 err = -EINVAL;
3378 goto err;
3379 }
3380
3381 if (dn) {
3382 macaddr = of_get_mac_address(dn);
3383 if (!macaddr) {
3384 dev_err(&pdev->dev, "can't find MAC address\n");
3385 err = -EINVAL;
3386 goto err;
3387 }
3388 } else {
3389 macaddr = pd->mac_address;
3390 }
3391
3392 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3393 priv->base = devm_ioremap_resource(&pdev->dev, r);
3394 if (IS_ERR(priv->base)) {
3395 err = PTR_ERR(priv->base);
3396 goto err;
3397 }
3398
3399 spin_lock_init(&priv->lock);
3400
3401 SET_NETDEV_DEV(dev, &pdev->dev);
3402 dev_set_drvdata(&pdev->dev, dev);
3403 ether_addr_copy(dev->dev_addr, macaddr);
3404 dev->watchdog_timeo = 2 * HZ;
3405 dev->ethtool_ops = &bcmgenet_ethtool_ops;
3406 dev->netdev_ops = &bcmgenet_netdev_ops;
3407
3408 priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
3409
3410 /* Set hardware features */
3411 dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
3412 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM;
3413
3414 /* Request the WOL interrupt and advertise suspend if available */
3415 priv->wol_irq_disabled = true;
3416 err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0,
3417 dev->name, priv);
3418 if (!err)
3419 device_set_wakeup_capable(&pdev->dev, 1);
3420
3421 /* Set the needed headroom to account for any possible
3422 * features enabling/disabling at runtime
3423 */
3424 dev->needed_headroom += 64;
3425
3426 netdev_boot_setup_check(dev);
3427
3428 priv->dev = dev;
3429 priv->pdev = pdev;
3430 if (of_id)
3431 priv->version = (enum bcmgenet_version)of_id->data;
3432 else
3433 priv->version = pd->genet_version;
3434
3435 priv->clk = devm_clk_get(&priv->pdev->dev, "enet");
3436 if (IS_ERR(priv->clk)) {
3437 dev_warn(&priv->pdev->dev, "failed to get enet clock\n");
3438 priv->clk = NULL;
3439 }
3440
3441 clk_prepare_enable(priv->clk);
3442
3443 bcmgenet_set_hw_params(priv);
3444
3445 /* Mii wait queue */
3446 init_waitqueue_head(&priv->wq);
3447 /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
3448 priv->rx_buf_len = RX_BUF_LENGTH;
3449 INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
3450
3451 priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol");
3452 if (IS_ERR(priv->clk_wol)) {
3453 dev_warn(&priv->pdev->dev, "failed to get enet-wol clock\n");
3454 priv->clk_wol = NULL;
3455 }
3456
3457 priv->clk_eee = devm_clk_get(&priv->pdev->dev, "enet-eee");
3458 if (IS_ERR(priv->clk_eee)) {
3459 dev_warn(&priv->pdev->dev, "failed to get enet-eee clock\n");
3460 priv->clk_eee = NULL;
3461 }
3462
3463 /* If this is an internal GPHY, power it on now, before UniMAC is
3464 * brought out of reset as absolutely no UniMAC activity is allowed
3465 */
3466 if (dn && !of_property_read_string(dn, "phy-mode", &phy_mode_str) &&
3467 !strcasecmp(phy_mode_str, "internal"))
3468 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
3469
3470 reset_umac(priv);
3471
3472 err = bcmgenet_mii_init(dev);
3473 if (err)
3474 goto err_clk_disable;
3475
3476 /* setup number of real queues + 1 (GENET_V1 has 0 hardware queues
3477 * just the ring 16 descriptor based TX
3478 */
3479 netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
3480 netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
3481
3482 /* libphy will determine the link state */
3483 netif_carrier_off(dev);
3484
3485 /* Turn off the main clock, WOL clock is handled separately */
3486 clk_disable_unprepare(priv->clk);
3487
3488 err = register_netdev(dev);
3489 if (err)
3490 goto err;
3491
3492 return err;
3493
3494 err_clk_disable:
3495 clk_disable_unprepare(priv->clk);
3496 err:
3497 free_netdev(dev);
3498 return err;
3499 }
3500
3501 static int bcmgenet_remove(struct platform_device *pdev)
3502 {
3503 struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
3504
3505 dev_set_drvdata(&pdev->dev, NULL);
3506 unregister_netdev(priv->dev);
3507 bcmgenet_mii_exit(priv->dev);
3508 free_netdev(priv->dev);
3509
3510 return 0;
3511 }
3512
3513 #ifdef CONFIG_PM_SLEEP
3514 static int bcmgenet_suspend(struct device *d)
3515 {
3516 struct net_device *dev = dev_get_drvdata(d);
3517 struct bcmgenet_priv *priv = netdev_priv(dev);
3518 int ret = 0;
3519
3520 if (!netif_running(dev))
3521 return 0;
3522
3523 bcmgenet_netif_stop(dev);
3524
3525 if (!device_may_wakeup(d))
3526 phy_suspend(dev->phydev);
3527
3528 netif_device_detach(dev);
3529
3530 /* Prepare the device for Wake-on-LAN and switch to the slow clock */
3531 if (device_may_wakeup(d) && priv->wolopts) {
3532 ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC);
3533 clk_prepare_enable(priv->clk_wol);
3534 } else if (priv->internal_phy) {
3535 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3536 }
3537
3538 /* Turn off the clocks */
3539 clk_disable_unprepare(priv->clk);
3540
3541 return ret;
3542 }
3543
3544 static int bcmgenet_resume(struct device *d)
3545 {
3546 struct net_device *dev = dev_get_drvdata(d);
3547 struct bcmgenet_priv *priv = netdev_priv(dev);
3548 unsigned long dma_ctrl;
3549 int ret;
3550 u32 reg;
3551
3552 if (!netif_running(dev))
3553 return 0;
3554
3555 /* Turn on the clock */
3556 ret = clk_prepare_enable(priv->clk);
3557 if (ret)
3558 return ret;
3559
3560 /* If this is an internal GPHY, power it back on now, before UniMAC is
3561 * brought out of reset as absolutely no UniMAC activity is allowed
3562 */
3563 if (priv->internal_phy)
3564 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
3565
3566 bcmgenet_umac_reset(priv);
3567
3568 init_umac(priv);
3569
3570 /* From WOL-enabled suspend, switch to regular clock */
3571 if (priv->wolopts)
3572 clk_disable_unprepare(priv->clk_wol);
3573
3574 phy_init_hw(dev->phydev);
3575
3576 /* Speed settings must be restored */
3577 bcmgenet_mii_config(priv->dev, false);
3578
3579 bcmgenet_set_hw_addr(priv, dev->dev_addr);
3580
3581 if (priv->internal_phy) {
3582 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
3583 reg |= EXT_ENERGY_DET_MASK;
3584 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
3585 }
3586
3587 if (priv->wolopts)
3588 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
3589
3590 /* Disable RX/TX DMA and flush TX queues */
3591 dma_ctrl = bcmgenet_dma_disable(priv);
3592
3593 /* Reinitialize TDMA and RDMA and SW housekeeping */
3594 ret = bcmgenet_init_dma(priv);
3595 if (ret) {
3596 netdev_err(dev, "failed to initialize DMA\n");
3597 goto out_clk_disable;
3598 }
3599
3600 /* Always enable ring 16 - descriptor ring */
3601 bcmgenet_enable_dma(priv, dma_ctrl);
3602
3603 netif_device_attach(dev);
3604
3605 if (!device_may_wakeup(d))
3606 phy_resume(dev->phydev);
3607
3608 if (priv->eee.eee_enabled)
3609 bcmgenet_eee_enable_set(dev, true);
3610
3611 bcmgenet_netif_start(dev);
3612
3613 return 0;
3614
3615 out_clk_disable:
3616 if (priv->internal_phy)
3617 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3618 clk_disable_unprepare(priv->clk);
3619 return ret;
3620 }
3621 #endif /* CONFIG_PM_SLEEP */
3622
3623 static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops, bcmgenet_suspend, bcmgenet_resume);
3624
3625 static struct platform_driver bcmgenet_driver = {
3626 .probe = bcmgenet_probe,
3627 .remove = bcmgenet_remove,
3628 .driver = {
3629 .name = "bcmgenet",
3630 .of_match_table = bcmgenet_match,
3631 .pm = &bcmgenet_pm_ops,
3632 },
3633 };
3634 module_platform_driver(bcmgenet_driver);
3635
3636 MODULE_AUTHOR("Broadcom Corporation");
3637 MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
3638 MODULE_ALIAS("platform:bcmgenet");
3639 MODULE_LICENSE("GPL");
CRIS linux kernel tree