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x86/topology: Fix function name in documentation
[cris-mirror.git] / drivers / net / ethernet / qlogic / qed / qed_dev.c
blob553a6d17260ed3c849140041e266420a60aa4cd0
1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015-2017 QLogic Corporation
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/types.h>
34 #include <asm/byteorder.h>
35 #include <linux/io.h>
36 #include <linux/delay.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/errno.h>
39 #include <linux/kernel.h>
40 #include <linux/mutex.h>
41 #include <linux/pci.h>
42 #include <linux/slab.h>
43 #include <linux/string.h>
44 #include <linux/vmalloc.h>
45 #include <linux/etherdevice.h>
46 #include <linux/qed/qed_chain.h>
47 #include <linux/qed/qed_if.h>
48 #include "qed.h"
49 #include "qed_cxt.h"
50 #include "qed_dcbx.h"
51 #include "qed_dev_api.h"
52 #include "qed_fcoe.h"
53 #include "qed_hsi.h"
54 #include "qed_hw.h"
55 #include "qed_init_ops.h"
56 #include "qed_int.h"
57 #include "qed_iscsi.h"
58 #include "qed_ll2.h"
59 #include "qed_mcp.h"
60 #include "qed_ooo.h"
61 #include "qed_reg_addr.h"
62 #include "qed_sp.h"
63 #include "qed_sriov.h"
64 #include "qed_vf.h"
65 #include "qed_rdma.h"
66
67 static DEFINE_SPINLOCK(qm_lock);
68
69 #define QED_MIN_DPIS (4)
70 #define QED_MIN_PWM_REGION (QED_WID_SIZE * QED_MIN_DPIS)
71
72 static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn,
73 struct qed_ptt *p_ptt, enum BAR_ID bar_id)
74 {
75 u32 bar_reg = (bar_id == BAR_ID_0 ?
76 PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
77 u32 val;
78
79 if (IS_VF(p_hwfn->cdev))
80 return qed_vf_hw_bar_size(p_hwfn, bar_id);
81
82 val = qed_rd(p_hwfn, p_ptt, bar_reg);
83 if (val)
84 return 1 << (val + 15);
85
86 /* Old MFW initialized above registered only conditionally */
87 if (p_hwfn->cdev->num_hwfns > 1) {
88 DP_INFO(p_hwfn,
89 "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
90 return BAR_ID_0 ? 256 * 1024 : 512 * 1024;
91 } else {
92 DP_INFO(p_hwfn,
93 "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
94 return 512 * 1024;
95 }
96 }
97
98 void qed_init_dp(struct qed_dev *cdev, u32 dp_module, u8 dp_level)
99 {
100 u32 i;
101
102 cdev->dp_level = dp_level;
103 cdev->dp_module = dp_module;
104 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
105 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
106
107 p_hwfn->dp_level = dp_level;
108 p_hwfn->dp_module = dp_module;
109 }
110 }
111
112 void qed_init_struct(struct qed_dev *cdev)
113 {
114 u8 i;
115
116 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
117 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
118
119 p_hwfn->cdev = cdev;
120 p_hwfn->my_id = i;
121 p_hwfn->b_active = false;
122
123 mutex_init(&p_hwfn->dmae_info.mutex);
124 }
125
126 /* hwfn 0 is always active */
127 cdev->hwfns[0].b_active = true;
128
129 /* set the default cache alignment to 128 */
130 cdev->cache_shift = 7;
131 }
132
133 static void qed_qm_info_free(struct qed_hwfn *p_hwfn)
134 {
135 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
136
137 kfree(qm_info->qm_pq_params);
138 qm_info->qm_pq_params = NULL;
139 kfree(qm_info->qm_vport_params);
140 qm_info->qm_vport_params = NULL;
141 kfree(qm_info->qm_port_params);
142 qm_info->qm_port_params = NULL;
143 kfree(qm_info->wfq_data);
144 qm_info->wfq_data = NULL;
145 }
146
147 void qed_resc_free(struct qed_dev *cdev)
148 {
149 int i;
150
151 if (IS_VF(cdev)) {
152 for_each_hwfn(cdev, i)
153 qed_l2_free(&cdev->hwfns[i]);
154 return;
155 }
156
157 kfree(cdev->fw_data);
158 cdev->fw_data = NULL;
159
160 kfree(cdev->reset_stats);
161 cdev->reset_stats = NULL;
162
163 for_each_hwfn(cdev, i) {
164 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
165
166 qed_cxt_mngr_free(p_hwfn);
167 qed_qm_info_free(p_hwfn);
168 qed_spq_free(p_hwfn);
169 qed_eq_free(p_hwfn);
170 qed_consq_free(p_hwfn);
171 qed_int_free(p_hwfn);
172 #ifdef CONFIG_QED_LL2
173 qed_ll2_free(p_hwfn);
174 #endif
175 if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
176 qed_fcoe_free(p_hwfn);
177
178 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
179 qed_iscsi_free(p_hwfn);
180 qed_ooo_free(p_hwfn);
181 }
182 qed_iov_free(p_hwfn);
183 qed_l2_free(p_hwfn);
184 qed_dmae_info_free(p_hwfn);
185 qed_dcbx_info_free(p_hwfn);
186 }
187 }
188
189 /******************** QM initialization *******************/
190 #define ACTIVE_TCS_BMAP 0x9f
191 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf
192
193 /* determines the physical queue flags for a given PF. */
194 static u32 qed_get_pq_flags(struct qed_hwfn *p_hwfn)
195 {
196 u32 flags;
197
198 /* common flags */
199 flags = PQ_FLAGS_LB;
200
201 /* feature flags */
202 if (IS_QED_SRIOV(p_hwfn->cdev))
203 flags |= PQ_FLAGS_VFS;
204
205 /* protocol flags */
206 switch (p_hwfn->hw_info.personality) {
207 case QED_PCI_ETH:
208 flags |= PQ_FLAGS_MCOS;
209 break;
210 case QED_PCI_FCOE:
211 flags |= PQ_FLAGS_OFLD;
212 break;
213 case QED_PCI_ISCSI:
214 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
215 break;
216 case QED_PCI_ETH_ROCE:
217 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD | PQ_FLAGS_LLT;
218 break;
219 case QED_PCI_ETH_IWARP:
220 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_ACK | PQ_FLAGS_OOO |
221 PQ_FLAGS_OFLD;
222 break;
223 default:
224 DP_ERR(p_hwfn,
225 "unknown personality %d\n", p_hwfn->hw_info.personality);
226 return 0;
227 }
228
229 return flags;
230 }
231
232 /* Getters for resource amounts necessary for qm initialization */
233 u8 qed_init_qm_get_num_tcs(struct qed_hwfn *p_hwfn)
234 {
235 return p_hwfn->hw_info.num_hw_tc;
236 }
237
238 u16 qed_init_qm_get_num_vfs(struct qed_hwfn *p_hwfn)
239 {
240 return IS_QED_SRIOV(p_hwfn->cdev) ?
241 p_hwfn->cdev->p_iov_info->total_vfs : 0;
242 }
243
244 #define NUM_DEFAULT_RLS 1
245
246 u16 qed_init_qm_get_num_pf_rls(struct qed_hwfn *p_hwfn)
247 {
248 u16 num_pf_rls, num_vfs = qed_init_qm_get_num_vfs(p_hwfn);
249
250 /* num RLs can't exceed resource amount of rls or vports */
251 num_pf_rls = (u16) min_t(u32, RESC_NUM(p_hwfn, QED_RL),
252 RESC_NUM(p_hwfn, QED_VPORT));
253
254 /* Make sure after we reserve there's something left */
255 if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS)
256 return 0;
257
258 /* subtract rls necessary for VFs and one default one for the PF */
259 num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
260
261 return num_pf_rls;
262 }
263
264 u16 qed_init_qm_get_num_vports(struct qed_hwfn *p_hwfn)
265 {
266 u32 pq_flags = qed_get_pq_flags(p_hwfn);
267
268 /* all pqs share the same vport, except for vfs and pf_rl pqs */
269 return (!!(PQ_FLAGS_RLS & pq_flags)) *
270 qed_init_qm_get_num_pf_rls(p_hwfn) +
271 (!!(PQ_FLAGS_VFS & pq_flags)) *
272 qed_init_qm_get_num_vfs(p_hwfn) + 1;
273 }
274
275 /* calc amount of PQs according to the requested flags */
276 u16 qed_init_qm_get_num_pqs(struct qed_hwfn *p_hwfn)
277 {
278 u32 pq_flags = qed_get_pq_flags(p_hwfn);
279
280 return (!!(PQ_FLAGS_RLS & pq_flags)) *
281 qed_init_qm_get_num_pf_rls(p_hwfn) +
282 (!!(PQ_FLAGS_MCOS & pq_flags)) *
283 qed_init_qm_get_num_tcs(p_hwfn) +
284 (!!(PQ_FLAGS_LB & pq_flags)) + (!!(PQ_FLAGS_OOO & pq_flags)) +
285 (!!(PQ_FLAGS_ACK & pq_flags)) + (!!(PQ_FLAGS_OFLD & pq_flags)) +
286 (!!(PQ_FLAGS_LLT & pq_flags)) +
287 (!!(PQ_FLAGS_VFS & pq_flags)) * qed_init_qm_get_num_vfs(p_hwfn);
288 }
289
290 /* initialize the top level QM params */
291 static void qed_init_qm_params(struct qed_hwfn *p_hwfn)
292 {
293 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
294 bool four_port;
295
296 /* pq and vport bases for this PF */
297 qm_info->start_pq = (u16) RESC_START(p_hwfn, QED_PQ);
298 qm_info->start_vport = (u8) RESC_START(p_hwfn, QED_VPORT);
299
300 /* rate limiting and weighted fair queueing are always enabled */
301 qm_info->vport_rl_en = 1;
302 qm_info->vport_wfq_en = 1;
303
304 /* TC config is different for AH 4 port */
305 four_port = p_hwfn->cdev->num_ports_in_engine == MAX_NUM_PORTS_K2;
306
307 /* in AH 4 port we have fewer TCs per port */
308 qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 :
309 NUM_OF_PHYS_TCS;
310
311 /* unless MFW indicated otherwise, ooo_tc == 3 for
312 * AH 4-port and 4 otherwise.
313 */
314 if (!qm_info->ooo_tc)
315 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC :
316 DCBX_TCP_OOO_TC;
317 }
318
319 /* initialize qm vport params */
320 static void qed_init_qm_vport_params(struct qed_hwfn *p_hwfn)
321 {
322 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
323 u8 i;
324
325 /* all vports participate in weighted fair queueing */
326 for (i = 0; i < qed_init_qm_get_num_vports(p_hwfn); i++)
327 qm_info->qm_vport_params[i].vport_wfq = 1;
328 }
329
330 /* initialize qm port params */
331 static void qed_init_qm_port_params(struct qed_hwfn *p_hwfn)
332 {
333 /* Initialize qm port parameters */
334 u8 i, active_phys_tcs, num_ports = p_hwfn->cdev->num_ports_in_engine;
335
336 /* indicate how ooo and high pri traffic is dealt with */
337 active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
338 ACTIVE_TCS_BMAP_4PORT_K2 :
339 ACTIVE_TCS_BMAP;
340
341 for (i = 0; i < num_ports; i++) {
342 struct init_qm_port_params *p_qm_port =
343 &p_hwfn->qm_info.qm_port_params[i];
344
345 p_qm_port->active = 1;
346 p_qm_port->active_phys_tcs = active_phys_tcs;
347 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
348 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
349 }
350 }
351
352 /* Reset the params which must be reset for qm init. QM init may be called as
353 * a result of flows other than driver load (e.g. dcbx renegotiation). Other
354 * params may be affected by the init but would simply recalculate to the same
355 * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
356 * affected as these amounts stay the same.
357 */
358 static void qed_init_qm_reset_params(struct qed_hwfn *p_hwfn)
359 {
360 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
361
362 qm_info->num_pqs = 0;
363 qm_info->num_vports = 0;
364 qm_info->num_pf_rls = 0;
365 qm_info->num_vf_pqs = 0;
366 qm_info->first_vf_pq = 0;
367 qm_info->first_mcos_pq = 0;
368 qm_info->first_rl_pq = 0;
369 }
370
371 static void qed_init_qm_advance_vport(struct qed_hwfn *p_hwfn)
372 {
373 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
374
375 qm_info->num_vports++;
376
377 if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn))
378 DP_ERR(p_hwfn,
379 "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n",
380 qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn));
381 }
382
383 /* initialize a single pq and manage qm_info resources accounting.
384 * The pq_init_flags param determines whether the PQ is rate limited
385 * (for VF or PF) and whether a new vport is allocated to the pq or not
386 * (i.e. vport will be shared).
387 */
388
389 /* flags for pq init */
390 #define PQ_INIT_SHARE_VPORT (1 << 0)
391 #define PQ_INIT_PF_RL (1 << 1)
392 #define PQ_INIT_VF_RL (1 << 2)
393
394 /* defines for pq init */
395 #define PQ_INIT_DEFAULT_WRR_GROUP 1
396 #define PQ_INIT_DEFAULT_TC 0
397 #define PQ_INIT_OFLD_TC (p_hwfn->hw_info.offload_tc)
398
399 static void qed_init_qm_pq(struct qed_hwfn *p_hwfn,
400 struct qed_qm_info *qm_info,
401 u8 tc, u32 pq_init_flags)
402 {
403 u16 pq_idx = qm_info->num_pqs, max_pq = qed_init_qm_get_num_pqs(p_hwfn);
404
405 if (pq_idx > max_pq)
406 DP_ERR(p_hwfn,
407 "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
408
409 /* init pq params */
410 qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
411 qm_info->num_vports;
412 qm_info->qm_pq_params[pq_idx].tc_id = tc;
413 qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
414 qm_info->qm_pq_params[pq_idx].rl_valid =
415 (pq_init_flags & PQ_INIT_PF_RL || pq_init_flags & PQ_INIT_VF_RL);
416
417 /* qm params accounting */
418 qm_info->num_pqs++;
419 if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
420 qm_info->num_vports++;
421
422 if (pq_init_flags & PQ_INIT_PF_RL)
423 qm_info->num_pf_rls++;
424
425 if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn))
426 DP_ERR(p_hwfn,
427 "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n",
428 qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn));
429
430 if (qm_info->num_pf_rls > qed_init_qm_get_num_pf_rls(p_hwfn))
431 DP_ERR(p_hwfn,
432 "rl overflow! qm_info->num_pf_rls %d, qm_init_get_num_pf_rls() %d\n",
433 qm_info->num_pf_rls, qed_init_qm_get_num_pf_rls(p_hwfn));
434 }
435
436 /* get pq index according to PQ_FLAGS */
437 static u16 *qed_init_qm_get_idx_from_flags(struct qed_hwfn *p_hwfn,
438 u32 pq_flags)
439 {
440 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
441
442 /* Can't have multiple flags set here */
443 if (bitmap_weight((unsigned long *)&pq_flags, sizeof(pq_flags)) > 1)
444 goto err;
445
446 switch (pq_flags) {
447 case PQ_FLAGS_RLS:
448 return &qm_info->first_rl_pq;
449 case PQ_FLAGS_MCOS:
450 return &qm_info->first_mcos_pq;
451 case PQ_FLAGS_LB:
452 return &qm_info->pure_lb_pq;
453 case PQ_FLAGS_OOO:
454 return &qm_info->ooo_pq;
455 case PQ_FLAGS_ACK:
456 return &qm_info->pure_ack_pq;
457 case PQ_FLAGS_OFLD:
458 return &qm_info->offload_pq;
459 case PQ_FLAGS_LLT:
460 return &qm_info->low_latency_pq;
461 case PQ_FLAGS_VFS:
462 return &qm_info->first_vf_pq;
463 default:
464 goto err;
465 }
466
467 err:
468 DP_ERR(p_hwfn, "BAD pq flags %d\n", pq_flags);
469 return NULL;
470 }
471
472 /* save pq index in qm info */
473 static void qed_init_qm_set_idx(struct qed_hwfn *p_hwfn,
474 u32 pq_flags, u16 pq_val)
475 {
476 u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
477
478 *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
479 }
480
481 /* get tx pq index, with the PQ TX base already set (ready for context init) */
482 u16 qed_get_cm_pq_idx(struct qed_hwfn *p_hwfn, u32 pq_flags)
483 {
484 u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
485
486 return *base_pq_idx + CM_TX_PQ_BASE;
487 }
488
489 u16 qed_get_cm_pq_idx_mcos(struct qed_hwfn *p_hwfn, u8 tc)
490 {
491 u8 max_tc = qed_init_qm_get_num_tcs(p_hwfn);
492
493 if (tc > max_tc)
494 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
495
496 return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + tc;
497 }
498
499 u16 qed_get_cm_pq_idx_vf(struct qed_hwfn *p_hwfn, u16 vf)
500 {
501 u16 max_vf = qed_init_qm_get_num_vfs(p_hwfn);
502
503 if (vf > max_vf)
504 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
505
506 return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + vf;
507 }
508
509 u16 qed_get_cm_pq_idx_rl(struct qed_hwfn *p_hwfn, u8 rl)
510 {
511 u16 max_rl = qed_init_qm_get_num_pf_rls(p_hwfn);
512
513 if (rl > max_rl)
514 DP_ERR(p_hwfn, "rl %d must be smaller than %d\n", rl, max_rl);
515
516 return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_RLS) + rl;
517 }
518
519 /* Functions for creating specific types of pqs */
520 static void qed_init_qm_lb_pq(struct qed_hwfn *p_hwfn)
521 {
522 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
523
524 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
525 return;
526
527 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
528 qed_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
529 }
530
531 static void qed_init_qm_ooo_pq(struct qed_hwfn *p_hwfn)
532 {
533 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
534
535 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
536 return;
537
538 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
539 qed_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT);
540 }
541
542 static void qed_init_qm_pure_ack_pq(struct qed_hwfn *p_hwfn)
543 {
544 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
545
546 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
547 return;
548
549 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
550 qed_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
551 }
552
553 static void qed_init_qm_offload_pq(struct qed_hwfn *p_hwfn)
554 {
555 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
556
557 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
558 return;
559
560 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
561 qed_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
562 }
563
564 static void qed_init_qm_low_latency_pq(struct qed_hwfn *p_hwfn)
565 {
566 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
567
568 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LLT))
569 return;
570
571 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LLT, qm_info->num_pqs);
572 qed_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
573 }
574
575 static void qed_init_qm_mcos_pqs(struct qed_hwfn *p_hwfn)
576 {
577 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
578 u8 tc_idx;
579
580 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
581 return;
582
583 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
584 for (tc_idx = 0; tc_idx < qed_init_qm_get_num_tcs(p_hwfn); tc_idx++)
585 qed_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
586 }
587
588 static void qed_init_qm_vf_pqs(struct qed_hwfn *p_hwfn)
589 {
590 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
591 u16 vf_idx, num_vfs = qed_init_qm_get_num_vfs(p_hwfn);
592
593 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
594 return;
595
596 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
597 qm_info->num_vf_pqs = num_vfs;
598 for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
599 qed_init_qm_pq(p_hwfn,
600 qm_info, PQ_INIT_DEFAULT_TC, PQ_INIT_VF_RL);
601 }
602
603 static void qed_init_qm_rl_pqs(struct qed_hwfn *p_hwfn)
604 {
605 u16 pf_rls_idx, num_pf_rls = qed_init_qm_get_num_pf_rls(p_hwfn);
606 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
607
608 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
609 return;
610
611 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
612 for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
613 qed_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_PF_RL);
614 }
615
616 static void qed_init_qm_pq_params(struct qed_hwfn *p_hwfn)
617 {
618 /* rate limited pqs, must come first (FW assumption) */
619 qed_init_qm_rl_pqs(p_hwfn);
620
621 /* pqs for multi cos */
622 qed_init_qm_mcos_pqs(p_hwfn);
623
624 /* pure loopback pq */
625 qed_init_qm_lb_pq(p_hwfn);
626
627 /* out of order pq */
628 qed_init_qm_ooo_pq(p_hwfn);
629
630 /* pure ack pq */
631 qed_init_qm_pure_ack_pq(p_hwfn);
632
633 /* pq for offloaded protocol */
634 qed_init_qm_offload_pq(p_hwfn);
635
636 /* low latency pq */
637 qed_init_qm_low_latency_pq(p_hwfn);
638
639 /* done sharing vports */
640 qed_init_qm_advance_vport(p_hwfn);
641
642 /* pqs for vfs */
643 qed_init_qm_vf_pqs(p_hwfn);
644 }
645
646 /* compare values of getters against resources amounts */
647 static int qed_init_qm_sanity(struct qed_hwfn *p_hwfn)
648 {
649 if (qed_init_qm_get_num_vports(p_hwfn) > RESC_NUM(p_hwfn, QED_VPORT)) {
650 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
651 return -EINVAL;
652 }
653
654 if (qed_init_qm_get_num_pqs(p_hwfn) > RESC_NUM(p_hwfn, QED_PQ)) {
655 DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
656 return -EINVAL;
657 }
658
659 return 0;
660 }
661
662 static void qed_dp_init_qm_params(struct qed_hwfn *p_hwfn)
663 {
664 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
665 struct init_qm_vport_params *vport;
666 struct init_qm_port_params *port;
667 struct init_qm_pq_params *pq;
668 int i, tc;
669
670 /* top level params */
671 DP_VERBOSE(p_hwfn,
672 NETIF_MSG_HW,
673 "qm init top level params: start_pq %d, start_vport %d, pure_lb_pq %d, offload_pq %d, pure_ack_pq %d\n",
674 qm_info->start_pq,
675 qm_info->start_vport,
676 qm_info->pure_lb_pq,
677 qm_info->offload_pq, qm_info->pure_ack_pq);
678 DP_VERBOSE(p_hwfn,
679 NETIF_MSG_HW,
680 "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d, num_vports %d, max_phys_tcs_per_port %d\n",
681 qm_info->ooo_pq,
682 qm_info->first_vf_pq,
683 qm_info->num_pqs,
684 qm_info->num_vf_pqs,
685 qm_info->num_vports, qm_info->max_phys_tcs_per_port);
686 DP_VERBOSE(p_hwfn,
687 NETIF_MSG_HW,
688 "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d, pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
689 qm_info->pf_rl_en,
690 qm_info->pf_wfq_en,
691 qm_info->vport_rl_en,
692 qm_info->vport_wfq_en,
693 qm_info->pf_wfq,
694 qm_info->pf_rl,
695 qm_info->num_pf_rls, qed_get_pq_flags(p_hwfn));
696
697 /* port table */
698 for (i = 0; i < p_hwfn->cdev->num_ports_in_engine; i++) {
699 port = &(qm_info->qm_port_params[i]);
700 DP_VERBOSE(p_hwfn,
701 NETIF_MSG_HW,
702 "port idx %d, active %d, active_phys_tcs %d, num_pbf_cmd_lines %d, num_btb_blocks %d, reserved %d\n",
703 i,
704 port->active,
705 port->active_phys_tcs,
706 port->num_pbf_cmd_lines,
707 port->num_btb_blocks, port->reserved);
708 }
709
710 /* vport table */
711 for (i = 0; i < qm_info->num_vports; i++) {
712 vport = &(qm_info->qm_vport_params[i]);
713 DP_VERBOSE(p_hwfn,
714 NETIF_MSG_HW,
715 "vport idx %d, vport_rl %d, wfq %d, first_tx_pq_id [ ",
716 qm_info->start_vport + i,
717 vport->vport_rl, vport->vport_wfq);
718 for (tc = 0; tc < NUM_OF_TCS; tc++)
719 DP_VERBOSE(p_hwfn,
720 NETIF_MSG_HW,
721 "%d ", vport->first_tx_pq_id[tc]);
722 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "]\n");
723 }
724
725 /* pq table */
726 for (i = 0; i < qm_info->num_pqs; i++) {
727 pq = &(qm_info->qm_pq_params[i]);
728 DP_VERBOSE(p_hwfn,
729 NETIF_MSG_HW,
730 "pq idx %d, vport_id %d, tc %d, wrr_grp %d, rl_valid %d\n",
731 qm_info->start_pq + i,
732 pq->vport_id,
733 pq->tc_id, pq->wrr_group, pq->rl_valid);
734 }
735 }
736
737 static void qed_init_qm_info(struct qed_hwfn *p_hwfn)
738 {
739 /* reset params required for init run */
740 qed_init_qm_reset_params(p_hwfn);
741
742 /* init QM top level params */
743 qed_init_qm_params(p_hwfn);
744
745 /* init QM port params */
746 qed_init_qm_port_params(p_hwfn);
747
748 /* init QM vport params */
749 qed_init_qm_vport_params(p_hwfn);
750
751 /* init QM physical queue params */
752 qed_init_qm_pq_params(p_hwfn);
753
754 /* display all that init */
755 qed_dp_init_qm_params(p_hwfn);
756 }
757
758 /* This function reconfigures the QM pf on the fly.
759 * For this purpose we:
760 * 1. reconfigure the QM database
761 * 2. set new values to runtime array
762 * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
763 * 4. activate init tool in QM_PF stage
764 * 5. send an sdm_qm_cmd through rbc interface to release the QM
765 */
766 int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
767 {
768 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
769 bool b_rc;
770 int rc;
771
772 /* initialize qed's qm data structure */
773 qed_init_qm_info(p_hwfn);
774
775 /* stop PF's qm queues */
776 spin_lock_bh(&qm_lock);
777 b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
778 qm_info->start_pq, qm_info->num_pqs);
779 spin_unlock_bh(&qm_lock);
780 if (!b_rc)
781 return -EINVAL;
782
783 /* clear the QM_PF runtime phase leftovers from previous init */
784 qed_init_clear_rt_data(p_hwfn);
785
786 /* prepare QM portion of runtime array */
787 qed_qm_init_pf(p_hwfn, p_ptt, false);
788
789 /* activate init tool on runtime array */
790 rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
791 p_hwfn->hw_info.hw_mode);
792 if (rc)
793 return rc;
794
795 /* start PF's qm queues */
796 spin_lock_bh(&qm_lock);
797 b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
798 qm_info->start_pq, qm_info->num_pqs);
799 spin_unlock_bh(&qm_lock);
800 if (!b_rc)
801 return -EINVAL;
802
803 return 0;
804 }
805
806 static int qed_alloc_qm_data(struct qed_hwfn *p_hwfn)
807 {
808 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
809 int rc;
810
811 rc = qed_init_qm_sanity(p_hwfn);
812 if (rc)
813 goto alloc_err;
814
815 qm_info->qm_pq_params = kzalloc(sizeof(*qm_info->qm_pq_params) *
816 qed_init_qm_get_num_pqs(p_hwfn),
817 GFP_KERNEL);
818 if (!qm_info->qm_pq_params)
819 goto alloc_err;
820
821 qm_info->qm_vport_params = kzalloc(sizeof(*qm_info->qm_vport_params) *
822 qed_init_qm_get_num_vports(p_hwfn),
823 GFP_KERNEL);
824 if (!qm_info->qm_vport_params)
825 goto alloc_err;
826
827 qm_info->qm_port_params = kzalloc(sizeof(*qm_info->qm_port_params) *
828 p_hwfn->cdev->num_ports_in_engine,
829 GFP_KERNEL);
830 if (!qm_info->qm_port_params)
831 goto alloc_err;
832
833 qm_info->wfq_data = kzalloc(sizeof(*qm_info->wfq_data) *
834 qed_init_qm_get_num_vports(p_hwfn),
835 GFP_KERNEL);
836 if (!qm_info->wfq_data)
837 goto alloc_err;
838
839 return 0;
840
841 alloc_err:
842 DP_NOTICE(p_hwfn, "Failed to allocate memory for QM params\n");
843 qed_qm_info_free(p_hwfn);
844 return -ENOMEM;
845 }
846
847 int qed_resc_alloc(struct qed_dev *cdev)
848 {
849 u32 rdma_tasks, excess_tasks;
850 u32 line_count;
851 int i, rc = 0;
852
853 if (IS_VF(cdev)) {
854 for_each_hwfn(cdev, i) {
855 rc = qed_l2_alloc(&cdev->hwfns[i]);
856 if (rc)
857 return rc;
858 }
859 return rc;
860 }
861
862 cdev->fw_data = kzalloc(sizeof(*cdev->fw_data), GFP_KERNEL);
863 if (!cdev->fw_data)
864 return -ENOMEM;
865
866 for_each_hwfn(cdev, i) {
867 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
868 u32 n_eqes, num_cons;
869
870 /* First allocate the context manager structure */
871 rc = qed_cxt_mngr_alloc(p_hwfn);
872 if (rc)
873 goto alloc_err;
874
875 /* Set the HW cid/tid numbers (in the contest manager)
876 * Must be done prior to any further computations.
877 */
878 rc = qed_cxt_set_pf_params(p_hwfn, RDMA_MAX_TIDS);
879 if (rc)
880 goto alloc_err;
881
882 rc = qed_alloc_qm_data(p_hwfn);
883 if (rc)
884 goto alloc_err;
885
886 /* init qm info */
887 qed_init_qm_info(p_hwfn);
888
889 /* Compute the ILT client partition */
890 rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count);
891 if (rc) {
892 DP_NOTICE(p_hwfn,
893 "too many ILT lines; re-computing with less lines\n");
894 /* In case there are not enough ILT lines we reduce the
895 * number of RDMA tasks and re-compute.
896 */
897 excess_tasks =
898 qed_cxt_cfg_ilt_compute_excess(p_hwfn, line_count);
899 if (!excess_tasks)
900 goto alloc_err;
901
902 rdma_tasks = RDMA_MAX_TIDS - excess_tasks;
903 rc = qed_cxt_set_pf_params(p_hwfn, rdma_tasks);
904 if (rc)
905 goto alloc_err;
906
907 rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count);
908 if (rc) {
909 DP_ERR(p_hwfn,
910 "failed ILT compute. Requested too many lines: %u\n",
911 line_count);
912
913 goto alloc_err;
914 }
915 }
916
917 /* CID map / ILT shadow table / T2
918 * The talbes sizes are determined by the computations above
919 */
920 rc = qed_cxt_tables_alloc(p_hwfn);
921 if (rc)
922 goto alloc_err;
923
924 /* SPQ, must follow ILT because initializes SPQ context */
925 rc = qed_spq_alloc(p_hwfn);
926 if (rc)
927 goto alloc_err;
928
929 /* SP status block allocation */
930 p_hwfn->p_dpc_ptt = qed_get_reserved_ptt(p_hwfn,
931 RESERVED_PTT_DPC);
932
933 rc = qed_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
934 if (rc)
935 goto alloc_err;
936
937 rc = qed_iov_alloc(p_hwfn);
938 if (rc)
939 goto alloc_err;
940
941 /* EQ */
942 n_eqes = qed_chain_get_capacity(&p_hwfn->p_spq->chain);
943 if (QED_IS_RDMA_PERSONALITY(p_hwfn)) {
944 enum protocol_type rdma_proto;
945
946 if (QED_IS_ROCE_PERSONALITY(p_hwfn))
947 rdma_proto = PROTOCOLID_ROCE;
948 else
949 rdma_proto = PROTOCOLID_IWARP;
950
951 num_cons = qed_cxt_get_proto_cid_count(p_hwfn,
952 rdma_proto,
953 NULL) * 2;
954 n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
955 } else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
956 num_cons =
957 qed_cxt_get_proto_cid_count(p_hwfn,
958 PROTOCOLID_ISCSI,
959 NULL);
960 n_eqes += 2 * num_cons;
961 }
962
963 if (n_eqes > 0xFFFF) {
964 DP_ERR(p_hwfn,
965 "Cannot allocate 0x%x EQ elements. The maximum of a u16 chain is 0x%x\n",
966 n_eqes, 0xFFFF);
967 goto alloc_no_mem;
968 }
969
970 rc = qed_eq_alloc(p_hwfn, (u16) n_eqes);
971 if (rc)
972 goto alloc_err;
973
974 rc = qed_consq_alloc(p_hwfn);
975 if (rc)
976 goto alloc_err;
977
978 rc = qed_l2_alloc(p_hwfn);
979 if (rc)
980 goto alloc_err;
981
982 #ifdef CONFIG_QED_LL2
983 if (p_hwfn->using_ll2) {
984 rc = qed_ll2_alloc(p_hwfn);
985 if (rc)
986 goto alloc_err;
987 }
988 #endif
989
990 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) {
991 rc = qed_fcoe_alloc(p_hwfn);
992 if (rc)
993 goto alloc_err;
994 }
995
996 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
997 rc = qed_iscsi_alloc(p_hwfn);
998 if (rc)
999 goto alloc_err;
1000 rc = qed_ooo_alloc(p_hwfn);
1001 if (rc)
1002 goto alloc_err;
1003 }
1004
1005 /* DMA info initialization */
1006 rc = qed_dmae_info_alloc(p_hwfn);
1007 if (rc)
1008 goto alloc_err;
1009
1010 /* DCBX initialization */
1011 rc = qed_dcbx_info_alloc(p_hwfn);
1012 if (rc)
1013 goto alloc_err;
1014 }
1015
1016 cdev->reset_stats = kzalloc(sizeof(*cdev->reset_stats), GFP_KERNEL);
1017 if (!cdev->reset_stats)
1018 goto alloc_no_mem;
1019
1020 return 0;
1021
1022 alloc_no_mem:
1023 rc = -ENOMEM;
1024 alloc_err:
1025 qed_resc_free(cdev);
1026 return rc;
1027 }
1028
1029 void qed_resc_setup(struct qed_dev *cdev)
1030 {
1031 int i;
1032
1033 if (IS_VF(cdev)) {
1034 for_each_hwfn(cdev, i)
1035 qed_l2_setup(&cdev->hwfns[i]);
1036 return;
1037 }
1038
1039 for_each_hwfn(cdev, i) {
1040 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1041
1042 qed_cxt_mngr_setup(p_hwfn);
1043 qed_spq_setup(p_hwfn);
1044 qed_eq_setup(p_hwfn);
1045 qed_consq_setup(p_hwfn);
1046
1047 /* Read shadow of current MFW mailbox */
1048 qed_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
1049 memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
1050 p_hwfn->mcp_info->mfw_mb_cur,
1051 p_hwfn->mcp_info->mfw_mb_length);
1052
1053 qed_int_setup(p_hwfn, p_hwfn->p_main_ptt);
1054
1055 qed_l2_setup(p_hwfn);
1056 qed_iov_setup(p_hwfn);
1057 #ifdef CONFIG_QED_LL2
1058 if (p_hwfn->using_ll2)
1059 qed_ll2_setup(p_hwfn);
1060 #endif
1061 if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
1062 qed_fcoe_setup(p_hwfn);
1063
1064 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
1065 qed_iscsi_setup(p_hwfn);
1066 qed_ooo_setup(p_hwfn);
1067 }
1068 }
1069 }
1070
1071 #define FINAL_CLEANUP_POLL_CNT (100)
1072 #define FINAL_CLEANUP_POLL_TIME (10)
1073 int qed_final_cleanup(struct qed_hwfn *p_hwfn,
1074 struct qed_ptt *p_ptt, u16 id, bool is_vf)
1075 {
1076 u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
1077 int rc = -EBUSY;
1078
1079 addr = GTT_BAR0_MAP_REG_USDM_RAM +
1080 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
1081
1082 if (is_vf)
1083 id += 0x10;
1084
1085 command |= X_FINAL_CLEANUP_AGG_INT <<
1086 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
1087 command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
1088 command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
1089 command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
1090
1091 /* Make sure notification is not set before initiating final cleanup */
1092 if (REG_RD(p_hwfn, addr)) {
1093 DP_NOTICE(p_hwfn,
1094 "Unexpected; Found final cleanup notification before initiating final cleanup\n");
1095 REG_WR(p_hwfn, addr, 0);
1096 }
1097
1098 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
1099 "Sending final cleanup for PFVF[%d] [Command %08x\n]",
1100 id, command);
1101
1102 qed_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
1103
1104 /* Poll until completion */
1105 while (!REG_RD(p_hwfn, addr) && count--)
1106 msleep(FINAL_CLEANUP_POLL_TIME);
1107
1108 if (REG_RD(p_hwfn, addr))
1109 rc = 0;
1110 else
1111 DP_NOTICE(p_hwfn,
1112 "Failed to receive FW final cleanup notification\n");
1113
1114 /* Cleanup afterwards */
1115 REG_WR(p_hwfn, addr, 0);
1116
1117 return rc;
1118 }
1119
1120 static int qed_calc_hw_mode(struct qed_hwfn *p_hwfn)
1121 {
1122 int hw_mode = 0;
1123
1124 if (QED_IS_BB_B0(p_hwfn->cdev)) {
1125 hw_mode |= 1 << MODE_BB;
1126 } else if (QED_IS_AH(p_hwfn->cdev)) {
1127 hw_mode |= 1 << MODE_K2;
1128 } else {
1129 DP_NOTICE(p_hwfn, "Unknown chip type %#x\n",
1130 p_hwfn->cdev->type);
1131 return -EINVAL;
1132 }
1133
1134 switch (p_hwfn->cdev->num_ports_in_engine) {
1135 case 1:
1136 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
1137 break;
1138 case 2:
1139 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
1140 break;
1141 case 4:
1142 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
1143 break;
1144 default:
1145 DP_NOTICE(p_hwfn, "num_ports_in_engine = %d not supported\n",
1146 p_hwfn->cdev->num_ports_in_engine);
1147 return -EINVAL;
1148 }
1149
1150 switch (p_hwfn->cdev->mf_mode) {
1151 case QED_MF_DEFAULT:
1152 case QED_MF_NPAR:
1153 hw_mode |= 1 << MODE_MF_SI;
1154 break;
1155 case QED_MF_OVLAN:
1156 hw_mode |= 1 << MODE_MF_SD;
1157 break;
1158 default:
1159 DP_NOTICE(p_hwfn, "Unsupported MF mode, init as DEFAULT\n");
1160 hw_mode |= 1 << MODE_MF_SI;
1161 }
1162
1163 hw_mode |= 1 << MODE_ASIC;
1164
1165 if (p_hwfn->cdev->num_hwfns > 1)
1166 hw_mode |= 1 << MODE_100G;
1167
1168 p_hwfn->hw_info.hw_mode = hw_mode;
1169
1170 DP_VERBOSE(p_hwfn, (NETIF_MSG_PROBE | NETIF_MSG_IFUP),
1171 "Configuring function for hw_mode: 0x%08x\n",
1172 p_hwfn->hw_info.hw_mode);
1173
1174 return 0;
1175 }
1176
1177 /* Init run time data for all PFs on an engine. */
1178 static void qed_init_cau_rt_data(struct qed_dev *cdev)
1179 {
1180 u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
1181 int i, igu_sb_id;
1182
1183 for_each_hwfn(cdev, i) {
1184 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1185 struct qed_igu_info *p_igu_info;
1186 struct qed_igu_block *p_block;
1187 struct cau_sb_entry sb_entry;
1188
1189 p_igu_info = p_hwfn->hw_info.p_igu_info;
1190
1191 for (igu_sb_id = 0;
1192 igu_sb_id < QED_MAPPING_MEMORY_SIZE(cdev); igu_sb_id++) {
1193 p_block = &p_igu_info->entry[igu_sb_id];
1194
1195 if (!p_block->is_pf)
1196 continue;
1197
1198 qed_init_cau_sb_entry(p_hwfn, &sb_entry,
1199 p_block->function_id, 0, 0);
1200 STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2,
1201 sb_entry);
1202 }
1203 }
1204 }
1205
1206 static void qed_init_cache_line_size(struct qed_hwfn *p_hwfn,
1207 struct qed_ptt *p_ptt)
1208 {
1209 u32 val, wr_mbs, cache_line_size;
1210
1211 val = qed_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0);
1212 switch (val) {
1213 case 0:
1214 wr_mbs = 128;
1215 break;
1216 case 1:
1217 wr_mbs = 256;
1218 break;
1219 case 2:
1220 wr_mbs = 512;
1221 break;
1222 default:
1223 DP_INFO(p_hwfn,
1224 "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1225 val);
1226 return;
1227 }
1228
1229 cache_line_size = min_t(u32, L1_CACHE_BYTES, wr_mbs);
1230 switch (cache_line_size) {
1231 case 32:
1232 val = 0;
1233 break;
1234 case 64:
1235 val = 1;
1236 break;
1237 case 128:
1238 val = 2;
1239 break;
1240 case 256:
1241 val = 3;
1242 break;
1243 default:
1244 DP_INFO(p_hwfn,
1245 "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1246 cache_line_size);
1247 }
1248
1249 if (L1_CACHE_BYTES > wr_mbs)
1250 DP_INFO(p_hwfn,
1251 "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n",
1252 L1_CACHE_BYTES, wr_mbs);
1253
1254 STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val);
1255 if (val > 0) {
1256 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val);
1257 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val);
1258 }
1259 }
1260
1261 static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
1262 struct qed_ptt *p_ptt, int hw_mode)
1263 {
1264 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1265 struct qed_qm_common_rt_init_params params;
1266 struct qed_dev *cdev = p_hwfn->cdev;
1267 u8 vf_id, max_num_vfs;
1268 u16 num_pfs, pf_id;
1269 u32 concrete_fid;
1270 int rc = 0;
1271
1272 qed_init_cau_rt_data(cdev);
1273
1274 /* Program GTT windows */
1275 qed_gtt_init(p_hwfn);
1276
1277 if (p_hwfn->mcp_info) {
1278 if (p_hwfn->mcp_info->func_info.bandwidth_max)
1279 qm_info->pf_rl_en = 1;
1280 if (p_hwfn->mcp_info->func_info.bandwidth_min)
1281 qm_info->pf_wfq_en = 1;
1282 }
1283
1284 memset(&params, 0, sizeof(params));
1285 params.max_ports_per_engine = p_hwfn->cdev->num_ports_in_engine;
1286 params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port;
1287 params.pf_rl_en = qm_info->pf_rl_en;
1288 params.pf_wfq_en = qm_info->pf_wfq_en;
1289 params.vport_rl_en = qm_info->vport_rl_en;
1290 params.vport_wfq_en = qm_info->vport_wfq_en;
1291 params.port_params = qm_info->qm_port_params;
1292
1293 qed_qm_common_rt_init(p_hwfn, &params);
1294
1295 qed_cxt_hw_init_common(p_hwfn);
1296
1297 qed_init_cache_line_size(p_hwfn, p_ptt);
1298
1299 rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
1300 if (rc)
1301 return rc;
1302
1303 qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1304 qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1305
1306 if (QED_IS_BB(p_hwfn->cdev)) {
1307 num_pfs = NUM_OF_ENG_PFS(p_hwfn->cdev);
1308 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1309 qed_fid_pretend(p_hwfn, p_ptt, pf_id);
1310 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1311 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1312 }
1313 /* pretend to original PF */
1314 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1315 }
1316
1317 max_num_vfs = QED_IS_AH(cdev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
1318 for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1319 concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id);
1320 qed_fid_pretend(p_hwfn, p_ptt, (u16) concrete_fid);
1321 qed_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
1322 qed_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1323 qed_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1324 qed_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1325 }
1326 /* pretend to original PF */
1327 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1328
1329 return rc;
1330 }
1331
1332 static int
1333 qed_hw_init_dpi_size(struct qed_hwfn *p_hwfn,
1334 struct qed_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1335 {
1336 u32 dpi_bit_shift, dpi_count, dpi_page_size;
1337 u32 min_dpis;
1338 u32 n_wids;
1339
1340 /* Calculate DPI size */
1341 n_wids = max_t(u32, QED_MIN_WIDS, n_cpus);
1342 dpi_page_size = QED_WID_SIZE * roundup_pow_of_two(n_wids);
1343 dpi_page_size = (dpi_page_size + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1);
1344 dpi_bit_shift = ilog2(dpi_page_size / 4096);
1345 dpi_count = pwm_region_size / dpi_page_size;
1346
1347 min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1348 min_dpis = max_t(u32, QED_MIN_DPIS, min_dpis);
1349
1350 p_hwfn->dpi_size = dpi_page_size;
1351 p_hwfn->dpi_count = dpi_count;
1352
1353 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1354
1355 if (dpi_count < min_dpis)
1356 return -EINVAL;
1357
1358 return 0;
1359 }
1360
1361 enum QED_ROCE_EDPM_MODE {
1362 QED_ROCE_EDPM_MODE_ENABLE = 0,
1363 QED_ROCE_EDPM_MODE_FORCE_ON = 1,
1364 QED_ROCE_EDPM_MODE_DISABLE = 2,
1365 };
1366
1367 static int
1368 qed_hw_init_pf_doorbell_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1369 {
1370 u32 pwm_regsize, norm_regsize;
1371 u32 non_pwm_conn, min_addr_reg1;
1372 u32 db_bar_size, n_cpus = 1;
1373 u32 roce_edpm_mode;
1374 u32 pf_dems_shift;
1375 int rc = 0;
1376 u8 cond;
1377
1378 db_bar_size = qed_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1);
1379 if (p_hwfn->cdev->num_hwfns > 1)
1380 db_bar_size /= 2;
1381
1382 /* Calculate doorbell regions */
1383 non_pwm_conn = qed_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1384 qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1385 NULL) +
1386 qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
1387 NULL);
1388 norm_regsize = roundup(QED_PF_DEMS_SIZE * non_pwm_conn, PAGE_SIZE);
1389 min_addr_reg1 = norm_regsize / 4096;
1390 pwm_regsize = db_bar_size - norm_regsize;
1391
1392 /* Check that the normal and PWM sizes are valid */
1393 if (db_bar_size < norm_regsize) {
1394 DP_ERR(p_hwfn->cdev,
1395 "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
1396 db_bar_size, norm_regsize);
1397 return -EINVAL;
1398 }
1399
1400 if (pwm_regsize < QED_MIN_PWM_REGION) {
1401 DP_ERR(p_hwfn->cdev,
1402 "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
1403 pwm_regsize,
1404 QED_MIN_PWM_REGION, db_bar_size, norm_regsize);
1405 return -EINVAL;
1406 }
1407
1408 /* Calculate number of DPIs */
1409 roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
1410 if ((roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE) ||
1411 ((roce_edpm_mode == QED_ROCE_EDPM_MODE_FORCE_ON))) {
1412 /* Either EDPM is mandatory, or we are attempting to allocate a
1413 * WID per CPU.
1414 */
1415 n_cpus = num_present_cpus();
1416 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1417 }
1418
1419 cond = (rc && (roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE)) ||
1420 (roce_edpm_mode == QED_ROCE_EDPM_MODE_DISABLE);
1421 if (cond || p_hwfn->dcbx_no_edpm) {
1422 /* Either EDPM is disabled from user configuration, or it is
1423 * disabled via DCBx, or it is not mandatory and we failed to
1424 * allocated a WID per CPU.
1425 */
1426 n_cpus = 1;
1427 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1428
1429 if (cond)
1430 qed_rdma_dpm_bar(p_hwfn, p_ptt);
1431 }
1432
1433 p_hwfn->wid_count = (u16) n_cpus;
1434
1435 DP_INFO(p_hwfn,
1436 "doorbell bar: normal_region_size=%d, pwm_region_size=%d, dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
1437 norm_regsize,
1438 pwm_regsize,
1439 p_hwfn->dpi_size,
1440 p_hwfn->dpi_count,
1441 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
1442 "disabled" : "enabled");
1443
1444 if (rc) {
1445 DP_ERR(p_hwfn,
1446 "Failed to allocate enough DPIs. Allocated %d but the current minimum is %d.\n",
1447 p_hwfn->dpi_count,
1448 p_hwfn->pf_params.rdma_pf_params.min_dpis);
1449 return -EINVAL;
1450 }
1451
1452 p_hwfn->dpi_start_offset = norm_regsize;
1453
1454 /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
1455 pf_dems_shift = ilog2(QED_PF_DEMS_SIZE / 4);
1456 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
1457 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
1458
1459 return 0;
1460 }
1461
1462 static int qed_hw_init_port(struct qed_hwfn *p_hwfn,
1463 struct qed_ptt *p_ptt, int hw_mode)
1464 {
1465 int rc = 0;
1466
1467 rc = qed_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id, hw_mode);
1468 if (rc)
1469 return rc;
1470
1471 qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE, 0);
1472
1473 return 0;
1474 }
1475
1476 static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
1477 struct qed_ptt *p_ptt,
1478 struct qed_tunnel_info *p_tunn,
1479 int hw_mode,
1480 bool b_hw_start,
1481 enum qed_int_mode int_mode,
1482 bool allow_npar_tx_switch)
1483 {
1484 u8 rel_pf_id = p_hwfn->rel_pf_id;
1485 int rc = 0;
1486
1487 if (p_hwfn->mcp_info) {
1488 struct qed_mcp_function_info *p_info;
1489
1490 p_info = &p_hwfn->mcp_info->func_info;
1491 if (p_info->bandwidth_min)
1492 p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
1493
1494 /* Update rate limit once we'll actually have a link */
1495 p_hwfn->qm_info.pf_rl = 100000;
1496 }
1497
1498 qed_cxt_hw_init_pf(p_hwfn, p_ptt);
1499
1500 qed_int_igu_init_rt(p_hwfn);
1501
1502 /* Set VLAN in NIG if needed */
1503 if (hw_mode & BIT(MODE_MF_SD)) {
1504 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Configuring LLH_FUNC_TAG\n");
1505 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
1506 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
1507 p_hwfn->hw_info.ovlan);
1508 }
1509
1510 /* Enable classification by MAC if needed */
1511 if (hw_mode & BIT(MODE_MF_SI)) {
1512 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
1513 "Configuring TAGMAC_CLS_TYPE\n");
1514 STORE_RT_REG(p_hwfn,
1515 NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1);
1516 }
1517
1518 /* Protocol Configuration */
1519 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
1520 (p_hwfn->hw_info.personality == QED_PCI_ISCSI) ? 1 : 0);
1521 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
1522 (p_hwfn->hw_info.personality == QED_PCI_FCOE) ? 1 : 0);
1523 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
1524
1525 /* Cleanup chip from previous driver if such remains exist */
1526 rc = qed_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false);
1527 if (rc)
1528 return rc;
1529
1530 /* Sanity check before the PF init sequence that uses DMAE */
1531 rc = qed_dmae_sanity(p_hwfn, p_ptt, "pf_phase");
1532 if (rc)
1533 return rc;
1534
1535 /* PF Init sequence */
1536 rc = qed_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
1537 if (rc)
1538 return rc;
1539
1540 /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
1541 rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
1542 if (rc)
1543 return rc;
1544
1545 /* Pure runtime initializations - directly to the HW */
1546 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
1547
1548 rc = qed_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
1549 if (rc)
1550 return rc;
1551
1552 if (b_hw_start) {
1553 /* enable interrupts */
1554 qed_int_igu_enable(p_hwfn, p_ptt, int_mode);
1555
1556 /* send function start command */
1557 rc = qed_sp_pf_start(p_hwfn, p_ptt, p_tunn,
1558 p_hwfn->cdev->mf_mode,
1559 allow_npar_tx_switch);
1560 if (rc) {
1561 DP_NOTICE(p_hwfn, "Function start ramrod failed\n");
1562 return rc;
1563 }
1564 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) {
1565 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1, BIT(2));
1566 qed_wr(p_hwfn, p_ptt,
1567 PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
1568 0x100);
1569 }
1570 }
1571 return rc;
1572 }
1573
1574 static int qed_change_pci_hwfn(struct qed_hwfn *p_hwfn,
1575 struct qed_ptt *p_ptt,
1576 u8 enable)
1577 {
1578 u32 delay_idx = 0, val, set_val = enable ? 1 : 0;
1579
1580 /* Change PF in PXP */
1581 qed_wr(p_hwfn, p_ptt,
1582 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
1583
1584 /* wait until value is set - try for 1 second every 50us */
1585 for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
1586 val = qed_rd(p_hwfn, p_ptt,
1587 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1588 if (val == set_val)
1589 break;
1590
1591 usleep_range(50, 60);
1592 }
1593
1594 if (val != set_val) {
1595 DP_NOTICE(p_hwfn,
1596 "PFID_ENABLE_MASTER wasn't changed after a second\n");
1597 return -EAGAIN;
1598 }
1599
1600 return 0;
1601 }
1602
1603 static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn,
1604 struct qed_ptt *p_main_ptt)
1605 {
1606 /* Read shadow of current MFW mailbox */
1607 qed_mcp_read_mb(p_hwfn, p_main_ptt);
1608 memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
1609 p_hwfn->mcp_info->mfw_mb_cur, p_hwfn->mcp_info->mfw_mb_length);
1610 }
1611
1612 static void
1613 qed_fill_load_req_params(struct qed_load_req_params *p_load_req,
1614 struct qed_drv_load_params *p_drv_load)
1615 {
1616 memset(p_load_req, 0, sizeof(*p_load_req));
1617
1618 p_load_req->drv_role = p_drv_load->is_crash_kernel ?
1619 QED_DRV_ROLE_KDUMP : QED_DRV_ROLE_OS;
1620 p_load_req->timeout_val = p_drv_load->mfw_timeout_val;
1621 p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset;
1622 p_load_req->override_force_load = p_drv_load->override_force_load;
1623 }
1624
1625 static int qed_vf_start(struct qed_hwfn *p_hwfn,
1626 struct qed_hw_init_params *p_params)
1627 {
1628 if (p_params->p_tunn) {
1629 qed_vf_set_vf_start_tunn_update_param(p_params->p_tunn);
1630 qed_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn);
1631 }
1632
1633 p_hwfn->b_int_enabled = 1;
1634
1635 return 0;
1636 }
1637
1638 int qed_hw_init(struct qed_dev *cdev, struct qed_hw_init_params *p_params)
1639 {
1640 struct qed_load_req_params load_req_params;
1641 u32 load_code, param, drv_mb_param;
1642 bool b_default_mtu = true;
1643 struct qed_hwfn *p_hwfn;
1644 int rc = 0, mfw_rc, i;
1645
1646 if ((p_params->int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) {
1647 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n");
1648 return -EINVAL;
1649 }
1650
1651 if (IS_PF(cdev)) {
1652 rc = qed_init_fw_data(cdev, p_params->bin_fw_data);
1653 if (rc)
1654 return rc;
1655 }
1656
1657 for_each_hwfn(cdev, i) {
1658 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1659
1660 /* If management didn't provide a default, set one of our own */
1661 if (!p_hwfn->hw_info.mtu) {
1662 p_hwfn->hw_info.mtu = 1500;
1663 b_default_mtu = false;
1664 }
1665
1666 if (IS_VF(cdev)) {
1667 qed_vf_start(p_hwfn, p_params);
1668 continue;
1669 }
1670
1671 /* Enable DMAE in PXP */
1672 rc = qed_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);
1673
1674 rc = qed_calc_hw_mode(p_hwfn);
1675 if (rc)
1676 return rc;
1677
1678 qed_fill_load_req_params(&load_req_params,
1679 p_params->p_drv_load_params);
1680 rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
1681 &load_req_params);
1682 if (rc) {
1683 DP_NOTICE(p_hwfn, "Failed sending a LOAD_REQ command\n");
1684 return rc;
1685 }
1686
1687 load_code = load_req_params.load_code;
1688 DP_VERBOSE(p_hwfn, QED_MSG_SP,
1689 "Load request was sent. Load code: 0x%x\n",
1690 load_code);
1691
1692 qed_mcp_set_capabilities(p_hwfn, p_hwfn->p_main_ptt);
1693
1694 qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
1695
1696 p_hwfn->first_on_engine = (load_code ==
1697 FW_MSG_CODE_DRV_LOAD_ENGINE);
1698
1699 switch (load_code) {
1700 case FW_MSG_CODE_DRV_LOAD_ENGINE:
1701 rc = qed_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
1702 p_hwfn->hw_info.hw_mode);
1703 if (rc)
1704 break;
1705 /* Fall into */
1706 case FW_MSG_CODE_DRV_LOAD_PORT:
1707 rc = qed_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
1708 p_hwfn->hw_info.hw_mode);
1709 if (rc)
1710 break;
1711
1712 /* Fall into */
1713 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
1714 rc = qed_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
1715 p_params->p_tunn,
1716 p_hwfn->hw_info.hw_mode,
1717 p_params->b_hw_start,
1718 p_params->int_mode,
1719 p_params->allow_npar_tx_switch);
1720 break;
1721 default:
1722 DP_NOTICE(p_hwfn,
1723 "Unexpected load code [0x%08x]", load_code);
1724 rc = -EINVAL;
1725 break;
1726 }
1727
1728 if (rc)
1729 DP_NOTICE(p_hwfn,
1730 "init phase failed for loadcode 0x%x (rc %d)\n",
1731 load_code, rc);
1732
1733 /* ACK mfw regardless of success or failure of initialization */
1734 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1735 DRV_MSG_CODE_LOAD_DONE,
1736 0, &load_code, &param);
1737 if (rc)
1738 return rc;
1739 if (mfw_rc) {
1740 DP_NOTICE(p_hwfn, "Failed sending LOAD_DONE command\n");
1741 return mfw_rc;
1742 }
1743
1744 /* Check if there is a DID mismatch between nvm-cfg/efuse */
1745 if (param & FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR)
1746 DP_NOTICE(p_hwfn,
1747 "warning: device configuration is not supported on this board type. The device may not function as expected.\n");
1748
1749 /* send DCBX attention request command */
1750 DP_VERBOSE(p_hwfn,
1751 QED_MSG_DCB,
1752 "sending phony dcbx set command to trigger DCBx attention handling\n");
1753 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1754 DRV_MSG_CODE_SET_DCBX,
1755 1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
1756 &load_code, &param);
1757 if (mfw_rc) {
1758 DP_NOTICE(p_hwfn,
1759 "Failed to send DCBX attention request\n");
1760 return mfw_rc;
1761 }
1762
1763 p_hwfn->hw_init_done = true;
1764 }
1765
1766 if (IS_PF(cdev)) {
1767 p_hwfn = QED_LEADING_HWFN(cdev);
1768 drv_mb_param = STORM_FW_VERSION;
1769 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1770 DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
1771 drv_mb_param, &load_code, &param);
1772 if (rc)
1773 DP_INFO(p_hwfn, "Failed to update firmware version\n");
1774
1775 if (!b_default_mtu) {
1776 rc = qed_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
1777 p_hwfn->hw_info.mtu);
1778 if (rc)
1779 DP_INFO(p_hwfn,
1780 "Failed to update default mtu\n");
1781 }
1782
1783 rc = qed_mcp_ov_update_driver_state(p_hwfn,
1784 p_hwfn->p_main_ptt,
1785 QED_OV_DRIVER_STATE_DISABLED);
1786 if (rc)
1787 DP_INFO(p_hwfn, "Failed to update driver state\n");
1788
1789 rc = qed_mcp_ov_update_eswitch(p_hwfn, p_hwfn->p_main_ptt,
1790 QED_OV_ESWITCH_VEB);
1791 if (rc)
1792 DP_INFO(p_hwfn, "Failed to update eswitch mode\n");
1793 }
1794
1795 return 0;
1796 }
1797
1798 #define QED_HW_STOP_RETRY_LIMIT (10)
1799 static void qed_hw_timers_stop(struct qed_dev *cdev,
1800 struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1801 {
1802 int i;
1803
1804 /* close timers */
1805 qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
1806 qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
1807
1808 for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) {
1809 if ((!qed_rd(p_hwfn, p_ptt,
1810 TM_REG_PF_SCAN_ACTIVE_CONN)) &&
1811 (!qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
1812 break;
1813
1814 /* Dependent on number of connection/tasks, possibly
1815 * 1ms sleep is required between polls
1816 */
1817 usleep_range(1000, 2000);
1818 }
1819
1820 if (i < QED_HW_STOP_RETRY_LIMIT)
1821 return;
1822
1823 DP_NOTICE(p_hwfn,
1824 "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
1825 (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
1826 (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
1827 }
1828
1829 void qed_hw_timers_stop_all(struct qed_dev *cdev)
1830 {
1831 int j;
1832
1833 for_each_hwfn(cdev, j) {
1834 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
1835 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
1836
1837 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
1838 }
1839 }
1840
1841 int qed_hw_stop(struct qed_dev *cdev)
1842 {
1843 struct qed_hwfn *p_hwfn;
1844 struct qed_ptt *p_ptt;
1845 int rc, rc2 = 0;
1846 int j;
1847
1848 for_each_hwfn(cdev, j) {
1849 p_hwfn = &cdev->hwfns[j];
1850 p_ptt = p_hwfn->p_main_ptt;
1851
1852 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Stopping hw/fw\n");
1853
1854 if (IS_VF(cdev)) {
1855 qed_vf_pf_int_cleanup(p_hwfn);
1856 rc = qed_vf_pf_reset(p_hwfn);
1857 if (rc) {
1858 DP_NOTICE(p_hwfn,
1859 "qed_vf_pf_reset failed. rc = %d.\n",
1860 rc);
1861 rc2 = -EINVAL;
1862 }
1863 continue;
1864 }
1865
1866 /* mark the hw as uninitialized... */
1867 p_hwfn->hw_init_done = false;
1868
1869 /* Send unload command to MCP */
1870 rc = qed_mcp_unload_req(p_hwfn, p_ptt);
1871 if (rc) {
1872 DP_NOTICE(p_hwfn,
1873 "Failed sending a UNLOAD_REQ command. rc = %d.\n",
1874 rc);
1875 rc2 = -EINVAL;
1876 }
1877
1878 qed_slowpath_irq_sync(p_hwfn);
1879
1880 /* After this point no MFW attentions are expected, e.g. prevent
1881 * race between pf stop and dcbx pf update.
1882 */
1883 rc = qed_sp_pf_stop(p_hwfn);
1884 if (rc) {
1885 DP_NOTICE(p_hwfn,
1886 "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n",
1887 rc);
1888 rc2 = -EINVAL;
1889 }
1890
1891 qed_wr(p_hwfn, p_ptt,
1892 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1893
1894 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1895 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1896 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1897 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1898 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1899
1900 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
1901
1902 /* Disable Attention Generation */
1903 qed_int_igu_disable_int(p_hwfn, p_ptt);
1904
1905 qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
1906 qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
1907
1908 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
1909
1910 /* Need to wait 1ms to guarantee SBs are cleared */
1911 usleep_range(1000, 2000);
1912
1913 /* Disable PF in HW blocks */
1914 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0);
1915 qed_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0);
1916
1917 qed_mcp_unload_done(p_hwfn, p_ptt);
1918 if (rc) {
1919 DP_NOTICE(p_hwfn,
1920 "Failed sending a UNLOAD_DONE command. rc = %d.\n",
1921 rc);
1922 rc2 = -EINVAL;
1923 }
1924 }
1925
1926 if (IS_PF(cdev)) {
1927 p_hwfn = QED_LEADING_HWFN(cdev);
1928 p_ptt = QED_LEADING_HWFN(cdev)->p_main_ptt;
1929
1930 /* Disable DMAE in PXP - in CMT, this should only be done for
1931 * first hw-function, and only after all transactions have
1932 * stopped for all active hw-functions.
1933 */
1934 rc = qed_change_pci_hwfn(p_hwfn, p_ptt, false);
1935 if (rc) {
1936 DP_NOTICE(p_hwfn,
1937 "qed_change_pci_hwfn failed. rc = %d.\n", rc);
1938 rc2 = -EINVAL;
1939 }
1940 }
1941
1942 return rc2;
1943 }
1944
1945 int qed_hw_stop_fastpath(struct qed_dev *cdev)
1946 {
1947 int j;
1948
1949 for_each_hwfn(cdev, j) {
1950 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
1951 struct qed_ptt *p_ptt;
1952
1953 if (IS_VF(cdev)) {
1954 qed_vf_pf_int_cleanup(p_hwfn);
1955 continue;
1956 }
1957 p_ptt = qed_ptt_acquire(p_hwfn);
1958 if (!p_ptt)
1959 return -EAGAIN;
1960
1961 DP_VERBOSE(p_hwfn,
1962 NETIF_MSG_IFDOWN, "Shutting down the fastpath\n");
1963
1964 qed_wr(p_hwfn, p_ptt,
1965 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1966
1967 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1968 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1969 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1970 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1971 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1972
1973 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
1974
1975 /* Need to wait 1ms to guarantee SBs are cleared */
1976 usleep_range(1000, 2000);
1977 qed_ptt_release(p_hwfn, p_ptt);
1978 }
1979
1980 return 0;
1981 }
1982
1983 int qed_hw_start_fastpath(struct qed_hwfn *p_hwfn)
1984 {
1985 struct qed_ptt *p_ptt;
1986
1987 if (IS_VF(p_hwfn->cdev))
1988 return 0;
1989
1990 p_ptt = qed_ptt_acquire(p_hwfn);
1991 if (!p_ptt)
1992 return -EAGAIN;
1993
1994 /* If roce info is allocated it means roce is initialized and should
1995 * be enabled in searcher.
1996 */
1997 if (p_hwfn->p_rdma_info &&
1998 p_hwfn->b_rdma_enabled_in_prs)
1999 qed_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 0x1);
2000
2001 /* Re-open incoming traffic */
2002 qed_wr(p_hwfn, p_ptt, NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
2003 qed_ptt_release(p_hwfn, p_ptt);
2004
2005 return 0;
2006 }
2007
2008 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
2009 static void qed_hw_hwfn_free(struct qed_hwfn *p_hwfn)
2010 {
2011 qed_ptt_pool_free(p_hwfn);
2012 kfree(p_hwfn->hw_info.p_igu_info);
2013 p_hwfn->hw_info.p_igu_info = NULL;
2014 }
2015
2016 /* Setup bar access */
2017 static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn)
2018 {
2019 /* clear indirect access */
2020 if (QED_IS_AH(p_hwfn->cdev)) {
2021 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2022 PGLUE_B_REG_PGL_ADDR_E8_F0_K2, 0);
2023 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2024 PGLUE_B_REG_PGL_ADDR_EC_F0_K2, 0);
2025 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2026 PGLUE_B_REG_PGL_ADDR_F0_F0_K2, 0);
2027 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2028 PGLUE_B_REG_PGL_ADDR_F4_F0_K2, 0);
2029 } else {
2030 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2031 PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
2032 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2033 PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
2034 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2035 PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
2036 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2037 PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
2038 }
2039
2040 /* Clean Previous errors if such exist */
2041 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2042 PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id);
2043
2044 /* enable internal target-read */
2045 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2046 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
2047 }
2048
2049 static void get_function_id(struct qed_hwfn *p_hwfn)
2050 {
2051 /* ME Register */
2052 p_hwfn->hw_info.opaque_fid = (u16) REG_RD(p_hwfn,
2053 PXP_PF_ME_OPAQUE_ADDR);
2054
2055 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
2056
2057 p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
2058 p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2059 PXP_CONCRETE_FID_PFID);
2060 p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2061 PXP_CONCRETE_FID_PORT);
2062
2063 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
2064 "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
2065 p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
2066 }
2067
2068 static void qed_hw_set_feat(struct qed_hwfn *p_hwfn)
2069 {
2070 u32 *feat_num = p_hwfn->hw_info.feat_num;
2071 struct qed_sb_cnt_info sb_cnt;
2072 u32 non_l2_sbs = 0;
2073
2074 memset(&sb_cnt, 0, sizeof(sb_cnt));
2075 qed_int_get_num_sbs(p_hwfn, &sb_cnt);
2076
2077 if (IS_ENABLED(CONFIG_QED_RDMA) &&
2078 QED_IS_RDMA_PERSONALITY(p_hwfn)) {
2079 /* Roce CNQ each requires: 1 status block + 1 CNQ. We divide
2080 * the status blocks equally between L2 / RoCE but with
2081 * consideration as to how many l2 queues / cnqs we have.
2082 */
2083 feat_num[QED_RDMA_CNQ] =
2084 min_t(u32, sb_cnt.cnt / 2,
2085 RESC_NUM(p_hwfn, QED_RDMA_CNQ_RAM));
2086
2087 non_l2_sbs = feat_num[QED_RDMA_CNQ];
2088 }
2089 if (QED_IS_L2_PERSONALITY(p_hwfn)) {
2090 /* Start by allocating VF queues, then PF's */
2091 feat_num[QED_VF_L2_QUE] = min_t(u32,
2092 RESC_NUM(p_hwfn, QED_L2_QUEUE),
2093 sb_cnt.iov_cnt);
2094 feat_num[QED_PF_L2_QUE] = min_t(u32,
2095 sb_cnt.cnt - non_l2_sbs,
2096 RESC_NUM(p_hwfn,
2097 QED_L2_QUEUE) -
2098 FEAT_NUM(p_hwfn,
2099 QED_VF_L2_QUE));
2100 }
2101
2102 if (QED_IS_FCOE_PERSONALITY(p_hwfn))
2103 feat_num[QED_FCOE_CQ] = min_t(u32, sb_cnt.cnt,
2104 RESC_NUM(p_hwfn,
2105 QED_CMDQS_CQS));
2106
2107 if (QED_IS_ISCSI_PERSONALITY(p_hwfn))
2108 feat_num[QED_ISCSI_CQ] = min_t(u32, sb_cnt.cnt,
2109 RESC_NUM(p_hwfn,
2110 QED_CMDQS_CQS));
2111 DP_VERBOSE(p_hwfn,
2112 NETIF_MSG_PROBE,
2113 "#PF_L2_QUEUES=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d FCOE_CQ=%d ISCSI_CQ=%d #SBS=%d\n",
2114 (int)FEAT_NUM(p_hwfn, QED_PF_L2_QUE),
2115 (int)FEAT_NUM(p_hwfn, QED_VF_L2_QUE),
2116 (int)FEAT_NUM(p_hwfn, QED_RDMA_CNQ),
2117 (int)FEAT_NUM(p_hwfn, QED_FCOE_CQ),
2118 (int)FEAT_NUM(p_hwfn, QED_ISCSI_CQ),
2119 (int)sb_cnt.cnt);
2120 }
2121
2122 const char *qed_hw_get_resc_name(enum qed_resources res_id)
2123 {
2124 switch (res_id) {
2125 case QED_L2_QUEUE:
2126 return "L2_QUEUE";
2127 case QED_VPORT:
2128 return "VPORT";
2129 case QED_RSS_ENG:
2130 return "RSS_ENG";
2131 case QED_PQ:
2132 return "PQ";
2133 case QED_RL:
2134 return "RL";
2135 case QED_MAC:
2136 return "MAC";
2137 case QED_VLAN:
2138 return "VLAN";
2139 case QED_RDMA_CNQ_RAM:
2140 return "RDMA_CNQ_RAM";
2141 case QED_ILT:
2142 return "ILT";
2143 case QED_LL2_QUEUE:
2144 return "LL2_QUEUE";
2145 case QED_CMDQS_CQS:
2146 return "CMDQS_CQS";
2147 case QED_RDMA_STATS_QUEUE:
2148 return "RDMA_STATS_QUEUE";
2149 case QED_BDQ:
2150 return "BDQ";
2151 case QED_SB:
2152 return "SB";
2153 default:
2154 return "UNKNOWN_RESOURCE";
2155 }
2156 }
2157
2158 static int
2159 __qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn,
2160 struct qed_ptt *p_ptt,
2161 enum qed_resources res_id,
2162 u32 resc_max_val, u32 *p_mcp_resp)
2163 {
2164 int rc;
2165
2166 rc = qed_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id,
2167 resc_max_val, p_mcp_resp);
2168 if (rc) {
2169 DP_NOTICE(p_hwfn,
2170 "MFW response failure for a max value setting of resource %d [%s]\n",
2171 res_id, qed_hw_get_resc_name(res_id));
2172 return rc;
2173 }
2174
2175 if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK)
2176 DP_INFO(p_hwfn,
2177 "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n",
2178 res_id, qed_hw_get_resc_name(res_id), *p_mcp_resp);
2179
2180 return 0;
2181 }
2182
2183 static int
2184 qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2185 {
2186 bool b_ah = QED_IS_AH(p_hwfn->cdev);
2187 u32 resc_max_val, mcp_resp;
2188 u8 res_id;
2189 int rc;
2190
2191 for (res_id = 0; res_id < QED_MAX_RESC; res_id++) {
2192 switch (res_id) {
2193 case QED_LL2_QUEUE:
2194 resc_max_val = MAX_NUM_LL2_RX_QUEUES;
2195 break;
2196 case QED_RDMA_CNQ_RAM:
2197 /* No need for a case for QED_CMDQS_CQS since
2198 * CNQ/CMDQS are the same resource.
2199 */
2200 resc_max_val = NUM_OF_GLOBAL_QUEUES;
2201 break;
2202 case QED_RDMA_STATS_QUEUE:
2203 resc_max_val = b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2
2204 : RDMA_NUM_STATISTIC_COUNTERS_BB;
2205 break;
2206 case QED_BDQ:
2207 resc_max_val = BDQ_NUM_RESOURCES;
2208 break;
2209 default:
2210 continue;
2211 }
2212
2213 rc = __qed_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id,
2214 resc_max_val, &mcp_resp);
2215 if (rc)
2216 return rc;
2217
2218 /* There's no point to continue to the next resource if the
2219 * command is not supported by the MFW.
2220 * We do continue if the command is supported but the resource
2221 * is unknown to the MFW. Such a resource will be later
2222 * configured with the default allocation values.
2223 */
2224 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED)
2225 return -EINVAL;
2226 }
2227
2228 return 0;
2229 }
2230
2231 static
2232 int qed_hw_get_dflt_resc(struct qed_hwfn *p_hwfn,
2233 enum qed_resources res_id,
2234 u32 *p_resc_num, u32 *p_resc_start)
2235 {
2236 u8 num_funcs = p_hwfn->num_funcs_on_engine;
2237 bool b_ah = QED_IS_AH(p_hwfn->cdev);
2238
2239 switch (res_id) {
2240 case QED_L2_QUEUE:
2241 *p_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
2242 MAX_NUM_L2_QUEUES_BB) / num_funcs;
2243 break;
2244 case QED_VPORT:
2245 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2246 MAX_NUM_VPORTS_BB) / num_funcs;
2247 break;
2248 case QED_RSS_ENG:
2249 *p_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
2250 ETH_RSS_ENGINE_NUM_BB) / num_funcs;
2251 break;
2252 case QED_PQ:
2253 *p_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
2254 MAX_QM_TX_QUEUES_BB) / num_funcs;
2255 *p_resc_num &= ~0x7; /* The granularity of the PQs is 8 */
2256 break;
2257 case QED_RL:
2258 *p_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
2259 break;
2260 case QED_MAC:
2261 case QED_VLAN:
2262 /* Each VFC resource can accommodate both a MAC and a VLAN */
2263 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
2264 break;
2265 case QED_ILT:
2266 *p_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
2267 PXP_NUM_ILT_RECORDS_BB) / num_funcs;
2268 break;
2269 case QED_LL2_QUEUE:
2270 *p_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
2271 break;
2272 case QED_RDMA_CNQ_RAM:
2273 case QED_CMDQS_CQS:
2274 /* CNQ/CMDQS are the same resource */
2275 *p_resc_num = NUM_OF_GLOBAL_QUEUES / num_funcs;
2276 break;
2277 case QED_RDMA_STATS_QUEUE:
2278 *p_resc_num = (b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2 :
2279 RDMA_NUM_STATISTIC_COUNTERS_BB) / num_funcs;
2280 break;
2281 case QED_BDQ:
2282 if (p_hwfn->hw_info.personality != QED_PCI_ISCSI &&
2283 p_hwfn->hw_info.personality != QED_PCI_FCOE)
2284 *p_resc_num = 0;
2285 else
2286 *p_resc_num = 1;
2287 break;
2288 case QED_SB:
2289 /* Since we want its value to reflect whether MFW supports
2290 * the new scheme, have a default of 0.
2291 */
2292 *p_resc_num = 0;
2293 break;
2294 default:
2295 return -EINVAL;
2296 }
2297
2298 switch (res_id) {
2299 case QED_BDQ:
2300 if (!*p_resc_num)
2301 *p_resc_start = 0;
2302 else if (p_hwfn->cdev->num_ports_in_engine == 4)
2303 *p_resc_start = p_hwfn->port_id;
2304 else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI)
2305 *p_resc_start = p_hwfn->port_id;
2306 else if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
2307 *p_resc_start = p_hwfn->port_id + 2;
2308 break;
2309 default:
2310 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx;
2311 break;
2312 }
2313
2314 return 0;
2315 }
2316
2317 static int __qed_hw_set_resc_info(struct qed_hwfn *p_hwfn,
2318 enum qed_resources res_id)
2319 {
2320 u32 dflt_resc_num = 0, dflt_resc_start = 0;
2321 u32 mcp_resp, *p_resc_num, *p_resc_start;
2322 int rc;
2323
2324 p_resc_num = &RESC_NUM(p_hwfn, res_id);
2325 p_resc_start = &RESC_START(p_hwfn, res_id);
2326
2327 rc = qed_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num,
2328 &dflt_resc_start);
2329 if (rc) {
2330 DP_ERR(p_hwfn,
2331 "Failed to get default amount for resource %d [%s]\n",
2332 res_id, qed_hw_get_resc_name(res_id));
2333 return rc;
2334 }
2335
2336 rc = qed_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id,
2337 &mcp_resp, p_resc_num, p_resc_start);
2338 if (rc) {
2339 DP_NOTICE(p_hwfn,
2340 "MFW response failure for an allocation request for resource %d [%s]\n",
2341 res_id, qed_hw_get_resc_name(res_id));
2342 return rc;
2343 }
2344
2345 /* Default driver values are applied in the following cases:
2346 * - The resource allocation MB command is not supported by the MFW
2347 * - There is an internal error in the MFW while processing the request
2348 * - The resource ID is unknown to the MFW
2349 */
2350 if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) {
2351 DP_INFO(p_hwfn,
2352 "Failed to receive allocation info for resource %d [%s]. mcp_resp = 0x%x. Applying default values [%d,%d].\n",
2353 res_id,
2354 qed_hw_get_resc_name(res_id),
2355 mcp_resp, dflt_resc_num, dflt_resc_start);
2356 *p_resc_num = dflt_resc_num;
2357 *p_resc_start = dflt_resc_start;
2358 goto out;
2359 }
2360
2361 out:
2362 /* PQs have to divide by 8 [that's the HW granularity].
2363 * Reduce number so it would fit.
2364 */
2365 if ((res_id == QED_PQ) && ((*p_resc_num % 8) || (*p_resc_start % 8))) {
2366 DP_INFO(p_hwfn,
2367 "PQs need to align by 8; Number %08x --> %08x, Start %08x --> %08x\n",
2368 *p_resc_num,
2369 (*p_resc_num) & ~0x7,
2370 *p_resc_start, (*p_resc_start) & ~0x7);
2371 *p_resc_num &= ~0x7;
2372 *p_resc_start &= ~0x7;
2373 }
2374
2375 return 0;
2376 }
2377
2378 static int qed_hw_set_resc_info(struct qed_hwfn *p_hwfn)
2379 {
2380 int rc;
2381 u8 res_id;
2382
2383 for (res_id = 0; res_id < QED_MAX_RESC; res_id++) {
2384 rc = __qed_hw_set_resc_info(p_hwfn, res_id);
2385 if (rc)
2386 return rc;
2387 }
2388
2389 return 0;
2390 }
2391
2392 static int qed_hw_get_resc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2393 {
2394 struct qed_resc_unlock_params resc_unlock_params;
2395 struct qed_resc_lock_params resc_lock_params;
2396 bool b_ah = QED_IS_AH(p_hwfn->cdev);
2397 u8 res_id;
2398 int rc;
2399
2400 /* Setting the max values of the soft resources and the following
2401 * resources allocation queries should be atomic. Since several PFs can
2402 * run in parallel - a resource lock is needed.
2403 * If either the resource lock or resource set value commands are not
2404 * supported - skip the the max values setting, release the lock if
2405 * needed, and proceed to the queries. Other failures, including a
2406 * failure to acquire the lock, will cause this function to fail.
2407 */
2408 qed_mcp_resc_lock_default_init(&resc_lock_params, &resc_unlock_params,
2409 QED_RESC_LOCK_RESC_ALLOC, false);
2410
2411 rc = qed_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params);
2412 if (rc && rc != -EINVAL) {
2413 return rc;
2414 } else if (rc == -EINVAL) {
2415 DP_INFO(p_hwfn,
2416 "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n");
2417 } else if (!rc && !resc_lock_params.b_granted) {
2418 DP_NOTICE(p_hwfn,
2419 "Failed to acquire the resource lock for the resource allocation commands\n");
2420 return -EBUSY;
2421 } else {
2422 rc = qed_hw_set_soft_resc_size(p_hwfn, p_ptt);
2423 if (rc && rc != -EINVAL) {
2424 DP_NOTICE(p_hwfn,
2425 "Failed to set the max values of the soft resources\n");
2426 goto unlock_and_exit;
2427 } else if (rc == -EINVAL) {
2428 DP_INFO(p_hwfn,
2429 "Skip the max values setting of the soft resources since it is not supported by the MFW\n");
2430 rc = qed_mcp_resc_unlock(p_hwfn, p_ptt,
2431 &resc_unlock_params);
2432 if (rc)
2433 DP_INFO(p_hwfn,
2434 "Failed to release the resource lock for the resource allocation commands\n");
2435 }
2436 }
2437
2438 rc = qed_hw_set_resc_info(p_hwfn);
2439 if (rc)
2440 goto unlock_and_exit;
2441
2442 if (resc_lock_params.b_granted && !resc_unlock_params.b_released) {
2443 rc = qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params);
2444 if (rc)
2445 DP_INFO(p_hwfn,
2446 "Failed to release the resource lock for the resource allocation commands\n");
2447 }
2448
2449 /* Sanity for ILT */
2450 if ((b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
2451 (!b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
2452 DP_NOTICE(p_hwfn, "Can't assign ILT pages [%08x,...,%08x]\n",
2453 RESC_START(p_hwfn, QED_ILT),
2454 RESC_END(p_hwfn, QED_ILT) - 1);
2455 return -EINVAL;
2456 }
2457
2458 /* This will also learn the number of SBs from MFW */
2459 if (qed_int_igu_reset_cam(p_hwfn, p_ptt))
2460 return -EINVAL;
2461
2462 qed_hw_set_feat(p_hwfn);
2463
2464 for (res_id = 0; res_id < QED_MAX_RESC; res_id++)
2465 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, "%s = %d start = %d\n",
2466 qed_hw_get_resc_name(res_id),
2467 RESC_NUM(p_hwfn, res_id),
2468 RESC_START(p_hwfn, res_id));
2469
2470 return 0;
2471
2472 unlock_and_exit:
2473 if (resc_lock_params.b_granted && !resc_unlock_params.b_released)
2474 qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params);
2475 return rc;
2476 }
2477
2478 static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2479 {
2480 u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
2481 u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg;
2482 struct qed_mcp_link_capabilities *p_caps;
2483 struct qed_mcp_link_params *link;
2484
2485 /* Read global nvm_cfg address */
2486 nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
2487
2488 /* Verify MCP has initialized it */
2489 if (!nvm_cfg_addr) {
2490 DP_NOTICE(p_hwfn, "Shared memory not initialized\n");
2491 return -EINVAL;
2492 }
2493
2494 /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */
2495 nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
2496
2497 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2498 offsetof(struct nvm_cfg1, glob) +
2499 offsetof(struct nvm_cfg1_glob, core_cfg);
2500
2501 core_cfg = qed_rd(p_hwfn, p_ptt, addr);
2502
2503 switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
2504 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
2505 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
2506 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X40G;
2507 break;
2508 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
2509 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X50G;
2510 break;
2511 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
2512 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X100G;
2513 break;
2514 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
2515 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_F;
2516 break;
2517 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
2518 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_E;
2519 break;
2520 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
2521 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X20G;
2522 break;
2523 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
2524 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X40G;
2525 break;
2526 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
2527 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X25G;
2528 break;
2529 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
2530 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X10G;
2531 break;
2532 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
2533 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X25G;
2534 break;
2535 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
2536 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X25G;
2537 break;
2538 default:
2539 DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n", core_cfg);
2540 break;
2541 }
2542
2543 /* Read default link configuration */
2544 link = &p_hwfn->mcp_info->link_input;
2545 p_caps = &p_hwfn->mcp_info->link_capabilities;
2546 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2547 offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2548 link_temp = qed_rd(p_hwfn, p_ptt,
2549 port_cfg_addr +
2550 offsetof(struct nvm_cfg1_port, speed_cap_mask));
2551 link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
2552 link->speed.advertised_speeds = link_temp;
2553
2554 link_temp = link->speed.advertised_speeds;
2555 p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
2556
2557 link_temp = qed_rd(p_hwfn, p_ptt,
2558 port_cfg_addr +
2559 offsetof(struct nvm_cfg1_port, link_settings));
2560 switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
2561 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
2562 case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
2563 link->speed.autoneg = true;
2564 break;
2565 case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
2566 link->speed.forced_speed = 1000;
2567 break;
2568 case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
2569 link->speed.forced_speed = 10000;
2570 break;
2571 case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
2572 link->speed.forced_speed = 25000;
2573 break;
2574 case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
2575 link->speed.forced_speed = 40000;
2576 break;
2577 case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
2578 link->speed.forced_speed = 50000;
2579 break;
2580 case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
2581 link->speed.forced_speed = 100000;
2582 break;
2583 default:
2584 DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n", link_temp);
2585 }
2586
2587 p_hwfn->mcp_info->link_capabilities.default_speed_autoneg =
2588 link->speed.autoneg;
2589
2590 link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
2591 link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
2592 link->pause.autoneg = !!(link_temp &
2593 NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
2594 link->pause.forced_rx = !!(link_temp &
2595 NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
2596 link->pause.forced_tx = !!(link_temp &
2597 NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
2598 link->loopback_mode = 0;
2599
2600 if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) {
2601 link_temp = qed_rd(p_hwfn, p_ptt, port_cfg_addr +
2602 offsetof(struct nvm_cfg1_port, ext_phy));
2603 link_temp &= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK;
2604 link_temp >>= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET;
2605 p_caps->default_eee = QED_MCP_EEE_ENABLED;
2606 link->eee.enable = true;
2607 switch (link_temp) {
2608 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED:
2609 p_caps->default_eee = QED_MCP_EEE_DISABLED;
2610 link->eee.enable = false;
2611 break;
2612 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED:
2613 p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_BALANCED_TIME;
2614 break;
2615 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE:
2616 p_caps->eee_lpi_timer =
2617 EEE_TX_TIMER_USEC_AGGRESSIVE_TIME;
2618 break;
2619 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY:
2620 p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_LATENCY_TIME;
2621 break;
2622 }
2623
2624 link->eee.tx_lpi_timer = p_caps->eee_lpi_timer;
2625 link->eee.tx_lpi_enable = link->eee.enable;
2626 link->eee.adv_caps = QED_EEE_1G_ADV | QED_EEE_10G_ADV;
2627 } else {
2628 p_caps->default_eee = QED_MCP_EEE_UNSUPPORTED;
2629 }
2630
2631 DP_VERBOSE(p_hwfn,
2632 NETIF_MSG_LINK,
2633 "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x EEE: %02x [%08x usec]\n",
2634 link->speed.forced_speed,
2635 link->speed.advertised_speeds,
2636 link->speed.autoneg,
2637 link->pause.autoneg,
2638 p_caps->default_eee, p_caps->eee_lpi_timer);
2639
2640 /* Read Multi-function information from shmem */
2641 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2642 offsetof(struct nvm_cfg1, glob) +
2643 offsetof(struct nvm_cfg1_glob, generic_cont0);
2644
2645 generic_cont0 = qed_rd(p_hwfn, p_ptt, addr);
2646
2647 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
2648 NVM_CFG1_GLOB_MF_MODE_OFFSET;
2649
2650 switch (mf_mode) {
2651 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
2652 p_hwfn->cdev->mf_mode = QED_MF_OVLAN;
2653 break;
2654 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
2655 p_hwfn->cdev->mf_mode = QED_MF_NPAR;
2656 break;
2657 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
2658 p_hwfn->cdev->mf_mode = QED_MF_DEFAULT;
2659 break;
2660 }
2661 DP_INFO(p_hwfn, "Multi function mode is %08x\n",
2662 p_hwfn->cdev->mf_mode);
2663
2664 /* Read Multi-function information from shmem */
2665 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2666 offsetof(struct nvm_cfg1, glob) +
2667 offsetof(struct nvm_cfg1_glob, device_capabilities);
2668
2669 device_capabilities = qed_rd(p_hwfn, p_ptt, addr);
2670 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
2671 __set_bit(QED_DEV_CAP_ETH,
2672 &p_hwfn->hw_info.device_capabilities);
2673 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
2674 __set_bit(QED_DEV_CAP_FCOE,
2675 &p_hwfn->hw_info.device_capabilities);
2676 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
2677 __set_bit(QED_DEV_CAP_ISCSI,
2678 &p_hwfn->hw_info.device_capabilities);
2679 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
2680 __set_bit(QED_DEV_CAP_ROCE,
2681 &p_hwfn->hw_info.device_capabilities);
2682
2683 return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
2684 }
2685
2686 static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2687 {
2688 u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
2689 u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
2690 struct qed_dev *cdev = p_hwfn->cdev;
2691
2692 num_funcs = QED_IS_AH(cdev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
2693
2694 /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
2695 * in the other bits are selected.
2696 * Bits 1-15 are for functions 1-15, respectively, and their value is
2697 * '0' only for enabled functions (function 0 always exists and
2698 * enabled).
2699 * In case of CMT, only the "even" functions are enabled, and thus the
2700 * number of functions for both hwfns is learnt from the same bits.
2701 */
2702 reg_function_hide = qed_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE);
2703
2704 if (reg_function_hide & 0x1) {
2705 if (QED_IS_BB(cdev)) {
2706 if (QED_PATH_ID(p_hwfn) && cdev->num_hwfns == 1) {
2707 num_funcs = 0;
2708 eng_mask = 0xaaaa;
2709 } else {
2710 num_funcs = 1;
2711 eng_mask = 0x5554;
2712 }
2713 } else {
2714 num_funcs = 1;
2715 eng_mask = 0xfffe;
2716 }
2717
2718 /* Get the number of the enabled functions on the engine */
2719 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
2720 while (tmp) {
2721 if (tmp & 0x1)
2722 num_funcs++;
2723 tmp >>= 0x1;
2724 }
2725
2726 /* Get the PF index within the enabled functions */
2727 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
2728 tmp = reg_function_hide & eng_mask & low_pfs_mask;
2729 while (tmp) {
2730 if (tmp & 0x1)
2731 enabled_func_idx--;
2732 tmp >>= 0x1;
2733 }
2734 }
2735
2736 p_hwfn->num_funcs_on_engine = num_funcs;
2737 p_hwfn->enabled_func_idx = enabled_func_idx;
2738
2739 DP_VERBOSE(p_hwfn,
2740 NETIF_MSG_PROBE,
2741 "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
2742 p_hwfn->rel_pf_id,
2743 p_hwfn->abs_pf_id,
2744 p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
2745 }
2746
2747 static void qed_hw_info_port_num_bb(struct qed_hwfn *p_hwfn,
2748 struct qed_ptt *p_ptt)
2749 {
2750 u32 port_mode;
2751
2752 port_mode = qed_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB_B0);
2753
2754 if (port_mode < 3) {
2755 p_hwfn->cdev->num_ports_in_engine = 1;
2756 } else if (port_mode <= 5) {
2757 p_hwfn->cdev->num_ports_in_engine = 2;
2758 } else {
2759 DP_NOTICE(p_hwfn, "PORT MODE: %d not supported\n",
2760 p_hwfn->cdev->num_ports_in_engine);
2761
2762 /* Default num_ports_in_engine to something */
2763 p_hwfn->cdev->num_ports_in_engine = 1;
2764 }
2765 }
2766
2767 static void qed_hw_info_port_num_ah(struct qed_hwfn *p_hwfn,
2768 struct qed_ptt *p_ptt)
2769 {
2770 u32 port;
2771 int i;
2772
2773 p_hwfn->cdev->num_ports_in_engine = 0;
2774
2775 for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
2776 port = qed_rd(p_hwfn, p_ptt,
2777 CNIG_REG_NIG_PORT0_CONF_K2 + (i * 4));
2778 if (port & 1)
2779 p_hwfn->cdev->num_ports_in_engine++;
2780 }
2781
2782 if (!p_hwfn->cdev->num_ports_in_engine) {
2783 DP_NOTICE(p_hwfn, "All NIG ports are inactive\n");
2784
2785 /* Default num_ports_in_engine to something */
2786 p_hwfn->cdev->num_ports_in_engine = 1;
2787 }
2788 }
2789
2790 static void qed_hw_info_port_num(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2791 {
2792 if (QED_IS_BB(p_hwfn->cdev))
2793 qed_hw_info_port_num_bb(p_hwfn, p_ptt);
2794 else
2795 qed_hw_info_port_num_ah(p_hwfn, p_ptt);
2796 }
2797
2798 static void qed_get_eee_caps(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2799 {
2800 struct qed_mcp_link_capabilities *p_caps;
2801 u32 eee_status;
2802
2803 p_caps = &p_hwfn->mcp_info->link_capabilities;
2804 if (p_caps->default_eee == QED_MCP_EEE_UNSUPPORTED)
2805 return;
2806
2807 p_caps->eee_speed_caps = 0;
2808 eee_status = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
2809 offsetof(struct public_port, eee_status));
2810 eee_status = (eee_status & EEE_SUPPORTED_SPEED_MASK) >>
2811 EEE_SUPPORTED_SPEED_OFFSET;
2812
2813 if (eee_status & EEE_1G_SUPPORTED)
2814 p_caps->eee_speed_caps |= QED_EEE_1G_ADV;
2815 if (eee_status & EEE_10G_ADV)
2816 p_caps->eee_speed_caps |= QED_EEE_10G_ADV;
2817 }
2818
2819 static int
2820 qed_get_hw_info(struct qed_hwfn *p_hwfn,
2821 struct qed_ptt *p_ptt,
2822 enum qed_pci_personality personality)
2823 {
2824 int rc;
2825
2826 /* Since all information is common, only first hwfns should do this */
2827 if (IS_LEAD_HWFN(p_hwfn)) {
2828 rc = qed_iov_hw_info(p_hwfn);
2829 if (rc)
2830 return rc;
2831 }
2832
2833 qed_hw_info_port_num(p_hwfn, p_ptt);
2834
2835 qed_mcp_get_capabilities(p_hwfn, p_ptt);
2836
2837 qed_hw_get_nvm_info(p_hwfn, p_ptt);
2838
2839 rc = qed_int_igu_read_cam(p_hwfn, p_ptt);
2840 if (rc)
2841 return rc;
2842
2843 if (qed_mcp_is_init(p_hwfn))
2844 ether_addr_copy(p_hwfn->hw_info.hw_mac_addr,
2845 p_hwfn->mcp_info->func_info.mac);
2846 else
2847 eth_random_addr(p_hwfn->hw_info.hw_mac_addr);
2848
2849 if (qed_mcp_is_init(p_hwfn)) {
2850 if (p_hwfn->mcp_info->func_info.ovlan != QED_MCP_VLAN_UNSET)
2851 p_hwfn->hw_info.ovlan =
2852 p_hwfn->mcp_info->func_info.ovlan;
2853
2854 qed_mcp_cmd_port_init(p_hwfn, p_ptt);
2855
2856 qed_get_eee_caps(p_hwfn, p_ptt);
2857 }
2858
2859 if (qed_mcp_is_init(p_hwfn)) {
2860 enum qed_pci_personality protocol;
2861
2862 protocol = p_hwfn->mcp_info->func_info.protocol;
2863 p_hwfn->hw_info.personality = protocol;
2864 }
2865
2866 p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
2867 p_hwfn->hw_info.num_active_tc = 1;
2868
2869 qed_get_num_funcs(p_hwfn, p_ptt);
2870
2871 if (qed_mcp_is_init(p_hwfn))
2872 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
2873
2874 return qed_hw_get_resc(p_hwfn, p_ptt);
2875 }
2876
2877 static int qed_get_dev_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2878 {
2879 struct qed_dev *cdev = p_hwfn->cdev;
2880 u16 device_id_mask;
2881 u32 tmp;
2882
2883 /* Read Vendor Id / Device Id */
2884 pci_read_config_word(cdev->pdev, PCI_VENDOR_ID, &cdev->vendor_id);
2885 pci_read_config_word(cdev->pdev, PCI_DEVICE_ID, &cdev->device_id);
2886
2887 /* Determine type */
2888 device_id_mask = cdev->device_id & QED_DEV_ID_MASK;
2889 switch (device_id_mask) {
2890 case QED_DEV_ID_MASK_BB:
2891 cdev->type = QED_DEV_TYPE_BB;
2892 break;
2893 case QED_DEV_ID_MASK_AH:
2894 cdev->type = QED_DEV_TYPE_AH;
2895 break;
2896 default:
2897 DP_NOTICE(p_hwfn, "Unknown device id 0x%x\n", cdev->device_id);
2898 return -EBUSY;
2899 }
2900
2901 cdev->chip_num = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM);
2902 cdev->chip_rev = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV);
2903
2904 MASK_FIELD(CHIP_REV, cdev->chip_rev);
2905
2906 /* Learn number of HW-functions */
2907 tmp = qed_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR);
2908
2909 if (tmp & (1 << p_hwfn->rel_pf_id)) {
2910 DP_NOTICE(cdev->hwfns, "device in CMT mode\n");
2911 cdev->num_hwfns = 2;
2912 } else {
2913 cdev->num_hwfns = 1;
2914 }
2915
2916 cdev->chip_bond_id = qed_rd(p_hwfn, p_ptt,
2917 MISCS_REG_CHIP_TEST_REG) >> 4;
2918 MASK_FIELD(CHIP_BOND_ID, cdev->chip_bond_id);
2919 cdev->chip_metal = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL);
2920 MASK_FIELD(CHIP_METAL, cdev->chip_metal);
2921
2922 DP_INFO(cdev->hwfns,
2923 "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
2924 QED_IS_BB(cdev) ? "BB" : "AH",
2925 'A' + cdev->chip_rev,
2926 (int)cdev->chip_metal,
2927 cdev->chip_num, cdev->chip_rev,
2928 cdev->chip_bond_id, cdev->chip_metal);
2929
2930 return 0;
2931 }
2932
2933 static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn,
2934 void __iomem *p_regview,
2935 void __iomem *p_doorbells,
2936 enum qed_pci_personality personality)
2937 {
2938 int rc = 0;
2939
2940 /* Split PCI bars evenly between hwfns */
2941 p_hwfn->regview = p_regview;
2942 p_hwfn->doorbells = p_doorbells;
2943
2944 if (IS_VF(p_hwfn->cdev))
2945 return qed_vf_hw_prepare(p_hwfn);
2946
2947 /* Validate that chip access is feasible */
2948 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
2949 DP_ERR(p_hwfn,
2950 "Reading the ME register returns all Fs; Preventing further chip access\n");
2951 return -EINVAL;
2952 }
2953
2954 get_function_id(p_hwfn);
2955
2956 /* Allocate PTT pool */
2957 rc = qed_ptt_pool_alloc(p_hwfn);
2958 if (rc)
2959 goto err0;
2960
2961 /* Allocate the main PTT */
2962 p_hwfn->p_main_ptt = qed_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
2963
2964 /* First hwfn learns basic information, e.g., number of hwfns */
2965 if (!p_hwfn->my_id) {
2966 rc = qed_get_dev_info(p_hwfn, p_hwfn->p_main_ptt);
2967 if (rc)
2968 goto err1;
2969 }
2970
2971 qed_hw_hwfn_prepare(p_hwfn);
2972
2973 /* Initialize MCP structure */
2974 rc = qed_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
2975 if (rc) {
2976 DP_NOTICE(p_hwfn, "Failed initializing mcp command\n");
2977 goto err1;
2978 }
2979
2980 /* Read the device configuration information from the HW and SHMEM */
2981 rc = qed_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality);
2982 if (rc) {
2983 DP_NOTICE(p_hwfn, "Failed to get HW information\n");
2984 goto err2;
2985 }
2986
2987 /* Sending a mailbox to the MFW should be done after qed_get_hw_info()
2988 * is called as it sets the ports number in an engine.
2989 */
2990 if (IS_LEAD_HWFN(p_hwfn)) {
2991 rc = qed_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
2992 if (rc)
2993 DP_NOTICE(p_hwfn, "Failed to initiate PF FLR\n");
2994 }
2995
2996 /* Allocate the init RT array and initialize the init-ops engine */
2997 rc = qed_init_alloc(p_hwfn);
2998 if (rc)
2999 goto err2;
3000
3001 return rc;
3002 err2:
3003 if (IS_LEAD_HWFN(p_hwfn))
3004 qed_iov_free_hw_info(p_hwfn->cdev);
3005 qed_mcp_free(p_hwfn);
3006 err1:
3007 qed_hw_hwfn_free(p_hwfn);
3008 err0:
3009 return rc;
3010 }
3011
3012 int qed_hw_prepare(struct qed_dev *cdev,
3013 int personality)
3014 {
3015 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
3016 int rc;
3017
3018 /* Store the precompiled init data ptrs */
3019 if (IS_PF(cdev))
3020 qed_init_iro_array(cdev);
3021
3022 /* Initialize the first hwfn - will learn number of hwfns */
3023 rc = qed_hw_prepare_single(p_hwfn,
3024 cdev->regview,
3025 cdev->doorbells, personality);
3026 if (rc)
3027 return rc;
3028
3029 personality = p_hwfn->hw_info.personality;
3030
3031 /* Initialize the rest of the hwfns */
3032 if (cdev->num_hwfns > 1) {
3033 void __iomem *p_regview, *p_doorbell;
3034 u8 __iomem *addr;
3035
3036 /* adjust bar offset for second engine */
3037 addr = cdev->regview +
3038 qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
3039 BAR_ID_0) / 2;
3040 p_regview = addr;
3041
3042 addr = cdev->doorbells +
3043 qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
3044 BAR_ID_1) / 2;
3045 p_doorbell = addr;
3046
3047 /* prepare second hw function */
3048 rc = qed_hw_prepare_single(&cdev->hwfns[1], p_regview,
3049 p_doorbell, personality);
3050
3051 /* in case of error, need to free the previously
3052 * initiliazed hwfn 0.
3053 */
3054 if (rc) {
3055 if (IS_PF(cdev)) {
3056 qed_init_free(p_hwfn);
3057 qed_mcp_free(p_hwfn);
3058 qed_hw_hwfn_free(p_hwfn);
3059 }
3060 }
3061 }
3062
3063 return rc;
3064 }
3065
3066 void qed_hw_remove(struct qed_dev *cdev)
3067 {
3068 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
3069 int i;
3070
3071 if (IS_PF(cdev))
3072 qed_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
3073 QED_OV_DRIVER_STATE_NOT_LOADED);
3074
3075 for_each_hwfn(cdev, i) {
3076 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
3077
3078 if (IS_VF(cdev)) {
3079 qed_vf_pf_release(p_hwfn);
3080 continue;
3081 }
3082
3083 qed_init_free(p_hwfn);
3084 qed_hw_hwfn_free(p_hwfn);
3085 qed_mcp_free(p_hwfn);
3086 }
3087
3088 qed_iov_free_hw_info(cdev);
3089 }
3090
3091 static void qed_chain_free_next_ptr(struct qed_dev *cdev,
3092 struct qed_chain *p_chain)
3093 {
3094 void *p_virt = p_chain->p_virt_addr, *p_virt_next = NULL;
3095 dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
3096 struct qed_chain_next *p_next;
3097 u32 size, i;
3098
3099 if (!p_virt)
3100 return;
3101
3102 size = p_chain->elem_size * p_chain->usable_per_page;
3103
3104 for (i = 0; i < p_chain->page_cnt; i++) {
3105 if (!p_virt)
3106 break;
3107
3108 p_next = (struct qed_chain_next *)((u8 *)p_virt + size);
3109 p_virt_next = p_next->next_virt;
3110 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
3111
3112 dma_free_coherent(&cdev->pdev->dev,
3113 QED_CHAIN_PAGE_SIZE, p_virt, p_phys);
3114
3115 p_virt = p_virt_next;
3116 p_phys = p_phys_next;
3117 }
3118 }
3119
3120 static void qed_chain_free_single(struct qed_dev *cdev,
3121 struct qed_chain *p_chain)
3122 {
3123 if (!p_chain->p_virt_addr)
3124 return;
3125
3126 dma_free_coherent(&cdev->pdev->dev,
3127 QED_CHAIN_PAGE_SIZE,
3128 p_chain->p_virt_addr, p_chain->p_phys_addr);
3129 }
3130
3131 static void qed_chain_free_pbl(struct qed_dev *cdev, struct qed_chain *p_chain)
3132 {
3133 void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
3134 u32 page_cnt = p_chain->page_cnt, i, pbl_size;
3135 u8 *p_pbl_virt = p_chain->pbl_sp.p_virt_table;
3136
3137 if (!pp_virt_addr_tbl)
3138 return;
3139
3140 if (!p_pbl_virt)
3141 goto out;
3142
3143 for (i = 0; i < page_cnt; i++) {
3144 if (!pp_virt_addr_tbl[i])
3145 break;
3146
3147 dma_free_coherent(&cdev->pdev->dev,
3148 QED_CHAIN_PAGE_SIZE,
3149 pp_virt_addr_tbl[i],
3150 *(dma_addr_t *)p_pbl_virt);
3151
3152 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
3153 }
3154
3155 pbl_size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
3156
3157 if (!p_chain->b_external_pbl)
3158 dma_free_coherent(&cdev->pdev->dev,
3159 pbl_size,
3160 p_chain->pbl_sp.p_virt_table,
3161 p_chain->pbl_sp.p_phys_table);
3162 out:
3163 vfree(p_chain->pbl.pp_virt_addr_tbl);
3164 p_chain->pbl.pp_virt_addr_tbl = NULL;
3165 }
3166
3167 void qed_chain_free(struct qed_dev *cdev, struct qed_chain *p_chain)
3168 {
3169 switch (p_chain->mode) {
3170 case QED_CHAIN_MODE_NEXT_PTR:
3171 qed_chain_free_next_ptr(cdev, p_chain);
3172 break;
3173 case QED_CHAIN_MODE_SINGLE:
3174 qed_chain_free_single(cdev, p_chain);
3175 break;
3176 case QED_CHAIN_MODE_PBL:
3177 qed_chain_free_pbl(cdev, p_chain);
3178 break;
3179 }
3180 }
3181
3182 static int
3183 qed_chain_alloc_sanity_check(struct qed_dev *cdev,
3184 enum qed_chain_cnt_type cnt_type,
3185 size_t elem_size, u32 page_cnt)
3186 {
3187 u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
3188
3189 /* The actual chain size can be larger than the maximal possible value
3190 * after rounding up the requested elements number to pages, and after
3191 * taking into acount the unusuable elements (next-ptr elements).
3192 * The size of a "u16" chain can be (U16_MAX + 1) since the chain
3193 * size/capacity fields are of a u32 type.
3194 */
3195 if ((cnt_type == QED_CHAIN_CNT_TYPE_U16 &&
3196 chain_size > ((u32)U16_MAX + 1)) ||
3197 (cnt_type == QED_CHAIN_CNT_TYPE_U32 && chain_size > U32_MAX)) {
3198 DP_NOTICE(cdev,
3199 "The actual chain size (0x%llx) is larger than the maximal possible value\n",
3200 chain_size);
3201 return -EINVAL;
3202 }
3203
3204 return 0;
3205 }
3206
3207 static int
3208 qed_chain_alloc_next_ptr(struct qed_dev *cdev, struct qed_chain *p_chain)
3209 {
3210 void *p_virt = NULL, *p_virt_prev = NULL;
3211 dma_addr_t p_phys = 0;
3212 u32 i;
3213
3214 for (i = 0; i < p_chain->page_cnt; i++) {
3215 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
3216 QED_CHAIN_PAGE_SIZE,
3217 &p_phys, GFP_KERNEL);
3218 if (!p_virt)
3219 return -ENOMEM;
3220
3221 if (i == 0) {
3222 qed_chain_init_mem(p_chain, p_virt, p_phys);
3223 qed_chain_reset(p_chain);
3224 } else {
3225 qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3226 p_virt, p_phys);
3227 }
3228
3229 p_virt_prev = p_virt;
3230 }
3231 /* Last page's next element should point to the beginning of the
3232 * chain.
3233 */
3234 qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3235 p_chain->p_virt_addr,
3236 p_chain->p_phys_addr);
3237
3238 return 0;
3239 }
3240
3241 static int
3242 qed_chain_alloc_single(struct qed_dev *cdev, struct qed_chain *p_chain)
3243 {
3244 dma_addr_t p_phys = 0;
3245 void *p_virt = NULL;
3246
3247 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
3248 QED_CHAIN_PAGE_SIZE, &p_phys, GFP_KERNEL);
3249 if (!p_virt)
3250 return -ENOMEM;
3251
3252 qed_chain_init_mem(p_chain, p_virt, p_phys);
3253 qed_chain_reset(p_chain);
3254
3255 return 0;
3256 }
3257
3258 static int
3259 qed_chain_alloc_pbl(struct qed_dev *cdev,
3260 struct qed_chain *p_chain,
3261 struct qed_chain_ext_pbl *ext_pbl)
3262 {
3263 u32 page_cnt = p_chain->page_cnt, size, i;
3264 dma_addr_t p_phys = 0, p_pbl_phys = 0;
3265 void **pp_virt_addr_tbl = NULL;
3266 u8 *p_pbl_virt = NULL;
3267 void *p_virt = NULL;
3268
3269 size = page_cnt * sizeof(*pp_virt_addr_tbl);
3270 pp_virt_addr_tbl = vzalloc(size);
3271 if (!pp_virt_addr_tbl)
3272 return -ENOMEM;
3273
3274 /* The allocation of the PBL table is done with its full size, since it
3275 * is expected to be successive.
3276 * qed_chain_init_pbl_mem() is called even in a case of an allocation
3277 * failure, since pp_virt_addr_tbl was previously allocated, and it
3278 * should be saved to allow its freeing during the error flow.
3279 */
3280 size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
3281
3282 if (!ext_pbl) {
3283 p_pbl_virt = dma_alloc_coherent(&cdev->pdev->dev,
3284 size, &p_pbl_phys, GFP_KERNEL);
3285 } else {
3286 p_pbl_virt = ext_pbl->p_pbl_virt;
3287 p_pbl_phys = ext_pbl->p_pbl_phys;
3288 p_chain->b_external_pbl = true;
3289 }
3290
3291 qed_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
3292 pp_virt_addr_tbl);
3293 if (!p_pbl_virt)
3294 return -ENOMEM;
3295
3296 for (i = 0; i < page_cnt; i++) {
3297 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
3298 QED_CHAIN_PAGE_SIZE,
3299 &p_phys, GFP_KERNEL);
3300 if (!p_virt)
3301 return -ENOMEM;
3302
3303 if (i == 0) {
3304 qed_chain_init_mem(p_chain, p_virt, p_phys);
3305 qed_chain_reset(p_chain);
3306 }
3307
3308 /* Fill the PBL table with the physical address of the page */
3309 *(dma_addr_t *)p_pbl_virt = p_phys;
3310 /* Keep the virtual address of the page */
3311 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
3312
3313 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
3314 }
3315
3316 return 0;
3317 }
3318
3319 int qed_chain_alloc(struct qed_dev *cdev,
3320 enum qed_chain_use_mode intended_use,
3321 enum qed_chain_mode mode,
3322 enum qed_chain_cnt_type cnt_type,
3323 u32 num_elems,
3324 size_t elem_size,
3325 struct qed_chain *p_chain,
3326 struct qed_chain_ext_pbl *ext_pbl)
3327 {
3328 u32 page_cnt;
3329 int rc = 0;
3330
3331 if (mode == QED_CHAIN_MODE_SINGLE)
3332 page_cnt = 1;
3333 else
3334 page_cnt = QED_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
3335
3336 rc = qed_chain_alloc_sanity_check(cdev, cnt_type, elem_size, page_cnt);
3337 if (rc) {
3338 DP_NOTICE(cdev,
3339 "Cannot allocate a chain with the given arguments:\n");
3340 DP_NOTICE(cdev,
3341 "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
3342 intended_use, mode, cnt_type, num_elems, elem_size);
3343 return rc;
3344 }
3345
3346 qed_chain_init_params(p_chain, page_cnt, (u8) elem_size, intended_use,
3347 mode, cnt_type);
3348
3349 switch (mode) {
3350 case QED_CHAIN_MODE_NEXT_PTR:
3351 rc = qed_chain_alloc_next_ptr(cdev, p_chain);
3352 break;
3353 case QED_CHAIN_MODE_SINGLE:
3354 rc = qed_chain_alloc_single(cdev, p_chain);
3355 break;
3356 case QED_CHAIN_MODE_PBL:
3357 rc = qed_chain_alloc_pbl(cdev, p_chain, ext_pbl);
3358 break;
3359 }
3360 if (rc)
3361 goto nomem;
3362
3363 return 0;
3364
3365 nomem:
3366 qed_chain_free(cdev, p_chain);
3367 return rc;
3368 }
3369
3370 int qed_fw_l2_queue(struct qed_hwfn *p_hwfn, u16 src_id, u16 *dst_id)
3371 {
3372 if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) {
3373 u16 min, max;
3374
3375 min = (u16) RESC_START(p_hwfn, QED_L2_QUEUE);
3376 max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE);
3377 DP_NOTICE(p_hwfn,
3378 "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
3379 src_id, min, max);
3380
3381 return -EINVAL;
3382 }
3383
3384 *dst_id = RESC_START(p_hwfn, QED_L2_QUEUE) + src_id;
3385
3386 return 0;
3387 }
3388
3389 int qed_fw_vport(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
3390 {
3391 if (src_id >= RESC_NUM(p_hwfn, QED_VPORT)) {
3392 u8 min, max;
3393
3394 min = (u8)RESC_START(p_hwfn, QED_VPORT);
3395 max = min + RESC_NUM(p_hwfn, QED_VPORT);
3396 DP_NOTICE(p_hwfn,
3397 "vport id [%d] is not valid, available indices [%d - %d]\n",
3398 src_id, min, max);
3399
3400 return -EINVAL;
3401 }
3402
3403 *dst_id = RESC_START(p_hwfn, QED_VPORT) + src_id;
3404
3405 return 0;
3406 }
3407
3408 int qed_fw_rss_eng(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
3409 {
3410 if (src_id >= RESC_NUM(p_hwfn, QED_RSS_ENG)) {
3411 u8 min, max;
3412
3413 min = (u8)RESC_START(p_hwfn, QED_RSS_ENG);
3414 max = min + RESC_NUM(p_hwfn, QED_RSS_ENG);
3415 DP_NOTICE(p_hwfn,
3416 "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
3417 src_id, min, max);
3418
3419 return -EINVAL;
3420 }
3421
3422 *dst_id = RESC_START(p_hwfn, QED_RSS_ENG) + src_id;
3423
3424 return 0;
3425 }
3426
3427 static void qed_llh_mac_to_filter(u32 *p_high, u32 *p_low,
3428 u8 *p_filter)
3429 {
3430 *p_high = p_filter[1] | (p_filter[0] << 8);
3431 *p_low = p_filter[5] | (p_filter[4] << 8) |
3432 (p_filter[3] << 16) | (p_filter[2] << 24);
3433 }
3434
3435 int qed_llh_add_mac_filter(struct qed_hwfn *p_hwfn,
3436 struct qed_ptt *p_ptt, u8 *p_filter)
3437 {
3438 u32 high = 0, low = 0, en;
3439 int i;
3440
3441 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3442 return 0;
3443
3444 qed_llh_mac_to_filter(&high, &low, p_filter);
3445
3446 /* Find a free entry and utilize it */
3447 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3448 en = qed_rd(p_hwfn, p_ptt,
3449 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3450 if (en)
3451 continue;
3452 qed_wr(p_hwfn, p_ptt,
3453 NIG_REG_LLH_FUNC_FILTER_VALUE +
3454 2 * i * sizeof(u32), low);
3455 qed_wr(p_hwfn, p_ptt,
3456 NIG_REG_LLH_FUNC_FILTER_VALUE +
3457 (2 * i + 1) * sizeof(u32), high);
3458 qed_wr(p_hwfn, p_ptt,
3459 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3460 qed_wr(p_hwfn, p_ptt,
3461 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3462 i * sizeof(u32), 0);
3463 qed_wr(p_hwfn, p_ptt,
3464 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3465 break;
3466 }
3467 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3468 DP_NOTICE(p_hwfn,
3469 "Failed to find an empty LLH filter to utilize\n");
3470 return -EINVAL;
3471 }
3472
3473 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3474 "mac: %pM is added at %d\n",
3475 p_filter, i);
3476
3477 return 0;
3478 }
3479
3480 void qed_llh_remove_mac_filter(struct qed_hwfn *p_hwfn,
3481 struct qed_ptt *p_ptt, u8 *p_filter)
3482 {
3483 u32 high = 0, low = 0;
3484 int i;
3485
3486 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3487 return;
3488
3489 qed_llh_mac_to_filter(&high, &low, p_filter);
3490
3491 /* Find the entry and clean it */
3492 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3493 if (qed_rd(p_hwfn, p_ptt,
3494 NIG_REG_LLH_FUNC_FILTER_VALUE +
3495 2 * i * sizeof(u32)) != low)
3496 continue;
3497 if (qed_rd(p_hwfn, p_ptt,
3498 NIG_REG_LLH_FUNC_FILTER_VALUE +
3499 (2 * i + 1) * sizeof(u32)) != high)
3500 continue;
3501
3502 qed_wr(p_hwfn, p_ptt,
3503 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3504 qed_wr(p_hwfn, p_ptt,
3505 NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0);
3506 qed_wr(p_hwfn, p_ptt,
3507 NIG_REG_LLH_FUNC_FILTER_VALUE +
3508 (2 * i + 1) * sizeof(u32), 0);
3509
3510 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3511 "mac: %pM is removed from %d\n",
3512 p_filter, i);
3513 break;
3514 }
3515 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3516 DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n");
3517 }
3518
3519 int
3520 qed_llh_add_protocol_filter(struct qed_hwfn *p_hwfn,
3521 struct qed_ptt *p_ptt,
3522 u16 source_port_or_eth_type,
3523 u16 dest_port, enum qed_llh_port_filter_type_t type)
3524 {
3525 u32 high = 0, low = 0, en;
3526 int i;
3527
3528 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3529 return 0;
3530
3531 switch (type) {
3532 case QED_LLH_FILTER_ETHERTYPE:
3533 high = source_port_or_eth_type;
3534 break;
3535 case QED_LLH_FILTER_TCP_SRC_PORT:
3536 case QED_LLH_FILTER_UDP_SRC_PORT:
3537 low = source_port_or_eth_type << 16;
3538 break;
3539 case QED_LLH_FILTER_TCP_DEST_PORT:
3540 case QED_LLH_FILTER_UDP_DEST_PORT:
3541 low = dest_port;
3542 break;
3543 case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3544 case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3545 low = (source_port_or_eth_type << 16) | dest_port;
3546 break;
3547 default:
3548 DP_NOTICE(p_hwfn,
3549 "Non valid LLH protocol filter type %d\n", type);
3550 return -EINVAL;
3551 }
3552 /* Find a free entry and utilize it */
3553 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3554 en = qed_rd(p_hwfn, p_ptt,
3555 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3556 if (en)
3557 continue;
3558 qed_wr(p_hwfn, p_ptt,
3559 NIG_REG_LLH_FUNC_FILTER_VALUE +
3560 2 * i * sizeof(u32), low);
3561 qed_wr(p_hwfn, p_ptt,
3562 NIG_REG_LLH_FUNC_FILTER_VALUE +
3563 (2 * i + 1) * sizeof(u32), high);
3564 qed_wr(p_hwfn, p_ptt,
3565 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 1);
3566 qed_wr(p_hwfn, p_ptt,
3567 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3568 i * sizeof(u32), 1 << type);
3569 qed_wr(p_hwfn, p_ptt,
3570 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3571 break;
3572 }
3573 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3574 DP_NOTICE(p_hwfn,
3575 "Failed to find an empty LLH filter to utilize\n");
3576 return -EINVAL;
3577 }
3578 switch (type) {
3579 case QED_LLH_FILTER_ETHERTYPE:
3580 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3581 "ETH type %x is added at %d\n",
3582 source_port_or_eth_type, i);
3583 break;
3584 case QED_LLH_FILTER_TCP_SRC_PORT:
3585 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3586 "TCP src port %x is added at %d\n",
3587 source_port_or_eth_type, i);
3588 break;
3589 case QED_LLH_FILTER_UDP_SRC_PORT:
3590 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3591 "UDP src port %x is added at %d\n",
3592 source_port_or_eth_type, i);
3593 break;
3594 case QED_LLH_FILTER_TCP_DEST_PORT:
3595 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3596 "TCP dst port %x is added at %d\n", dest_port, i);
3597 break;
3598 case QED_LLH_FILTER_UDP_DEST_PORT:
3599 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3600 "UDP dst port %x is added at %d\n", dest_port, i);
3601 break;
3602 case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3603 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3604 "TCP src/dst ports %x/%x are added at %d\n",
3605 source_port_or_eth_type, dest_port, i);
3606 break;
3607 case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3608 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3609 "UDP src/dst ports %x/%x are added at %d\n",
3610 source_port_or_eth_type, dest_port, i);
3611 break;
3612 }
3613 return 0;
3614 }
3615
3616 void
3617 qed_llh_remove_protocol_filter(struct qed_hwfn *p_hwfn,
3618 struct qed_ptt *p_ptt,
3619 u16 source_port_or_eth_type,
3620 u16 dest_port,
3621 enum qed_llh_port_filter_type_t type)
3622 {
3623 u32 high = 0, low = 0;
3624 int i;
3625
3626 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3627 return;
3628
3629 switch (type) {
3630 case QED_LLH_FILTER_ETHERTYPE:
3631 high = source_port_or_eth_type;
3632 break;
3633 case QED_LLH_FILTER_TCP_SRC_PORT:
3634 case QED_LLH_FILTER_UDP_SRC_PORT:
3635 low = source_port_or_eth_type << 16;
3636 break;
3637 case QED_LLH_FILTER_TCP_DEST_PORT:
3638 case QED_LLH_FILTER_UDP_DEST_PORT:
3639 low = dest_port;
3640 break;
3641 case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3642 case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3643 low = (source_port_or_eth_type << 16) | dest_port;
3644 break;
3645 default:
3646 DP_NOTICE(p_hwfn,
3647 "Non valid LLH protocol filter type %d\n", type);
3648 return;
3649 }
3650
3651 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3652 if (!qed_rd(p_hwfn, p_ptt,
3653 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)))
3654 continue;
3655 if (!qed_rd(p_hwfn, p_ptt,
3656 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32)))
3657 continue;
3658 if (!(qed_rd(p_hwfn, p_ptt,
3659 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3660 i * sizeof(u32)) & BIT(type)))
3661 continue;
3662 if (qed_rd(p_hwfn, p_ptt,
3663 NIG_REG_LLH_FUNC_FILTER_VALUE +
3664 2 * i * sizeof(u32)) != low)
3665 continue;
3666 if (qed_rd(p_hwfn, p_ptt,
3667 NIG_REG_LLH_FUNC_FILTER_VALUE +
3668 (2 * i + 1) * sizeof(u32)) != high)
3669 continue;
3670
3671 qed_wr(p_hwfn, p_ptt,
3672 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3673 qed_wr(p_hwfn, p_ptt,
3674 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3675 qed_wr(p_hwfn, p_ptt,
3676 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3677 i * sizeof(u32), 0);
3678 qed_wr(p_hwfn, p_ptt,
3679 NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0);
3680 qed_wr(p_hwfn, p_ptt,
3681 NIG_REG_LLH_FUNC_FILTER_VALUE +
3682 (2 * i + 1) * sizeof(u32), 0);
3683 break;
3684 }
3685
3686 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3687 DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n");
3688 }
3689
3690 static int qed_set_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
3691 u32 hw_addr, void *p_eth_qzone,
3692 size_t eth_qzone_size, u8 timeset)
3693 {
3694 struct coalescing_timeset *p_coal_timeset;
3695
3696 if (p_hwfn->cdev->int_coalescing_mode != QED_COAL_MODE_ENABLE) {
3697 DP_NOTICE(p_hwfn, "Coalescing configuration not enabled\n");
3698 return -EINVAL;
3699 }
3700
3701 p_coal_timeset = p_eth_qzone;
3702 memset(p_eth_qzone, 0, eth_qzone_size);
3703 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
3704 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
3705 qed_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
3706
3707 return 0;
3708 }
3709
3710 int qed_set_queue_coalesce(u16 rx_coal, u16 tx_coal, void *p_handle)
3711 {
3712 struct qed_queue_cid *p_cid = p_handle;
3713 struct qed_hwfn *p_hwfn;
3714 struct qed_ptt *p_ptt;
3715 int rc = 0;
3716
3717 p_hwfn = p_cid->p_owner;
3718
3719 if (IS_VF(p_hwfn->cdev))
3720 return qed_vf_pf_set_coalesce(p_hwfn, rx_coal, tx_coal, p_cid);
3721
3722 p_ptt = qed_ptt_acquire(p_hwfn);
3723 if (!p_ptt)
3724 return -EAGAIN;
3725
3726 if (rx_coal) {
3727 rc = qed_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid);
3728 if (rc)
3729 goto out;
3730 p_hwfn->cdev->rx_coalesce_usecs = rx_coal;
3731 }
3732
3733 if (tx_coal) {
3734 rc = qed_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid);
3735 if (rc)
3736 goto out;
3737 p_hwfn->cdev->tx_coalesce_usecs = tx_coal;
3738 }
3739 out:
3740 qed_ptt_release(p_hwfn, p_ptt);
3741 return rc;
3742 }
3743
3744 int qed_set_rxq_coalesce(struct qed_hwfn *p_hwfn,
3745 struct qed_ptt *p_ptt,
3746 u16 coalesce, struct qed_queue_cid *p_cid)
3747 {
3748 struct ustorm_eth_queue_zone eth_qzone;
3749 u8 timeset, timer_res;
3750 u32 address;
3751 int rc;
3752
3753 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3754 if (coalesce <= 0x7F) {
3755 timer_res = 0;
3756 } else if (coalesce <= 0xFF) {
3757 timer_res = 1;
3758 } else if (coalesce <= 0x1FF) {
3759 timer_res = 2;
3760 } else {
3761 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3762 return -EINVAL;
3763 }
3764 timeset = (u8)(coalesce >> timer_res);
3765
3766 rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res,
3767 p_cid->sb_igu_id, false);
3768 if (rc)
3769 goto out;
3770
3771 address = BAR0_MAP_REG_USDM_RAM +
3772 USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
3773
3774 rc = qed_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
3775 sizeof(struct ustorm_eth_queue_zone), timeset);
3776 if (rc)
3777 goto out;
3778
3779 out:
3780 return rc;
3781 }
3782
3783 int qed_set_txq_coalesce(struct qed_hwfn *p_hwfn,
3784 struct qed_ptt *p_ptt,
3785 u16 coalesce, struct qed_queue_cid *p_cid)
3786 {
3787 struct xstorm_eth_queue_zone eth_qzone;
3788 u8 timeset, timer_res;
3789 u32 address;
3790 int rc;
3791
3792 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3793 if (coalesce <= 0x7F) {
3794 timer_res = 0;
3795 } else if (coalesce <= 0xFF) {
3796 timer_res = 1;
3797 } else if (coalesce <= 0x1FF) {
3798 timer_res = 2;
3799 } else {
3800 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3801 return -EINVAL;
3802 }
3803 timeset = (u8)(coalesce >> timer_res);
3804
3805 rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res,
3806 p_cid->sb_igu_id, true);
3807 if (rc)
3808 goto out;
3809
3810 address = BAR0_MAP_REG_XSDM_RAM +
3811 XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
3812
3813 rc = qed_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
3814 sizeof(struct xstorm_eth_queue_zone), timeset);
3815 out:
3816 return rc;
3817 }
3818
3819 /* Calculate final WFQ values for all vports and configure them.
3820 * After this configuration each vport will have
3821 * approx min rate = min_pf_rate * (vport_wfq / QED_WFQ_UNIT)
3822 */
3823 static void qed_configure_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
3824 struct qed_ptt *p_ptt,
3825 u32 min_pf_rate)
3826 {
3827 struct init_qm_vport_params *vport_params;
3828 int i;
3829
3830 vport_params = p_hwfn->qm_info.qm_vport_params;
3831
3832 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
3833 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
3834
3835 vport_params[i].vport_wfq = (wfq_speed * QED_WFQ_UNIT) /
3836 min_pf_rate;
3837 qed_init_vport_wfq(p_hwfn, p_ptt,
3838 vport_params[i].first_tx_pq_id,
3839 vport_params[i].vport_wfq);
3840 }
3841 }
3842
3843 static void qed_init_wfq_default_param(struct qed_hwfn *p_hwfn,
3844 u32 min_pf_rate)
3845
3846 {
3847 int i;
3848
3849 for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
3850 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
3851 }
3852
3853 static void qed_disable_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
3854 struct qed_ptt *p_ptt,
3855 u32 min_pf_rate)
3856 {
3857 struct init_qm_vport_params *vport_params;
3858 int i;
3859
3860 vport_params = p_hwfn->qm_info.qm_vport_params;
3861
3862 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
3863 qed_init_wfq_default_param(p_hwfn, min_pf_rate);
3864 qed_init_vport_wfq(p_hwfn, p_ptt,
3865 vport_params[i].first_tx_pq_id,
3866 vport_params[i].vport_wfq);
3867 }
3868 }
3869
3870 /* This function performs several validations for WFQ
3871 * configuration and required min rate for a given vport
3872 * 1. req_rate must be greater than one percent of min_pf_rate.
3873 * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
3874 * rates to get less than one percent of min_pf_rate.
3875 * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
3876 */
3877 static int qed_init_wfq_param(struct qed_hwfn *p_hwfn,
3878 u16 vport_id, u32 req_rate, u32 min_pf_rate)
3879 {
3880 u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
3881 int non_requested_count = 0, req_count = 0, i, num_vports;
3882
3883 num_vports = p_hwfn->qm_info.num_vports;
3884
3885 /* Accounting for the vports which are configured for WFQ explicitly */
3886 for (i = 0; i < num_vports; i++) {
3887 u32 tmp_speed;
3888
3889 if ((i != vport_id) &&
3890 p_hwfn->qm_info.wfq_data[i].configured) {
3891 req_count++;
3892 tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
3893 total_req_min_rate += tmp_speed;
3894 }
3895 }
3896
3897 /* Include current vport data as well */
3898 req_count++;
3899 total_req_min_rate += req_rate;
3900 non_requested_count = num_vports - req_count;
3901
3902 if (req_rate < min_pf_rate / QED_WFQ_UNIT) {
3903 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3904 "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
3905 vport_id, req_rate, min_pf_rate);
3906 return -EINVAL;
3907 }
3908
3909 if (num_vports > QED_WFQ_UNIT) {
3910 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3911 "Number of vports is greater than %d\n",
3912 QED_WFQ_UNIT);
3913 return -EINVAL;
3914 }
3915
3916 if (total_req_min_rate > min_pf_rate) {
3917 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3918 "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
3919 total_req_min_rate, min_pf_rate);
3920 return -EINVAL;
3921 }
3922
3923 total_left_rate = min_pf_rate - total_req_min_rate;
3924
3925 left_rate_per_vp = total_left_rate / non_requested_count;
3926 if (left_rate_per_vp < min_pf_rate / QED_WFQ_UNIT) {
3927 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3928 "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
3929 left_rate_per_vp, min_pf_rate);
3930 return -EINVAL;
3931 }
3932
3933 p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
3934 p_hwfn->qm_info.wfq_data[vport_id].configured = true;
3935
3936 for (i = 0; i < num_vports; i++) {
3937 if (p_hwfn->qm_info.wfq_data[i].configured)
3938 continue;
3939
3940 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
3941 }
3942
3943 return 0;
3944 }
3945
3946 static int __qed_configure_vport_wfq(struct qed_hwfn *p_hwfn,
3947 struct qed_ptt *p_ptt, u16 vp_id, u32 rate)
3948 {
3949 struct qed_mcp_link_state *p_link;
3950 int rc = 0;
3951
3952 p_link = &p_hwfn->cdev->hwfns[0].mcp_info->link_output;
3953
3954 if (!p_link->min_pf_rate) {
3955 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
3956 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
3957 return rc;
3958 }
3959
3960 rc = qed_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
3961
3962 if (!rc)
3963 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt,
3964 p_link->min_pf_rate);
3965 else
3966 DP_NOTICE(p_hwfn,
3967 "Validation failed while configuring min rate\n");
3968
3969 return rc;
3970 }
3971
3972 static int __qed_configure_vp_wfq_on_link_change(struct qed_hwfn *p_hwfn,
3973 struct qed_ptt *p_ptt,
3974 u32 min_pf_rate)
3975 {
3976 bool use_wfq = false;
3977 int rc = 0;
3978 u16 i;
3979
3980 /* Validate all pre configured vports for wfq */
3981 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
3982 u32 rate;
3983
3984 if (!p_hwfn->qm_info.wfq_data[i].configured)
3985 continue;
3986
3987 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
3988 use_wfq = true;
3989
3990 rc = qed_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
3991 if (rc) {
3992 DP_NOTICE(p_hwfn,
3993 "WFQ validation failed while configuring min rate\n");
3994 break;
3995 }
3996 }
3997
3998 if (!rc && use_wfq)
3999 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4000 else
4001 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4002
4003 return rc;
4004 }
4005
4006 /* Main API for qed clients to configure vport min rate.
4007 * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
4008 * rate - Speed in Mbps needs to be assigned to a given vport.
4009 */
4010 int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate)
4011 {
4012 int i, rc = -EINVAL;
4013
4014 /* Currently not supported; Might change in future */
4015 if (cdev->num_hwfns > 1) {
4016 DP_NOTICE(cdev,
4017 "WFQ configuration is not supported for this device\n");
4018 return rc;
4019 }
4020
4021 for_each_hwfn(cdev, i) {
4022 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4023 struct qed_ptt *p_ptt;
4024
4025 p_ptt = qed_ptt_acquire(p_hwfn);
4026 if (!p_ptt)
4027 return -EBUSY;
4028
4029 rc = __qed_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
4030
4031 if (rc) {
4032 qed_ptt_release(p_hwfn, p_ptt);
4033 return rc;
4034 }
4035
4036 qed_ptt_release(p_hwfn, p_ptt);
4037 }
4038
4039 return rc;
4040 }
4041
4042 /* API to configure WFQ from mcp link change */
4043 void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev,
4044 struct qed_ptt *p_ptt, u32 min_pf_rate)
4045 {
4046 int i;
4047
4048 if (cdev->num_hwfns > 1) {
4049 DP_VERBOSE(cdev,
4050 NETIF_MSG_LINK,
4051 "WFQ configuration is not supported for this device\n");
4052 return;
4053 }
4054
4055 for_each_hwfn(cdev, i) {
4056 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4057
4058 __qed_configure_vp_wfq_on_link_change(p_hwfn, p_ptt,
4059 min_pf_rate);
4060 }
4061 }
4062
4063 int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn,
4064 struct qed_ptt *p_ptt,
4065 struct qed_mcp_link_state *p_link,
4066 u8 max_bw)
4067 {
4068 int rc = 0;
4069
4070 p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
4071
4072 if (!p_link->line_speed && (max_bw != 100))
4073 return rc;
4074
4075 p_link->speed = (p_link->line_speed * max_bw) / 100;
4076 p_hwfn->qm_info.pf_rl = p_link->speed;
4077
4078 /* Since the limiter also affects Tx-switched traffic, we don't want it
4079 * to limit such traffic in case there's no actual limit.
4080 * In that case, set limit to imaginary high boundary.
4081 */
4082 if (max_bw == 100)
4083 p_hwfn->qm_info.pf_rl = 100000;
4084
4085 rc = qed_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
4086 p_hwfn->qm_info.pf_rl);
4087
4088 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4089 "Configured MAX bandwidth to be %08x Mb/sec\n",
4090 p_link->speed);
4091
4092 return rc;
4093 }
4094
4095 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
4096 int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw)
4097 {
4098 int i, rc = -EINVAL;
4099
4100 if (max_bw < 1 || max_bw > 100) {
4101 DP_NOTICE(cdev, "PF max bw valid range is [1-100]\n");
4102 return rc;
4103 }
4104
4105 for_each_hwfn(cdev, i) {
4106 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4107 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
4108 struct qed_mcp_link_state *p_link;
4109 struct qed_ptt *p_ptt;
4110
4111 p_link = &p_lead->mcp_info->link_output;
4112
4113 p_ptt = qed_ptt_acquire(p_hwfn);
4114 if (!p_ptt)
4115 return -EBUSY;
4116
4117 rc = __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt,
4118 p_link, max_bw);
4119
4120 qed_ptt_release(p_hwfn, p_ptt);
4121
4122 if (rc)
4123 break;
4124 }
4125
4126 return rc;
4127 }
4128
4129 int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn,
4130 struct qed_ptt *p_ptt,
4131 struct qed_mcp_link_state *p_link,
4132 u8 min_bw)
4133 {
4134 int rc = 0;
4135
4136 p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
4137 p_hwfn->qm_info.pf_wfq = min_bw;
4138
4139 if (!p_link->line_speed)
4140 return rc;
4141
4142 p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
4143
4144 rc = qed_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
4145
4146 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4147 "Configured MIN bandwidth to be %d Mb/sec\n",
4148 p_link->min_pf_rate);
4149
4150 return rc;
4151 }
4152
4153 /* Main API to configure PF min bandwidth where bw range is [1-100] */
4154 int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw)
4155 {
4156 int i, rc = -EINVAL;
4157
4158 if (min_bw < 1 || min_bw > 100) {
4159 DP_NOTICE(cdev, "PF min bw valid range is [1-100]\n");
4160 return rc;
4161 }
4162
4163 for_each_hwfn(cdev, i) {
4164 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4165 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
4166 struct qed_mcp_link_state *p_link;
4167 struct qed_ptt *p_ptt;
4168
4169 p_link = &p_lead->mcp_info->link_output;
4170
4171 p_ptt = qed_ptt_acquire(p_hwfn);
4172 if (!p_ptt)
4173 return -EBUSY;
4174
4175 rc = __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt,
4176 p_link, min_bw);
4177 if (rc) {
4178 qed_ptt_release(p_hwfn, p_ptt);
4179 return rc;
4180 }
4181
4182 if (p_link->min_pf_rate) {
4183 u32 min_rate = p_link->min_pf_rate;
4184
4185 rc = __qed_configure_vp_wfq_on_link_change(p_hwfn,
4186 p_ptt,
4187 min_rate);
4188 }
4189
4190 qed_ptt_release(p_hwfn, p_ptt);
4191 }
4192
4193 return rc;
4194 }
4195
4196 void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
4197 {
4198 struct qed_mcp_link_state *p_link;
4199
4200 p_link = &p_hwfn->mcp_info->link_output;
4201
4202 if (p_link->min_pf_rate)
4203 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt,
4204 p_link->min_pf_rate);
4205
4206 memset(p_hwfn->qm_info.wfq_data, 0,
4207 sizeof(*p_hwfn->qm_info.wfq_data) * p_hwfn->qm_info.num_vports);
4208 }
4209
4210 int qed_device_num_engines(struct qed_dev *cdev)
4211 {
4212 return QED_IS_BB(cdev) ? 2 : 1;
4213 }
4214
4215 static int qed_device_num_ports(struct qed_dev *cdev)
4216 {
4217 /* in CMT always only one port */
4218 if (cdev->num_hwfns > 1)
4219 return 1;
4220
4221 return cdev->num_ports_in_engine * qed_device_num_engines(cdev);
4222 }
4223
4224 int qed_device_get_port_id(struct qed_dev *cdev)
4225 {
4226 return (QED_LEADING_HWFN(cdev)->abs_pf_id) % qed_device_num_ports(cdev);
4227 }
4228
4229 void qed_set_fw_mac_addr(__le16 *fw_msb,
4230 __le16 *fw_mid, __le16 *fw_lsb, u8 *mac)
4231 {
4232 ((u8 *)fw_msb)[0] = mac[1];
4233 ((u8 *)fw_msb)[1] = mac[0];
4234 ((u8 *)fw_mid)[0] = mac[3];
4235 ((u8 *)fw_mid)[1] = mac[2];
4236 ((u8 *)fw_lsb)[0] = mac[5];
4237 ((u8 *)fw_lsb)[1] = mac[4];
4238 }
CRIS linux kernel tree