drivers/net/ethernet/qlogic/qed/qed_hsi.h

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015-2017  QLogic Corporation
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and /or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #ifndef _QED_HSI_H
  34 #define _QED_HSI_H
  35
  36 #include <linux/types.h>
  37 #include <linux/io.h>
  38 #include <linux/bitops.h>
  39 #include <linux/delay.h>
  40 #include <linux/kernel.h>
  41 #include <linux/list.h>
  42 #include <linux/slab.h>
  43 #include <linux/qed/common_hsi.h>
  44 #include <linux/qed/storage_common.h>
  45 #include <linux/qed/tcp_common.h>
  46 #include <linux/qed/fcoe_common.h>
  47 #include <linux/qed/eth_common.h>
  48 #include <linux/qed/iscsi_common.h>
  49 #include <linux/qed/iwarp_common.h>
  50 #include <linux/qed/rdma_common.h>
  51 #include <linux/qed/roce_common.h>
  52 #include <linux/qed/qed_fcoe_if.h>
  53
  54 struct qed_hwfn;
  55 struct qed_ptt;
  56
  57 /* Opcodes for the event ring */
  58 enum common_event_opcode {
  59         COMMON_EVENT_PF_START,
  60         COMMON_EVENT_PF_STOP,
  61         COMMON_EVENT_VF_START,
  62         COMMON_EVENT_VF_STOP,
  63         COMMON_EVENT_VF_PF_CHANNEL,
  64         COMMON_EVENT_VF_FLR,
  65         COMMON_EVENT_PF_UPDATE,
  66         COMMON_EVENT_MALICIOUS_VF,
  67         COMMON_EVENT_RL_UPDATE,
  68         COMMON_EVENT_EMPTY,
  69         MAX_COMMON_EVENT_OPCODE
  70 };
  71
  72 /* Common Ramrod Command IDs */
  73 enum common_ramrod_cmd_id {
  74         COMMON_RAMROD_UNUSED,
  75         COMMON_RAMROD_PF_START,
  76         COMMON_RAMROD_PF_STOP,
  77         COMMON_RAMROD_VF_START,
  78         COMMON_RAMROD_VF_STOP,
  79         COMMON_RAMROD_PF_UPDATE,
  80         COMMON_RAMROD_RL_UPDATE,
  81         COMMON_RAMROD_EMPTY,
  82         MAX_COMMON_RAMROD_CMD_ID
  83 };
  84
  85 /* How ll2 should deal with packet upon errors */
  86 enum core_error_handle {
  87         LL2_DROP_PACKET,
  88         LL2_DO_NOTHING,
  89         LL2_ASSERT,
  90         MAX_CORE_ERROR_HANDLE
  91 };
  92
  93 /* Opcodes for the event ring */
  94 enum core_event_opcode {
  95         CORE_EVENT_TX_QUEUE_START,
  96         CORE_EVENT_TX_QUEUE_STOP,
  97         CORE_EVENT_RX_QUEUE_START,
  98         CORE_EVENT_RX_QUEUE_STOP,
  99         CORE_EVENT_RX_QUEUE_FLUSH,
 100         CORE_EVENT_TX_QUEUE_UPDATE,
 101         MAX_CORE_EVENT_OPCODE
 102 };
 103
 104 /* The L4 pseudo checksum mode for Core */
 105 enum core_l4_pseudo_checksum_mode {
 106         CORE_L4_PSEUDO_CSUM_CORRECT_LENGTH,
 107         CORE_L4_PSEUDO_CSUM_ZERO_LENGTH,
 108         MAX_CORE_L4_PSEUDO_CHECKSUM_MODE
 109 };
 110
 111 /* Light-L2 RX Producers in Tstorm RAM */
 112 struct core_ll2_port_stats {
 113         struct regpair gsi_invalid_hdr;
 114         struct regpair gsi_invalid_pkt_length;
 115         struct regpair gsi_unsupported_pkt_typ;
 116         struct regpair gsi_crcchksm_error;
 117 };
 118
 119 /* Ethernet TX Per Queue Stats */
 120 struct core_ll2_pstorm_per_queue_stat {
 121         struct regpair sent_ucast_bytes;
 122         struct regpair sent_mcast_bytes;
 123         struct regpair sent_bcast_bytes;
 124         struct regpair sent_ucast_pkts;
 125         struct regpair sent_mcast_pkts;
 126         struct regpair sent_bcast_pkts;
 127 };
 128
 129 /* Light-L2 RX Producers in Tstorm RAM */
 130 struct core_ll2_rx_prod {
 131         __le16 bd_prod;
 132         __le16 cqe_prod;
 133         __le32 reserved;
 134 };
 135
 136 struct core_ll2_tstorm_per_queue_stat {
 137         struct regpair packet_too_big_discard;
 138         struct regpair no_buff_discard;
 139 };
 140
 141 struct core_ll2_ustorm_per_queue_stat {
 142         struct regpair rcv_ucast_bytes;
 143         struct regpair rcv_mcast_bytes;
 144         struct regpair rcv_bcast_bytes;
 145         struct regpair rcv_ucast_pkts;
 146         struct regpair rcv_mcast_pkts;
 147         struct regpair rcv_bcast_pkts;
 148 };
 149
 150 /* Core Ramrod Command IDs (light L2) */
 151 enum core_ramrod_cmd_id {
 152         CORE_RAMROD_UNUSED,
 153         CORE_RAMROD_RX_QUEUE_START,
 154         CORE_RAMROD_TX_QUEUE_START,
 155         CORE_RAMROD_RX_QUEUE_STOP,
 156         CORE_RAMROD_TX_QUEUE_STOP,
 157         CORE_RAMROD_RX_QUEUE_FLUSH,
 158         CORE_RAMROD_TX_QUEUE_UPDATE,
 159         MAX_CORE_RAMROD_CMD_ID
 160 };
 161
 162 /* Core RX CQE Type for Light L2 */
 163 enum core_roce_flavor_type {
 164         CORE_ROCE,
 165         CORE_RROCE,
 166         MAX_CORE_ROCE_FLAVOR_TYPE
 167 };
 168
 169 /* Specifies how ll2 should deal with packets errors: packet_too_big and
 170  * no_buff.
 171  */
 172 struct core_rx_action_on_error {
 173         u8 error_type;
 174 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_MASK     0x3
 175 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_SHIFT    0
 176 #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_MASK            0x3
 177 #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_SHIFT           2
 178 #define CORE_RX_ACTION_ON_ERROR_RESERVED_MASK           0xF
 179 #define CORE_RX_ACTION_ON_ERROR_RESERVED_SHIFT          4
 180 };
 181
 182 /* Core RX BD for Light L2 */
 183 struct core_rx_bd {
 184         struct regpair addr;
 185         __le16 reserved[4];
 186 };
 187
 188 /* Core RX CM offload BD for Light L2 */
 189 struct core_rx_bd_with_buff_len {
 190         struct regpair addr;
 191         __le16 buff_length;
 192         __le16 reserved[3];
 193 };
 194
 195 /* Core RX CM offload BD for Light L2 */
 196 union core_rx_bd_union {
 197         struct core_rx_bd rx_bd;
 198         struct core_rx_bd_with_buff_len rx_bd_with_len;
 199 };
 200
 201 /* Opaque Data for Light L2 RX CQE */
 202 struct core_rx_cqe_opaque_data {
 203         __le32 data[2];
 204 };
 205
 206 /* Core RX CQE Type for Light L2 */
 207 enum core_rx_cqe_type {
 208         CORE_RX_CQE_ILLEGAL_TYPE,
 209         CORE_RX_CQE_TYPE_REGULAR,
 210         CORE_RX_CQE_TYPE_GSI_OFFLOAD,
 211         CORE_RX_CQE_TYPE_SLOW_PATH,
 212         MAX_CORE_RX_CQE_TYPE
 213 };
 214
 215 /* Core RX CQE for Light L2 */
 216 struct core_rx_fast_path_cqe {
 217         u8 type;
 218         u8 placement_offset;
 219         struct parsing_and_err_flags parse_flags;
 220         __le16 packet_length;
 221         __le16 vlan;
 222         struct core_rx_cqe_opaque_data opaque_data;
 223         struct parsing_err_flags err_flags;
 224         __le16 reserved0;
 225         __le32 reserved1[3];
 226 };
 227
 228 /* Core Rx CM offload CQE */
 229 struct core_rx_gsi_offload_cqe {
 230         u8 type;
 231         u8 data_length_error;
 232         struct parsing_and_err_flags parse_flags;
 233         __le16 data_length;
 234         __le16 vlan;
 235         __le32 src_mac_addrhi;
 236         __le16 src_mac_addrlo;
 237         __le16 qp_id;
 238         __le32 src_qp;
 239         __le32 reserved[3];
 240 };
 241
 242 /* Core RX CQE for Light L2 */
 243 struct core_rx_slow_path_cqe {
 244         u8 type;
 245         u8 ramrod_cmd_id;
 246         __le16 echo;
 247         struct core_rx_cqe_opaque_data opaque_data;
 248         __le32 reserved1[5];
 249 };
 250
 251 /* Core RX CM offload BD for Light L2 */
 252 union core_rx_cqe_union {
 253         struct core_rx_fast_path_cqe rx_cqe_fp;
 254         struct core_rx_gsi_offload_cqe rx_cqe_gsi;
 255         struct core_rx_slow_path_cqe rx_cqe_sp;
 256 };
 257
 258 /* Ramrod data for rx queue start ramrod */
 259 struct core_rx_start_ramrod_data {
 260         struct regpair bd_base;
 261         struct regpair cqe_pbl_addr;
 262         __le16 mtu;
 263         __le16 sb_id;
 264         u8 sb_index;
 265         u8 complete_cqe_flg;
 266         u8 complete_event_flg;
 267         u8 drop_ttl0_flg;
 268         __le16 num_of_pbl_pages;
 269         u8 inner_vlan_stripping_en;
 270         u8 report_outer_vlan;
 271         u8 queue_id;
 272         u8 main_func_queue;
 273         u8 mf_si_bcast_accept_all;
 274         u8 mf_si_mcast_accept_all;
 275         struct core_rx_action_on_error action_on_error;
 276         u8 gsi_offload_flag;
 277         u8 reserved[6];
 278 };
 279
 280 /* Ramrod data for rx queue stop ramrod */
 281 struct core_rx_stop_ramrod_data {
 282         u8 complete_cqe_flg;
 283         u8 complete_event_flg;
 284         u8 queue_id;
 285         u8 reserved1;
 286         __le16 reserved2[2];
 287 };
 288
 289 /* Flags for Core TX BD */
 290 struct core_tx_bd_data {
 291         __le16 as_bitfield;
 292 #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_MASK            0x1
 293 #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_SHIFT           0
 294 #define CORE_TX_BD_DATA_VLAN_INSERTION_MASK             0x1
 295 #define CORE_TX_BD_DATA_VLAN_INSERTION_SHIFT            1
 296 #define CORE_TX_BD_DATA_START_BD_MASK                   0x1
 297 #define CORE_TX_BD_DATA_START_BD_SHIFT                  2
 298 #define CORE_TX_BD_DATA_IP_CSUM_MASK                    0x1
 299 #define CORE_TX_BD_DATA_IP_CSUM_SHIFT                   3
 300 #define CORE_TX_BD_DATA_L4_CSUM_MASK                    0x1
 301 #define CORE_TX_BD_DATA_L4_CSUM_SHIFT                   4
 302 #define CORE_TX_BD_DATA_IPV6_EXT_MASK                   0x1
 303 #define CORE_TX_BD_DATA_IPV6_EXT_SHIFT                  5
 304 #define CORE_TX_BD_DATA_L4_PROTOCOL_MASK                0x1
 305 #define CORE_TX_BD_DATA_L4_PROTOCOL_SHIFT               6
 306 #define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_MASK        0x1
 307 #define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_SHIFT       7
 308 #define CORE_TX_BD_DATA_NBDS_MASK                       0xF
 309 #define CORE_TX_BD_DATA_NBDS_SHIFT                      8
 310 #define CORE_TX_BD_DATA_ROCE_FLAV_MASK                  0x1
 311 #define CORE_TX_BD_DATA_ROCE_FLAV_SHIFT                 12
 312 #define CORE_TX_BD_DATA_IP_LEN_MASK                     0x1
 313 #define CORE_TX_BD_DATA_IP_LEN_SHIFT                    13
 314 #define CORE_TX_BD_DATA_DISABLE_STAG_INSERTION_MASK     0x1
 315 #define CORE_TX_BD_DATA_DISABLE_STAG_INSERTION_SHIFT    14
 316 #define CORE_TX_BD_DATA_RESERVED0_MASK                  0x1
 317 #define CORE_TX_BD_DATA_RESERVED0_SHIFT                 15
 318 };
 319
 320 /* Core TX BD for Light L2 */
 321 struct core_tx_bd {
 322         struct regpair addr;
 323         __le16 nbytes;
 324         __le16 nw_vlan_or_lb_echo;
 325         struct core_tx_bd_data bd_data;
 326         __le16 bitfield1;
 327 #define CORE_TX_BD_L4_HDR_OFFSET_W_MASK         0x3FFF
 328 #define CORE_TX_BD_L4_HDR_OFFSET_W_SHIFT        0
 329 #define CORE_TX_BD_TX_DST_MASK                  0x3
 330 #define CORE_TX_BD_TX_DST_SHIFT                 14
 331 };
 332
 333 /* Light L2 TX Destination */
 334 enum core_tx_dest {
 335         CORE_TX_DEST_NW,
 336         CORE_TX_DEST_LB,
 337         CORE_TX_DEST_RESERVED,
 338         CORE_TX_DEST_DROP,
 339         MAX_CORE_TX_DEST
 340 };
 341
 342 /* Ramrod data for tx queue start ramrod */
 343 struct core_tx_start_ramrod_data {
 344         struct regpair pbl_base_addr;
 345         __le16 mtu;
 346         __le16 sb_id;
 347         u8 sb_index;
 348         u8 stats_en;
 349         u8 stats_id;
 350         u8 conn_type;
 351         __le16 pbl_size;
 352         __le16 qm_pq_id;
 353         u8 gsi_offload_flag;
 354         u8 resrved[3];
 355 };
 356
 357 /* Ramrod data for tx queue stop ramrod */
 358 struct core_tx_stop_ramrod_data {
 359         __le32 reserved0[2];
 360 };
 361
 362 /* Ramrod data for tx queue update ramrod */
 363 struct core_tx_update_ramrod_data {
 364         u8 update_qm_pq_id_flg;
 365         u8 reserved0;
 366         __le16 qm_pq_id;
 367         __le32 reserved1[1];
 368 };
 369
 370 /* Enum flag for what type of dcb data to update */
 371 enum dcb_dscp_update_mode {
 372         DONT_UPDATE_DCB_DSCP,
 373         UPDATE_DCB,
 374         UPDATE_DSCP,
 375         UPDATE_DCB_DSCP,
 376         MAX_DCB_DSCP_UPDATE_MODE
 377 };
 378
 379 /* The core storm context for the Ystorm */
 380 struct ystorm_core_conn_st_ctx {
 381         __le32 reserved[4];
 382 };
 383
 384 /* The core storm context for the Pstorm */
 385 struct pstorm_core_conn_st_ctx {
 386         __le32 reserved[4];
 387 };
 388
 389 /* Core Slowpath Connection storm context of Xstorm */
 390 struct xstorm_core_conn_st_ctx {
 391         __le32 spq_base_lo;
 392         __le32 spq_base_hi;
 393         struct regpair consolid_base_addr;
 394         __le16 spq_cons;
 395         __le16 consolid_cons;
 396         __le32 reserved0[55];
 397 };
 398
 399 struct e4_xstorm_core_conn_ag_ctx {
 400         u8 reserved0;
 401         u8 state;
 402         u8 flags0;
 403 #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_MASK    0x1
 404 #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT   0
 405 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED1_MASK       0x1
 406 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED1_SHIFT      1
 407 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED2_MASK       0x1
 408 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED2_SHIFT      2
 409 #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_MASK    0x1
 410 #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT   3
 411 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED3_MASK       0x1
 412 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED3_SHIFT      4
 413 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED4_MASK       0x1
 414 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED4_SHIFT      5
 415 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED5_MASK       0x1
 416 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED5_SHIFT      6
 417 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED6_MASK       0x1
 418 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED6_SHIFT      7
 419         u8 flags1;
 420 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED7_MASK       0x1
 421 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED7_SHIFT      0
 422 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED8_MASK       0x1
 423 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED8_SHIFT      1
 424 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED9_MASK       0x1
 425 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED9_SHIFT      2
 426 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT11_MASK           0x1
 427 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT11_SHIFT          3
 428 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT12_MASK           0x1
 429 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT12_SHIFT          4
 430 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT13_MASK           0x1
 431 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT13_SHIFT          5
 432 #define E4_XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_MASK  0x1
 433 #define E4_XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
 434 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_MASK    0x1
 435 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT   7
 436         u8 flags2;
 437 #define E4_XSTORM_CORE_CONN_AG_CTX_CF0_MASK     0x3
 438 #define E4_XSTORM_CORE_CONN_AG_CTX_CF0_SHIFT    0
 439 #define E4_XSTORM_CORE_CONN_AG_CTX_CF1_MASK     0x3
 440 #define E4_XSTORM_CORE_CONN_AG_CTX_CF1_SHIFT    2
 441 #define E4_XSTORM_CORE_CONN_AG_CTX_CF2_MASK     0x3
 442 #define E4_XSTORM_CORE_CONN_AG_CTX_CF2_SHIFT    4
 443 #define E4_XSTORM_CORE_CONN_AG_CTX_CF3_MASK     0x3
 444 #define E4_XSTORM_CORE_CONN_AG_CTX_CF3_SHIFT    6
 445         u8 flags3;
 446 #define E4_XSTORM_CORE_CONN_AG_CTX_CF4_MASK     0x3
 447 #define E4_XSTORM_CORE_CONN_AG_CTX_CF4_SHIFT    0
 448 #define E4_XSTORM_CORE_CONN_AG_CTX_CF5_MASK     0x3
 449 #define E4_XSTORM_CORE_CONN_AG_CTX_CF5_SHIFT    2
 450 #define E4_XSTORM_CORE_CONN_AG_CTX_CF6_MASK     0x3
 451 #define E4_XSTORM_CORE_CONN_AG_CTX_CF6_SHIFT    4
 452 #define E4_XSTORM_CORE_CONN_AG_CTX_CF7_MASK     0x3
 453 #define E4_XSTORM_CORE_CONN_AG_CTX_CF7_SHIFT    6
 454         u8 flags4;
 455 #define E4_XSTORM_CORE_CONN_AG_CTX_CF8_MASK     0x3
 456 #define E4_XSTORM_CORE_CONN_AG_CTX_CF8_SHIFT    0
 457 #define E4_XSTORM_CORE_CONN_AG_CTX_CF9_MASK     0x3
 458 #define E4_XSTORM_CORE_CONN_AG_CTX_CF9_SHIFT    2
 459 #define E4_XSTORM_CORE_CONN_AG_CTX_CF10_MASK    0x3
 460 #define E4_XSTORM_CORE_CONN_AG_CTX_CF10_SHIFT   4
 461 #define E4_XSTORM_CORE_CONN_AG_CTX_CF11_MASK    0x3
 462 #define E4_XSTORM_CORE_CONN_AG_CTX_CF11_SHIFT   6
 463         u8 flags5;
 464 #define E4_XSTORM_CORE_CONN_AG_CTX_CF12_MASK    0x3
 465 #define E4_XSTORM_CORE_CONN_AG_CTX_CF12_SHIFT   0
 466 #define E4_XSTORM_CORE_CONN_AG_CTX_CF13_MASK    0x3
 467 #define E4_XSTORM_CORE_CONN_AG_CTX_CF13_SHIFT   2
 468 #define E4_XSTORM_CORE_CONN_AG_CTX_CF14_MASK    0x3
 469 #define E4_XSTORM_CORE_CONN_AG_CTX_CF14_SHIFT   4
 470 #define E4_XSTORM_CORE_CONN_AG_CTX_CF15_MASK    0x3
 471 #define E4_XSTORM_CORE_CONN_AG_CTX_CF15_SHIFT   6
 472         u8 flags6;
 473 #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_MASK        0x3
 474 #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_SHIFT       0
 475 #define E4_XSTORM_CORE_CONN_AG_CTX_CF17_MASK                    0x3
 476 #define E4_XSTORM_CORE_CONN_AG_CTX_CF17_SHIFT                   2
 477 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_MASK                   0x3
 478 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_SHIFT                  4
 479 #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_MASK            0x3
 480 #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_SHIFT           6
 481         u8 flags7;
 482 #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_MASK        0x3
 483 #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_SHIFT       0
 484 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED10_MASK      0x3
 485 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED10_SHIFT     2
 486 #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_MASK       0x3
 487 #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_SHIFT      4
 488 #define E4_XSTORM_CORE_CONN_AG_CTX_CF0EN_MASK           0x1
 489 #define E4_XSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT          6
 490 #define E4_XSTORM_CORE_CONN_AG_CTX_CF1EN_MASK           0x1
 491 #define E4_XSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT          7
 492         u8 flags8;
 493 #define E4_XSTORM_CORE_CONN_AG_CTX_CF2EN_MASK   0x1
 494 #define E4_XSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT  0
 495 #define E4_XSTORM_CORE_CONN_AG_CTX_CF3EN_MASK   0x1
 496 #define E4_XSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT  1
 497 #define E4_XSTORM_CORE_CONN_AG_CTX_CF4EN_MASK   0x1
 498 #define E4_XSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT  2
 499 #define E4_XSTORM_CORE_CONN_AG_CTX_CF5EN_MASK   0x1
 500 #define E4_XSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT  3
 501 #define E4_XSTORM_CORE_CONN_AG_CTX_CF6EN_MASK   0x1
 502 #define E4_XSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT  4
 503 #define E4_XSTORM_CORE_CONN_AG_CTX_CF7EN_MASK   0x1
 504 #define E4_XSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT  5
 505 #define E4_XSTORM_CORE_CONN_AG_CTX_CF8EN_MASK   0x1
 506 #define E4_XSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT  6
 507 #define E4_XSTORM_CORE_CONN_AG_CTX_CF9EN_MASK   0x1
 508 #define E4_XSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT  7
 509         u8 flags9;
 510 #define E4_XSTORM_CORE_CONN_AG_CTX_CF10EN_MASK                  0x1
 511 #define E4_XSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT                 0
 512 #define E4_XSTORM_CORE_CONN_AG_CTX_CF11EN_MASK                  0x1
 513 #define E4_XSTORM_CORE_CONN_AG_CTX_CF11EN_SHIFT                 1
 514 #define E4_XSTORM_CORE_CONN_AG_CTX_CF12EN_MASK                  0x1
 515 #define E4_XSTORM_CORE_CONN_AG_CTX_CF12EN_SHIFT                 2
 516 #define E4_XSTORM_CORE_CONN_AG_CTX_CF13EN_MASK                  0x1
 517 #define E4_XSTORM_CORE_CONN_AG_CTX_CF13EN_SHIFT                 3
 518 #define E4_XSTORM_CORE_CONN_AG_CTX_CF14EN_MASK                  0x1
 519 #define E4_XSTORM_CORE_CONN_AG_CTX_CF14EN_SHIFT                 4
 520 #define E4_XSTORM_CORE_CONN_AG_CTX_CF15EN_MASK                  0x1
 521 #define E4_XSTORM_CORE_CONN_AG_CTX_CF15EN_SHIFT                 5
 522 #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_MASK     0x1
 523 #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_SHIFT    6
 524 #define E4_XSTORM_CORE_CONN_AG_CTX_CF17EN_MASK                  0x1
 525 #define E4_XSTORM_CORE_CONN_AG_CTX_CF17EN_SHIFT                 7
 526         u8 flags10;
 527 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_MASK                0x1
 528 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_SHIFT               0
 529 #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_MASK         0x1
 530 #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT        1
 531 #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_MASK             0x1
 532 #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT            2
 533 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED11_MASK              0x1
 534 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED11_SHIFT             3
 535 #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_MASK            0x1
 536 #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT           4
 537 #define E4_XSTORM_CORE_CONN_AG_CTX_CF23EN_MASK                  0x1
 538 #define E4_XSTORM_CORE_CONN_AG_CTX_CF23EN_SHIFT                 5
 539 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED12_MASK              0x1
 540 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED12_SHIFT             6
 541 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED13_MASK              0x1
 542 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED13_SHIFT             7
 543         u8 flags11;
 544 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED14_MASK      0x1
 545 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED14_SHIFT     0
 546 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED15_MASK      0x1
 547 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED15_SHIFT     1
 548 #define E4_XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_MASK  0x1
 549 #define E4_XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
 550 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK         0x1
 551 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT        3
 552 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK         0x1
 553 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT        4
 554 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK         0x1
 555 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT        5
 556 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_MASK    0x1
 557 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_SHIFT   6
 558 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE9EN_MASK         0x1
 559 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE9EN_SHIFT        7
 560         u8 flags12;
 561 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE10EN_MASK        0x1
 562 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE10EN_SHIFT       0
 563 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE11EN_MASK        0x1
 564 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE11EN_SHIFT       1
 565 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_MASK    0x1
 566 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_SHIFT   2
 567 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_MASK    0x1
 568 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_SHIFT   3
 569 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE14EN_MASK        0x1
 570 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE14EN_SHIFT       4
 571 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE15EN_MASK        0x1
 572 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE15EN_SHIFT       5
 573 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE16EN_MASK        0x1
 574 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE16EN_SHIFT       6
 575 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE17EN_MASK        0x1
 576 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE17EN_SHIFT       7
 577         u8 flags13;
 578 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE18EN_MASK        0x1
 579 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE18EN_SHIFT       0
 580 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE19EN_MASK        0x1
 581 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE19EN_SHIFT       1
 582 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_MASK    0x1
 583 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_SHIFT   2
 584 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_MASK    0x1
 585 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_SHIFT   3
 586 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_MASK    0x1
 587 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_SHIFT   4
 588 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_MASK    0x1
 589 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_SHIFT   5
 590 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_MASK    0x1
 591 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_SHIFT   6
 592 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_MASK    0x1
 593 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_SHIFT   7
 594         u8 flags14;
 595 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT16_MASK   0x1
 596 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT16_SHIFT  0
 597 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT17_MASK   0x1
 598 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT17_SHIFT  1
 599 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT18_MASK   0x1
 600 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT18_SHIFT  2
 601 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT19_MASK   0x1
 602 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT19_SHIFT  3
 603 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT20_MASK   0x1
 604 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT20_SHIFT  4
 605 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT21_MASK   0x1
 606 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT21_SHIFT  5
 607 #define E4_XSTORM_CORE_CONN_AG_CTX_CF23_MASK    0x3
 608 #define E4_XSTORM_CORE_CONN_AG_CTX_CF23_SHIFT   6
 609         u8 byte2;
 610         __le16 physical_q0;
 611         __le16 consolid_prod;
 612         __le16 reserved16;
 613         __le16 tx_bd_cons;
 614         __le16 tx_bd_or_spq_prod;
 615         __le16 word5;
 616         __le16 conn_dpi;
 617         u8 byte3;
 618         u8 byte4;
 619         u8 byte5;
 620         u8 byte6;
 621         __le32 reg0;
 622         __le32 reg1;
 623         __le32 reg2;
 624         __le32 reg3;
 625         __le32 reg4;
 626         __le32 reg5;
 627         __le32 reg6;
 628         __le16 word7;
 629         __le16 word8;
 630         __le16 word9;
 631         __le16 word10;
 632         __le32 reg7;
 633         __le32 reg8;
 634         __le32 reg9;
 635         u8 byte7;
 636         u8 byte8;
 637         u8 byte9;
 638         u8 byte10;
 639         u8 byte11;
 640         u8 byte12;
 641         u8 byte13;
 642         u8 byte14;
 643         u8 byte15;
 644         u8 e5_reserved;
 645         __le16 word11;
 646         __le32 reg10;
 647         __le32 reg11;
 648         __le32 reg12;
 649         __le32 reg13;
 650         __le32 reg14;
 651         __le32 reg15;
 652         __le32 reg16;
 653         __le32 reg17;
 654         __le32 reg18;
 655         __le32 reg19;
 656         __le16 word12;
 657         __le16 word13;
 658         __le16 word14;
 659         __le16 word15;
 660 };
 661
 662 struct e4_tstorm_core_conn_ag_ctx {
 663         u8 byte0;
 664         u8 byte1;
 665         u8 flags0;
 666 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT0_MASK    0x1
 667 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT   0
 668 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT1_MASK    0x1
 669 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT   1
 670 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT2_MASK    0x1
 671 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT2_SHIFT   2
 672 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT3_MASK    0x1
 673 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT3_SHIFT   3
 674 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT4_MASK    0x1
 675 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT4_SHIFT   4
 676 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT5_MASK    0x1
 677 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT5_SHIFT   5
 678 #define E4_TSTORM_CORE_CONN_AG_CTX_CF0_MASK     0x3
 679 #define E4_TSTORM_CORE_CONN_AG_CTX_CF0_SHIFT    6
 680         u8 flags1;
 681 #define E4_TSTORM_CORE_CONN_AG_CTX_CF1_MASK     0x3
 682 #define E4_TSTORM_CORE_CONN_AG_CTX_CF1_SHIFT    0
 683 #define E4_TSTORM_CORE_CONN_AG_CTX_CF2_MASK     0x3
 684 #define E4_TSTORM_CORE_CONN_AG_CTX_CF2_SHIFT    2
 685 #define E4_TSTORM_CORE_CONN_AG_CTX_CF3_MASK     0x3
 686 #define E4_TSTORM_CORE_CONN_AG_CTX_CF3_SHIFT    4
 687 #define E4_TSTORM_CORE_CONN_AG_CTX_CF4_MASK     0x3
 688 #define E4_TSTORM_CORE_CONN_AG_CTX_CF4_SHIFT    6
 689         u8 flags2;
 690 #define E4_TSTORM_CORE_CONN_AG_CTX_CF5_MASK     0x3
 691 #define E4_TSTORM_CORE_CONN_AG_CTX_CF5_SHIFT    0
 692 #define E4_TSTORM_CORE_CONN_AG_CTX_CF6_MASK     0x3
 693 #define E4_TSTORM_CORE_CONN_AG_CTX_CF6_SHIFT    2
 694 #define E4_TSTORM_CORE_CONN_AG_CTX_CF7_MASK     0x3
 695 #define E4_TSTORM_CORE_CONN_AG_CTX_CF7_SHIFT    4
 696 #define E4_TSTORM_CORE_CONN_AG_CTX_CF8_MASK     0x3
 697 #define E4_TSTORM_CORE_CONN_AG_CTX_CF8_SHIFT    6
 698         u8 flags3;
 699 #define E4_TSTORM_CORE_CONN_AG_CTX_CF9_MASK     0x3
 700 #define E4_TSTORM_CORE_CONN_AG_CTX_CF9_SHIFT    0
 701 #define E4_TSTORM_CORE_CONN_AG_CTX_CF10_MASK    0x3
 702 #define E4_TSTORM_CORE_CONN_AG_CTX_CF10_SHIFT   2
 703 #define E4_TSTORM_CORE_CONN_AG_CTX_CF0EN_MASK   0x1
 704 #define E4_TSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT  4
 705 #define E4_TSTORM_CORE_CONN_AG_CTX_CF1EN_MASK   0x1
 706 #define E4_TSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT  5
 707 #define E4_TSTORM_CORE_CONN_AG_CTX_CF2EN_MASK   0x1
 708 #define E4_TSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT  6
 709 #define E4_TSTORM_CORE_CONN_AG_CTX_CF3EN_MASK   0x1
 710 #define E4_TSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT  7
 711         u8 flags4;
 712 #define E4_TSTORM_CORE_CONN_AG_CTX_CF4EN_MASK           0x1
 713 #define E4_TSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT          0
 714 #define E4_TSTORM_CORE_CONN_AG_CTX_CF5EN_MASK           0x1
 715 #define E4_TSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT          1
 716 #define E4_TSTORM_CORE_CONN_AG_CTX_CF6EN_MASK           0x1
 717 #define E4_TSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT          2
 718 #define E4_TSTORM_CORE_CONN_AG_CTX_CF7EN_MASK           0x1
 719 #define E4_TSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT          3
 720 #define E4_TSTORM_CORE_CONN_AG_CTX_CF8EN_MASK           0x1
 721 #define E4_TSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT          4
 722 #define E4_TSTORM_CORE_CONN_AG_CTX_CF9EN_MASK           0x1
 723 #define E4_TSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT          5
 724 #define E4_TSTORM_CORE_CONN_AG_CTX_CF10EN_MASK          0x1
 725 #define E4_TSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT         6
 726 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK         0x1
 727 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT        7
 728         u8 flags5;
 729 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK         0x1
 730 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT        0
 731 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK         0x1
 732 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT        1
 733 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK         0x1
 734 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT        2
 735 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK         0x1
 736 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT        3
 737 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK         0x1
 738 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT        4
 739 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK         0x1
 740 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT        5
 741 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK         0x1
 742 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT        6
 743 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE8EN_MASK         0x1
 744 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT        7
 745         __le32 reg0;
 746         __le32 reg1;
 747         __le32 reg2;
 748         __le32 reg3;
 749         __le32 reg4;
 750         __le32 reg5;
 751         __le32 reg6;
 752         __le32 reg7;
 753         __le32 reg8;
 754         u8 byte2;
 755         u8 byte3;
 756         __le16 word0;
 757         u8 byte4;
 758         u8 byte5;
 759         __le16 word1;
 760         __le16 word2;
 761         __le16 word3;
 762         __le32 reg9;
 763         __le32 reg10;
 764 };
 765
 766 struct e4_ustorm_core_conn_ag_ctx {
 767         u8 reserved;
 768         u8 byte1;
 769         u8 flags0;
 770 #define E4_USTORM_CORE_CONN_AG_CTX_BIT0_MASK    0x1
 771 #define E4_USTORM_CORE_CONN_AG_CTX_BIT0_SHIFT   0
 772 #define E4_USTORM_CORE_CONN_AG_CTX_BIT1_MASK    0x1
 773 #define E4_USTORM_CORE_CONN_AG_CTX_BIT1_SHIFT   1
 774 #define E4_USTORM_CORE_CONN_AG_CTX_CF0_MASK     0x3
 775 #define E4_USTORM_CORE_CONN_AG_CTX_CF0_SHIFT    2
 776 #define E4_USTORM_CORE_CONN_AG_CTX_CF1_MASK     0x3
 777 #define E4_USTORM_CORE_CONN_AG_CTX_CF1_SHIFT    4
 778 #define E4_USTORM_CORE_CONN_AG_CTX_CF2_MASK     0x3
 779 #define E4_USTORM_CORE_CONN_AG_CTX_CF2_SHIFT    6
 780         u8 flags1;
 781 #define E4_USTORM_CORE_CONN_AG_CTX_CF3_MASK     0x3
 782 #define E4_USTORM_CORE_CONN_AG_CTX_CF3_SHIFT    0
 783 #define E4_USTORM_CORE_CONN_AG_CTX_CF4_MASK     0x3
 784 #define E4_USTORM_CORE_CONN_AG_CTX_CF4_SHIFT    2
 785 #define E4_USTORM_CORE_CONN_AG_CTX_CF5_MASK     0x3
 786 #define E4_USTORM_CORE_CONN_AG_CTX_CF5_SHIFT    4
 787 #define E4_USTORM_CORE_CONN_AG_CTX_CF6_MASK     0x3
 788 #define E4_USTORM_CORE_CONN_AG_CTX_CF6_SHIFT    6
 789         u8 flags2;
 790 #define E4_USTORM_CORE_CONN_AG_CTX_CF0EN_MASK           0x1
 791 #define E4_USTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT          0
 792 #define E4_USTORM_CORE_CONN_AG_CTX_CF1EN_MASK           0x1
 793 #define E4_USTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT          1
 794 #define E4_USTORM_CORE_CONN_AG_CTX_CF2EN_MASK           0x1
 795 #define E4_USTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT          2
 796 #define E4_USTORM_CORE_CONN_AG_CTX_CF3EN_MASK           0x1
 797 #define E4_USTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT          3
 798 #define E4_USTORM_CORE_CONN_AG_CTX_CF4EN_MASK           0x1
 799 #define E4_USTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT          4
 800 #define E4_USTORM_CORE_CONN_AG_CTX_CF5EN_MASK           0x1
 801 #define E4_USTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT          5
 802 #define E4_USTORM_CORE_CONN_AG_CTX_CF6EN_MASK           0x1
 803 #define E4_USTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT          6
 804 #define E4_USTORM_CORE_CONN_AG_CTX_RULE0EN_MASK         0x1
 805 #define E4_USTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT        7
 806         u8 flags3;
 807 #define E4_USTORM_CORE_CONN_AG_CTX_RULE1EN_MASK         0x1
 808 #define E4_USTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT        0
 809 #define E4_USTORM_CORE_CONN_AG_CTX_RULE2EN_MASK         0x1
 810 #define E4_USTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT        1
 811 #define E4_USTORM_CORE_CONN_AG_CTX_RULE3EN_MASK         0x1
 812 #define E4_USTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT        2
 813 #define E4_USTORM_CORE_CONN_AG_CTX_RULE4EN_MASK         0x1
 814 #define E4_USTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT        3
 815 #define E4_USTORM_CORE_CONN_AG_CTX_RULE5EN_MASK         0x1
 816 #define E4_USTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT        4
 817 #define E4_USTORM_CORE_CONN_AG_CTX_RULE6EN_MASK         0x1
 818 #define E4_USTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT        5
 819 #define E4_USTORM_CORE_CONN_AG_CTX_RULE7EN_MASK         0x1
 820 #define E4_USTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT        6
 821 #define E4_USTORM_CORE_CONN_AG_CTX_RULE8EN_MASK         0x1
 822 #define E4_USTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT        7
 823         u8 byte2;
 824         u8 byte3;
 825         __le16 word0;
 826         __le16 word1;
 827         __le32 rx_producers;
 828         __le32 reg1;
 829         __le32 reg2;
 830         __le32 reg3;
 831         __le16 word2;
 832         __le16 word3;
 833 };
 834
 835 /* The core storm context for the Mstorm */
 836 struct mstorm_core_conn_st_ctx {
 837         __le32 reserved[24];
 838 };
 839
 840 /* The core storm context for the Ustorm */
 841 struct ustorm_core_conn_st_ctx {
 842         __le32 reserved[4];
 843 };
 844
 845 /* core connection context */
 846 struct e4_core_conn_context {
 847         struct ystorm_core_conn_st_ctx ystorm_st_context;
 848         struct regpair ystorm_st_padding[2];
 849         struct pstorm_core_conn_st_ctx pstorm_st_context;
 850         struct regpair pstorm_st_padding[2];
 851         struct xstorm_core_conn_st_ctx xstorm_st_context;
 852         struct e4_xstorm_core_conn_ag_ctx xstorm_ag_context;
 853         struct e4_tstorm_core_conn_ag_ctx tstorm_ag_context;
 854         struct e4_ustorm_core_conn_ag_ctx ustorm_ag_context;
 855         struct mstorm_core_conn_st_ctx mstorm_st_context;
 856         struct ustorm_core_conn_st_ctx ustorm_st_context;
 857         struct regpair ustorm_st_padding[2];
 858 };
 859
 860 struct eth_mstorm_per_pf_stat {
 861         struct regpair gre_discard_pkts;
 862         struct regpair vxlan_discard_pkts;
 863         struct regpair geneve_discard_pkts;
 864         struct regpair lb_discard_pkts;
 865 };
 866
 867 struct eth_mstorm_per_queue_stat {
 868         struct regpair ttl0_discard;
 869         struct regpair packet_too_big_discard;
 870         struct regpair no_buff_discard;
 871         struct regpair not_active_discard;
 872         struct regpair tpa_coalesced_pkts;
 873         struct regpair tpa_coalesced_events;
 874         struct regpair tpa_aborts_num;
 875         struct regpair tpa_coalesced_bytes;
 876 };
 877
 878 /* Ethernet TX Per PF */
 879 struct eth_pstorm_per_pf_stat {
 880         struct regpair sent_lb_ucast_bytes;
 881         struct regpair sent_lb_mcast_bytes;
 882         struct regpair sent_lb_bcast_bytes;
 883         struct regpair sent_lb_ucast_pkts;
 884         struct regpair sent_lb_mcast_pkts;
 885         struct regpair sent_lb_bcast_pkts;
 886         struct regpair sent_gre_bytes;
 887         struct regpair sent_vxlan_bytes;
 888         struct regpair sent_geneve_bytes;
 889         struct regpair sent_gre_pkts;
 890         struct regpair sent_vxlan_pkts;
 891         struct regpair sent_geneve_pkts;
 892         struct regpair gre_drop_pkts;
 893         struct regpair vxlan_drop_pkts;
 894         struct regpair geneve_drop_pkts;
 895 };
 896
 897 /* Ethernet TX Per Queue Stats */
 898 struct eth_pstorm_per_queue_stat {
 899         struct regpair sent_ucast_bytes;
 900         struct regpair sent_mcast_bytes;
 901         struct regpair sent_bcast_bytes;
 902         struct regpair sent_ucast_pkts;
 903         struct regpair sent_mcast_pkts;
 904         struct regpair sent_bcast_pkts;
 905         struct regpair error_drop_pkts;
 906 };
 907
 908 /* ETH Rx producers data */
 909 struct eth_rx_rate_limit {
 910         __le16 mult;
 911         __le16 cnst;
 912         u8 add_sub_cnst;
 913         u8 reserved0;
 914         __le16 reserved1;
 915 };
 916
 917 struct eth_ustorm_per_pf_stat {
 918         struct regpair rcv_lb_ucast_bytes;
 919         struct regpair rcv_lb_mcast_bytes;
 920         struct regpair rcv_lb_bcast_bytes;
 921         struct regpair rcv_lb_ucast_pkts;
 922         struct regpair rcv_lb_mcast_pkts;
 923         struct regpair rcv_lb_bcast_pkts;
 924         struct regpair rcv_gre_bytes;
 925         struct regpair rcv_vxlan_bytes;
 926         struct regpair rcv_geneve_bytes;
 927         struct regpair rcv_gre_pkts;
 928         struct regpair rcv_vxlan_pkts;
 929         struct regpair rcv_geneve_pkts;
 930 };
 931
 932 struct eth_ustorm_per_queue_stat {
 933         struct regpair rcv_ucast_bytes;
 934         struct regpair rcv_mcast_bytes;
 935         struct regpair rcv_bcast_bytes;
 936         struct regpair rcv_ucast_pkts;
 937         struct regpair rcv_mcast_pkts;
 938         struct regpair rcv_bcast_pkts;
 939 };
 940
 941 /* Event Ring VF-PF Channel data */
 942 struct vf_pf_channel_eqe_data {
 943         struct regpair msg_addr;
 944 };
 945
 946 /* Event Ring malicious VF data */
 947 struct malicious_vf_eqe_data {
 948         u8 vf_id;
 949         u8 err_id;
 950         __le16 reserved[3];
 951 };
 952
 953 /* Event Ring initial cleanup data */
 954 struct initial_cleanup_eqe_data {
 955         u8 vf_id;
 956         u8 reserved[7];
 957 };
 958
 959 /* Event Data Union */
 960 union event_ring_data {
 961         u8 bytes[8];
 962         struct vf_pf_channel_eqe_data vf_pf_channel;
 963         struct iscsi_eqe_data iscsi_info;
 964         struct iscsi_connect_done_results iscsi_conn_done_info;
 965         union rdma_eqe_data rdma_data;
 966         struct malicious_vf_eqe_data malicious_vf;
 967         struct initial_cleanup_eqe_data vf_init_cleanup;
 968 };
 969
 970 /* Event Ring Entry */
 971 struct event_ring_entry {
 972         u8 protocol_id;
 973         u8 opcode;
 974         __le16 reserved0;
 975         __le16 echo;
 976         u8 fw_return_code;
 977         u8 flags;
 978 #define EVENT_RING_ENTRY_ASYNC_MASK             0x1
 979 #define EVENT_RING_ENTRY_ASYNC_SHIFT            0
 980 #define EVENT_RING_ENTRY_RESERVED1_MASK         0x7F
 981 #define EVENT_RING_ENTRY_RESERVED1_SHIFT        1
 982         union event_ring_data data;
 983 };
 984
 985 /* Event Ring Next Page Address */
 986 struct event_ring_next_addr {
 987         struct regpair addr;
 988         __le32 reserved[2];
 989 };
 990
 991 /* Event Ring Element */
 992 union event_ring_element {
 993         struct event_ring_entry entry;
 994         struct event_ring_next_addr next_addr;
 995 };
 996
 997 /* Ports mode */
 998 enum fw_flow_ctrl_mode {
 999         flow_ctrl_pause,
1000         flow_ctrl_pfc,
1001         MAX_FW_FLOW_CTRL_MODE
1002 };
1003
1004 /* GFT profile type */
1005 enum gft_profile_type {
1006         GFT_PROFILE_TYPE_4_TUPLE,
1007         GFT_PROFILE_TYPE_L4_DST_PORT,
1008         GFT_PROFILE_TYPE_IP_DST_PORT,
1009         MAX_GFT_PROFILE_TYPE
1010 };
1011
1012 /* Major and Minor hsi Versions */
1013 struct hsi_fp_ver_struct {
1014         u8 minor_ver_arr[2];
1015         u8 major_ver_arr[2];
1016 };
1017
1018 enum iwarp_ll2_tx_queues {
1019         IWARP_LL2_IN_ORDER_TX_QUEUE = 1,
1020         IWARP_LL2_ALIGNED_TX_QUEUE,
1021         IWARP_LL2_ALIGNED_RIGHT_TRIMMED_TX_QUEUE,
1022         IWARP_LL2_ERROR,
1023         MAX_IWARP_LL2_TX_QUEUES
1024 };
1025
1026 /* Malicious VF error ID */
1027 enum malicious_vf_error_id {
1028         MALICIOUS_VF_NO_ERROR,
1029         VF_PF_CHANNEL_NOT_READY,
1030         VF_ZONE_MSG_NOT_VALID,
1031         VF_ZONE_FUNC_NOT_ENABLED,
1032         ETH_PACKET_TOO_SMALL,
1033         ETH_ILLEGAL_VLAN_MODE,
1034         ETH_MTU_VIOLATION,
1035         ETH_ILLEGAL_INBAND_TAGS,
1036         ETH_VLAN_INSERT_AND_INBAND_VLAN,
1037         ETH_ILLEGAL_NBDS,
1038         ETH_FIRST_BD_WO_SOP,
1039         ETH_INSUFFICIENT_BDS,
1040         ETH_ILLEGAL_LSO_HDR_NBDS,
1041         ETH_ILLEGAL_LSO_MSS,
1042         ETH_ZERO_SIZE_BD,
1043         ETH_ILLEGAL_LSO_HDR_LEN,
1044         ETH_INSUFFICIENT_PAYLOAD,
1045         ETH_EDPM_OUT_OF_SYNC,
1046         ETH_TUNN_IPV6_EXT_NBD_ERR,
1047         ETH_CONTROL_PACKET_VIOLATION,
1048         ETH_ANTI_SPOOFING_ERR,
1049         ETH_PACKET_SIZE_TOO_LARGE,
1050         MAX_MALICIOUS_VF_ERROR_ID
1051 };
1052
1053 /* Mstorm non-triggering VF zone */
1054 struct mstorm_non_trigger_vf_zone {
1055         struct eth_mstorm_per_queue_stat eth_queue_stat;
1056         struct eth_rx_prod_data eth_rx_queue_producers[ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD];
1057 };
1058
1059 /* Mstorm VF zone */
1060 struct mstorm_vf_zone {
1061         struct mstorm_non_trigger_vf_zone non_trigger;
1062 };
1063
1064 /* vlan header including TPID and TCI fields */
1065 struct vlan_header {
1066         __le16 tpid;
1067         __le16 tci;
1068 };
1069
1070 /* outer tag configurations */
1071 struct outer_tag_config_struct {
1072         u8 enable_stag_pri_change;
1073         u8 pri_map_valid;
1074         u8 reserved[2];
1075         struct vlan_header outer_tag;
1076         u8 inner_to_outer_pri_map[8];
1077 };
1078
1079 /* personality per PF */
1080 enum personality_type {
1081         BAD_PERSONALITY_TYP,
1082         PERSONALITY_ISCSI,
1083         PERSONALITY_FCOE,
1084         PERSONALITY_RDMA_AND_ETH,
1085         PERSONALITY_RDMA,
1086         PERSONALITY_CORE,
1087         PERSONALITY_ETH,
1088         PERSONALITY_RESERVED,
1089         MAX_PERSONALITY_TYPE
1090 };
1091
1092 /* tunnel configuration */
1093 struct pf_start_tunnel_config {
1094         u8 set_vxlan_udp_port_flg;
1095         u8 set_geneve_udp_port_flg;
1096         u8 tunnel_clss_vxlan;
1097         u8 tunnel_clss_l2geneve;
1098         u8 tunnel_clss_ipgeneve;
1099         u8 tunnel_clss_l2gre;
1100         u8 tunnel_clss_ipgre;
1101         u8 reserved;
1102         __le16 vxlan_udp_port;
1103         __le16 geneve_udp_port;
1104 };
1105
1106 /* Ramrod data for PF start ramrod */
1107 struct pf_start_ramrod_data {
1108         struct regpair event_ring_pbl_addr;
1109         struct regpair consolid_q_pbl_addr;
1110         struct pf_start_tunnel_config tunnel_config;
1111         __le16 event_ring_sb_id;
1112         u8 base_vf_id;
1113         u8 num_vfs;
1114         u8 event_ring_num_pages;
1115         u8 event_ring_sb_index;
1116         u8 path_id;
1117         u8 warning_as_error;
1118         u8 dont_log_ramrods;
1119         u8 personality;
1120         __le16 log_type_mask;
1121         u8 mf_mode;
1122         u8 integ_phase;
1123         u8 allow_npar_tx_switching;
1124         u8 reserved0;
1125         struct hsi_fp_ver_struct hsi_fp_ver;
1126         struct outer_tag_config_struct outer_tag_config;
1127 };
1128
1129 /* Data for port update ramrod */
1130 struct protocol_dcb_data {
1131         u8 dcb_enable_flag;
1132         u8 dscp_enable_flag;
1133         u8 dcb_priority;
1134         u8 dcb_tc;
1135         u8 dscp_val;
1136         u8 reserved0;
1137 };
1138
1139 /* Update tunnel configuration */
1140 struct pf_update_tunnel_config {
1141         u8 update_rx_pf_clss;
1142         u8 update_rx_def_ucast_clss;
1143         u8 update_rx_def_non_ucast_clss;
1144         u8 set_vxlan_udp_port_flg;
1145         u8 set_geneve_udp_port_flg;
1146         u8 tunnel_clss_vxlan;
1147         u8 tunnel_clss_l2geneve;
1148         u8 tunnel_clss_ipgeneve;
1149         u8 tunnel_clss_l2gre;
1150         u8 tunnel_clss_ipgre;
1151         __le16 vxlan_udp_port;
1152         __le16 geneve_udp_port;
1153         __le16 reserved;
1154 };
1155
1156 /* Data for port update ramrod */
1157 struct pf_update_ramrod_data {
1158         u8 update_eth_dcb_data_mode;
1159         u8 update_fcoe_dcb_data_mode;
1160         u8 update_iscsi_dcb_data_mode;
1161         u8 update_roce_dcb_data_mode;
1162         u8 update_rroce_dcb_data_mode;
1163         u8 update_iwarp_dcb_data_mode;
1164         u8 update_mf_vlan_flag;
1165         u8 update_enable_stag_pri_change;
1166         struct protocol_dcb_data eth_dcb_data;
1167         struct protocol_dcb_data fcoe_dcb_data;
1168         struct protocol_dcb_data iscsi_dcb_data;
1169         struct protocol_dcb_data roce_dcb_data;
1170         struct protocol_dcb_data rroce_dcb_data;
1171         struct protocol_dcb_data iwarp_dcb_data;
1172         __le16 mf_vlan;
1173         u8 enable_stag_pri_change;
1174         u8 reserved;
1175         struct pf_update_tunnel_config tunnel_config;
1176 };
1177
1178 /* Ports mode */
1179 enum ports_mode {
1180         ENGX2_PORTX1,
1181         ENGX2_PORTX2,
1182         ENGX1_PORTX1,
1183         ENGX1_PORTX2,
1184         ENGX1_PORTX4,
1185         MAX_PORTS_MODE
1186 };
1187
1188 /* use to index in hsi_fp_[major|minor]_ver_arr per protocol */
1189 enum protocol_version_array_key {
1190         ETH_VER_KEY = 0,
1191         ROCE_VER_KEY,
1192         MAX_PROTOCOL_VERSION_ARRAY_KEY
1193 };
1194
1195 /* RDMA TX Stats */
1196 struct rdma_sent_stats {
1197         struct regpair sent_bytes;
1198         struct regpair sent_pkts;
1199 };
1200
1201 /* Pstorm non-triggering VF zone */
1202 struct pstorm_non_trigger_vf_zone {
1203         struct eth_pstorm_per_queue_stat eth_queue_stat;
1204         struct rdma_sent_stats rdma_stats;
1205 };
1206
1207 /* Pstorm VF zone */
1208 struct pstorm_vf_zone {
1209         struct pstorm_non_trigger_vf_zone non_trigger;
1210         struct regpair reserved[7];
1211 };
1212
1213 /* Ramrod Header of SPQE */
1214 struct ramrod_header {
1215         __le32 cid;
1216         u8 cmd_id;
1217         u8 protocol_id;
1218         __le16 echo;
1219 };
1220
1221 /* RDMA RX Stats */
1222 struct rdma_rcv_stats {
1223         struct regpair rcv_bytes;
1224         struct regpair rcv_pkts;
1225 };
1226
1227 /* Data for update QCN/DCQCN RL ramrod */
1228 struct rl_update_ramrod_data {
1229         u8 qcn_update_param_flg;
1230         u8 dcqcn_update_param_flg;
1231         u8 rl_init_flg;
1232         u8 rl_start_flg;
1233         u8 rl_stop_flg;
1234         u8 rl_id_first;
1235         u8 rl_id_last;
1236         u8 rl_dc_qcn_flg;
1237         __le32 rl_bc_rate;
1238         __le16 rl_max_rate;
1239         __le16 rl_r_ai;
1240         __le16 rl_r_hai;
1241         __le16 dcqcn_g;
1242         __le32 dcqcn_k_us;
1243         __le32 dcqcn_timeuot_us;
1244         __le32 qcn_timeuot_us;
1245         __le32 reserved[2];
1246 };
1247
1248 /* Slowpath Element (SPQE) */
1249 struct slow_path_element {
1250         struct ramrod_header hdr;
1251         struct regpair data_ptr;
1252 };
1253
1254 /* Tstorm non-triggering VF zone */
1255 struct tstorm_non_trigger_vf_zone {
1256         struct rdma_rcv_stats rdma_stats;
1257 };
1258
1259 struct tstorm_per_port_stat {
1260         struct regpair trunc_error_discard;
1261         struct regpair mac_error_discard;
1262         struct regpair mftag_filter_discard;
1263         struct regpair eth_mac_filter_discard;
1264         struct regpair ll2_mac_filter_discard;
1265         struct regpair ll2_conn_disabled_discard;
1266         struct regpair iscsi_irregular_pkt;
1267         struct regpair fcoe_irregular_pkt;
1268         struct regpair roce_irregular_pkt;
1269         struct regpair iwarp_irregular_pkt;
1270         struct regpair eth_irregular_pkt;
1271         struct regpair toe_irregular_pkt;
1272         struct regpair preroce_irregular_pkt;
1273         struct regpair eth_gre_tunn_filter_discard;
1274         struct regpair eth_vxlan_tunn_filter_discard;
1275         struct regpair eth_geneve_tunn_filter_discard;
1276         struct regpair eth_gft_drop_pkt;
1277 };
1278
1279 /* Tstorm VF zone */
1280 struct tstorm_vf_zone {
1281         struct tstorm_non_trigger_vf_zone non_trigger;
1282 };
1283
1284 /* Tunnel classification scheme */
1285 enum tunnel_clss {
1286         TUNNEL_CLSS_MAC_VLAN = 0,
1287         TUNNEL_CLSS_MAC_VNI,
1288         TUNNEL_CLSS_INNER_MAC_VLAN,
1289         TUNNEL_CLSS_INNER_MAC_VNI,
1290         TUNNEL_CLSS_MAC_VLAN_DUAL_STAGE,
1291         MAX_TUNNEL_CLSS
1292 };
1293
1294 /* Ustorm non-triggering VF zone */
1295 struct ustorm_non_trigger_vf_zone {
1296         struct eth_ustorm_per_queue_stat eth_queue_stat;
1297         struct regpair vf_pf_msg_addr;
1298 };
1299
1300 /* Ustorm triggering VF zone */
1301 struct ustorm_trigger_vf_zone {
1302         u8 vf_pf_msg_valid;
1303         u8 reserved[7];
1304 };
1305
1306 /* Ustorm VF zone */
1307 struct ustorm_vf_zone {
1308         struct ustorm_non_trigger_vf_zone non_trigger;
1309         struct ustorm_trigger_vf_zone trigger;
1310 };
1311
1312 /* VF-PF channel data */
1313 struct vf_pf_channel_data {
1314         __le32 ready;
1315         u8 valid;
1316         u8 reserved0;
1317         __le16 reserved1;
1318 };
1319
1320 /* Ramrod data for VF start ramrod */
1321 struct vf_start_ramrod_data {
1322         u8 vf_id;
1323         u8 enable_flr_ack;
1324         __le16 opaque_fid;
1325         u8 personality;
1326         u8 reserved[7];
1327         struct hsi_fp_ver_struct hsi_fp_ver;
1328
1329 };
1330
1331 /* Ramrod data for VF start ramrod */
1332 struct vf_stop_ramrod_data {
1333         u8 vf_id;
1334         u8 reserved0;
1335         __le16 reserved1;
1336         __le32 reserved2;
1337 };
1338
1339 /* VF zone size mode */
1340 enum vf_zone_size_mode {
1341         VF_ZONE_SIZE_MODE_DEFAULT,
1342         VF_ZONE_SIZE_MODE_DOUBLE,
1343         VF_ZONE_SIZE_MODE_QUAD,
1344         MAX_VF_ZONE_SIZE_MODE
1345 };
1346
1347 /* Attentions status block */
1348 struct atten_status_block {
1349         __le32 atten_bits;
1350         __le32 atten_ack;
1351         __le16 reserved0;
1352         __le16 sb_index;
1353         __le32 reserved1;
1354 };
1355
1356 /* DMAE command */
1357 struct dmae_cmd {
1358         __le32 opcode;
1359 #define DMAE_CMD_SRC_MASK               0x1
1360 #define DMAE_CMD_SRC_SHIFT              0
1361 #define DMAE_CMD_DST_MASK               0x3
1362 #define DMAE_CMD_DST_SHIFT              1
1363 #define DMAE_CMD_C_DST_MASK             0x1
1364 #define DMAE_CMD_C_DST_SHIFT            3
1365 #define DMAE_CMD_CRC_RESET_MASK         0x1
1366 #define DMAE_CMD_CRC_RESET_SHIFT        4
1367 #define DMAE_CMD_SRC_ADDR_RESET_MASK    0x1
1368 #define DMAE_CMD_SRC_ADDR_RESET_SHIFT   5
1369 #define DMAE_CMD_DST_ADDR_RESET_MASK    0x1
1370 #define DMAE_CMD_DST_ADDR_RESET_SHIFT   6
1371 #define DMAE_CMD_COMP_FUNC_MASK         0x1
1372 #define DMAE_CMD_COMP_FUNC_SHIFT        7
1373 #define DMAE_CMD_COMP_WORD_EN_MASK      0x1
1374 #define DMAE_CMD_COMP_WORD_EN_SHIFT     8
1375 #define DMAE_CMD_COMP_CRC_EN_MASK       0x1
1376 #define DMAE_CMD_COMP_CRC_EN_SHIFT      9
1377 #define DMAE_CMD_COMP_CRC_OFFSET_MASK   0x7
1378 #define DMAE_CMD_COMP_CRC_OFFSET_SHIFT 10
1379 #define DMAE_CMD_RESERVED1_MASK         0x1
1380 #define DMAE_CMD_RESERVED1_SHIFT        13
1381 #define DMAE_CMD_ENDIANITY_MODE_MASK    0x3
1382 #define DMAE_CMD_ENDIANITY_MODE_SHIFT   14
1383 #define DMAE_CMD_ERR_HANDLING_MASK      0x3
1384 #define DMAE_CMD_ERR_HANDLING_SHIFT     16
1385 #define DMAE_CMD_PORT_ID_MASK           0x3
1386 #define DMAE_CMD_PORT_ID_SHIFT          18
1387 #define DMAE_CMD_SRC_PF_ID_MASK         0xF
1388 #define DMAE_CMD_SRC_PF_ID_SHIFT        20
1389 #define DMAE_CMD_DST_PF_ID_MASK         0xF
1390 #define DMAE_CMD_DST_PF_ID_SHIFT        24
1391 #define DMAE_CMD_SRC_VF_ID_VALID_MASK   0x1
1392 #define DMAE_CMD_SRC_VF_ID_VALID_SHIFT 28
1393 #define DMAE_CMD_DST_VF_ID_VALID_MASK   0x1
1394 #define DMAE_CMD_DST_VF_ID_VALID_SHIFT 29
1395 #define DMAE_CMD_RESERVED2_MASK         0x3
1396 #define DMAE_CMD_RESERVED2_SHIFT        30
1397         __le32 src_addr_lo;
1398         __le32 src_addr_hi;
1399         __le32 dst_addr_lo;
1400         __le32 dst_addr_hi;
1401         __le16 length_dw;
1402         __le16 opcode_b;
1403 #define DMAE_CMD_SRC_VF_ID_MASK         0xFF
1404 #define DMAE_CMD_SRC_VF_ID_SHIFT        0
1405 #define DMAE_CMD_DST_VF_ID_MASK         0xFF
1406 #define DMAE_CMD_DST_VF_ID_SHIFT        8
1407         __le32 comp_addr_lo;
1408         __le32 comp_addr_hi;
1409         __le32 comp_val;
1410         __le32 crc32;
1411         __le32 crc_32_c;
1412         __le16 crc16;
1413         __le16 crc16_c;
1414         __le16 crc10;
1415         __le16 reserved;
1416         __le16 xsum16;
1417         __le16 xsum8;
1418 };
1419
1420 enum dmae_cmd_comp_crc_en_enum {
1421         dmae_cmd_comp_crc_disabled,
1422         dmae_cmd_comp_crc_enabled,
1423         MAX_DMAE_CMD_COMP_CRC_EN_ENUM
1424 };
1425
1426 enum dmae_cmd_comp_func_enum {
1427         dmae_cmd_comp_func_to_src,
1428         dmae_cmd_comp_func_to_dst,
1429         MAX_DMAE_CMD_COMP_FUNC_ENUM
1430 };
1431
1432 enum dmae_cmd_comp_word_en_enum {
1433         dmae_cmd_comp_word_disabled,
1434         dmae_cmd_comp_word_enabled,
1435         MAX_DMAE_CMD_COMP_WORD_EN_ENUM
1436 };
1437
1438 enum dmae_cmd_c_dst_enum {
1439         dmae_cmd_c_dst_pcie,
1440         dmae_cmd_c_dst_grc,
1441         MAX_DMAE_CMD_C_DST_ENUM
1442 };
1443
1444 enum dmae_cmd_dst_enum {
1445         dmae_cmd_dst_none_0,
1446         dmae_cmd_dst_pcie,
1447         dmae_cmd_dst_grc,
1448         dmae_cmd_dst_none_3,
1449         MAX_DMAE_CMD_DST_ENUM
1450 };
1451
1452 enum dmae_cmd_error_handling_enum {
1453         dmae_cmd_error_handling_send_regular_comp,
1454         dmae_cmd_error_handling_send_comp_with_err,
1455         dmae_cmd_error_handling_dont_send_comp,
1456         MAX_DMAE_CMD_ERROR_HANDLING_ENUM
1457 };
1458
1459 enum dmae_cmd_src_enum {
1460         dmae_cmd_src_pcie,
1461         dmae_cmd_src_grc,
1462         MAX_DMAE_CMD_SRC_ENUM
1463 };
1464
1465 struct e4_mstorm_core_conn_ag_ctx {
1466         u8 byte0;
1467         u8 byte1;
1468         u8 flags0;
1469 #define E4_MSTORM_CORE_CONN_AG_CTX_BIT0_MASK    0x1
1470 #define E4_MSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT   0
1471 #define E4_MSTORM_CORE_CONN_AG_CTX_BIT1_MASK    0x1
1472 #define E4_MSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT   1
1473 #define E4_MSTORM_CORE_CONN_AG_CTX_CF0_MASK     0x3
1474 #define E4_MSTORM_CORE_CONN_AG_CTX_CF0_SHIFT    2
1475 #define E4_MSTORM_CORE_CONN_AG_CTX_CF1_MASK     0x3
1476 #define E4_MSTORM_CORE_CONN_AG_CTX_CF1_SHIFT    4
1477 #define E4_MSTORM_CORE_CONN_AG_CTX_CF2_MASK     0x3
1478 #define E4_MSTORM_CORE_CONN_AG_CTX_CF2_SHIFT    6
1479         u8 flags1;
1480 #define E4_MSTORM_CORE_CONN_AG_CTX_CF0EN_MASK           0x1
1481 #define E4_MSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT          0
1482 #define E4_MSTORM_CORE_CONN_AG_CTX_CF1EN_MASK           0x1
1483 #define E4_MSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT          1
1484 #define E4_MSTORM_CORE_CONN_AG_CTX_CF2EN_MASK           0x1
1485 #define E4_MSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT          2
1486 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK         0x1
1487 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT        3
1488 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK         0x1
1489 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT        4
1490 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK         0x1
1491 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT        5
1492 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK         0x1
1493 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT        6
1494 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK         0x1
1495 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT        7
1496         __le16 word0;
1497         __le16 word1;
1498         __le32 reg0;
1499         __le32 reg1;
1500 };
1501
1502 struct e4_ystorm_core_conn_ag_ctx {
1503         u8 byte0;
1504         u8 byte1;
1505         u8 flags0;
1506 #define E4_YSTORM_CORE_CONN_AG_CTX_BIT0_MASK    0x1
1507 #define E4_YSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT   0
1508 #define E4_YSTORM_CORE_CONN_AG_CTX_BIT1_MASK    0x1
1509 #define E4_YSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT   1
1510 #define E4_YSTORM_CORE_CONN_AG_CTX_CF0_MASK     0x3
1511 #define E4_YSTORM_CORE_CONN_AG_CTX_CF0_SHIFT    2
1512 #define E4_YSTORM_CORE_CONN_AG_CTX_CF1_MASK     0x3
1513 #define E4_YSTORM_CORE_CONN_AG_CTX_CF1_SHIFT    4
1514 #define E4_YSTORM_CORE_CONN_AG_CTX_CF2_MASK     0x3
1515 #define E4_YSTORM_CORE_CONN_AG_CTX_CF2_SHIFT    6
1516         u8 flags1;
1517 #define E4_YSTORM_CORE_CONN_AG_CTX_CF0EN_MASK           0x1
1518 #define E4_YSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT          0
1519 #define E4_YSTORM_CORE_CONN_AG_CTX_CF1EN_MASK           0x1
1520 #define E4_YSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT          1
1521 #define E4_YSTORM_CORE_CONN_AG_CTX_CF2EN_MASK           0x1
1522 #define E4_YSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT          2
1523 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK         0x1
1524 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT        3
1525 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK         0x1
1526 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT        4
1527 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK         0x1
1528 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT        5
1529 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK         0x1
1530 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT        6
1531 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK         0x1
1532 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT        7
1533         u8 byte2;
1534         u8 byte3;
1535         __le16 word0;
1536         __le32 reg0;
1537         __le32 reg1;
1538         __le16 word1;
1539         __le16 word2;
1540         __le16 word3;
1541         __le16 word4;
1542         __le32 reg2;
1543         __le32 reg3;
1544 };
1545
1546 /* IGU cleanup command */
1547 struct igu_cleanup {
1548         __le32 sb_id_and_flags;
1549 #define IGU_CLEANUP_RESERVED0_MASK      0x7FFFFFF
1550 #define IGU_CLEANUP_RESERVED0_SHIFT     0
1551 #define IGU_CLEANUP_CLEANUP_SET_MASK    0x1
1552 #define IGU_CLEANUP_CLEANUP_SET_SHIFT   27
1553 #define IGU_CLEANUP_CLEANUP_TYPE_MASK   0x7
1554 #define IGU_CLEANUP_CLEANUP_TYPE_SHIFT  28
1555 #define IGU_CLEANUP_COMMAND_TYPE_MASK   0x1
1556 #define IGU_CLEANUP_COMMAND_TYPE_SHIFT  31
1557         __le32 reserved1;
1558 };
1559
1560 /* IGU firmware driver command */
1561 union igu_command {
1562         struct igu_prod_cons_update prod_cons_update;
1563         struct igu_cleanup cleanup;
1564 };
1565
1566 /* IGU firmware driver command */
1567 struct igu_command_reg_ctrl {
1568         __le16 opaque_fid;
1569         __le16 igu_command_reg_ctrl_fields;
1570 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_MASK  0xFFF
1571 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_SHIFT 0
1572 #define IGU_COMMAND_REG_CTRL_RESERVED_MASK      0x7
1573 #define IGU_COMMAND_REG_CTRL_RESERVED_SHIFT     12
1574 #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_MASK  0x1
1575 #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_SHIFT 15
1576 };
1577
1578 /* IGU mapping line structure */
1579 struct igu_mapping_line {
1580         __le32 igu_mapping_line_fields;
1581 #define IGU_MAPPING_LINE_VALID_MASK             0x1
1582 #define IGU_MAPPING_LINE_VALID_SHIFT            0
1583 #define IGU_MAPPING_LINE_VECTOR_NUMBER_MASK     0xFF
1584 #define IGU_MAPPING_LINE_VECTOR_NUMBER_SHIFT    1
1585 #define IGU_MAPPING_LINE_FUNCTION_NUMBER_MASK   0xFF
1586 #define IGU_MAPPING_LINE_FUNCTION_NUMBER_SHIFT  9
1587 #define IGU_MAPPING_LINE_PF_VALID_MASK          0x1
1588 #define IGU_MAPPING_LINE_PF_VALID_SHIFT         17
1589 #define IGU_MAPPING_LINE_IPS_GROUP_MASK         0x3F
1590 #define IGU_MAPPING_LINE_IPS_GROUP_SHIFT        18
1591 #define IGU_MAPPING_LINE_RESERVED_MASK          0xFF
1592 #define IGU_MAPPING_LINE_RESERVED_SHIFT         24
1593 };
1594
1595 /* IGU MSIX line structure */
1596 struct igu_msix_vector {
1597         struct regpair address;
1598         __le32 data;
1599         __le32 msix_vector_fields;
1600 #define IGU_MSIX_VECTOR_MASK_BIT_MASK           0x1
1601 #define IGU_MSIX_VECTOR_MASK_BIT_SHIFT          0
1602 #define IGU_MSIX_VECTOR_RESERVED0_MASK          0x7FFF
1603 #define IGU_MSIX_VECTOR_RESERVED0_SHIFT         1
1604 #define IGU_MSIX_VECTOR_STEERING_TAG_MASK       0xFF
1605 #define IGU_MSIX_VECTOR_STEERING_TAG_SHIFT      16
1606 #define IGU_MSIX_VECTOR_RESERVED1_MASK          0xFF
1607 #define IGU_MSIX_VECTOR_RESERVED1_SHIFT         24
1608 };
1609 /* per encapsulation type enabling flags */
1610 struct prs_reg_encapsulation_type_en {
1611         u8 flags;
1612 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_MASK          0x1
1613 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_SHIFT         0
1614 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_MASK           0x1
1615 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_SHIFT          1
1616 #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_MASK                 0x1
1617 #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_SHIFT                2
1618 #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_MASK                 0x1
1619 #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_SHIFT                3
1620 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_MASK       0x1
1621 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_SHIFT      4
1622 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_MASK        0x1
1623 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_SHIFT       5
1624 #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_MASK                     0x3
1625 #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_SHIFT                    6
1626 };
1627
1628 enum pxp_tph_st_hint {
1629         TPH_ST_HINT_BIDIR,
1630         TPH_ST_HINT_REQUESTER,
1631         TPH_ST_HINT_TARGET,
1632         TPH_ST_HINT_TARGET_PRIO,
1633         MAX_PXP_TPH_ST_HINT
1634 };
1635
1636 /* QM hardware structure of enable bypass credit mask */
1637 struct qm_rf_bypass_mask {
1638         u8 flags;
1639 #define QM_RF_BYPASS_MASK_LINEVOQ_MASK          0x1
1640 #define QM_RF_BYPASS_MASK_LINEVOQ_SHIFT         0
1641 #define QM_RF_BYPASS_MASK_RESERVED0_MASK        0x1
1642 #define QM_RF_BYPASS_MASK_RESERVED0_SHIFT       1
1643 #define QM_RF_BYPASS_MASK_PFWFQ_MASK            0x1
1644 #define QM_RF_BYPASS_MASK_PFWFQ_SHIFT           2
1645 #define QM_RF_BYPASS_MASK_VPWFQ_MASK            0x1
1646 #define QM_RF_BYPASS_MASK_VPWFQ_SHIFT           3
1647 #define QM_RF_BYPASS_MASK_PFRL_MASK             0x1
1648 #define QM_RF_BYPASS_MASK_PFRL_SHIFT            4
1649 #define QM_RF_BYPASS_MASK_VPQCNRL_MASK          0x1
1650 #define QM_RF_BYPASS_MASK_VPQCNRL_SHIFT         5
1651 #define QM_RF_BYPASS_MASK_FWPAUSE_MASK          0x1
1652 #define QM_RF_BYPASS_MASK_FWPAUSE_SHIFT         6
1653 #define QM_RF_BYPASS_MASK_RESERVED1_MASK        0x1
1654 #define QM_RF_BYPASS_MASK_RESERVED1_SHIFT       7
1655 };
1656
1657 /* QM hardware structure of opportunistic credit mask */
1658 struct qm_rf_opportunistic_mask {
1659         __le16 flags;
1660 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_MASK           0x1
1661 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_SHIFT          0
1662 #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_MASK           0x1
1663 #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_SHIFT          1
1664 #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_MASK             0x1
1665 #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_SHIFT            2
1666 #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_MASK             0x1
1667 #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_SHIFT            3
1668 #define QM_RF_OPPORTUNISTIC_MASK_PFRL_MASK              0x1
1669 #define QM_RF_OPPORTUNISTIC_MASK_PFRL_SHIFT             4
1670 #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_MASK           0x1
1671 #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_SHIFT          5
1672 #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_MASK           0x1
1673 #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_SHIFT          6
1674 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_MASK         0x1
1675 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_SHIFT        7
1676 #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_MASK        0x1
1677 #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_SHIFT       8
1678 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_MASK         0x7F
1679 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_SHIFT        9
1680 };
1681
1682 /* QM hardware structure of QM map memory */
1683 struct qm_rf_pq_map_e4 {
1684         __le32 reg;
1685 #define QM_RF_PQ_MAP_E4_PQ_VALID_MASK           0x1
1686 #define QM_RF_PQ_MAP_E4_PQ_VALID_SHIFT          0
1687 #define QM_RF_PQ_MAP_E4_RL_ID_MASK              0xFF
1688 #define QM_RF_PQ_MAP_E4_RL_ID_SHIFT             1
1689 #define QM_RF_PQ_MAP_E4_VP_PQ_ID_MASK           0x1FF
1690 #define QM_RF_PQ_MAP_E4_VP_PQ_ID_SHIFT          9
1691 #define QM_RF_PQ_MAP_E4_VOQ_MASK                0x1F
1692 #define QM_RF_PQ_MAP_E4_VOQ_SHIFT               18
1693 #define QM_RF_PQ_MAP_E4_WRR_WEIGHT_GROUP_MASK   0x3
1694 #define QM_RF_PQ_MAP_E4_WRR_WEIGHT_GROUP_SHIFT  23
1695 #define QM_RF_PQ_MAP_E4_RL_VALID_MASK           0x1
1696 #define QM_RF_PQ_MAP_E4_RL_VALID_SHIFT          25
1697 #define QM_RF_PQ_MAP_E4_RESERVED_MASK           0x3F
1698 #define QM_RF_PQ_MAP_E4_RESERVED_SHIFT          26
1699 };
1700
1701 /* Completion params for aggregated interrupt completion */
1702 struct sdm_agg_int_comp_params {
1703         __le16 params;
1704 #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_MASK      0x3F
1705 #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT     0
1706 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_MASK  0x1
1707 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT 6
1708 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_MASK     0x1FF
1709 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT    7
1710 };
1711
1712 /* SDM operation gen command (generate aggregative interrupt) */
1713 struct sdm_op_gen {
1714         __le32 command;
1715 #define SDM_OP_GEN_COMP_PARAM_MASK      0xFFFF
1716 #define SDM_OP_GEN_COMP_PARAM_SHIFT     0
1717 #define SDM_OP_GEN_COMP_TYPE_MASK       0xF
1718 #define SDM_OP_GEN_COMP_TYPE_SHIFT      16
1719 #define SDM_OP_GEN_RESERVED_MASK        0xFFF
1720 #define SDM_OP_GEN_RESERVED_SHIFT       20
1721 };
1722
1723 /****************************************/
1724 /* Debug Tools HSI constants and macros */
1725 /****************************************/
1726
1727 enum block_addr {
1728         GRCBASE_GRC = 0x50000,
1729         GRCBASE_MISCS = 0x9000,
1730         GRCBASE_MISC = 0x8000,
1731         GRCBASE_DBU = 0xa000,
1732         GRCBASE_PGLUE_B = 0x2a8000,
1733         GRCBASE_CNIG = 0x218000,
1734         GRCBASE_CPMU = 0x30000,
1735         GRCBASE_NCSI = 0x40000,
1736         GRCBASE_OPTE = 0x53000,
1737         GRCBASE_BMB = 0x540000,
1738         GRCBASE_PCIE = 0x54000,
1739         GRCBASE_MCP = 0xe00000,
1740         GRCBASE_MCP2 = 0x52000,
1741         GRCBASE_PSWHST = 0x2a0000,
1742         GRCBASE_PSWHST2 = 0x29e000,
1743         GRCBASE_PSWRD = 0x29c000,
1744         GRCBASE_PSWRD2 = 0x29d000,
1745         GRCBASE_PSWWR = 0x29a000,
1746         GRCBASE_PSWWR2 = 0x29b000,
1747         GRCBASE_PSWRQ = 0x280000,
1748         GRCBASE_PSWRQ2 = 0x240000,
1749         GRCBASE_PGLCS = 0x0,
1750         GRCBASE_DMAE = 0xc000,
1751         GRCBASE_PTU = 0x560000,
1752         GRCBASE_TCM = 0x1180000,
1753         GRCBASE_MCM = 0x1200000,
1754         GRCBASE_UCM = 0x1280000,
1755         GRCBASE_XCM = 0x1000000,
1756         GRCBASE_YCM = 0x1080000,
1757         GRCBASE_PCM = 0x1100000,
1758         GRCBASE_QM = 0x2f0000,
1759         GRCBASE_TM = 0x2c0000,
1760         GRCBASE_DORQ = 0x100000,
1761         GRCBASE_BRB = 0x340000,
1762         GRCBASE_SRC = 0x238000,
1763         GRCBASE_PRS = 0x1f0000,
1764         GRCBASE_TSDM = 0xfb0000,
1765         GRCBASE_MSDM = 0xfc0000,
1766         GRCBASE_USDM = 0xfd0000,
1767         GRCBASE_XSDM = 0xf80000,
1768         GRCBASE_YSDM = 0xf90000,
1769         GRCBASE_PSDM = 0xfa0000,
1770         GRCBASE_TSEM = 0x1700000,
1771         GRCBASE_MSEM = 0x1800000,
1772         GRCBASE_USEM = 0x1900000,
1773         GRCBASE_XSEM = 0x1400000,
1774         GRCBASE_YSEM = 0x1500000,
1775         GRCBASE_PSEM = 0x1600000,
1776         GRCBASE_RSS = 0x238800,
1777         GRCBASE_TMLD = 0x4d0000,
1778         GRCBASE_MULD = 0x4e0000,
1779         GRCBASE_YULD = 0x4c8000,
1780         GRCBASE_XYLD = 0x4c0000,
1781         GRCBASE_PTLD = 0x5a0000,
1782         GRCBASE_YPLD = 0x5c0000,
1783         GRCBASE_PRM = 0x230000,
1784         GRCBASE_PBF_PB1 = 0xda0000,
1785         GRCBASE_PBF_PB2 = 0xda4000,
1786         GRCBASE_RPB = 0x23c000,
1787         GRCBASE_BTB = 0xdb0000,
1788         GRCBASE_PBF = 0xd80000,
1789         GRCBASE_RDIF = 0x300000,
1790         GRCBASE_TDIF = 0x310000,
1791         GRCBASE_CDU = 0x580000,
1792         GRCBASE_CCFC = 0x2e0000,
1793         GRCBASE_TCFC = 0x2d0000,
1794         GRCBASE_IGU = 0x180000,
1795         GRCBASE_CAU = 0x1c0000,
1796         GRCBASE_RGFS = 0xf00000,
1797         GRCBASE_RGSRC = 0x320000,
1798         GRCBASE_TGFS = 0xd00000,
1799         GRCBASE_TGSRC = 0x322000,
1800         GRCBASE_UMAC = 0x51000,
1801         GRCBASE_XMAC = 0x210000,
1802         GRCBASE_DBG = 0x10000,
1803         GRCBASE_NIG = 0x500000,
1804         GRCBASE_WOL = 0x600000,
1805         GRCBASE_BMBN = 0x610000,
1806         GRCBASE_IPC = 0x20000,
1807         GRCBASE_NWM = 0x800000,
1808         GRCBASE_NWS = 0x700000,
1809         GRCBASE_MS = 0x6a0000,
1810         GRCBASE_PHY_PCIE = 0x620000,
1811         GRCBASE_LED = 0x6b8000,
1812         GRCBASE_AVS_WRAP = 0x6b0000,
1813         GRCBASE_PXPREQBUS = 0x56000,
1814         GRCBASE_MISC_AEU = 0x8000,
1815         GRCBASE_BAR0_MAP = 0x1c00000,
1816         MAX_BLOCK_ADDR
1817 };
1818
1819 enum block_id {
1820         BLOCK_GRC,
1821         BLOCK_MISCS,
1822         BLOCK_MISC,
1823         BLOCK_DBU,
1824         BLOCK_PGLUE_B,
1825         BLOCK_CNIG,
1826         BLOCK_CPMU,
1827         BLOCK_NCSI,
1828         BLOCK_OPTE,
1829         BLOCK_BMB,
1830         BLOCK_PCIE,
1831         BLOCK_MCP,
1832         BLOCK_MCP2,
1833         BLOCK_PSWHST,
1834         BLOCK_PSWHST2,
1835         BLOCK_PSWRD,
1836         BLOCK_PSWRD2,
1837         BLOCK_PSWWR,
1838         BLOCK_PSWWR2,
1839         BLOCK_PSWRQ,
1840         BLOCK_PSWRQ2,
1841         BLOCK_PGLCS,
1842         BLOCK_DMAE,
1843         BLOCK_PTU,
1844         BLOCK_TCM,
1845         BLOCK_MCM,
1846         BLOCK_UCM,
1847         BLOCK_XCM,
1848         BLOCK_YCM,
1849         BLOCK_PCM,
1850         BLOCK_QM,
1851         BLOCK_TM,
1852         BLOCK_DORQ,
1853         BLOCK_BRB,
1854         BLOCK_SRC,
1855         BLOCK_PRS,
1856         BLOCK_TSDM,
1857         BLOCK_MSDM,
1858         BLOCK_USDM,
1859         BLOCK_XSDM,
1860         BLOCK_YSDM,
1861         BLOCK_PSDM,
1862         BLOCK_TSEM,
1863         BLOCK_MSEM,
1864         BLOCK_USEM,
1865         BLOCK_XSEM,
1866         BLOCK_YSEM,
1867         BLOCK_PSEM,
1868         BLOCK_RSS,
1869         BLOCK_TMLD,
1870         BLOCK_MULD,
1871         BLOCK_YULD,
1872         BLOCK_XYLD,
1873         BLOCK_PTLD,
1874         BLOCK_YPLD,
1875         BLOCK_PRM,
1876         BLOCK_PBF_PB1,
1877         BLOCK_PBF_PB2,
1878         BLOCK_RPB,
1879         BLOCK_BTB,
1880         BLOCK_PBF,
1881         BLOCK_RDIF,
1882         BLOCK_TDIF,
1883         BLOCK_CDU,
1884         BLOCK_CCFC,
1885         BLOCK_TCFC,
1886         BLOCK_IGU,
1887         BLOCK_CAU,
1888         BLOCK_RGFS,
1889         BLOCK_RGSRC,
1890         BLOCK_TGFS,
1891         BLOCK_TGSRC,
1892         BLOCK_UMAC,
1893         BLOCK_XMAC,
1894         BLOCK_DBG,
1895         BLOCK_NIG,
1896         BLOCK_WOL,
1897         BLOCK_BMBN,
1898         BLOCK_IPC,
1899         BLOCK_NWM,
1900         BLOCK_NWS,
1901         BLOCK_MS,
1902         BLOCK_PHY_PCIE,
1903         BLOCK_LED,
1904         BLOCK_AVS_WRAP,
1905         BLOCK_PXPREQBUS,
1906         BLOCK_MISC_AEU,
1907         BLOCK_BAR0_MAP,
1908         MAX_BLOCK_ID
1909 };
1910
1911 /* binary debug buffer types */
1912 enum bin_dbg_buffer_type {
1913         BIN_BUF_DBG_MODE_TREE,
1914         BIN_BUF_DBG_DUMP_REG,
1915         BIN_BUF_DBG_DUMP_MEM,
1916         BIN_BUF_DBG_IDLE_CHK_REGS,
1917         BIN_BUF_DBG_IDLE_CHK_IMMS,
1918         BIN_BUF_DBG_IDLE_CHK_RULES,
1919         BIN_BUF_DBG_IDLE_CHK_PARSING_DATA,
1920         BIN_BUF_DBG_ATTN_BLOCKS,
1921         BIN_BUF_DBG_ATTN_REGS,
1922         BIN_BUF_DBG_ATTN_INDEXES,
1923         BIN_BUF_DBG_ATTN_NAME_OFFSETS,
1924         BIN_BUF_DBG_BUS_BLOCKS,
1925         BIN_BUF_DBG_BUS_LINES,
1926         BIN_BUF_DBG_BUS_BLOCKS_USER_DATA,
1927         BIN_BUF_DBG_BUS_LINE_NAME_OFFSETS,
1928         BIN_BUF_DBG_PARSING_STRINGS,
1929         MAX_BIN_DBG_BUFFER_TYPE
1930 };
1931
1932
1933 /* Attention bit mapping */
1934 struct dbg_attn_bit_mapping {
1935         __le16 data;
1936 #define DBG_ATTN_BIT_MAPPING_VAL_MASK                   0x7FFF
1937 #define DBG_ATTN_BIT_MAPPING_VAL_SHIFT                  0
1938 #define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_MASK     0x1
1939 #define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_SHIFT    15
1940 };
1941
1942 /* Attention block per-type data */
1943 struct dbg_attn_block_type_data {
1944         __le16 names_offset;
1945         __le16 reserved1;
1946         u8 num_regs;
1947         u8 reserved2;
1948         __le16 regs_offset;
1949 };
1950
1951 /* Block attentions */
1952 struct dbg_attn_block {
1953         struct dbg_attn_block_type_data per_type_data[2];
1954 };
1955
1956 /* Attention register result */
1957 struct dbg_attn_reg_result {
1958         __le32 data;
1959 #define DBG_ATTN_REG_RESULT_STS_ADDRESS_MASK    0xFFFFFF
1960 #define DBG_ATTN_REG_RESULT_STS_ADDRESS_SHIFT   0
1961 #define DBG_ATTN_REG_RESULT_NUM_REG_ATTN_MASK   0xFF
1962 #define DBG_ATTN_REG_RESULT_NUM_REG_ATTN_SHIFT  24
1963         __le16 block_attn_offset;
1964         __le16 reserved;
1965         __le32 sts_val;
1966         __le32 mask_val;
1967 };
1968
1969 /* Attention block result */
1970 struct dbg_attn_block_result {
1971         u8 block_id;
1972         u8 data;
1973 #define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_MASK    0x3
1974 #define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_SHIFT   0
1975 #define DBG_ATTN_BLOCK_RESULT_NUM_REGS_MASK     0x3F
1976 #define DBG_ATTN_BLOCK_RESULT_NUM_REGS_SHIFT    2
1977         __le16 names_offset;
1978         struct dbg_attn_reg_result reg_results[15];
1979 };
1980
1981 /* Mode header */
1982 struct dbg_mode_hdr {
1983         __le16 data;
1984 #define DBG_MODE_HDR_EVAL_MODE_MASK             0x1
1985 #define DBG_MODE_HDR_EVAL_MODE_SHIFT            0
1986 #define DBG_MODE_HDR_MODES_BUF_OFFSET_MASK      0x7FFF
1987 #define DBG_MODE_HDR_MODES_BUF_OFFSET_SHIFT     1
1988 };
1989
1990 /* Attention register */
1991 struct dbg_attn_reg {
1992         struct dbg_mode_hdr mode;
1993         __le16 block_attn_offset;
1994         __le32 data;
1995 #define DBG_ATTN_REG_STS_ADDRESS_MASK   0xFFFFFF
1996 #define DBG_ATTN_REG_STS_ADDRESS_SHIFT  0
1997 #define DBG_ATTN_REG_NUM_REG_ATTN_MASK  0xFF
1998 #define DBG_ATTN_REG_NUM_REG_ATTN_SHIFT 24
1999         __le32 sts_clr_address;
2000         __le32 mask_address;
2001 };
2002
2003 /* Attention types */
2004 enum dbg_attn_type {
2005         ATTN_TYPE_INTERRUPT,
2006         ATTN_TYPE_PARITY,
2007         MAX_DBG_ATTN_TYPE
2008 };
2009
2010 /* Debug Bus block data */
2011 struct dbg_bus_block {
2012         u8 num_of_lines;
2013         u8 has_latency_events;
2014         __le16 lines_offset;
2015 };
2016
2017 /* Debug Bus block user data */
2018 struct dbg_bus_block_user_data {
2019         u8 num_of_lines;
2020         u8 has_latency_events;
2021         __le16 names_offset;
2022 };
2023
2024 /* Block Debug line data */
2025 struct dbg_bus_line {
2026         u8 data;
2027 #define DBG_BUS_LINE_NUM_OF_GROUPS_MASK         0xF
2028 #define DBG_BUS_LINE_NUM_OF_GROUPS_SHIFT        0
2029 #define DBG_BUS_LINE_IS_256B_MASK               0x1
2030 #define DBG_BUS_LINE_IS_256B_SHIFT              4
2031 #define DBG_BUS_LINE_RESERVED_MASK              0x7
2032 #define DBG_BUS_LINE_RESERVED_SHIFT             5
2033         u8 group_sizes;
2034 };
2035
2036 /* Condition header for registers dump */
2037 struct dbg_dump_cond_hdr {
2038         struct dbg_mode_hdr mode; /* Mode header */
2039         u8 block_id; /* block ID */
2040         u8 data_size; /* size in dwords of the data following this header */
2041 };
2042
2043 /* Memory data for registers dump */
2044 struct dbg_dump_mem {
2045         __le32 dword0;
2046 #define DBG_DUMP_MEM_ADDRESS_MASK       0xFFFFFF
2047 #define DBG_DUMP_MEM_ADDRESS_SHIFT      0
2048 #define DBG_DUMP_MEM_MEM_GROUP_ID_MASK  0xFF
2049 #define DBG_DUMP_MEM_MEM_GROUP_ID_SHIFT 24
2050         __le32 dword1;
2051 #define DBG_DUMP_MEM_LENGTH_MASK        0xFFFFFF
2052 #define DBG_DUMP_MEM_LENGTH_SHIFT       0
2053 #define DBG_DUMP_MEM_WIDE_BUS_MASK      0x1
2054 #define DBG_DUMP_MEM_WIDE_BUS_SHIFT     24
2055 #define DBG_DUMP_MEM_RESERVED_MASK      0x7F
2056 #define DBG_DUMP_MEM_RESERVED_SHIFT     25
2057 };
2058
2059 /* Register data for registers dump */
2060 struct dbg_dump_reg {
2061         __le32 data;
2062 #define DBG_DUMP_REG_ADDRESS_MASK       0x7FFFFF
2063 #define DBG_DUMP_REG_ADDRESS_SHIFT      0
2064 #define DBG_DUMP_REG_WIDE_BUS_MASK      0x1
2065 #define DBG_DUMP_REG_WIDE_BUS_SHIFT     23
2066 #define DBG_DUMP_REG_LENGTH_MASK        0xFF
2067 #define DBG_DUMP_REG_LENGTH_SHIFT       24
2068 };
2069
2070 /* Split header for registers dump */
2071 struct dbg_dump_split_hdr {
2072         __le32 hdr;
2073 #define DBG_DUMP_SPLIT_HDR_DATA_SIZE_MASK       0xFFFFFF
2074 #define DBG_DUMP_SPLIT_HDR_DATA_SIZE_SHIFT      0
2075 #define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_MASK   0xFF
2076 #define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_SHIFT  24
2077 };
2078
2079 /* Condition header for idle check */
2080 struct dbg_idle_chk_cond_hdr {
2081         struct dbg_mode_hdr mode; /* Mode header */
2082         __le16 data_size; /* size in dwords of the data following this header */
2083 };
2084
2085 /* Idle Check condition register */
2086 struct dbg_idle_chk_cond_reg {
2087         __le32 data;
2088 #define DBG_IDLE_CHK_COND_REG_ADDRESS_MASK      0x7FFFFF
2089 #define DBG_IDLE_CHK_COND_REG_ADDRESS_SHIFT     0
2090 #define DBG_IDLE_CHK_COND_REG_WIDE_BUS_MASK     0x1
2091 #define DBG_IDLE_CHK_COND_REG_WIDE_BUS_SHIFT    23
2092 #define DBG_IDLE_CHK_COND_REG_BLOCK_ID_MASK     0xFF
2093 #define DBG_IDLE_CHK_COND_REG_BLOCK_ID_SHIFT    24
2094         __le16 num_entries;
2095         u8 entry_size;
2096         u8 start_entry;
2097 };
2098
2099 /* Idle Check info register */
2100 struct dbg_idle_chk_info_reg {
2101         __le32 data;
2102 #define DBG_IDLE_CHK_INFO_REG_ADDRESS_MASK      0x7FFFFF
2103 #define DBG_IDLE_CHK_INFO_REG_ADDRESS_SHIFT     0
2104 #define DBG_IDLE_CHK_INFO_REG_WIDE_BUS_MASK     0x1
2105 #define DBG_IDLE_CHK_INFO_REG_WIDE_BUS_SHIFT    23
2106 #define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_MASK     0xFF
2107 #define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_SHIFT    24
2108         __le16 size; /* register size in dwords */
2109         struct dbg_mode_hdr mode; /* Mode header */
2110 };
2111
2112 /* Idle Check register */
2113 union dbg_idle_chk_reg {
2114         struct dbg_idle_chk_cond_reg cond_reg; /* condition register */
2115         struct dbg_idle_chk_info_reg info_reg; /* info register */
2116 };
2117
2118 /* Idle Check result header */
2119 struct dbg_idle_chk_result_hdr {
2120         __le16 rule_id; /* Failing rule index */
2121         __le16 mem_entry_id; /* Failing memory entry index */
2122         u8 num_dumped_cond_regs; /* number of dumped condition registers */
2123         u8 num_dumped_info_regs; /* number of dumped condition registers */
2124         u8 severity; /* from dbg_idle_chk_severity_types enum */
2125         u8 reserved;
2126 };
2127
2128 /* Idle Check result register header */
2129 struct dbg_idle_chk_result_reg_hdr {
2130         u8 data;
2131 #define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_MASK  0x1
2132 #define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_SHIFT 0
2133 #define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_MASK  0x7F
2134 #define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_SHIFT 1
2135         u8 start_entry; /* index of the first checked entry */
2136         __le16 size; /* register size in dwords */
2137 };
2138
2139 /* Idle Check rule */
2140 struct dbg_idle_chk_rule {
2141         __le16 rule_id; /* Idle Check rule ID */
2142         u8 severity; /* value from dbg_idle_chk_severity_types enum */
2143         u8 cond_id; /* Condition ID */
2144         u8 num_cond_regs; /* number of condition registers */
2145         u8 num_info_regs; /* number of info registers */
2146         u8 num_imms; /* number of immediates in the condition */
2147         u8 reserved1;
2148         __le16 reg_offset; /* offset of this rules registers in the idle check
2149                             * register array (in dbg_idle_chk_reg units).
2150                             */
2151         __le16 imm_offset; /* offset of this rules immediate values in the
2152                             * immediate values array (in dwords).
2153                             */
2154 };
2155
2156 /* Idle Check rule parsing data */
2157 struct dbg_idle_chk_rule_parsing_data {
2158         __le32 data;
2159 #define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_MASK  0x1
2160 #define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_SHIFT 0
2161 #define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_MASK  0x7FFFFFFF
2162 #define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_SHIFT 1
2163 };
2164
2165 /* Idle check severity types */
2166 enum dbg_idle_chk_severity_types {
2167         /* idle check failure should cause an error */
2168         IDLE_CHK_SEVERITY_ERROR,
2169         /* idle check failure should cause an error only if theres no traffic */
2170         IDLE_CHK_SEVERITY_ERROR_NO_TRAFFIC,
2171         /* idle check failure should cause a warning */
2172         IDLE_CHK_SEVERITY_WARNING,
2173         MAX_DBG_IDLE_CHK_SEVERITY_TYPES
2174 };
2175
2176 /* Debug Bus block data */
2177 struct dbg_bus_block_data {
2178         __le16 data;
2179 #define DBG_BUS_BLOCK_DATA_ENABLE_MASK_MASK             0xF
2180 #define DBG_BUS_BLOCK_DATA_ENABLE_MASK_SHIFT            0
2181 #define DBG_BUS_BLOCK_DATA_RIGHT_SHIFT_MASK             0xF
2182 #define DBG_BUS_BLOCK_DATA_RIGHT_SHIFT_SHIFT            4
2183 #define DBG_BUS_BLOCK_DATA_FORCE_VALID_MASK_MASK        0xF
2184 #define DBG_BUS_BLOCK_DATA_FORCE_VALID_MASK_SHIFT       8
2185 #define DBG_BUS_BLOCK_DATA_FORCE_FRAME_MASK_MASK        0xF
2186 #define DBG_BUS_BLOCK_DATA_FORCE_FRAME_MASK_SHIFT       12
2187         u8 line_num;
2188         u8 hw_id;
2189 };
2190
2191 /* Debug Bus Clients */
2192 enum dbg_bus_clients {
2193         DBG_BUS_CLIENT_RBCN,
2194         DBG_BUS_CLIENT_RBCP,
2195         DBG_BUS_CLIENT_RBCR,
2196         DBG_BUS_CLIENT_RBCT,
2197         DBG_BUS_CLIENT_RBCU,
2198         DBG_BUS_CLIENT_RBCF,
2199         DBG_BUS_CLIENT_RBCX,
2200         DBG_BUS_CLIENT_RBCS,
2201         DBG_BUS_CLIENT_RBCH,
2202         DBG_BUS_CLIENT_RBCZ,
2203         DBG_BUS_CLIENT_OTHER_ENGINE,
2204         DBG_BUS_CLIENT_TIMESTAMP,
2205         DBG_BUS_CLIENT_CPU,
2206         DBG_BUS_CLIENT_RBCY,
2207         DBG_BUS_CLIENT_RBCQ,
2208         DBG_BUS_CLIENT_RBCM,
2209         DBG_BUS_CLIENT_RBCB,
2210         DBG_BUS_CLIENT_RBCW,
2211         DBG_BUS_CLIENT_RBCV,
2212         MAX_DBG_BUS_CLIENTS
2213 };
2214
2215 /* Debug Bus constraint operation types */
2216 enum dbg_bus_constraint_ops {
2217         DBG_BUS_CONSTRAINT_OP_EQ,
2218         DBG_BUS_CONSTRAINT_OP_NE,
2219         DBG_BUS_CONSTRAINT_OP_LT,
2220         DBG_BUS_CONSTRAINT_OP_LTC,
2221         DBG_BUS_CONSTRAINT_OP_LE,
2222         DBG_BUS_CONSTRAINT_OP_LEC,
2223         DBG_BUS_CONSTRAINT_OP_GT,
2224         DBG_BUS_CONSTRAINT_OP_GTC,
2225         DBG_BUS_CONSTRAINT_OP_GE,
2226         DBG_BUS_CONSTRAINT_OP_GEC,
2227         MAX_DBG_BUS_CONSTRAINT_OPS
2228 };
2229
2230 /* Debug Bus trigger state data */
2231 struct dbg_bus_trigger_state_data {
2232         u8 data;
2233 #define DBG_BUS_TRIGGER_STATE_DATA_BLOCK_SHIFTED_ENABLE_MASK_MASK       0xF
2234 #define DBG_BUS_TRIGGER_STATE_DATA_BLOCK_SHIFTED_ENABLE_MASK_SHIFT      0
2235 #define DBG_BUS_TRIGGER_STATE_DATA_CONSTRAINT_DWORD_MASK_MASK           0xF
2236 #define DBG_BUS_TRIGGER_STATE_DATA_CONSTRAINT_DWORD_MASK_SHIFT          4
2237 };
2238
2239 /* Debug Bus memory address */
2240 struct dbg_bus_mem_addr {
2241         __le32 lo;
2242         __le32 hi;
2243 };
2244
2245 /* Debug Bus PCI buffer data */
2246 struct dbg_bus_pci_buf_data {
2247         struct dbg_bus_mem_addr phys_addr; /* PCI buffer physical address */
2248         struct dbg_bus_mem_addr virt_addr; /* PCI buffer virtual address */
2249         __le32 size; /* PCI buffer size in bytes */
2250 };
2251
2252 /* Debug Bus Storm EID range filter params */
2253 struct dbg_bus_storm_eid_range_params {
2254         u8 min; /* Minimal event ID to filter on */
2255         u8 max; /* Maximal event ID to filter on */
2256 };
2257
2258 /* Debug Bus Storm EID mask filter params */
2259 struct dbg_bus_storm_eid_mask_params {
2260         u8 val; /* Event ID value */
2261         u8 mask; /* Event ID mask. 1s in the mask = dont care bits. */
2262 };
2263
2264 /* Debug Bus Storm EID filter params */
2265 union dbg_bus_storm_eid_params {
2266         struct dbg_bus_storm_eid_range_params range;
2267         struct dbg_bus_storm_eid_mask_params mask;
2268 };
2269
2270 /* Debug Bus Storm data */
2271 struct dbg_bus_storm_data {
2272         u8 enabled;
2273         u8 mode;
2274         u8 hw_id;
2275         u8 eid_filter_en;
2276         u8 eid_range_not_mask;
2277         u8 cid_filter_en;
2278         union dbg_bus_storm_eid_params eid_filter_params;
2279         __le32 cid;
2280 };
2281
2282 /* Debug Bus data */
2283 struct dbg_bus_data {
2284         __le32 app_version;
2285         u8 state;
2286         u8 hw_dwords;
2287         __le16 hw_id_mask;
2288         u8 num_enabled_blocks;
2289         u8 num_enabled_storms;
2290         u8 target;
2291         u8 one_shot_en;
2292         u8 grc_input_en;
2293         u8 timestamp_input_en;
2294         u8 filter_en;
2295         u8 adding_filter;
2296         u8 filter_pre_trigger;
2297         u8 filter_post_trigger;
2298         __le16 reserved;
2299         u8 trigger_en;
2300         struct dbg_bus_trigger_state_data trigger_states[3];
2301         u8 next_trigger_state;
2302         u8 next_constraint_id;
2303         u8 unify_inputs;
2304         u8 rcv_from_other_engine;
2305         struct dbg_bus_pci_buf_data pci_buf;
2306         struct dbg_bus_block_data blocks[88];
2307         struct dbg_bus_storm_data storms[6];
2308 };
2309
2310 /* Debug bus filter types */
2311 enum dbg_bus_filter_types {
2312         DBG_BUS_FILTER_TYPE_OFF,
2313         DBG_BUS_FILTER_TYPE_PRE,
2314         DBG_BUS_FILTER_TYPE_POST,
2315         DBG_BUS_FILTER_TYPE_ON,
2316         MAX_DBG_BUS_FILTER_TYPES
2317 };
2318
2319 /* Debug bus frame modes */
2320 enum dbg_bus_frame_modes {
2321         DBG_BUS_FRAME_MODE_0HW_4ST = 0, /* 0 HW dwords, 4 Storm dwords */
2322         DBG_BUS_FRAME_MODE_4HW_0ST = 3, /* 4 HW dwords, 0 Storm dwords */
2323         DBG_BUS_FRAME_MODE_8HW_0ST = 4, /* 8 HW dwords, 0 Storm dwords */
2324         MAX_DBG_BUS_FRAME_MODES
2325 };
2326
2327 /* Debug bus other engine mode */
2328 enum dbg_bus_other_engine_modes {
2329         DBG_BUS_OTHER_ENGINE_MODE_NONE,
2330         DBG_BUS_OTHER_ENGINE_MODE_DOUBLE_BW_TX,
2331         DBG_BUS_OTHER_ENGINE_MODE_DOUBLE_BW_RX,
2332         DBG_BUS_OTHER_ENGINE_MODE_CROSS_ENGINE_TX,
2333         DBG_BUS_OTHER_ENGINE_MODE_CROSS_ENGINE_RX,
2334         MAX_DBG_BUS_OTHER_ENGINE_MODES
2335 };
2336
2337 /* Debug bus post-trigger recording types */
2338 enum dbg_bus_post_trigger_types {
2339         DBG_BUS_POST_TRIGGER_RECORD,
2340         DBG_BUS_POST_TRIGGER_DROP,
2341         MAX_DBG_BUS_POST_TRIGGER_TYPES
2342 };
2343
2344 /* Debug bus pre-trigger recording types */
2345 enum dbg_bus_pre_trigger_types {
2346         DBG_BUS_PRE_TRIGGER_START_FROM_ZERO,
2347         DBG_BUS_PRE_TRIGGER_NUM_CHUNKS,
2348         DBG_BUS_PRE_TRIGGER_DROP,
2349         MAX_DBG_BUS_PRE_TRIGGER_TYPES
2350 };
2351
2352 /* Debug bus SEMI frame modes */
2353 enum dbg_bus_semi_frame_modes {
2354         DBG_BUS_SEMI_FRAME_MODE_0SLOW_4FAST = 0,
2355         DBG_BUS_SEMI_FRAME_MODE_4SLOW_0FAST = 3,
2356         MAX_DBG_BUS_SEMI_FRAME_MODES
2357 };
2358
2359 /* Debug bus states */
2360 enum dbg_bus_states {
2361         DBG_BUS_STATE_IDLE,
2362         DBG_BUS_STATE_READY,
2363         DBG_BUS_STATE_RECORDING,
2364         DBG_BUS_STATE_STOPPED,
2365         MAX_DBG_BUS_STATES
2366 };
2367
2368 /* Debug Bus Storm modes */
2369 enum dbg_bus_storm_modes {
2370         DBG_BUS_STORM_MODE_PRINTF,
2371         DBG_BUS_STORM_MODE_PRAM_ADDR,
2372         DBG_BUS_STORM_MODE_DRA_RW,
2373         DBG_BUS_STORM_MODE_DRA_W,
2374         DBG_BUS_STORM_MODE_LD_ST_ADDR,
2375         DBG_BUS_STORM_MODE_DRA_FSM,
2376         DBG_BUS_STORM_MODE_RH,
2377         DBG_BUS_STORM_MODE_FOC,
2378         DBG_BUS_STORM_MODE_EXT_STORE,
2379         MAX_DBG_BUS_STORM_MODES
2380 };
2381
2382 /* Debug bus target IDs */
2383 enum dbg_bus_targets {
2384         DBG_BUS_TARGET_ID_INT_BUF,
2385         DBG_BUS_TARGET_ID_NIG,
2386         DBG_BUS_TARGET_ID_PCI,
2387         MAX_DBG_BUS_TARGETS
2388 };
2389
2390 /* GRC Dump data */
2391 struct dbg_grc_data {
2392         u8 params_initialized;
2393         u8 reserved1;
2394         __le16 reserved2;
2395         __le32 param_val[48];
2396 };
2397
2398 /* Debug GRC params */
2399 enum dbg_grc_params {
2400         DBG_GRC_PARAM_DUMP_TSTORM,
2401         DBG_GRC_PARAM_DUMP_MSTORM,
2402         DBG_GRC_PARAM_DUMP_USTORM,
2403         DBG_GRC_PARAM_DUMP_XSTORM,
2404         DBG_GRC_PARAM_DUMP_YSTORM,
2405         DBG_GRC_PARAM_DUMP_PSTORM,
2406         DBG_GRC_PARAM_DUMP_REGS,
2407         DBG_GRC_PARAM_DUMP_RAM,
2408         DBG_GRC_PARAM_DUMP_PBUF,
2409         DBG_GRC_PARAM_DUMP_IOR,
2410         DBG_GRC_PARAM_DUMP_VFC,
2411         DBG_GRC_PARAM_DUMP_CM_CTX,
2412         DBG_GRC_PARAM_DUMP_PXP,
2413         DBG_GRC_PARAM_DUMP_RSS,
2414         DBG_GRC_PARAM_DUMP_CAU,
2415         DBG_GRC_PARAM_DUMP_QM,
2416         DBG_GRC_PARAM_DUMP_MCP,
2417         DBG_GRC_PARAM_RESERVED,
2418         DBG_GRC_PARAM_DUMP_CFC,
2419         DBG_GRC_PARAM_DUMP_IGU,
2420         DBG_GRC_PARAM_DUMP_BRB,
2421         DBG_GRC_PARAM_DUMP_BTB,
2422         DBG_GRC_PARAM_DUMP_BMB,
2423         DBG_GRC_PARAM_DUMP_NIG,
2424         DBG_GRC_PARAM_DUMP_MULD,
2425         DBG_GRC_PARAM_DUMP_PRS,
2426         DBG_GRC_PARAM_DUMP_DMAE,
2427         DBG_GRC_PARAM_DUMP_TM,
2428         DBG_GRC_PARAM_DUMP_SDM,
2429         DBG_GRC_PARAM_DUMP_DIF,
2430         DBG_GRC_PARAM_DUMP_STATIC,
2431         DBG_GRC_PARAM_UNSTALL,
2432         DBG_GRC_PARAM_NUM_LCIDS,
2433         DBG_GRC_PARAM_NUM_LTIDS,
2434         DBG_GRC_PARAM_EXCLUDE_ALL,
2435         DBG_GRC_PARAM_CRASH,
2436         DBG_GRC_PARAM_PARITY_SAFE,
2437         DBG_GRC_PARAM_DUMP_CM,
2438         DBG_GRC_PARAM_DUMP_PHY,
2439         DBG_GRC_PARAM_NO_MCP,
2440         DBG_GRC_PARAM_NO_FW_VER,
2441         MAX_DBG_GRC_PARAMS
2442 };
2443
2444 /* Debug reset registers */
2445 enum dbg_reset_regs {
2446         DBG_RESET_REG_MISCS_PL_UA,
2447         DBG_RESET_REG_MISCS_PL_HV,
2448         DBG_RESET_REG_MISCS_PL_HV_2,
2449         DBG_RESET_REG_MISC_PL_UA,
2450         DBG_RESET_REG_MISC_PL_HV,
2451         DBG_RESET_REG_MISC_PL_PDA_VMAIN_1,
2452         DBG_RESET_REG_MISC_PL_PDA_VMAIN_2,
2453         DBG_RESET_REG_MISC_PL_PDA_VAUX,
2454         MAX_DBG_RESET_REGS
2455 };
2456
2457 /* Debug status codes */
2458 enum dbg_status {
2459         DBG_STATUS_OK,
2460         DBG_STATUS_APP_VERSION_NOT_SET,
2461         DBG_STATUS_UNSUPPORTED_APP_VERSION,
2462         DBG_STATUS_DBG_BLOCK_NOT_RESET,
2463         DBG_STATUS_INVALID_ARGS,
2464         DBG_STATUS_OUTPUT_ALREADY_SET,
2465         DBG_STATUS_INVALID_PCI_BUF_SIZE,
2466         DBG_STATUS_PCI_BUF_ALLOC_FAILED,
2467         DBG_STATUS_PCI_BUF_NOT_ALLOCATED,
2468         DBG_STATUS_TOO_MANY_INPUTS,
2469         DBG_STATUS_INPUT_OVERLAP,
2470         DBG_STATUS_HW_ONLY_RECORDING,
2471         DBG_STATUS_STORM_ALREADY_ENABLED,
2472         DBG_STATUS_STORM_NOT_ENABLED,
2473         DBG_STATUS_BLOCK_ALREADY_ENABLED,
2474         DBG_STATUS_BLOCK_NOT_ENABLED,
2475         DBG_STATUS_NO_INPUT_ENABLED,
2476         DBG_STATUS_NO_FILTER_TRIGGER_64B,
2477         DBG_STATUS_FILTER_ALREADY_ENABLED,
2478         DBG_STATUS_TRIGGER_ALREADY_ENABLED,
2479         DBG_STATUS_TRIGGER_NOT_ENABLED,
2480         DBG_STATUS_CANT_ADD_CONSTRAINT,
2481         DBG_STATUS_TOO_MANY_TRIGGER_STATES,
2482         DBG_STATUS_TOO_MANY_CONSTRAINTS,
2483         DBG_STATUS_RECORDING_NOT_STARTED,
2484         DBG_STATUS_DATA_DIDNT_TRIGGER,
2485         DBG_STATUS_NO_DATA_RECORDED,
2486         DBG_STATUS_DUMP_BUF_TOO_SMALL,
2487         DBG_STATUS_DUMP_NOT_CHUNK_ALIGNED,
2488         DBG_STATUS_UNKNOWN_CHIP,
2489         DBG_STATUS_VIRT_MEM_ALLOC_FAILED,
2490         DBG_STATUS_BLOCK_IN_RESET,
2491         DBG_STATUS_INVALID_TRACE_SIGNATURE,
2492         DBG_STATUS_INVALID_NVRAM_BUNDLE,
2493         DBG_STATUS_NVRAM_GET_IMAGE_FAILED,
2494         DBG_STATUS_NON_ALIGNED_NVRAM_IMAGE,
2495         DBG_STATUS_NVRAM_READ_FAILED,
2496         DBG_STATUS_IDLE_CHK_PARSE_FAILED,
2497         DBG_STATUS_MCP_TRACE_BAD_DATA,
2498         DBG_STATUS_MCP_TRACE_NO_META,
2499         DBG_STATUS_MCP_COULD_NOT_HALT,
2500         DBG_STATUS_MCP_COULD_NOT_RESUME,
2501         DBG_STATUS_RESERVED2,
2502         DBG_STATUS_SEMI_FIFO_NOT_EMPTY,
2503         DBG_STATUS_IGU_FIFO_BAD_DATA,
2504         DBG_STATUS_MCP_COULD_NOT_MASK_PRTY,
2505         DBG_STATUS_FW_ASSERTS_PARSE_FAILED,
2506         DBG_STATUS_REG_FIFO_BAD_DATA,
2507         DBG_STATUS_PROTECTION_OVERRIDE_BAD_DATA,
2508         DBG_STATUS_DBG_ARRAY_NOT_SET,
2509         DBG_STATUS_FILTER_BUG,
2510         DBG_STATUS_NON_MATCHING_LINES,
2511         DBG_STATUS_INVALID_TRIGGER_DWORD_OFFSET,
2512         DBG_STATUS_DBG_BUS_IN_USE,
2513         MAX_DBG_STATUS
2514 };
2515
2516 /* Debug Storms IDs */
2517 enum dbg_storms {
2518         DBG_TSTORM_ID,
2519         DBG_MSTORM_ID,
2520         DBG_USTORM_ID,
2521         DBG_XSTORM_ID,
2522         DBG_YSTORM_ID,
2523         DBG_PSTORM_ID,
2524         MAX_DBG_STORMS
2525 };
2526
2527 /* Idle Check data */
2528 struct idle_chk_data {
2529         __le32 buf_size;
2530         u8 buf_size_set;
2531         u8 reserved1;
2532         __le16 reserved2;
2533 };
2534
2535 /* Debug Tools data (per HW function) */
2536 struct dbg_tools_data {
2537         struct dbg_grc_data grc;
2538         struct dbg_bus_data bus;
2539         struct idle_chk_data idle_chk;
2540         u8 mode_enable[40];
2541         u8 block_in_reset[88];
2542         u8 chip_id;
2543         u8 platform_id;
2544         u8 initialized;
2545         u8 use_dmae;
2546         __le32 num_regs_read;
2547 };
2548
2549 /********************************/
2550 /* HSI Init Functions constants */
2551 /********************************/
2552
2553 /* Number of VLAN priorities */
2554 #define NUM_OF_VLAN_PRIORITIES  8
2555
2556 /* BRB RAM init requirements */
2557 struct init_brb_ram_req {
2558         __le32 guranteed_per_tc;
2559         __le32 headroom_per_tc;
2560         __le32 min_pkt_size;
2561         __le32 max_ports_per_engine;
2562         u8 num_active_tcs[MAX_NUM_PORTS];
2563 };
2564
2565 /* ETS per-TC init requirements */
2566 struct init_ets_tc_req {
2567         u8 use_sp;
2568         u8 use_wfq;
2569         __le16 weight;
2570 };
2571
2572 /* ETS init requirements */
2573 struct init_ets_req {
2574         __le32 mtu;
2575         struct init_ets_tc_req tc_req[NUM_OF_TCS];
2576 };
2577
2578 /* NIG LB RL init requirements */
2579 struct init_nig_lb_rl_req {
2580         __le16 lb_mac_rate;
2581         __le16 lb_rate;
2582         __le32 mtu;
2583         __le16 tc_rate[NUM_OF_PHYS_TCS];
2584 };
2585
2586 /* NIG TC mapping for each priority */
2587 struct init_nig_pri_tc_map_entry {
2588         u8 tc_id;
2589         u8 valid;
2590 };
2591
2592 /* NIG priority to TC map init requirements */
2593 struct init_nig_pri_tc_map_req {
2594         struct init_nig_pri_tc_map_entry pri[NUM_OF_VLAN_PRIORITIES];
2595 };
2596
2597 /* QM per-port init parameters */
2598 struct init_qm_port_params {
2599         u8 active;
2600         u8 active_phys_tcs;
2601         __le16 num_pbf_cmd_lines;
2602         __le16 num_btb_blocks;
2603         __le16 reserved;
2604 };
2605
2606 /* QM per-PQ init parameters */
2607 struct init_qm_pq_params {
2608         u8 vport_id;
2609         u8 tc_id;
2610         u8 wrr_group;
2611         u8 rl_valid;
2612 };
2613
2614 /* QM per-vport init parameters */
2615 struct init_qm_vport_params {
2616         __le32 vport_rl;
2617         __le16 vport_wfq;
2618         __le16 first_tx_pq_id[NUM_OF_TCS];
2619 };
2620
2621 /**************************************/
2622 /* Init Tool HSI constants and macros */
2623 /**************************************/
2624
2625 /* Width of GRC address in bits (addresses are specified in dwords) */
2626 #define GRC_ADDR_BITS   23
2627 #define MAX_GRC_ADDR    (BIT(GRC_ADDR_BITS) - 1)
2628
2629 /* indicates an init that should be applied to any phase ID */
2630 #define ANY_PHASE_ID    0xffff
2631
2632 /* Max size in dwords of a zipped array */
2633 #define MAX_ZIPPED_SIZE 8192
2634 enum chip_ids {
2635         CHIP_BB,
2636         CHIP_K2,
2637         CHIP_RESERVED,
2638         MAX_CHIP_IDS
2639 };
2640
2641 struct fw_asserts_ram_section {
2642         __le16 section_ram_line_offset;
2643         __le16 section_ram_line_size;
2644         u8 list_dword_offset;
2645         u8 list_element_dword_size;
2646         u8 list_num_elements;
2647         u8 list_next_index_dword_offset;
2648 };
2649
2650 struct fw_ver_num {
2651         u8 major;
2652         u8 minor;
2653         u8 rev;
2654         u8 eng;
2655 };
2656
2657 struct fw_ver_info {
2658         __le16 tools_ver;
2659         u8 image_id;
2660         u8 reserved1;
2661         struct fw_ver_num num;
2662         __le32 timestamp;
2663         __le32 reserved2;
2664 };
2665
2666 struct fw_info {
2667         struct fw_ver_info ver;
2668         struct fw_asserts_ram_section fw_asserts_section;
2669 };
2670
2671 struct fw_info_location {
2672         __le32 grc_addr;
2673         __le32 size;
2674 };
2675
2676 enum init_modes {
2677         MODE_RESERVED,
2678         MODE_BB,
2679         MODE_K2,
2680         MODE_ASIC,
2681         MODE_RESERVED2,
2682         MODE_RESERVED3,
2683         MODE_RESERVED4,
2684         MODE_RESERVED5,
2685         MODE_SF,
2686         MODE_MF_SD,
2687         MODE_MF_SI,
2688         MODE_PORTS_PER_ENG_1,
2689         MODE_PORTS_PER_ENG_2,
2690         MODE_PORTS_PER_ENG_4,
2691         MODE_100G,
2692         MODE_RESERVED6,
2693         MAX_INIT_MODES
2694 };
2695
2696 enum init_phases {
2697         PHASE_ENGINE,
2698         PHASE_PORT,
2699         PHASE_PF,
2700         PHASE_VF,
2701         PHASE_QM_PF,
2702         MAX_INIT_PHASES
2703 };
2704
2705 enum init_split_types {
2706         SPLIT_TYPE_NONE,
2707         SPLIT_TYPE_PORT,
2708         SPLIT_TYPE_PF,
2709         SPLIT_TYPE_PORT_PF,
2710         SPLIT_TYPE_VF,
2711         MAX_INIT_SPLIT_TYPES
2712 };
2713
2714 /* Binary buffer header */
2715 struct bin_buffer_hdr {
2716         __le32 offset;
2717         __le32 length;
2718 };
2719
2720 /* Binary init buffer types */
2721 enum bin_init_buffer_type {
2722         BIN_BUF_INIT_FW_VER_INFO,
2723         BIN_BUF_INIT_CMD,
2724         BIN_BUF_INIT_VAL,
2725         BIN_BUF_INIT_MODE_TREE,
2726         BIN_BUF_INIT_IRO,
2727         MAX_BIN_INIT_BUFFER_TYPE
2728 };
2729
2730 /* init array header: raw */
2731 struct init_array_raw_hdr {
2732         __le32 data;
2733 #define INIT_ARRAY_RAW_HDR_TYPE_MASK    0xF
2734 #define INIT_ARRAY_RAW_HDR_TYPE_SHIFT   0
2735 #define INIT_ARRAY_RAW_HDR_PARAMS_MASK  0xFFFFFFF
2736 #define INIT_ARRAY_RAW_HDR_PARAMS_SHIFT 4
2737 };
2738
2739 /* init array header: standard */
2740 struct init_array_standard_hdr {
2741         __le32 data;
2742 #define INIT_ARRAY_STANDARD_HDR_TYPE_MASK       0xF
2743 #define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT      0
2744 #define INIT_ARRAY_STANDARD_HDR_SIZE_MASK       0xFFFFFFF
2745 #define INIT_ARRAY_STANDARD_HDR_SIZE_SHIFT      4
2746 };
2747
2748 /* init array header: zipped */
2749 struct init_array_zipped_hdr {
2750         __le32 data;
2751 #define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK         0xF
2752 #define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT        0
2753 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK  0xFFFFFFF
2754 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_SHIFT 4
2755 };
2756
2757 /* init array header: pattern */
2758 struct init_array_pattern_hdr {
2759         __le32 data;
2760 #define INIT_ARRAY_PATTERN_HDR_TYPE_MASK                0xF
2761 #define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT               0
2762 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK        0xF
2763 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_SHIFT       4
2764 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_MASK         0xFFFFFF
2765 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_SHIFT        8
2766 };
2767
2768 /* init array header union */
2769 union init_array_hdr {
2770         struct init_array_raw_hdr raw;
2771         struct init_array_standard_hdr standard;
2772         struct init_array_zipped_hdr zipped;
2773         struct init_array_pattern_hdr pattern;
2774 };
2775
2776 /* init array types */
2777 enum init_array_types {
2778         INIT_ARR_STANDARD,
2779         INIT_ARR_ZIPPED,
2780         INIT_ARR_PATTERN,
2781         MAX_INIT_ARRAY_TYPES
2782 };
2783
2784 /* init operation: callback */
2785 struct init_callback_op {
2786         __le32 op_data;
2787 #define INIT_CALLBACK_OP_OP_MASK        0xF
2788 #define INIT_CALLBACK_OP_OP_SHIFT       0
2789 #define INIT_CALLBACK_OP_RESERVED_MASK  0xFFFFFFF
2790 #define INIT_CALLBACK_OP_RESERVED_SHIFT 4
2791         __le16 callback_id;
2792         __le16 block_id;
2793 };
2794
2795 /* init operation: delay */
2796 struct init_delay_op {
2797         __le32 op_data;
2798 #define INIT_DELAY_OP_OP_MASK           0xF
2799 #define INIT_DELAY_OP_OP_SHIFT          0
2800 #define INIT_DELAY_OP_RESERVED_MASK     0xFFFFFFF
2801 #define INIT_DELAY_OP_RESERVED_SHIFT    4
2802         __le32 delay;
2803 };
2804
2805 /* init operation: if_mode */
2806 struct init_if_mode_op {
2807         __le32 op_data;
2808 #define INIT_IF_MODE_OP_OP_MASK                 0xF
2809 #define INIT_IF_MODE_OP_OP_SHIFT                0
2810 #define INIT_IF_MODE_OP_RESERVED1_MASK          0xFFF
2811 #define INIT_IF_MODE_OP_RESERVED1_SHIFT         4
2812 #define INIT_IF_MODE_OP_CMD_OFFSET_MASK         0xFFFF
2813 #define INIT_IF_MODE_OP_CMD_OFFSET_SHIFT        16
2814         __le16 reserved2;
2815         __le16 modes_buf_offset;
2816 };
2817
2818 /* init operation: if_phase */
2819 struct init_if_phase_op {
2820         __le32 op_data;
2821 #define INIT_IF_PHASE_OP_OP_MASK                0xF
2822 #define INIT_IF_PHASE_OP_OP_SHIFT               0
2823 #define INIT_IF_PHASE_OP_DMAE_ENABLE_MASK       0x1
2824 #define INIT_IF_PHASE_OP_DMAE_ENABLE_SHIFT      4
2825 #define INIT_IF_PHASE_OP_RESERVED1_MASK         0x7FF
2826 #define INIT_IF_PHASE_OP_RESERVED1_SHIFT        5
2827 #define INIT_IF_PHASE_OP_CMD_OFFSET_MASK        0xFFFF
2828 #define INIT_IF_PHASE_OP_CMD_OFFSET_SHIFT       16
2829         __le32 phase_data;
2830 #define INIT_IF_PHASE_OP_PHASE_MASK             0xFF
2831 #define INIT_IF_PHASE_OP_PHASE_SHIFT            0
2832 #define INIT_IF_PHASE_OP_RESERVED2_MASK         0xFF
2833 #define INIT_IF_PHASE_OP_RESERVED2_SHIFT        8
2834 #define INIT_IF_PHASE_OP_PHASE_ID_MASK          0xFFFF
2835 #define INIT_IF_PHASE_OP_PHASE_ID_SHIFT         16
2836 };
2837
2838 /* init mode operators */
2839 enum init_mode_ops {
2840         INIT_MODE_OP_NOT,
2841         INIT_MODE_OP_OR,
2842         INIT_MODE_OP_AND,
2843         MAX_INIT_MODE_OPS
2844 };
2845
2846 /* init operation: raw */
2847 struct init_raw_op {
2848         __le32 op_data;
2849 #define INIT_RAW_OP_OP_MASK             0xF
2850 #define INIT_RAW_OP_OP_SHIFT            0
2851 #define INIT_RAW_OP_PARAM1_MASK         0xFFFFFFF
2852 #define INIT_RAW_OP_PARAM1_SHIFT        4
2853         __le32 param2;
2854 };
2855
2856 /* init array params */
2857 struct init_op_array_params {
2858         __le16 size;
2859         __le16 offset;
2860 };
2861
2862 /* Write init operation arguments */
2863 union init_write_args {
2864         __le32 inline_val;
2865         __le32 zeros_count;
2866         __le32 array_offset;
2867         struct init_op_array_params runtime;
2868 };
2869
2870 /* init operation: write */
2871 struct init_write_op {
2872         __le32 data;
2873 #define INIT_WRITE_OP_OP_MASK           0xF
2874 #define INIT_WRITE_OP_OP_SHIFT          0
2875 #define INIT_WRITE_OP_SOURCE_MASK       0x7
2876 #define INIT_WRITE_OP_SOURCE_SHIFT      4
2877 #define INIT_WRITE_OP_RESERVED_MASK     0x1
2878 #define INIT_WRITE_OP_RESERVED_SHIFT    7
2879 #define INIT_WRITE_OP_WIDE_BUS_MASK     0x1
2880 #define INIT_WRITE_OP_WIDE_BUS_SHIFT    8
2881 #define INIT_WRITE_OP_ADDRESS_MASK      0x7FFFFF
2882 #define INIT_WRITE_OP_ADDRESS_SHIFT     9
2883         union init_write_args args;
2884 };
2885
2886 /* init operation: read */
2887 struct init_read_op {
2888         __le32 op_data;
2889 #define INIT_READ_OP_OP_MASK            0xF
2890 #define INIT_READ_OP_OP_SHIFT           0
2891 #define INIT_READ_OP_POLL_TYPE_MASK     0xF
2892 #define INIT_READ_OP_POLL_TYPE_SHIFT    4
2893 #define INIT_READ_OP_RESERVED_MASK      0x1
2894 #define INIT_READ_OP_RESERVED_SHIFT     8
2895 #define INIT_READ_OP_ADDRESS_MASK       0x7FFFFF
2896 #define INIT_READ_OP_ADDRESS_SHIFT      9
2897         __le32 expected_val;
2898 };
2899
2900 /* Init operations union */
2901 union init_op {
2902         struct init_raw_op raw;
2903         struct init_write_op write;
2904         struct init_read_op read;
2905         struct init_if_mode_op if_mode;
2906         struct init_if_phase_op if_phase;
2907         struct init_callback_op callback;
2908         struct init_delay_op delay;
2909 };
2910
2911 /* Init command operation types */
2912 enum init_op_types {
2913         INIT_OP_READ,
2914         INIT_OP_WRITE,
2915         INIT_OP_IF_MODE,
2916         INIT_OP_IF_PHASE,
2917         INIT_OP_DELAY,
2918         INIT_OP_CALLBACK,
2919         MAX_INIT_OP_TYPES
2920 };
2921
2922 /* init polling types */
2923 enum init_poll_types {
2924         INIT_POLL_NONE,
2925         INIT_POLL_EQ,
2926         INIT_POLL_OR,
2927         INIT_POLL_AND,
2928         MAX_INIT_POLL_TYPES
2929 };
2930
2931 /* init source types */
2932 enum init_source_types {
2933         INIT_SRC_INLINE,
2934         INIT_SRC_ZEROS,
2935         INIT_SRC_ARRAY,
2936         INIT_SRC_RUNTIME,
2937         MAX_INIT_SOURCE_TYPES
2938 };
2939
2940 /* Internal RAM Offsets macro data */
2941 struct iro {
2942         __le32 base;
2943         __le16 m1;
2944         __le16 m2;
2945         __le16 m3;
2946         __le16 size;
2947 };
2948
2949 /***************************** Public Functions *******************************/
2950
2951 /**
2952  * @brief qed_dbg_set_bin_ptr - Sets a pointer to the binary data with debug
2953  *      arrays.
2954  *
2955  * @param bin_ptr - a pointer to the binary data with debug arrays.
2956  */
2957 enum dbg_status qed_dbg_set_bin_ptr(const u8 * const bin_ptr);
2958
2959 /**
2960  * @brief qed_read_regs - Reads registers into a buffer (using GRC).
2961  *
2962  * @param p_hwfn - HW device data
2963  * @param p_ptt - Ptt window used for writing the registers.
2964  * @param buf - Destination buffer.
2965  * @param addr - Source GRC address in dwords.
2966  * @param len - Number of registers to read.
2967  */
2968 void qed_read_regs(struct qed_hwfn *p_hwfn,
2969                    struct qed_ptt *p_ptt, u32 *buf, u32 addr, u32 len);
2970
2971 /**
2972  * @brief qed_dbg_grc_set_params_default - Reverts all GRC parameters to their
2973  *      default value.
2974  *
2975  * @param p_hwfn                - HW device data
2976  */
2977 void qed_dbg_grc_set_params_default(struct qed_hwfn *p_hwfn);
2978 /**
2979  * @brief qed_dbg_grc_get_dump_buf_size - Returns the required buffer size for
2980  *      GRC Dump.
2981  *
2982  * @param p_hwfn - HW device data
2983  * @param p_ptt - Ptt window used for writing the registers.
2984  * @param buf_size - OUT: required buffer size (in dwords) for the GRC Dump
2985  *      data.
2986  *
2987  * @return error if one of the following holds:
2988  *      - the version wasn't set
2989  * Otherwise, returns ok.
2990  */
2991 enum dbg_status qed_dbg_grc_get_dump_buf_size(struct qed_hwfn *p_hwfn,
2992                                               struct qed_ptt *p_ptt,
2993                                               u32 *buf_size);
2994
2995 /**
2996  * @brief qed_dbg_grc_dump - Dumps GRC data into the specified buffer.
2997  *
2998  * @param p_hwfn - HW device data
2999  * @param p_ptt - Ptt window used for writing the registers.
3000  * @param dump_buf - Pointer to write the collected GRC data into.
3001  * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3002  * @param num_dumped_dwords - OUT: number of dumped dwords.
3003  *
3004  * @return error if one of the following holds:
3005  *      - the version wasn't set
3006  *      - the specified dump buffer is too small
3007  * Otherwise, returns ok.
3008  */
3009 enum dbg_status qed_dbg_grc_dump(struct qed_hwfn *p_hwfn,
3010                                  struct qed_ptt *p_ptt,
3011                                  u32 *dump_buf,
3012                                  u32 buf_size_in_dwords,
3013                                  u32 *num_dumped_dwords);
3014
3015 /**
3016  * @brief qed_dbg_idle_chk_get_dump_buf_size - Returns the required buffer size
3017  *      for idle check results.
3018  *
3019  * @param p_hwfn - HW device data
3020  * @param p_ptt - Ptt window used for writing the registers.
3021  * @param buf_size - OUT: required buffer size (in dwords) for the idle check
3022  *      data.
3023  *
3024  * @return error if one of the following holds:
3025  *      - the version wasn't set
3026  * Otherwise, returns ok.
3027  */
3028 enum dbg_status qed_dbg_idle_chk_get_dump_buf_size(struct qed_hwfn *p_hwfn,
3029                                                    struct qed_ptt *p_ptt,
3030                                                    u32 *buf_size);
3031
3032 /**
3033  * @brief qed_dbg_idle_chk_dump - Performs idle check and writes the results
3034  *      into the specified buffer.
3035  *
3036  * @param p_hwfn - HW device data
3037  * @param p_ptt - Ptt window used for writing the registers.
3038  * @param dump_buf - Pointer to write the idle check data into.
3039  * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3040  * @param num_dumped_dwords - OUT: number of dumped dwords.
3041  *
3042  * @return error if one of the following holds:
3043  *      - the version wasn't set
3044  *      - the specified buffer is too small
3045  * Otherwise, returns ok.
3046  */
3047 enum dbg_status qed_dbg_idle_chk_dump(struct qed_hwfn *p_hwfn,
3048                                       struct qed_ptt *p_ptt,
3049                                       u32 *dump_buf,
3050                                       u32 buf_size_in_dwords,
3051                                       u32 *num_dumped_dwords);
3052
3053 /**
3054  * @brief qed_dbg_mcp_trace_get_dump_buf_size - Returns the required buffer size
3055  *      for mcp trace results.
3056  *
3057  * @param p_hwfn - HW device data
3058  * @param p_ptt - Ptt window used for writing the registers.
3059  * @param buf_size - OUT: required buffer size (in dwords) for mcp trace data.
3060  *
3061  * @return error if one of the following holds:
3062  *      - the version wasn't set
3063  *      - the trace data in MCP scratchpad contain an invalid signature
3064  *      - the bundle ID in NVRAM is invalid
3065  *      - the trace meta data cannot be found (in NVRAM or image file)
3066  * Otherwise, returns ok.
3067  */
3068 enum dbg_status qed_dbg_mcp_trace_get_dump_buf_size(struct qed_hwfn *p_hwfn,
3069                                                     struct qed_ptt *p_ptt,
3070                                                     u32 *buf_size);
3071
3072 /**
3073  * @brief qed_dbg_mcp_trace_dump - Performs mcp trace and writes the results
3074  *      into the specified buffer.
3075  *
3076  * @param p_hwfn - HW device data
3077  * @param p_ptt - Ptt window used for writing the registers.
3078  * @param dump_buf - Pointer to write the mcp trace data into.
3079  * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3080  * @param num_dumped_dwords - OUT: number of dumped dwords.
3081  *
3082  * @return error if one of the following holds:
3083  *      - the version wasn't set
3084  *      - the specified buffer is too small
3085  *      - the trace data in MCP scratchpad contain an invalid signature
3086  *      - the bundle ID in NVRAM is invalid
3087  *      - the trace meta data cannot be found (in NVRAM or image file)
3088  *      - the trace meta data cannot be read (from NVRAM or image file)
3089  * Otherwise, returns ok.
3090  */
3091 enum dbg_status qed_dbg_mcp_trace_dump(struct qed_hwfn *p_hwfn,
3092                                        struct qed_ptt *p_ptt,
3093                                        u32 *dump_buf,
3094                                        u32 buf_size_in_dwords,
3095                                        u32 *num_dumped_dwords);
3096
3097 /**
3098  * @brief qed_dbg_reg_fifo_get_dump_buf_size - Returns the required buffer size
3099  *      for grc trace fifo results.
3100  *
3101  * @param p_hwfn - HW device data
3102  * @param p_ptt - Ptt window used for writing the registers.
3103  * @param buf_size - OUT: required buffer size (in dwords) for reg fifo data.
3104  *
3105  * @return error if one of the following holds:
3106  *      - the version wasn't set
3107  * Otherwise, returns ok.
3108  */
3109 enum dbg_status qed_dbg_reg_fifo_get_dump_buf_size(struct qed_hwfn *p_hwfn,
3110                                                    struct qed_ptt *p_ptt,
3111                                                    u32 *buf_size);
3112
3113 /**
3114  * @brief qed_dbg_reg_fifo_dump - Reads the reg fifo and writes the results into
3115  *      the specified buffer.
3116  *
3117  * @param p_hwfn - HW device data
3118  * @param p_ptt - Ptt window used for writing the registers.
3119  * @param dump_buf - Pointer to write the reg fifo data into.
3120  * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3121  * @param num_dumped_dwords - OUT: number of dumped dwords.
3122  *
3123  * @return error if one of the following holds:
3124  *      - the version wasn't set
3125  *      - the specified buffer is too small
3126  *      - DMAE transaction failed
3127  * Otherwise, returns ok.
3128  */
3129 enum dbg_status qed_dbg_reg_fifo_dump(struct qed_hwfn *p_hwfn,
3130                                       struct qed_ptt *p_ptt,
3131                                       u32 *dump_buf,
3132                                       u32 buf_size_in_dwords,
3133                                       u32 *num_dumped_dwords);
3134
3135 /**
3136  * @brief qed_dbg_igu_fifo_get_dump_buf_size - Returns the required buffer size
3137  *      for the IGU fifo results.
3138  *
3139  * @param p_hwfn - HW device data
3140  * @param p_ptt - Ptt window used for writing the registers.
3141  * @param buf_size - OUT: required buffer size (in dwords) for the IGU fifo
3142  *      data.
3143  *
3144  * @return error if one of the following holds:
3145  *      - the version wasn't set
3146  * Otherwise, returns ok.
3147  */
3148 enum dbg_status qed_dbg_igu_fifo_get_dump_buf_size(struct qed_hwfn *p_hwfn,
3149                                                    struct qed_ptt *p_ptt,
3150                                                    u32 *buf_size);
3151
3152 /**
3153  * @brief qed_dbg_igu_fifo_dump - Reads the IGU fifo and writes the results into
3154  *      the specified buffer.
3155  *
3156  * @param p_hwfn - HW device data
3157  * @param p_ptt - Ptt window used for writing the registers.
3158  * @param dump_buf - Pointer to write the IGU fifo data into.
3159  * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3160  * @param num_dumped_dwords - OUT: number of dumped dwords.
3161  *
3162  * @return error if one of the following holds:
3163  *      - the version wasn't set
3164  *      - the specified buffer is too small
3165  *      - DMAE transaction failed
3166  * Otherwise, returns ok.
3167  */
3168 enum dbg_status qed_dbg_igu_fifo_dump(struct qed_hwfn *p_hwfn,
3169                                       struct qed_ptt *p_ptt,
3170                                       u32 *dump_buf,
3171                                       u32 buf_size_in_dwords,
3172                                       u32 *num_dumped_dwords);
3173
3174 /**
3175  * @brief qed_dbg_protection_override_get_dump_buf_size - Returns the required
3176  *      buffer size for protection override window results.
3177  *
3178  * @param p_hwfn - HW device data
3179  * @param p_ptt - Ptt window used for writing the registers.
3180  * @param buf_size - OUT: required buffer size (in dwords) for protection
3181  *      override data.
3182  *
3183  * @return error if one of the following holds:
3184  *      - the version wasn't set
3185  * Otherwise, returns ok.
3186  */
3187 enum dbg_status
3188 qed_dbg_protection_override_get_dump_buf_size(struct qed_hwfn *p_hwfn,
3189                                               struct qed_ptt *p_ptt,
3190                                               u32 *buf_size);
3191 /**
3192  * @brief qed_dbg_protection_override_dump - Reads protection override window
3193  *      entries and writes the results into the specified buffer.
3194  *
3195  * @param p_hwfn - HW device data
3196  * @param p_ptt - Ptt window used for writing the registers.
3197  * @param dump_buf - Pointer to write the protection override data into.
3198  * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3199  * @param num_dumped_dwords - OUT: number of dumped dwords.
3200  *
3201  * @return error if one of the following holds:
3202  *      - the version wasn't set
3203  *      - the specified buffer is too small
3204  *      - DMAE transaction failed
3205  * Otherwise, returns ok.
3206  */
3207 enum dbg_status qed_dbg_protection_override_dump(struct qed_hwfn *p_hwfn,
3208                                                  struct qed_ptt *p_ptt,
3209                                                  u32 *dump_buf,
3210                                                  u32 buf_size_in_dwords,
3211                                                  u32 *num_dumped_dwords);
3212 /**
3213  * @brief qed_dbg_fw_asserts_get_dump_buf_size - Returns the required buffer
3214  *      size for FW Asserts results.
3215  *
3216  * @param p_hwfn - HW device data
3217  * @param p_ptt - Ptt window used for writing the registers.
3218  * @param buf_size - OUT: required buffer size (in dwords) for FW Asserts data.
3219  *
3220  * @return error if one of the following holds:
3221  *      - the version wasn't set
3222  * Otherwise, returns ok.
3223  */
3224 enum dbg_status qed_dbg_fw_asserts_get_dump_buf_size(struct qed_hwfn *p_hwfn,
3225                                                      struct qed_ptt *p_ptt,
3226                                                      u32 *buf_size);
3227 /**
3228  * @brief qed_dbg_fw_asserts_dump - Reads the FW Asserts and writes the results
3229  *      into the specified buffer.
3230  *
3231  * @param p_hwfn - HW device data
3232  * @param p_ptt - Ptt window used for writing the registers.
3233  * @param dump_buf - Pointer to write the FW Asserts data into.
3234  * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3235  * @param num_dumped_dwords - OUT: number of dumped dwords.
3236  *
3237  * @return error if one of the following holds:
3238  *      - the version wasn't set
3239  *      - the specified buffer is too small
3240  * Otherwise, returns ok.
3241  */
3242 enum dbg_status qed_dbg_fw_asserts_dump(struct qed_hwfn *p_hwfn,
3243                                         struct qed_ptt *p_ptt,
3244                                         u32 *dump_buf,
3245                                         u32 buf_size_in_dwords,
3246                                         u32 *num_dumped_dwords);
3247
3248 /**
3249  * @brief qed_dbg_read_attn - Reads the attention registers of the specified
3250  * block and type, and writes the results into the specified buffer.
3251  *
3252  * @param p_hwfn -       HW device data
3253  * @param p_ptt -        Ptt window used for writing the registers.
3254  * @param block -        Block ID.
3255  * @param attn_type -    Attention type.
3256  * @param clear_status - Indicates if the attention status should be cleared.
3257  * @param results -      OUT: Pointer to write the read results into
3258  *
3259  * @return error if one of the following holds:
3260  *      - the version wasn't set
3261  * Otherwise, returns ok.
3262  */
3263 enum dbg_status qed_dbg_read_attn(struct qed_hwfn *p_hwfn,
3264                                   struct qed_ptt *p_ptt,
3265                                   enum block_id block,
3266                                   enum dbg_attn_type attn_type,
3267                                   bool clear_status,
3268                                   struct dbg_attn_block_result *results);
3269
3270 /**
3271  * @brief qed_dbg_print_attn - Prints attention registers values in the
3272  *      specified results struct.
3273  *
3274  * @param p_hwfn
3275  * @param results - Pointer to the attention read results
3276  *
3277  * @return error if one of the following holds:
3278  *      - the version wasn't set
3279  * Otherwise, returns ok.
3280  */
3281 enum dbg_status qed_dbg_print_attn(struct qed_hwfn *p_hwfn,
3282                                    struct dbg_attn_block_result *results);
3283
3284 /******************************** Constants **********************************/
3285
3286 #define MAX_NAME_LEN    16
3287
3288 /***************************** Public Functions *******************************/
3289
3290 /**
3291  * @brief qed_dbg_user_set_bin_ptr - Sets a pointer to the binary data with
3292  *      debug arrays.
3293  *
3294  * @param bin_ptr - a pointer to the binary data with debug arrays.
3295  */
3296 enum dbg_status qed_dbg_user_set_bin_ptr(const u8 * const bin_ptr);
3297
3298 /**
3299  * @brief qed_dbg_get_status_str - Returns a string for the specified status.
3300  *
3301  * @param status - a debug status code.
3302  *
3303  * @return a string for the specified status
3304  */
3305 const char *qed_dbg_get_status_str(enum dbg_status status);
3306
3307 /**
3308  * @brief qed_get_idle_chk_results_buf_size - Returns the required buffer size
3309  *      for idle check results (in bytes).
3310  *
3311  * @param p_hwfn - HW device data
3312  * @param dump_buf - idle check dump buffer.
3313  * @param num_dumped_dwords - number of dwords that were dumped.
3314  * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3315  *      results.
3316  *
3317  * @return error if the parsing fails, ok otherwise.
3318  */
3319 enum dbg_status qed_get_idle_chk_results_buf_size(struct qed_hwfn *p_hwfn,
3320                                                   u32 *dump_buf,
3321                                                   u32  num_dumped_dwords,
3322                                                   u32 *results_buf_size);
3323 /**
3324  * @brief qed_print_idle_chk_results - Prints idle check results
3325  *
3326  * @param p_hwfn - HW device data
3327  * @param dump_buf - idle check dump buffer.
3328  * @param num_dumped_dwords - number of dwords that were dumped.
3329  * @param results_buf - buffer for printing the idle check results.
3330  * @param num_errors - OUT: number of errors found in idle check.
3331  * @param num_warnings - OUT: number of warnings found in idle check.
3332  *
3333  * @return error if the parsing fails, ok otherwise.
3334  */
3335 enum dbg_status qed_print_idle_chk_results(struct qed_hwfn *p_hwfn,
3336                                            u32 *dump_buf,
3337                                            u32 num_dumped_dwords,
3338                                            char *results_buf,
3339                                            u32 *num_errors,
3340                                            u32 *num_warnings);
3341
3342 /**
3343  * @brief qed_dbg_mcp_trace_set_meta_data - Sets a pointer to the MCP Trace
3344  *      meta data.
3345  *
3346  * Needed in case the MCP Trace dump doesn't contain the meta data (e.g. due to
3347  * no NVRAM access).
3348  *
3349  * @param data - pointer to MCP Trace meta data
3350  * @param size - size of MCP Trace meta data in dwords
3351  */
3352 void qed_dbg_mcp_trace_set_meta_data(u32 *data, u32 size);
3353
3354 /**
3355  * @brief qed_get_mcp_trace_results_buf_size - Returns the required buffer size
3356  *      for MCP Trace results (in bytes).
3357  *
3358  * @param p_hwfn - HW device data
3359  * @param dump_buf - MCP Trace dump buffer.
3360  * @param num_dumped_dwords - number of dwords that were dumped.
3361  * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3362  *      results.
3363  *
3364  * @return error if the parsing fails, ok otherwise.
3365  */
3366 enum dbg_status qed_get_mcp_trace_results_buf_size(struct qed_hwfn *p_hwfn,
3367                                                    u32 *dump_buf,
3368                                                    u32 num_dumped_dwords,
3369                                                    u32 *results_buf_size);
3370
3371 /**
3372  * @brief qed_print_mcp_trace_results - Prints MCP Trace results
3373  *
3374  * @param p_hwfn - HW device data
3375  * @param dump_buf - mcp trace dump buffer, starting from the header.
3376  * @param num_dumped_dwords - number of dwords that were dumped.
3377  * @param results_buf - buffer for printing the mcp trace results.
3378  *
3379  * @return error if the parsing fails, ok otherwise.
3380  */
3381 enum dbg_status qed_print_mcp_trace_results(struct qed_hwfn *p_hwfn,
3382                                             u32 *dump_buf,
3383                                             u32 num_dumped_dwords,
3384                                             char *results_buf);
3385
3386 /**
3387  * @brief qed_get_reg_fifo_results_buf_size - Returns the required buffer size
3388  *      for reg_fifo results (in bytes).
3389  *
3390  * @param p_hwfn - HW device data
3391  * @param dump_buf - reg fifo dump buffer.
3392  * @param num_dumped_dwords - number of dwords that were dumped.
3393  * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3394  *      results.
3395  *
3396  * @return error if the parsing fails, ok otherwise.
3397  */
3398 enum dbg_status qed_get_reg_fifo_results_buf_size(struct qed_hwfn *p_hwfn,
3399                                                   u32 *dump_buf,
3400                                                   u32 num_dumped_dwords,
3401                                                   u32 *results_buf_size);
3402
3403 /**
3404  * @brief qed_print_reg_fifo_results - Prints reg fifo results
3405  *
3406  * @param p_hwfn - HW device data
3407  * @param dump_buf - reg fifo dump buffer, starting from the header.
3408  * @param num_dumped_dwords - number of dwords that were dumped.
3409  * @param results_buf - buffer for printing the reg fifo results.
3410  *
3411  * @return error if the parsing fails, ok otherwise.
3412  */
3413 enum dbg_status qed_print_reg_fifo_results(struct qed_hwfn *p_hwfn,
3414                                            u32 *dump_buf,
3415                                            u32 num_dumped_dwords,
3416                                            char *results_buf);
3417
3418 /**
3419  * @brief qed_get_igu_fifo_results_buf_size - Returns the required buffer size
3420  *      for igu_fifo results (in bytes).
3421  *
3422  * @param p_hwfn - HW device data
3423  * @param dump_buf - IGU fifo dump buffer.
3424  * @param num_dumped_dwords - number of dwords that were dumped.
3425  * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3426  *      results.
3427  *
3428  * @return error if the parsing fails, ok otherwise.
3429  */
3430 enum dbg_status qed_get_igu_fifo_results_buf_size(struct qed_hwfn *p_hwfn,
3431                                                   u32 *dump_buf,
3432                                                   u32 num_dumped_dwords,
3433                                                   u32 *results_buf_size);
3434
3435 /**
3436  * @brief qed_print_igu_fifo_results - Prints IGU fifo results
3437  *
3438  * @param p_hwfn - HW device data
3439  * @param dump_buf - IGU fifo dump buffer, starting from the header.
3440  * @param num_dumped_dwords - number of dwords that were dumped.
3441  * @param results_buf - buffer for printing the IGU fifo results.
3442  *
3443  * @return error if the parsing fails, ok otherwise.
3444  */
3445 enum dbg_status qed_print_igu_fifo_results(struct qed_hwfn *p_hwfn,
3446                                            u32 *dump_buf,
3447                                            u32 num_dumped_dwords,
3448                                            char *results_buf);
3449
3450 /**
3451  * @brief qed_get_protection_override_results_buf_size - Returns the required
3452  *      buffer size for protection override results (in bytes).
3453  *
3454  * @param p_hwfn - HW device data
3455  * @param dump_buf - protection override dump buffer.
3456  * @param num_dumped_dwords - number of dwords that were dumped.
3457  * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3458  *      results.
3459  *
3460  * @return error if the parsing fails, ok otherwise.
3461  */
3462 enum dbg_status
3463 qed_get_protection_override_results_buf_size(struct qed_hwfn *p_hwfn,
3464                                              u32 *dump_buf,
3465                                              u32 num_dumped_dwords,
3466                                              u32 *results_buf_size);
3467
3468 /**
3469  * @brief qed_print_protection_override_results - Prints protection override
3470  *      results.
3471  *
3472  * @param p_hwfn - HW device data
3473  * @param dump_buf - protection override dump buffer, starting from the header.
3474  * @param num_dumped_dwords - number of dwords that were dumped.
3475  * @param results_buf - buffer for printing the reg fifo results.
3476  *
3477  * @return error if the parsing fails, ok otherwise.
3478  */
3479 enum dbg_status qed_print_protection_override_results(struct qed_hwfn *p_hwfn,
3480                                                       u32 *dump_buf,
3481                                                       u32 num_dumped_dwords,
3482                                                       char *results_buf);
3483
3484 /**
3485  * @brief qed_get_fw_asserts_results_buf_size - Returns the required buffer size
3486  *      for FW Asserts results (in bytes).
3487  *
3488  * @param p_hwfn - HW device data
3489  * @param dump_buf - FW Asserts dump buffer.
3490  * @param num_dumped_dwords - number of dwords that were dumped.
3491  * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3492  *      results.
3493  *
3494  * @return error if the parsing fails, ok otherwise.
3495  */
3496 enum dbg_status qed_get_fw_asserts_results_buf_size(struct qed_hwfn *p_hwfn,
3497                                                     u32 *dump_buf,
3498                                                     u32 num_dumped_dwords,
3499                                                     u32 *results_buf_size);
3500
3501 /**
3502  * @brief qed_print_fw_asserts_results - Prints FW Asserts results
3503  *
3504  * @param p_hwfn - HW device data
3505  * @param dump_buf - FW Asserts dump buffer, starting from the header.
3506  * @param num_dumped_dwords - number of dwords that were dumped.
3507  * @param results_buf - buffer for printing the FW Asserts results.
3508  *
3509  * @return error if the parsing fails, ok otherwise.
3510  */
3511 enum dbg_status qed_print_fw_asserts_results(struct qed_hwfn *p_hwfn,
3512                                              u32 *dump_buf,
3513                                              u32 num_dumped_dwords,
3514                                              char *results_buf);
3515
3516 /**
3517  * @brief qed_dbg_parse_attn - Parses and prints attention registers values in
3518  * the specified results struct.
3519  *
3520  * @param p_hwfn -  HW device data
3521  * @param results - Pointer to the attention read results
3522  *
3523  * @return error if one of the following holds:
3524  *      - the version wasn't set
3525  * Otherwise, returns ok.
3526  */
3527 enum dbg_status qed_dbg_parse_attn(struct qed_hwfn *p_hwfn,
3528                                    struct dbg_attn_block_result *results);
3529
3530 /* Debug Bus blocks */
3531 static const u32 dbg_bus_blocks[] = {
3532         0x0000000f,             /* grc, bb, 15 lines */
3533         0x0000000f,             /* grc, k2, 15 lines */
3534         0x00000000,
3535         0x00000000,             /* miscs, bb, 0 lines */
3536         0x00000000,             /* miscs, k2, 0 lines */
3537         0x00000000,
3538         0x00000000,             /* misc, bb, 0 lines */
3539         0x00000000,             /* misc, k2, 0 lines */
3540         0x00000000,
3541         0x00000000,             /* dbu, bb, 0 lines */
3542         0x00000000,             /* dbu, k2, 0 lines */
3543         0x00000000,
3544         0x000f0127,             /* pglue_b, bb, 39 lines */
3545         0x0036012a,             /* pglue_b, k2, 42 lines */
3546         0x00000000,
3547         0x00000000,             /* cnig, bb, 0 lines */
3548         0x00120102,             /* cnig, k2, 2 lines */
3549         0x00000000,
3550         0x00000000,             /* cpmu, bb, 0 lines */
3551         0x00000000,             /* cpmu, k2, 0 lines */
3552         0x00000000,
3553         0x00000001,             /* ncsi, bb, 1 lines */
3554         0x00000001,             /* ncsi, k2, 1 lines */
3555         0x00000000,
3556         0x00000000,             /* opte, bb, 0 lines */
3557         0x00000000,             /* opte, k2, 0 lines */
3558         0x00000000,
3559         0x00600085,             /* bmb, bb, 133 lines */
3560         0x00600085,             /* bmb, k2, 133 lines */
3561         0x00000000,
3562         0x00000000,             /* pcie, bb, 0 lines */
3563         0x00e50033,             /* pcie, k2, 51 lines */
3564         0x00000000,
3565         0x00000000,             /* mcp, bb, 0 lines */
3566         0x00000000,             /* mcp, k2, 0 lines */
3567         0x00000000,
3568         0x01180009,             /* mcp2, bb, 9 lines */
3569         0x01180009,             /* mcp2, k2, 9 lines */
3570         0x00000000,
3571         0x01210104,             /* pswhst, bb, 4 lines */
3572         0x01210104,             /* pswhst, k2, 4 lines */
3573         0x00000000,
3574         0x01250103,             /* pswhst2, bb, 3 lines */
3575         0x01250103,             /* pswhst2, k2, 3 lines */
3576         0x00000000,
3577         0x00340101,             /* pswrd, bb, 1 lines */
3578         0x00340101,             /* pswrd, k2, 1 lines */
3579         0x00000000,
3580         0x01280119,             /* pswrd2, bb, 25 lines */
3581         0x01280119,             /* pswrd2, k2, 25 lines */
3582         0x00000000,
3583         0x01410109,             /* pswwr, bb, 9 lines */
3584         0x01410109,             /* pswwr, k2, 9 lines */
3585         0x00000000,
3586         0x00000000,             /* pswwr2, bb, 0 lines */
3587         0x00000000,             /* pswwr2, k2, 0 lines */
3588         0x00000000,
3589         0x001c0001,             /* pswrq, bb, 1 lines */
3590         0x001c0001,             /* pswrq, k2, 1 lines */
3591         0x00000000,
3592         0x014a0015,             /* pswrq2, bb, 21 lines */
3593         0x014a0015,             /* pswrq2, k2, 21 lines */
3594         0x00000000,
3595         0x00000000,             /* pglcs, bb, 0 lines */
3596         0x00120006,             /* pglcs, k2, 6 lines */
3597         0x00000000,
3598         0x00100001,             /* dmae, bb, 1 lines */
3599         0x00100001,             /* dmae, k2, 1 lines */
3600         0x00000000,
3601         0x015f0105,             /* ptu, bb, 5 lines */
3602         0x015f0105,             /* ptu, k2, 5 lines */
3603         0x00000000,
3604         0x01640120,             /* tcm, bb, 32 lines */
3605         0x01640120,             /* tcm, k2, 32 lines */
3606         0x00000000,
3607         0x01640120,             /* mcm, bb, 32 lines */
3608         0x01640120,             /* mcm, k2, 32 lines */
3609         0x00000000,
3610         0x01640120,             /* ucm, bb, 32 lines */
3611         0x01640120,             /* ucm, k2, 32 lines */
3612         0x00000000,
3613         0x01640120,             /* xcm, bb, 32 lines */
3614         0x01640120,             /* xcm, k2, 32 lines */
3615         0x00000000,
3616         0x01640120,             /* ycm, bb, 32 lines */
3617         0x01640120,             /* ycm, k2, 32 lines */
3618         0x00000000,
3619         0x01640120,             /* pcm, bb, 32 lines */
3620         0x01640120,             /* pcm, k2, 32 lines */
3621         0x00000000,
3622         0x01840062,             /* qm, bb, 98 lines */
3623         0x01840062,             /* qm, k2, 98 lines */
3624         0x00000000,
3625         0x01e60021,             /* tm, bb, 33 lines */
3626         0x01e60021,             /* tm, k2, 33 lines */
3627         0x00000000,
3628         0x02070107,             /* dorq, bb, 7 lines */
3629         0x02070107,             /* dorq, k2, 7 lines */
3630         0x00000000,
3631         0x00600185,             /* brb, bb, 133 lines */
3632         0x00600185,             /* brb, k2, 133 lines */
3633         0x00000000,
3634         0x020e0019,             /* src, bb, 25 lines */
3635         0x020c001a,             /* src, k2, 26 lines */
3636         0x00000000,
3637         0x02270104,             /* prs, bb, 4 lines */
3638         0x02270104,             /* prs, k2, 4 lines */
3639         0x00000000,
3640         0x022b0133,             /* tsdm, bb, 51 lines */
3641         0x022b0133,             /* tsdm, k2, 51 lines */
3642         0x00000000,
3643         0x022b0133,             /* msdm, bb, 51 lines */
3644         0x022b0133,             /* msdm, k2, 51 lines */
3645         0x00000000,
3646         0x022b0133,             /* usdm, bb, 51 lines */
3647         0x022b0133,             /* usdm, k2, 51 lines */
3648         0x00000000,
3649         0x022b0133,             /* xsdm, bb, 51 lines */
3650         0x022b0133,             /* xsdm, k2, 51 lines */
3651         0x00000000,
3652         0x022b0133,             /* ysdm, bb, 51 lines */
3653         0x022b0133,             /* ysdm, k2, 51 lines */
3654         0x00000000,
3655         0x022b0133,             /* psdm, bb, 51 lines */
3656         0x022b0133,             /* psdm, k2, 51 lines */
3657         0x00000000,
3658         0x025e010c,             /* tsem, bb, 12 lines */
3659         0x025e010c,             /* tsem, k2, 12 lines */
3660         0x00000000,
3661         0x025e010c,             /* msem, bb, 12 lines */
3662         0x025e010c,             /* msem, k2, 12 lines */
3663         0x00000000,
3664         0x025e010c,             /* usem, bb, 12 lines */
3665         0x025e010c,             /* usem, k2, 12 lines */
3666         0x00000000,
3667         0x025e010c,             /* xsem, bb, 12 lines */
3668         0x025e010c,             /* xsem, k2, 12 lines */
3669         0x00000000,
3670         0x025e010c,             /* ysem, bb, 12 lines */
3671         0x025e010c,             /* ysem, k2, 12 lines */
3672         0x00000000,
3673         0x025e010c,             /* psem, bb, 12 lines */
3674         0x025e010c,             /* psem, k2, 12 lines */
3675         0x00000000,
3676         0x026a000d,             /* rss, bb, 13 lines */
3677         0x026a000d,             /* rss, k2, 13 lines */
3678         0x00000000,
3679         0x02770106,             /* tmld, bb, 6 lines */
3680         0x02770106,             /* tmld, k2, 6 lines */
3681         0x00000000,
3682         0x027d0106,             /* muld, bb, 6 lines */
3683         0x027d0106,             /* muld, k2, 6 lines */
3684         0x00000000,
3685         0x02770005,             /* yuld, bb, 5 lines */
3686         0x02770005,             /* yuld, k2, 5 lines */
3687         0x00000000,
3688         0x02830107,             /* xyld, bb, 7 lines */
3689         0x027d0107,             /* xyld, k2, 7 lines */
3690         0x00000000,
3691         0x00000000,             /* ptld, bb, 0 lines */
3692         0x00000000,             /* ptld, k2, 0 lines */
3693         0x00000000,
3694         0x00000000,             /* ypld, bb, 0 lines */
3695         0x00000000,             /* ypld, k2, 0 lines */
3696         0x00000000,
3697         0x028a010e,             /* prm, bb, 14 lines */
3698         0x02980110,             /* prm, k2, 16 lines */
3699         0x00000000,
3700         0x02a8000d,             /* pbf_pb1, bb, 13 lines */
3701         0x02a8000d,             /* pbf_pb1, k2, 13 lines */
3702         0x00000000,
3703         0x02a8000d,             /* pbf_pb2, bb, 13 lines */
3704         0x02a8000d,             /* pbf_pb2, k2, 13 lines */
3705         0x00000000,
3706         0x02a8000d,             /* rpb, bb, 13 lines */
3707         0x02a8000d,             /* rpb, k2, 13 lines */
3708         0x00000000,
3709         0x00600185,             /* btb, bb, 133 lines */
3710         0x00600185,             /* btb, k2, 133 lines */
3711         0x00000000,
3712         0x02b50117,             /* pbf, bb, 23 lines */
3713         0x02b50117,             /* pbf, k2, 23 lines */
3714         0x00000000,
3715         0x02cc0006,             /* rdif, bb, 6 lines */
3716         0x02cc0006,             /* rdif, k2, 6 lines */
3717         0x00000000,
3718         0x02d20006,             /* tdif, bb, 6 lines */
3719         0x02d20006,             /* tdif, k2, 6 lines */
3720         0x00000000,
3721         0x02d80003,             /* cdu, bb, 3 lines */
3722         0x02db000e,             /* cdu, k2, 14 lines */
3723         0x00000000,
3724         0x02e9010d,             /* ccfc, bb, 13 lines */
3725         0x02f60117,             /* ccfc, k2, 23 lines */
3726         0x00000000,
3727         0x02e9010d,             /* tcfc, bb, 13 lines */
3728         0x02f60117,             /* tcfc, k2, 23 lines */
3729         0x00000000,
3730         0x030d0133,             /* igu, bb, 51 lines */
3731         0x030d0133,             /* igu, k2, 51 lines */
3732         0x00000000,
3733         0x03400106,             /* cau, bb, 6 lines */
3734         0x03400106,             /* cau, k2, 6 lines */
3735         0x00000000,
3736         0x00000000,             /* rgfs, bb, 0 lines */
3737         0x00000000,             /* rgfs, k2, 0 lines */
3738         0x00000000,
3739         0x00000000,             /* rgsrc, bb, 0 lines */
3740         0x00000000,             /* rgsrc, k2, 0 lines */
3741         0x00000000,
3742         0x00000000,             /* tgfs, bb, 0 lines */
3743         0x00000000,             /* tgfs, k2, 0 lines */
3744         0x00000000,
3745         0x00000000,             /* tgsrc, bb, 0 lines */
3746         0x00000000,             /* tgsrc, k2, 0 lines */
3747         0x00000000,
3748         0x00000000,             /* umac, bb, 0 lines */
3749         0x00120006,             /* umac, k2, 6 lines */
3750         0x00000000,
3751         0x00000000,             /* xmac, bb, 0 lines */
3752         0x00000000,             /* xmac, k2, 0 lines */
3753         0x00000000,
3754         0x00000000,             /* dbg, bb, 0 lines */
3755         0x00000000,             /* dbg, k2, 0 lines */
3756         0x00000000,
3757         0x0346012b,             /* nig, bb, 43 lines */
3758         0x0346011d,             /* nig, k2, 29 lines */
3759         0x00000000,
3760         0x00000000,             /* wol, bb, 0 lines */
3761         0x001c0002,             /* wol, k2, 2 lines */
3762         0x00000000,
3763         0x00000000,             /* bmbn, bb, 0 lines */
3764         0x00210008,             /* bmbn, k2, 8 lines */
3765         0x00000000,
3766         0x00000000,             /* ipc, bb, 0 lines */
3767         0x00000000,             /* ipc, k2, 0 lines */
3768         0x00000000,
3769         0x00000000,             /* nwm, bb, 0 lines */
3770         0x0371000b,             /* nwm, k2, 11 lines */
3771         0x00000000,
3772         0x00000000,             /* nws, bb, 0 lines */
3773         0x037c0009,             /* nws, k2, 9 lines */
3774         0x00000000,
3775         0x00000000,             /* ms, bb, 0 lines */
3776         0x00120004,             /* ms, k2, 4 lines */
3777         0x00000000,
3778         0x00000000,             /* phy_pcie, bb, 0 lines */
3779         0x00e5001a,             /* phy_pcie, k2, 26 lines */
3780         0x00000000,
3781         0x00000000,             /* led, bb, 0 lines */
3782         0x00000000,             /* led, k2, 0 lines */
3783         0x00000000,
3784         0x00000000,             /* avs_wrap, bb, 0 lines */
3785         0x00000000,             /* avs_wrap, k2, 0 lines */
3786         0x00000000,
3787         0x00000000,             /* bar0_map, bb, 0 lines */
3788         0x00000000,             /* bar0_map, k2, 0 lines */
3789         0x00000000,
3790         0x00000000,             /* bar0_map, bb, 0 lines */
3791         0x00000000,             /* bar0_map, k2, 0 lines */
3792         0x00000000,
3793 };
3794
3795 /* Win 2 */
3796 #define GTT_BAR0_MAP_REG_IGU_CMD        0x00f000UL
3797
3798 /* Win 3 */
3799 #define GTT_BAR0_MAP_REG_TSDM_RAM       0x010000UL
3800
3801 /* Win 4 */
3802 #define GTT_BAR0_MAP_REG_MSDM_RAM       0x011000UL
3803
3804 /* Win 5 */
3805 #define GTT_BAR0_MAP_REG_MSDM_RAM_1024  0x012000UL
3806
3807 /* Win 6 */
3808 #define GTT_BAR0_MAP_REG_USDM_RAM       0x013000UL
3809
3810 /* Win 7 */
3811 #define GTT_BAR0_MAP_REG_USDM_RAM_1024  0x014000UL
3812
3813 /* Win 8 */
3814 #define GTT_BAR0_MAP_REG_USDM_RAM_2048  0x015000UL
3815
3816 /* Win 9 */
3817 #define GTT_BAR0_MAP_REG_XSDM_RAM       0x016000UL
3818
3819 /* Win 10 */
3820 #define GTT_BAR0_MAP_REG_YSDM_RAM       0x017000UL
3821
3822 /* Win 11 */
3823 #define GTT_BAR0_MAP_REG_PSDM_RAM       0x018000UL
3824
3825 /**
3826  * @brief qed_qm_pf_mem_size - prepare QM ILT sizes
3827  *
3828  * Returns the required host memory size in 4KB units.
3829  * Must be called before all QM init HSI functions.
3830  *
3831  * @param num_pf_cids - number of connections used by this PF
3832  * @param num_vf_cids - number of connections used by VFs of this PF
3833  * @param num_tids - number of tasks used by this PF
3834  * @param num_pf_pqs - number of PQs used by this PF
3835  * @param num_vf_pqs - number of PQs used by VFs of this PF
3836  *
3837  * @return The required host memory size in 4KB units.
3838  */
3839 u32 qed_qm_pf_mem_size(u32 num_pf_cids,
3840                        u32 num_vf_cids,
3841                        u32 num_tids, u16 num_pf_pqs, u16 num_vf_pqs);
3842
3843 struct qed_qm_common_rt_init_params {
3844         u8 max_ports_per_engine;
3845         u8 max_phys_tcs_per_port;
3846         bool pf_rl_en;
3847         bool pf_wfq_en;
3848         bool vport_rl_en;
3849         bool vport_wfq_en;
3850         struct init_qm_port_params *port_params;
3851 };
3852
3853 int qed_qm_common_rt_init(struct qed_hwfn *p_hwfn,
3854                           struct qed_qm_common_rt_init_params *p_params);
3855
3856 struct qed_qm_pf_rt_init_params {
3857         u8 port_id;
3858         u8 pf_id;
3859         u8 max_phys_tcs_per_port;
3860         bool is_pf_loading;
3861         u32 num_pf_cids;
3862         u32 num_vf_cids;
3863         u32 num_tids;
3864         u16 start_pq;
3865         u16 num_pf_pqs;
3866         u16 num_vf_pqs;
3867         u8 start_vport;
3868         u8 num_vports;
3869         u16 pf_wfq;
3870         u32 pf_rl;
3871         u32 link_speed;
3872         struct init_qm_pq_params *pq_params;
3873         struct init_qm_vport_params *vport_params;
3874 };
3875
3876 int qed_qm_pf_rt_init(struct qed_hwfn *p_hwfn,
3877         struct qed_ptt *p_ptt,
3878         struct qed_qm_pf_rt_init_params *p_params);
3879
3880 /**
3881  * @brief qed_init_pf_wfq - Initializes the WFQ weight of the specified PF
3882  *
3883  * @param p_hwfn
3884  * @param p_ptt - ptt window used for writing the registers
3885  * @param pf_id - PF ID
3886  * @param pf_wfq - WFQ weight. Must be non-zero.
3887  *
3888  * @return 0 on success, -1 on error.
3889  */
3890 int qed_init_pf_wfq(struct qed_hwfn *p_hwfn,
3891                     struct qed_ptt *p_ptt, u8 pf_id, u16 pf_wfq);
3892
3893 /**
3894  * @brief qed_init_pf_rl - Initializes the rate limit of the specified PF
3895  *
3896  * @param p_hwfn
3897  * @param p_ptt - ptt window used for writing the registers
3898  * @param pf_id - PF ID
3899  * @param pf_rl - rate limit in Mb/sec units
3900  *
3901  * @return 0 on success, -1 on error.
3902  */
3903 int qed_init_pf_rl(struct qed_hwfn *p_hwfn,
3904                    struct qed_ptt *p_ptt, u8 pf_id, u32 pf_rl);
3905
3906 /**
3907  * @brief qed_init_vport_wfq Initializes the WFQ weight of the specified VPORT
3908  *
3909  * @param p_hwfn
3910  * @param p_ptt - ptt window used for writing the registers
3911  * @param first_tx_pq_id- An array containing the first Tx PQ ID associated
3912  *        with the VPORT for each TC. This array is filled by
3913  *        qed_qm_pf_rt_init
3914  * @param vport_wfq - WFQ weight. Must be non-zero.
3915  *
3916  * @return 0 on success, -1 on error.
3917  */
3918 int qed_init_vport_wfq(struct qed_hwfn *p_hwfn,
3919                        struct qed_ptt *p_ptt,
3920                        u16 first_tx_pq_id[NUM_OF_TCS], u16 vport_wfq);
3921
3922 /**
3923  * @brief qed_init_vport_rl - Initializes the rate limit of the specified VPORT
3924  *
3925  * @param p_hwfn
3926  * @param p_ptt - ptt window used for writing the registers
3927  * @param vport_id - VPORT ID
3928  * @param vport_rl - rate limit in Mb/sec units
3929  * @param link_speed - link speed in Mbps.
3930  *
3931  * @return 0 on success, -1 on error.
3932  */
3933 int qed_init_vport_rl(struct qed_hwfn *p_hwfn,
3934                       struct qed_ptt *p_ptt,
3935                       u8 vport_id, u32 vport_rl, u32 link_speed);
3936
3937 /**
3938  * @brief qed_send_qm_stop_cmd  Sends a stop command to the QM
3939  *
3940  * @param p_hwfn
3941  * @param p_ptt
3942  * @param is_release_cmd - true for release, false for stop.
3943  * @param is_tx_pq - true for Tx PQs, false for Other PQs.
3944  * @param start_pq - first PQ ID to stop
3945  * @param num_pqs - Number of PQs to stop, starting from start_pq.
3946  *
3947  * @return bool, true if successful, false if timeout occurred while waiting for
3948  *      QM command done.
3949  */
3950 bool qed_send_qm_stop_cmd(struct qed_hwfn *p_hwfn,
3951                           struct qed_ptt *p_ptt,
3952                           bool is_release_cmd,
3953                           bool is_tx_pq, u16 start_pq, u16 num_pqs);
3954
3955 /**
3956  * @brief qed_set_vxlan_dest_port - initializes vxlan tunnel destination udp port
3957  *
3958  * @param p_hwfn
3959  * @param p_ptt - ptt window used for writing the registers.
3960  * @param dest_port - vxlan destination udp port.
3961  */
3962 void qed_set_vxlan_dest_port(struct qed_hwfn *p_hwfn,
3963                              struct qed_ptt *p_ptt, u16 dest_port);
3964
3965 /**
3966  * @brief qed_set_vxlan_enable - enable or disable VXLAN tunnel in HW
3967  *
3968  * @param p_hwfn
3969  * @param p_ptt - ptt window used for writing the registers.
3970  * @param vxlan_enable - vxlan enable flag.
3971  */
3972 void qed_set_vxlan_enable(struct qed_hwfn *p_hwfn,
3973                           struct qed_ptt *p_ptt, bool vxlan_enable);
3974
3975 /**
3976  * @brief qed_set_gre_enable - enable or disable GRE tunnel in HW
3977  *
3978  * @param p_hwfn
3979  * @param p_ptt - ptt window used for writing the registers.
3980  * @param eth_gre_enable - eth GRE enable enable flag.
3981  * @param ip_gre_enable - IP GRE enable enable flag.
3982  */
3983 void qed_set_gre_enable(struct qed_hwfn *p_hwfn,
3984                         struct qed_ptt *p_ptt,
3985                         bool eth_gre_enable, bool ip_gre_enable);
3986
3987 /**
3988  * @brief qed_set_geneve_dest_port - initializes geneve tunnel destination udp port
3989  *
3990  * @param p_hwfn
3991  * @param p_ptt - ptt window used for writing the registers.
3992  * @param dest_port - geneve destination udp port.
3993  */
3994 void qed_set_geneve_dest_port(struct qed_hwfn *p_hwfn,
3995                               struct qed_ptt *p_ptt, u16 dest_port);
3996
3997 /**
3998  * @brief qed_set_gre_enable - enable or disable GRE tunnel in HW
3999  *
4000  * @param p_ptt - ptt window used for writing the registers.
4001  * @param eth_geneve_enable - eth GENEVE enable enable flag.
4002  * @param ip_geneve_enable - IP GENEVE enable enable flag.
4003  */
4004 void qed_set_geneve_enable(struct qed_hwfn *p_hwfn,
4005                            struct qed_ptt *p_ptt,
4006                            bool eth_geneve_enable, bool ip_geneve_enable);
4007
4008 /**
4009  * @brief qed_gft_disable - Disable GFT
4010  *
4011  * @param p_hwfn
4012  * @param p_ptt - ptt window used for writing the registers.
4013  * @param pf_id - pf on which to disable GFT.
4014  */
4015 void qed_gft_disable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u16 pf_id);
4016
4017 /**
4018  * @brief qed_gft_config - Enable and configure HW for GFT
4019  *
4020  * @param p_hwfn
4021  * @param p_ptt - ptt window used for writing the registers.
4022  * @param pf_id - pf on which to enable GFT.
4023  * @param tcp - set profile tcp packets.
4024  * @param udp - set profile udp  packet.
4025  * @param ipv4 - set profile ipv4 packet.
4026  * @param ipv6 - set profile ipv6 packet.
4027  * @param profile_type - define packet same fields. Use enum gft_profile_type.
4028  */
4029 void qed_gft_config(struct qed_hwfn *p_hwfn,
4030                     struct qed_ptt *p_ptt,
4031                     u16 pf_id,
4032                     bool tcp,
4033                     bool udp,
4034                     bool ipv4, bool ipv6, enum gft_profile_type profile_type);
4035
4036 /**
4037  * @brief qed_enable_context_validation - Enable and configure context
4038  *      validation.
4039  *
4040  * @param p_hwfn
4041  * @param p_ptt - ptt window used for writing the registers.
4042  */
4043 void qed_enable_context_validation(struct qed_hwfn *p_hwfn,
4044                                    struct qed_ptt *p_ptt);
4045
4046 /**
4047  * @brief qed_calc_session_ctx_validation - Calcualte validation byte for
4048  *      session context.
4049  *
4050  * @param p_ctx_mem - pointer to context memory.
4051  * @param ctx_size - context size.
4052  * @param ctx_type - context type.
4053  * @param cid - context cid.
4054  */
4055 void qed_calc_session_ctx_validation(void *p_ctx_mem,
4056                                      u16 ctx_size, u8 ctx_type, u32 cid);
4057
4058 /**
4059  * @brief qed_calc_task_ctx_validation - Calcualte validation byte for task
4060  *      context.
4061  *
4062  * @param p_ctx_mem - pointer to context memory.
4063  * @param ctx_size - context size.
4064  * @param ctx_type - context type.
4065  * @param tid - context tid.
4066  */
4067 void qed_calc_task_ctx_validation(void *p_ctx_mem,
4068                                   u16 ctx_size, u8 ctx_type, u32 tid);
4069
4070 /**
4071  * @brief qed_memset_session_ctx - Memset session context to 0 while
4072  *      preserving validation bytes.
4073  *
4074  * @param p_hwfn -
4075  * @param p_ctx_mem - pointer to context memory.
4076  * @param ctx_size - size to initialzie.
4077  * @param ctx_type - context type.
4078  */
4079 void qed_memset_session_ctx(void *p_ctx_mem, u32 ctx_size, u8 ctx_type);
4080
4081 /**
4082  * @brief qed_memset_task_ctx - Memset task context to 0 while preserving
4083  *      validation bytes.
4084  *
4085  * @param p_ctx_mem - pointer to context memory.
4086  * @param ctx_size - size to initialzie.
4087  * @param ctx_type - context type.
4088  */
4089 void qed_memset_task_ctx(void *p_ctx_mem, u32 ctx_size, u8 ctx_type);
4090
4091 /* Ystorm flow control mode. Use enum fw_flow_ctrl_mode */
4092 #define YSTORM_FLOW_CONTROL_MODE_OFFSET                 (IRO[0].base)
4093 #define YSTORM_FLOW_CONTROL_MODE_SIZE                   (IRO[0].size)
4094
4095 /* Tstorm port statistics */
4096 #define TSTORM_PORT_STAT_OFFSET(port_id) \
4097         (IRO[1].base + ((port_id) * IRO[1].m1))
4098 #define TSTORM_PORT_STAT_SIZE                           (IRO[1].size)
4099
4100 /* Tstorm ll2 port statistics */
4101 #define TSTORM_LL2_PORT_STAT_OFFSET(port_id) \
4102         (IRO[2].base + ((port_id) * IRO[2].m1))
4103 #define TSTORM_LL2_PORT_STAT_SIZE                       (IRO[2].size)
4104
4105 /* Ustorm VF-PF Channel ready flag */
4106 #define USTORM_VF_PF_CHANNEL_READY_OFFSET(vf_id) \
4107         (IRO[3].base + ((vf_id) * IRO[3].m1))
4108 #define USTORM_VF_PF_CHANNEL_READY_SIZE                 (IRO[3].size)
4109
4110 /* Ustorm Final flr cleanup ack */
4111 #define USTORM_FLR_FINAL_ACK_OFFSET(pf_id) \
4112         (IRO[4].base + ((pf_id) * IRO[4].m1))
4113 #define USTORM_FLR_FINAL_ACK_SIZE                       (IRO[4].size)
4114
4115 /* Ustorm Event ring consumer */
4116 #define USTORM_EQE_CONS_OFFSET(pf_id) \
4117         (IRO[5].base + ((pf_id) * IRO[5].m1))
4118 #define USTORM_EQE_CONS_SIZE                            (IRO[5].size)
4119
4120 /* Ustorm eth queue zone */
4121 #define USTORM_ETH_QUEUE_ZONE_OFFSET(queue_zone_id) \
4122         (IRO[6].base + ((queue_zone_id) * IRO[6].m1))
4123 #define USTORM_ETH_QUEUE_ZONE_SIZE                      (IRO[6].size)
4124
4125 /* Ustorm Common Queue ring consumer */
4126 #define USTORM_COMMON_QUEUE_CONS_OFFSET(queue_zone_id) \
4127         (IRO[7].base + ((queue_zone_id) * IRO[7].m1))
4128 #define USTORM_COMMON_QUEUE_CONS_SIZE                   (IRO[7].size)
4129
4130 /* Xstorm Integration Test Data */
4131 #define XSTORM_INTEG_TEST_DATA_OFFSET                   (IRO[8].base)
4132 #define XSTORM_INTEG_TEST_DATA_SIZE                     (IRO[8].size)
4133
4134 /* Ystorm Integration Test Data */
4135 #define YSTORM_INTEG_TEST_DATA_OFFSET                   (IRO[9].base)
4136 #define YSTORM_INTEG_TEST_DATA_SIZE                     (IRO[9].size)
4137
4138 /* Pstorm Integration Test Data */
4139 #define PSTORM_INTEG_TEST_DATA_OFFSET                   (IRO[10].base)
4140 #define PSTORM_INTEG_TEST_DATA_SIZE                     (IRO[10].size)
4141
4142 /* Tstorm Integration Test Data */
4143 #define TSTORM_INTEG_TEST_DATA_OFFSET                   (IRO[11].base)
4144 #define TSTORM_INTEG_TEST_DATA_SIZE                     (IRO[11].size)
4145
4146 /* Mstorm Integration Test Data */
4147 #define MSTORM_INTEG_TEST_DATA_OFFSET                   (IRO[12].base)
4148 #define MSTORM_INTEG_TEST_DATA_SIZE                     (IRO[12].size)
4149
4150 /* Ustorm Integration Test Data */
4151 #define USTORM_INTEG_TEST_DATA_OFFSET                   (IRO[13].base)
4152 #define USTORM_INTEG_TEST_DATA_SIZE                     (IRO[13].size)
4153
4154 /* Tstorm producers */
4155 #define TSTORM_LL2_RX_PRODS_OFFSET(core_rx_queue_id) \
4156         (IRO[14].base + ((core_rx_queue_id) * IRO[14].m1))
4157 #define TSTORM_LL2_RX_PRODS_SIZE                        (IRO[14].size)
4158
4159 /* Tstorm LightL2 queue statistics */
4160 #define CORE_LL2_TSTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \
4161         (IRO[15].base + ((core_rx_queue_id) * IRO[15].m1))
4162 #define CORE_LL2_TSTORM_PER_QUEUE_STAT_SIZE             (IRO[15].size)
4163
4164 /* Ustorm LiteL2 queue statistics */
4165 #define CORE_LL2_USTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \
4166         (IRO[16].base + ((core_rx_queue_id) * IRO[16].m1))
4167 #define CORE_LL2_USTORM_PER_QUEUE_STAT_SIZE             (IRO[16].size)
4168
4169 /* Pstorm LiteL2 queue statistics */
4170 #define CORE_LL2_PSTORM_PER_QUEUE_STAT_OFFSET(core_tx_stats_id) \
4171         (IRO[17].base + ((core_tx_stats_id) * IRO[17].m1))
4172 #define CORE_LL2_PSTORM_PER_QUEUE_STAT_SIZE             (IRO[17].size)
4173
4174 /* Mstorm queue statistics */
4175 #define MSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
4176         (IRO[18].base + ((stat_counter_id) * IRO[18].m1))
4177 #define MSTORM_QUEUE_STAT_SIZE                          (IRO[18].size)
4178
4179 /* Mstorm ETH PF queues producers */
4180 #define MSTORM_ETH_PF_PRODS_OFFSET(queue_id) \
4181         (IRO[19].base + ((queue_id) * IRO[19].m1))
4182 #define MSTORM_ETH_PF_PRODS_SIZE                        (IRO[19].size)
4183
4184 /* Mstorm ETH VF queues producers offset in RAM. Used in default VF zone size
4185  * mode.
4186  */
4187 #define MSTORM_ETH_VF_PRODS_OFFSET(vf_id, vf_queue_id) \
4188         (IRO[20].base + ((vf_id) * IRO[20].m1) + ((vf_queue_id) * IRO[20].m2))
4189 #define MSTORM_ETH_VF_PRODS_SIZE                        (IRO[20].size)
4190
4191 /* TPA agregation timeout in us resolution (on ASIC) */
4192 #define MSTORM_TPA_TIMEOUT_US_OFFSET                    (IRO[21].base)
4193 #define MSTORM_TPA_TIMEOUT_US_SIZE                      (IRO[21].size)
4194
4195 /* Mstorm pf statistics */
4196 #define MSTORM_ETH_PF_STAT_OFFSET(pf_id) \
4197         (IRO[22].base + ((pf_id) * IRO[22].m1))
4198 #define MSTORM_ETH_PF_STAT_SIZE                         (IRO[22].size)
4199
4200 /* Ustorm queue statistics */
4201 #define USTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
4202         (IRO[23].base + ((stat_counter_id) * IRO[23].m1))
4203 #define USTORM_QUEUE_STAT_SIZE                          (IRO[23].size)
4204
4205 /* Ustorm pf statistics */
4206 #define USTORM_ETH_PF_STAT_OFFSET(pf_id)\
4207         (IRO[24].base + ((pf_id) * IRO[24].m1))
4208 #define USTORM_ETH_PF_STAT_SIZE                         (IRO[24].size)
4209
4210 /* Pstorm queue statistics */
4211 #define PSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
4212         (IRO[25].base + ((stat_counter_id) * IRO[25].m1))
4213 #define PSTORM_QUEUE_STAT_SIZE                          (IRO[25].size)
4214
4215 /* Pstorm pf statistics */
4216 #define PSTORM_ETH_PF_STAT_OFFSET(pf_id) \
4217         (IRO[26].base + ((pf_id) * IRO[26].m1))
4218 #define PSTORM_ETH_PF_STAT_SIZE                         (IRO[26].size)
4219
4220 /* Control frame's EthType configuration for TX control frame security */
4221 #define PSTORM_CTL_FRAME_ETHTYPE_OFFSET(eth_type_id) \
4222         (IRO[27].base + ((eth_type_id) * IRO[27].m1))
4223 #define PSTORM_CTL_FRAME_ETHTYPE_SIZE                   (IRO[27].size)
4224
4225 /* Tstorm last parser message */
4226 #define TSTORM_ETH_PRS_INPUT_OFFSET                     (IRO[28].base)
4227 #define TSTORM_ETH_PRS_INPUT_SIZE                       (IRO[28].size)
4228
4229 /* Tstorm Eth limit Rx rate */
4230 #define ETH_RX_RATE_LIMIT_OFFSET(pf_id) \
4231         (IRO[29].base + ((pf_id) * IRO[29].m1))
4232 #define ETH_RX_RATE_LIMIT_SIZE                          (IRO[29].size)
4233
4234 /* Xstorm queue zone */
4235 #define XSTORM_ETH_QUEUE_ZONE_OFFSET(queue_id) \
4236         (IRO[30].base + ((queue_id) * IRO[30].m1))
4237 #define XSTORM_ETH_QUEUE_ZONE_SIZE                      (IRO[30].size)
4238
4239 /* Ystorm cqe producer */
4240 #define YSTORM_TOE_CQ_PROD_OFFSET(rss_id) \
4241         (IRO[31].base + ((rss_id) * IRO[31].m1))
4242 #define YSTORM_TOE_CQ_PROD_SIZE                         (IRO[31].size)
4243
4244 /* Ustorm cqe producer */
4245 #define USTORM_TOE_CQ_PROD_OFFSET(rss_id) \
4246         (IRO[32].base + ((rss_id) * IRO[32].m1))
4247 #define USTORM_TOE_CQ_PROD_SIZE                         (IRO[32].size)
4248
4249 /* Ustorm grq producer */
4250 #define USTORM_TOE_GRQ_PROD_OFFSET(pf_id) \
4251         (IRO[33].base + ((pf_id) * IRO[33].m1))
4252 #define USTORM_TOE_GRQ_PROD_SIZE                        (IRO[33].size)
4253
4254 /* Tstorm cmdq-cons of given command queue-id */
4255 #define TSTORM_SCSI_CMDQ_CONS_OFFSET(cmdq_queue_id) \
4256         (IRO[34].base + ((cmdq_queue_id) * IRO[34].m1))
4257 #define TSTORM_SCSI_CMDQ_CONS_SIZE                      (IRO[34].size)
4258
4259 /* Tstorm (reflects M-Storm) bdq-external-producer of given function ID,
4260  * BDqueue-id.
4261  */
4262 #define TSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id, bdq_id) \
4263         (IRO[35].base + ((func_id) * IRO[35].m1) + ((bdq_id) * IRO[35].m2))
4264 #define TSTORM_SCSI_BDQ_EXT_PROD_SIZE                   (IRO[35].size)
4265
4266 /* Mstorm bdq-external-producer of given BDQ resource ID, BDqueue-id */
4267 #define MSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id, bdq_id) \
4268         (IRO[36].base + ((func_id) * IRO[36].m1) + ((bdq_id) * IRO[36].m2))
4269 #define MSTORM_SCSI_BDQ_EXT_PROD_SIZE                   (IRO[36].size)
4270
4271 /* Tstorm iSCSI RX stats */
4272 #define TSTORM_ISCSI_RX_STATS_OFFSET(pf_id) \
4273         (IRO[37].base + ((pf_id) * IRO[37].m1))
4274 #define TSTORM_ISCSI_RX_STATS_SIZE                      (IRO[37].size)
4275
4276 /* Mstorm iSCSI RX stats */
4277 #define MSTORM_ISCSI_RX_STATS_OFFSET(pf_id) \
4278         (IRO[38].base + ((pf_id) * IRO[38].m1))
4279 #define MSTORM_ISCSI_RX_STATS_SIZE                      (IRO[38].size)
4280
4281 /* Ustorm iSCSI RX stats */
4282 #define USTORM_ISCSI_RX_STATS_OFFSET(pf_id) \
4283         (IRO[39].base + ((pf_id) * IRO[39].m1))
4284 #define USTORM_ISCSI_RX_STATS_SIZE                      (IRO[39].size)
4285
4286 /* Xstorm iSCSI TX stats */
4287 #define XSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \
4288         (IRO[40].base + ((pf_id) * IRO[40].m1))
4289 #define XSTORM_ISCSI_TX_STATS_SIZE                      (IRO[40].size)
4290
4291 /* Ystorm iSCSI TX stats */
4292 #define YSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \
4293         (IRO[41].base + ((pf_id) * IRO[41].m1))
4294 #define YSTORM_ISCSI_TX_STATS_SIZE                      (IRO[41].size)
4295
4296 /* Pstorm iSCSI TX stats */
4297 #define PSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \
4298         (IRO[42].base + ((pf_id) * IRO[42].m1))
4299 #define PSTORM_ISCSI_TX_STATS_SIZE                      (IRO[42].size)
4300
4301 /* Tstorm FCoE RX stats */
4302 #define TSTORM_FCOE_RX_STATS_OFFSET(pf_id) \
4303         (IRO[43].base + ((pf_id) * IRO[43].m1))
4304 #define TSTORM_FCOE_RX_STATS_SIZE                       (IRO[43].size)
4305
4306 /* Pstorm FCoE TX stats */
4307 #define PSTORM_FCOE_TX_STATS_OFFSET(pf_id) \
4308         (IRO[44].base + ((pf_id) * IRO[44].m1))
4309 #define PSTORM_FCOE_TX_STATS_SIZE                       (IRO[44].size)
4310
4311 /* Pstorm RDMA queue statistics */
4312 #define PSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) \
4313         (IRO[45].base + ((rdma_stat_counter_id) * IRO[45].m1))
4314 #define PSTORM_RDMA_QUEUE_STAT_SIZE                     (IRO[45].size)
4315
4316 /* Tstorm RDMA queue statistics */
4317 #define TSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) \
4318         (IRO[46].base + ((rdma_stat_counter_id) * IRO[46].m1))
4319 #define TSTORM_RDMA_QUEUE_STAT_SIZE                     (IRO[46].size)
4320
4321 /* Xstorm iWARP rxmit stats */
4322 #define XSTORM_IWARP_RXMIT_STATS_OFFSET(pf_id) \
4323         (IRO[47].base + ((pf_id) * IRO[47].m1))
4324 #define XSTORM_IWARP_RXMIT_STATS_SIZE                   (IRO[47].size)
4325
4326 /* Tstorm RoCE Event Statistics */
4327 #define TSTORM_ROCE_EVENTS_STAT_OFFSET(roce_pf_id) \
4328         (IRO[48].base + ((roce_pf_id) * IRO[48].m1))
4329 #define TSTORM_ROCE_EVENTS_STAT_SIZE                    (IRO[48].size)
4330
4331 /* DCQCN Received Statistics */
4332 #define YSTORM_ROCE_DCQCN_RECEIVED_STATS_OFFSET(roce_pf_id) \
4333         (IRO[49].base + ((roce_pf_id) * IRO[49].m1))
4334 #define YSTORM_ROCE_DCQCN_RECEIVED_STATS_SIZE           (IRO[49].size)
4335
4336 /* DCQCN Sent Statistics */
4337 #define PSTORM_ROCE_DCQCN_SENT_STATS_OFFSET(roce_pf_id) \
4338         (IRO[50].base + ((roce_pf_id) * IRO[50].m1))
4339 #define PSTORM_ROCE_DCQCN_SENT_STATS_SIZE               (IRO[50].size)
4340
4341 static const struct iro iro_arr[51] = {
4342         {0x0, 0x0, 0x0, 0x0, 0x8},
4343         {0x4cb8, 0x88, 0x0, 0x0, 0x88},
4344         {0x6530, 0x20, 0x0, 0x0, 0x20},
4345         {0xb00, 0x8, 0x0, 0x0, 0x4},
4346         {0xa80, 0x8, 0x0, 0x0, 0x4},
4347         {0x0, 0x8, 0x0, 0x0, 0x2},
4348         {0x80, 0x8, 0x0, 0x0, 0x4},
4349         {0x84, 0x8, 0x0, 0x0, 0x2},
4350         {0x4c48, 0x0, 0x0, 0x0, 0x78},
4351         {0x3e18, 0x0, 0x0, 0x0, 0x78},
4352         {0x2b58, 0x0, 0x0, 0x0, 0x78},
4353         {0x4c40, 0x0, 0x0, 0x0, 0x78},
4354         {0x4998, 0x0, 0x0, 0x0, 0x78},
4355         {0x7f50, 0x0, 0x0, 0x0, 0x78},
4356         {0xa28, 0x8, 0x0, 0x0, 0x8},
4357         {0x6210, 0x10, 0x0, 0x0, 0x10},
4358         {0xb820, 0x30, 0x0, 0x0, 0x30},
4359         {0x96c0, 0x30, 0x0, 0x0, 0x30},
4360         {0x4b68, 0x80, 0x0, 0x0, 0x40},
4361         {0x1f8, 0x4, 0x0, 0x0, 0x4},
4362         {0x53a8, 0x80, 0x4, 0x0, 0x4},
4363         {0xc7d0, 0x0, 0x0, 0x0, 0x4},
4364         {0x4ba8, 0x80, 0x0, 0x0, 0x20},
4365         {0x8158, 0x40, 0x0, 0x0, 0x30},
4366         {0xe770, 0x60, 0x0, 0x0, 0x60},
4367         {0x2cf0, 0x80, 0x0, 0x0, 0x38},
4368         {0xf2b8, 0x78, 0x0, 0x0, 0x78},
4369         {0x1f8, 0x4, 0x0, 0x0, 0x4},
4370         {0xaf20, 0x0, 0x0, 0x0, 0xf0},
4371         {0xb010, 0x8, 0x0, 0x0, 0x8},
4372         {0x1f8, 0x8, 0x0, 0x0, 0x8},
4373         {0xac0, 0x8, 0x0, 0x0, 0x8},
4374         {0x2578, 0x8, 0x0, 0x0, 0x8},
4375         {0x24f8, 0x8, 0x0, 0x0, 0x8},
4376         {0x0, 0x8, 0x0, 0x0, 0x8},
4377         {0x400, 0x18, 0x8, 0x0, 0x8},
4378         {0xb78, 0x18, 0x8, 0x0, 0x2},
4379         {0xd898, 0x50, 0x0, 0x0, 0x3c},
4380         {0x12908, 0x18, 0x0, 0x0, 0x10},
4381         {0x11aa8, 0x40, 0x0, 0x0, 0x18},
4382         {0xa588, 0x50, 0x0, 0x0, 0x20},
4383         {0x8700, 0x40, 0x0, 0x0, 0x28},
4384         {0x10300, 0x18, 0x0, 0x0, 0x10},
4385         {0xde48, 0x48, 0x0, 0x0, 0x38},
4386         {0x10768, 0x20, 0x0, 0x0, 0x20},
4387         {0x2d28, 0x80, 0x0, 0x0, 0x10},
4388         {0x5048, 0x10, 0x0, 0x0, 0x10},
4389         {0xc9b8, 0x30, 0x0, 0x0, 0x10},
4390         {0xeee0, 0x10, 0x0, 0x0, 0x10},
4391         {0xa3a0, 0x10, 0x0, 0x0, 0x10},
4392         {0x13108, 0x8, 0x0, 0x0, 0x8},
4393 };
4394
4395 /* Runtime array offsets */
4396 #define DORQ_REG_PF_MAX_ICID_0_RT_OFFSET                        0
4397 #define DORQ_REG_PF_MAX_ICID_1_RT_OFFSET                        1
4398 #define DORQ_REG_PF_MAX_ICID_2_RT_OFFSET                        2
4399 #define DORQ_REG_PF_MAX_ICID_3_RT_OFFSET                        3
4400 #define DORQ_REG_PF_MAX_ICID_4_RT_OFFSET                        4
4401 #define DORQ_REG_PF_MAX_ICID_5_RT_OFFSET                        5
4402 #define DORQ_REG_PF_MAX_ICID_6_RT_OFFSET                        6
4403 #define DORQ_REG_PF_MAX_ICID_7_RT_OFFSET                        7
4404 #define DORQ_REG_VF_MAX_ICID_0_RT_OFFSET                        8
4405 #define DORQ_REG_VF_MAX_ICID_1_RT_OFFSET                        9
4406 #define DORQ_REG_VF_MAX_ICID_2_RT_OFFSET                        10
4407 #define DORQ_REG_VF_MAX_ICID_3_RT_OFFSET                        11
4408 #define DORQ_REG_VF_MAX_ICID_4_RT_OFFSET                        12
4409 #define DORQ_REG_VF_MAX_ICID_5_RT_OFFSET                        13
4410 #define DORQ_REG_VF_MAX_ICID_6_RT_OFFSET                        14
4411 #define DORQ_REG_VF_MAX_ICID_7_RT_OFFSET                        15
4412 #define DORQ_REG_PF_WAKE_ALL_RT_OFFSET                          16
4413 #define DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET                       17
4414 #define DORQ_REG_GLB_MAX_ICID_0_RT_OFFSET                       18
4415 #define DORQ_REG_GLB_MAX_ICID_1_RT_OFFSET                       19
4416 #define DORQ_REG_GLB_RANGE2CONN_TYPE_0_RT_OFFSET                20
4417 #define DORQ_REG_GLB_RANGE2CONN_TYPE_1_RT_OFFSET                21
4418 #define DORQ_REG_PRV_PF_MAX_ICID_2_RT_OFFSET                    22
4419 #define DORQ_REG_PRV_PF_MAX_ICID_3_RT_OFFSET                    23
4420 #define DORQ_REG_PRV_PF_MAX_ICID_4_RT_OFFSET                    24
4421 #define DORQ_REG_PRV_PF_MAX_ICID_5_RT_OFFSET                    25
4422 #define DORQ_REG_PRV_VF_MAX_ICID_2_RT_OFFSET                    26
4423 #define DORQ_REG_PRV_VF_MAX_ICID_3_RT_OFFSET                    27
4424 #define DORQ_REG_PRV_VF_MAX_ICID_4_RT_OFFSET                    28
4425 #define DORQ_REG_PRV_VF_MAX_ICID_5_RT_OFFSET                    29
4426 #define DORQ_REG_PRV_PF_RANGE2CONN_TYPE_2_RT_OFFSET             30
4427 #define DORQ_REG_PRV_PF_RANGE2CONN_TYPE_3_RT_OFFSET             31
4428 #define DORQ_REG_PRV_PF_RANGE2CONN_TYPE_4_RT_OFFSET             32
4429 #define DORQ_REG_PRV_PF_RANGE2CONN_TYPE_5_RT_OFFSET             33
4430 #define DORQ_REG_PRV_VF_RANGE2CONN_TYPE_2_RT_OFFSET             34
4431 #define DORQ_REG_PRV_VF_RANGE2CONN_TYPE_3_RT_OFFSET             35
4432 #define DORQ_REG_PRV_VF_RANGE2CONN_TYPE_4_RT_OFFSET             36
4433 #define DORQ_REG_PRV_VF_RANGE2CONN_TYPE_5_RT_OFFSET             37
4434 #define IGU_REG_PF_CONFIGURATION_RT_OFFSET                      38
4435 #define IGU_REG_VF_CONFIGURATION_RT_OFFSET                      39
4436 #define IGU_REG_ATTN_MSG_ADDR_L_RT_OFFSET                       40
4437 #define IGU_REG_ATTN_MSG_ADDR_H_RT_OFFSET                       41
4438 #define IGU_REG_LEADING_EDGE_LATCH_RT_OFFSET                    42
4439 #define IGU_REG_TRAILING_EDGE_LATCH_RT_OFFSET                   43
4440 #define CAU_REG_CQE_AGG_UNIT_SIZE_RT_OFFSET                     44
4441 #define CAU_REG_SB_VAR_MEMORY_RT_OFFSET                         45
4442 #define CAU_REG_SB_VAR_MEMORY_RT_SIZE                           1024
4443 #define CAU_REG_SB_ADDR_MEMORY_RT_OFFSET                        1069
4444 #define CAU_REG_SB_ADDR_MEMORY_RT_SIZE                          1024
4445 #define CAU_REG_PI_MEMORY_RT_OFFSET                             2093
4446 #define CAU_REG_PI_MEMORY_RT_SIZE                               4416
4447 #define PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET            6509
4448 #define PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET              6510
4449 #define PRS_REG_TASK_ID_MAX_INITIATOR_VF_RT_OFFSET              6511
4450 #define PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET                 6512
4451 #define PRS_REG_TASK_ID_MAX_TARGET_VF_RT_OFFSET                 6513
4452 #define PRS_REG_SEARCH_TCP_RT_OFFSET                            6514
4453 #define PRS_REG_SEARCH_FCOE_RT_OFFSET                           6515
4454 #define PRS_REG_SEARCH_ROCE_RT_OFFSET                           6516
4455 #define PRS_REG_ROCE_DEST_QP_MAX_VF_RT_OFFSET                   6517
4456 #define PRS_REG_ROCE_DEST_QP_MAX_PF_RT_OFFSET                   6518
4457 #define PRS_REG_SEARCH_OPENFLOW_RT_OFFSET                       6519
4458 #define PRS_REG_SEARCH_NON_IP_AS_OPENFLOW_RT_OFFSET             6520
4459 #define PRS_REG_OPENFLOW_SUPPORT_ONLY_KNOWN_OVER_IP_RT_OFFSET   6521
4460 #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_RT_OFFSET              6522
4461 #define PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET                       6523
4462 #define PRS_REG_LIGHT_L2_ETHERTYPE_EN_RT_OFFSET                 6524
4463 #define SRC_REG_FIRSTFREE_RT_OFFSET                             6525
4464 #define SRC_REG_FIRSTFREE_RT_SIZE                               2
4465 #define SRC_REG_LASTFREE_RT_OFFSET                              6527
4466 #define SRC_REG_LASTFREE_RT_SIZE                                2
4467 #define SRC_REG_COUNTFREE_RT_OFFSET                             6529
4468 #define SRC_REG_NUMBER_HASH_BITS_RT_OFFSET                      6530
4469 #define PSWRQ2_REG_CDUT_P_SIZE_RT_OFFSET                        6531
4470 #define PSWRQ2_REG_CDUC_P_SIZE_RT_OFFSET                        6532
4471 #define PSWRQ2_REG_TM_P_SIZE_RT_OFFSET                          6533
4472 #define PSWRQ2_REG_QM_P_SIZE_RT_OFFSET                          6534
4473 #define PSWRQ2_REG_SRC_P_SIZE_RT_OFFSET                         6535
4474 #define PSWRQ2_REG_TSDM_P_SIZE_RT_OFFSET                        6536
4475 #define PSWRQ2_REG_TM_FIRST_ILT_RT_OFFSET                       6537
4476 #define PSWRQ2_REG_TM_LAST_ILT_RT_OFFSET                        6538
4477 #define PSWRQ2_REG_QM_FIRST_ILT_RT_OFFSET                       6539
4478 #define PSWRQ2_REG_QM_LAST_ILT_RT_OFFSET                        6540
4479 #define PSWRQ2_REG_SRC_FIRST_ILT_RT_OFFSET                      6541
4480 #define PSWRQ2_REG_SRC_LAST_ILT_RT_OFFSET                       6542
4481 #define PSWRQ2_REG_CDUC_FIRST_ILT_RT_OFFSET                     6543
4482 #define PSWRQ2_REG_CDUC_LAST_ILT_RT_OFFSET                      6544
4483 #define PSWRQ2_REG_CDUT_FIRST_ILT_RT_OFFSET                     6545
4484 #define PSWRQ2_REG_CDUT_LAST_ILT_RT_OFFSET                      6546
4485 #define PSWRQ2_REG_TSDM_FIRST_ILT_RT_OFFSET                     6547
4486 #define PSWRQ2_REG_TSDM_LAST_ILT_RT_OFFSET                      6548
4487 #define PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET             6549
4488 #define PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET           6550
4489 #define PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET           6551
4490 #define PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET                       6552
4491 #define PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET                     6553
4492 #define PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET                     6554
4493 #define PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET                   6555
4494 #define PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET                 6556
4495 #define PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET                 6557
4496 #define PSWRQ2_REG_VF_BASE_RT_OFFSET                            6558
4497 #define PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET                        6559
4498 #define PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET                      6560
4499 #define PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET                      6561
4500 #define PSWRQ2_REG_TGSRC_FIRST_ILT_RT_OFFSET                    6562
4501 #define PSWRQ2_REG_RGSRC_FIRST_ILT_RT_OFFSET                    6563
4502 #define PSWRQ2_REG_TGSRC_LAST_ILT_RT_OFFSET                     6564
4503 #define PSWRQ2_REG_RGSRC_LAST_ILT_RT_OFFSET                     6565
4504 #define PSWRQ2_REG_ILT_MEMORY_RT_OFFSET                         6566
4505 #define PSWRQ2_REG_ILT_MEMORY_RT_SIZE                           26414
4506 #define PGLUE_REG_B_VF_BASE_RT_OFFSET                           32980
4507 #define PGLUE_REG_B_MSDM_OFFSET_MASK_B_RT_OFFSET                32981
4508 #define PGLUE_REG_B_MSDM_VF_SHIFT_B_RT_OFFSET                   32982
4509 #define PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET                   32983
4510 #define PGLUE_REG_B_PF_BAR0_SIZE_RT_OFFSET                      32984
4511 #define PGLUE_REG_B_PF_BAR1_SIZE_RT_OFFSET                      32985
4512 #define PGLUE_REG_B_VF_BAR1_SIZE_RT_OFFSET                      32986
4513 #define TM_REG_VF_ENABLE_CONN_RT_OFFSET                         32987
4514 #define TM_REG_PF_ENABLE_CONN_RT_OFFSET                         32988
4515 #define TM_REG_PF_ENABLE_TASK_RT_OFFSET                         32989
4516 #define TM_REG_GROUP_SIZE_RESOLUTION_CONN_RT_OFFSET             32990
4517 #define TM_REG_GROUP_SIZE_RESOLUTION_TASK_RT_OFFSET             32991
4518 #define TM_REG_CONFIG_CONN_MEM_RT_OFFSET                        32992
4519 #define TM_REG_CONFIG_CONN_MEM_RT_SIZE                          416
4520 #define TM_REG_CONFIG_TASK_MEM_RT_OFFSET                        33408
4521 #define TM_REG_CONFIG_TASK_MEM_RT_SIZE                          608
4522 #define QM_REG_MAXPQSIZE_0_RT_OFFSET                            34016
4523 #define QM_REG_MAXPQSIZE_1_RT_OFFSET                            34017
4524 #define QM_REG_MAXPQSIZE_2_RT_OFFSET                            34018
4525 #define QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET                       34019
4526 #define QM_REG_MAXPQSIZETXSEL_1_RT_OFFSET                       34020
4527 #define QM_REG_MAXPQSIZETXSEL_2_RT_OFFSET                       34021
4528 #define QM_REG_MAXPQSIZETXSEL_3_RT_OFFSET                       34022
4529 #define QM_REG_MAXPQSIZETXSEL_4_RT_OFFSET                       34023
4530 #define QM_REG_MAXPQSIZETXSEL_5_RT_OFFSET                       34024
4531 #define QM_REG_MAXPQSIZETXSEL_6_RT_OFFSET                       34025
4532 #define QM_REG_MAXPQSIZETXSEL_7_RT_OFFSET                       34026
4533 #define QM_REG_MAXPQSIZETXSEL_8_RT_OFFSET                       34027
4534 #define QM_REG_MAXPQSIZETXSEL_9_RT_OFFSET                       34028
4535 #define QM_REG_MAXPQSIZETXSEL_10_RT_OFFSET                      34029
4536 #define QM_REG_MAXPQSIZETXSEL_11_RT_OFFSET                      34030
4537 #define QM_REG_MAXPQSIZETXSEL_12_RT_OFFSET                      34031
4538 #define QM_REG_MAXPQSIZETXSEL_13_RT_OFFSET                      34032
4539 #define QM_REG_MAXPQSIZETXSEL_14_RT_OFFSET                      34033
4540 #define QM_REG_MAXPQSIZETXSEL_15_RT_OFFSET                      34034
4541 #define QM_REG_MAXPQSIZETXSEL_16_RT_OFFSET                      34035
4542 #define QM_REG_MAXPQSIZETXSEL_17_RT_OFFSET                      34036
4543 #define QM_REG_MAXPQSIZETXSEL_18_RT_OFFSET                      34037
4544 #define QM_REG_MAXPQSIZETXSEL_19_RT_OFFSET                      34038
4545 #define QM_REG_MAXPQSIZETXSEL_20_RT_OFFSET                      34039
4546 #define QM_REG_MAXPQSIZETXSEL_21_RT_OFFSET                      34040
4547 #define QM_REG_MAXPQSIZETXSEL_22_RT_OFFSET                      34041
4548 #define QM_REG_MAXPQSIZETXSEL_23_RT_OFFSET                      34042
4549 #define QM_REG_MAXPQSIZETXSEL_24_RT_OFFSET                      34043
4550 #define QM_REG_MAXPQSIZETXSEL_25_RT_OFFSET                      34044
4551 #define QM_REG_MAXPQSIZETXSEL_26_RT_OFFSET                      34045
4552 #define QM_REG_MAXPQSIZETXSEL_27_RT_OFFSET                      34046
4553 #define QM_REG_MAXPQSIZETXSEL_28_RT_OFFSET                      34047
4554 #define QM_REG_MAXPQSIZETXSEL_29_RT_OFFSET                      34048
4555 #define QM_REG_MAXPQSIZETXSEL_30_RT_OFFSET                      34049
4556 #define QM_REG_MAXPQSIZETXSEL_31_RT_OFFSET                      34050
4557 #define QM_REG_MAXPQSIZETXSEL_32_RT_OFFSET                      34051
4558 #define QM_REG_MAXPQSIZETXSEL_33_RT_OFFSET                      34052
4559 #define QM_REG_MAXPQSIZETXSEL_34_RT_OFFSET                      34053
4560 #define QM_REG_MAXPQSIZETXSEL_35_RT_OFFSET                      34054
4561 #define QM_REG_MAXPQSIZETXSEL_36_RT_OFFSET                      34055
4562 #define QM_REG_MAXPQSIZETXSEL_37_RT_OFFSET                      34056
4563 #define QM_REG_MAXPQSIZETXSEL_38_RT_OFFSET                      34057
4564 #define QM_REG_MAXPQSIZETXSEL_39_RT_OFFSET                      34058
4565 #define QM_REG_MAXPQSIZETXSEL_40_RT_OFFSET                      34059
4566 #define QM_REG_MAXPQSIZETXSEL_41_RT_OFFSET                      34060
4567 #define QM_REG_MAXPQSIZETXSEL_42_RT_OFFSET                      34061
4568 #define QM_REG_MAXPQSIZETXSEL_43_RT_OFFSET                      34062
4569 #define QM_REG_MAXPQSIZETXSEL_44_RT_OFFSET                      34063
4570 #define QM_REG_MAXPQSIZETXSEL_45_RT_OFFSET                      34064
4571 #define QM_REG_MAXPQSIZETXSEL_46_RT_OFFSET                      34065
4572 #define QM_REG_MAXPQSIZETXSEL_47_RT_OFFSET                      34066
4573 #define QM_REG_MAXPQSIZETXSEL_48_RT_OFFSET                      34067
4574 #define QM_REG_MAXPQSIZETXSEL_49_RT_OFFSET                      34068
4575 #define QM_REG_MAXPQSIZETXSEL_50_RT_OFFSET                      34069
4576 #define QM_REG_MAXPQSIZETXSEL_51_RT_OFFSET                      34070
4577 #define QM_REG_MAXPQSIZETXSEL_52_RT_OFFSET                      34071
4578 #define QM_REG_MAXPQSIZETXSEL_53_RT_OFFSET                      34072
4579 #define QM_REG_MAXPQSIZETXSEL_54_RT_OFFSET                      34073
4580 #define QM_REG_MAXPQSIZETXSEL_55_RT_OFFSET                      34074
4581 #define QM_REG_MAXPQSIZETXSEL_56_RT_OFFSET                      34075
4582 #define QM_REG_MAXPQSIZETXSEL_57_RT_OFFSET                      34076
4583 #define QM_REG_MAXPQSIZETXSEL_58_RT_OFFSET                      34077
4584 #define QM_REG_MAXPQSIZETXSEL_59_RT_OFFSET                      34078
4585 #define QM_REG_MAXPQSIZETXSEL_60_RT_OFFSET                      34079
4586 #define QM_REG_MAXPQSIZETXSEL_61_RT_OFFSET                      34080
4587 #define QM_REG_MAXPQSIZETXSEL_62_RT_OFFSET                      34081
4588 #define QM_REG_MAXPQSIZETXSEL_63_RT_OFFSET                      34082
4589 #define QM_REG_BASEADDROTHERPQ_RT_OFFSET                        34083
4590 #define QM_REG_BASEADDROTHERPQ_RT_SIZE                          128
4591 #define QM_REG_PTRTBLOTHER_RT_OFFSET                            34211
4592 #define QM_REG_PTRTBLOTHER_RT_SIZE                              256
4593 #define QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET                     34467
4594 #define QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET                     34468
4595 #define QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET                      34469
4596 #define QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET                    34470
4597 #define QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET                   34471
4598 #define QM_REG_WRROTHERPQGRP_0_RT_OFFSET                        34472
4599 #define QM_REG_WRROTHERPQGRP_1_RT_OFFSET                        34473
4600 #define QM_REG_WRROTHERPQGRP_2_RT_OFFSET                        34474
4601 #define QM_REG_WRROTHERPQGRP_3_RT_OFFSET                        34475
4602 #define QM_REG_WRROTHERPQGRP_4_RT_OFFSET                        34476
4603 #define QM_REG_WRROTHERPQGRP_5_RT_OFFSET                        34477
4604 #define QM_REG_WRROTHERPQGRP_6_RT_OFFSET                        34478
4605 #define QM_REG_WRROTHERPQGRP_7_RT_OFFSET                        34479
4606 #define QM_REG_WRROTHERPQGRP_8_RT_OFFSET                        34480
4607 #define QM_REG_WRROTHERPQGRP_9_RT_OFFSET                        34481
4608 #define QM_REG_WRROTHERPQGRP_10_RT_OFFSET                       34482
4609 #define QM_REG_WRROTHERPQGRP_11_RT_OFFSET                       34483
4610 #define QM_REG_WRROTHERPQGRP_12_RT_OFFSET                       34484
4611 #define QM_REG_WRROTHERPQGRP_13_RT_OFFSET                       34485
4612 #define QM_REG_WRROTHERPQGRP_14_RT_OFFSET                       34486
4613 #define QM_REG_WRROTHERPQGRP_15_RT_OFFSET                       34487
4614 #define QM_REG_WRROTHERGRPWEIGHT_0_RT_OFFSET                    34488
4615 #define QM_REG_WRROTHERGRPWEIGHT_1_RT_OFFSET                    34489
4616 #define QM_REG_WRROTHERGRPWEIGHT_2_RT_OFFSET                    34490
4617 #define QM_REG_WRROTHERGRPWEIGHT_3_RT_OFFSET                    34491
4618 #define QM_REG_WRRTXGRPWEIGHT_0_RT_OFFSET                       34492
4619 #define QM_REG_WRRTXGRPWEIGHT_1_RT_OFFSET                       34493
4620 #define QM_REG_PQTX2PF_0_RT_OFFSET                              34494
4621 #define QM_REG_PQTX2PF_1_RT_OFFSET                              34495
4622 #define QM_REG_PQTX2PF_2_RT_OFFSET                              34496
4623 #define QM_REG_PQTX2PF_3_RT_OFFSET                              34497
4624 #define QM_REG_PQTX2PF_4_RT_OFFSET                              34498
4625 #define QM_REG_PQTX2PF_5_RT_OFFSET                              34499
4626 #define QM_REG_PQTX2PF_6_RT_OFFSET                              34500
4627 #define QM_REG_PQTX2PF_7_RT_OFFSET                              34501
4628 #define QM_REG_PQTX2PF_8_RT_OFFSET                              34502
4629 #define QM_REG_PQTX2PF_9_RT_OFFSET                              34503
4630 #define QM_REG_PQTX2PF_10_RT_OFFSET                             34504
4631 #define QM_REG_PQTX2PF_11_RT_OFFSET                             34505
4632 #define QM_REG_PQTX2PF_12_RT_OFFSET                             34506
4633 #define QM_REG_PQTX2PF_13_RT_OFFSET                             34507
4634 #define QM_REG_PQTX2PF_14_RT_OFFSET                             34508
4635 #define QM_REG_PQTX2PF_15_RT_OFFSET                             34509
4636 #define QM_REG_PQTX2PF_16_RT_OFFSET                             34510
4637 #define QM_REG_PQTX2PF_17_RT_OFFSET                             34511
4638 #define QM_REG_PQTX2PF_18_RT_OFFSET                             34512
4639 #define QM_REG_PQTX2PF_19_RT_OFFSET                             34513
4640 #define QM_REG_PQTX2PF_20_RT_OFFSET                             34514
4641 #define QM_REG_PQTX2PF_21_RT_OFFSET                             34515
4642 #define QM_REG_PQTX2PF_22_RT_OFFSET                             34516
4643 #define QM_REG_PQTX2PF_23_RT_OFFSET                             34517
4644 #define QM_REG_PQTX2PF_24_RT_OFFSET                             34518
4645 #define QM_REG_PQTX2PF_25_RT_OFFSET                             34519
4646 #define QM_REG_PQTX2PF_26_RT_OFFSET                             34520
4647 #define QM_REG_PQTX2PF_27_RT_OFFSET                             34521
4648 #define QM_REG_PQTX2PF_28_RT_OFFSET                             34522
4649 #define QM_REG_PQTX2PF_29_RT_OFFSET                             34523
4650 #define QM_REG_PQTX2PF_30_RT_OFFSET                             34524
4651 #define QM_REG_PQTX2PF_31_RT_OFFSET                             34525
4652 #define QM_REG_PQTX2PF_32_RT_OFFSET                             34526
4653 #define QM_REG_PQTX2PF_33_RT_OFFSET                             34527
4654 #define QM_REG_PQTX2PF_34_RT_OFFSET                             34528
4655 #define QM_REG_PQTX2PF_35_RT_OFFSET                             34529
4656 #define QM_REG_PQTX2PF_36_RT_OFFSET                             34530
4657 #define QM_REG_PQTX2PF_37_RT_OFFSET                             34531
4658 #define QM_REG_PQTX2PF_38_RT_OFFSET                             34532
4659 #define QM_REG_PQTX2PF_39_RT_OFFSET                             34533
4660 #define QM_REG_PQTX2PF_40_RT_OFFSET                             34534
4661 #define QM_REG_PQTX2PF_41_RT_OFFSET                             34535
4662 #define QM_REG_PQTX2PF_42_RT_OFFSET                             34536
4663 #define QM_REG_PQTX2PF_43_RT_OFFSET                             34537
4664 #define QM_REG_PQTX2PF_44_RT_OFFSET                             34538
4665 #define QM_REG_PQTX2PF_45_RT_OFFSET                             34539
4666 #define QM_REG_PQTX2PF_46_RT_OFFSET                             34540
4667 #define QM_REG_PQTX2PF_47_RT_OFFSET                             34541
4668 #define QM_REG_PQTX2PF_48_RT_OFFSET                             34542
4669 #define QM_REG_PQTX2PF_49_RT_OFFSET                             34543
4670 #define QM_REG_PQTX2PF_50_RT_OFFSET                             34544
4671 #define QM_REG_PQTX2PF_51_RT_OFFSET                             34545
4672 #define QM_REG_PQTX2PF_52_RT_OFFSET                             34546
4673 #define QM_REG_PQTX2PF_53_RT_OFFSET                             34547
4674 #define QM_REG_PQTX2PF_54_RT_OFFSET                             34548
4675 #define QM_REG_PQTX2PF_55_RT_OFFSET                             34549
4676 #define QM_REG_PQTX2PF_56_RT_OFFSET                             34550
4677 #define QM_REG_PQTX2PF_57_RT_OFFSET                             34551
4678 #define QM_REG_PQTX2PF_58_RT_OFFSET                             34552
4679 #define QM_REG_PQTX2PF_59_RT_OFFSET                             34553
4680 #define QM_REG_PQTX2PF_60_RT_OFFSET                             34554
4681 #define QM_REG_PQTX2PF_61_RT_OFFSET                             34555
4682 #define QM_REG_PQTX2PF_62_RT_OFFSET                             34556
4683 #define QM_REG_PQTX2PF_63_RT_OFFSET                             34557
4684 #define QM_REG_PQOTHER2PF_0_RT_OFFSET                           34558
4685 #define QM_REG_PQOTHER2PF_1_RT_OFFSET                           34559
4686 #define QM_REG_PQOTHER2PF_2_RT_OFFSET                           34560
4687 #define QM_REG_PQOTHER2PF_3_RT_OFFSET                           34561
4688 #define QM_REG_PQOTHER2PF_4_RT_OFFSET                           34562
4689 #define QM_REG_PQOTHER2PF_5_RT_OFFSET                           34563
4690 #define QM_REG_PQOTHER2PF_6_RT_OFFSET                           34564
4691 #define QM_REG_PQOTHER2PF_7_RT_OFFSET                           34565
4692 #define QM_REG_PQOTHER2PF_8_RT_OFFSET                           34566
4693 #define QM_REG_PQOTHER2PF_9_RT_OFFSET                           34567
4694 #define QM_REG_PQOTHER2PF_10_RT_OFFSET                          34568
4695 #define QM_REG_PQOTHER2PF_11_RT_OFFSET                          34569
4696 #define QM_REG_PQOTHER2PF_12_RT_OFFSET                          34570
4697 #define QM_REG_PQOTHER2PF_13_RT_OFFSET                          34571
4698 #define QM_REG_PQOTHER2PF_14_RT_OFFSET                          34572
4699 #define QM_REG_PQOTHER2PF_15_RT_OFFSET                          34573
4700 #define QM_REG_RLGLBLPERIOD_0_RT_OFFSET                         34574
4701 #define QM_REG_RLGLBLPERIOD_1_RT_OFFSET                         34575
4702 #define QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET                    34576
4703 #define QM_REG_RLGLBLPERIODTIMER_1_RT_OFFSET                    34577
4704 #define QM_REG_RLGLBLPERIODSEL_0_RT_OFFSET                      34578
4705 #define QM_REG_RLGLBLPERIODSEL_1_RT_OFFSET                      34579
4706 #define QM_REG_RLGLBLPERIODSEL_2_RT_OFFSET                      34580
4707 #define QM_REG_RLGLBLPERIODSEL_3_RT_OFFSET                      34581
4708 #define QM_REG_RLGLBLPERIODSEL_4_RT_OFFSET                      34582
4709 #define QM_REG_RLGLBLPERIODSEL_5_RT_OFFSET                      34583
4710 #define QM_REG_RLGLBLPERIODSEL_6_RT_OFFSET                      34584
4711 #define QM_REG_RLGLBLPERIODSEL_7_RT_OFFSET                      34585
4712 #define QM_REG_RLGLBLINCVAL_RT_OFFSET                           34586
4713 #define QM_REG_RLGLBLINCVAL_RT_SIZE                             256
4714 #define QM_REG_RLGLBLUPPERBOUND_RT_OFFSET                       34842
4715 #define QM_REG_RLGLBLUPPERBOUND_RT_SIZE                         256
4716 #define QM_REG_RLGLBLCRD_RT_OFFSET                              35098
4717 #define QM_REG_RLGLBLCRD_RT_SIZE                                256
4718 #define QM_REG_RLGLBLENABLE_RT_OFFSET                           35354
4719 #define QM_REG_RLPFPERIOD_RT_OFFSET                             35355
4720 #define QM_REG_RLPFPERIODTIMER_RT_OFFSET                        35356
4721 #define QM_REG_RLPFINCVAL_RT_OFFSET                             35357
4722 #define QM_REG_RLPFINCVAL_RT_SIZE                               16
4723 #define QM_REG_RLPFUPPERBOUND_RT_OFFSET                         35373
4724 #define QM_REG_RLPFUPPERBOUND_RT_SIZE                           16
4725 #define QM_REG_RLPFCRD_RT_OFFSET                                35389
4726 #define QM_REG_RLPFCRD_RT_SIZE                                  16
4727 #define QM_REG_RLPFENABLE_RT_OFFSET                             35405
4728 #define QM_REG_RLPFVOQENABLE_RT_OFFSET                          35406
4729 #define QM_REG_WFQPFWEIGHT_RT_OFFSET                            35407
4730 #define QM_REG_WFQPFWEIGHT_RT_SIZE                              16
4731 #define QM_REG_WFQPFUPPERBOUND_RT_OFFSET                        35423
4732 #define QM_REG_WFQPFUPPERBOUND_RT_SIZE                          16
4733 #define QM_REG_WFQPFCRD_RT_OFFSET                               35439
4734 #define QM_REG_WFQPFCRD_RT_SIZE                                 256
4735 #define QM_REG_WFQPFENABLE_RT_OFFSET                            35695
4736 #define QM_REG_WFQVPENABLE_RT_OFFSET                            35696
4737 #define QM_REG_BASEADDRTXPQ_RT_OFFSET                           35697
4738 #define QM_REG_BASEADDRTXPQ_RT_SIZE                             512
4739 #define QM_REG_TXPQMAP_RT_OFFSET                                36209
4740 #define QM_REG_TXPQMAP_RT_SIZE                                  512
4741 #define QM_REG_WFQVPWEIGHT_RT_OFFSET                            36721
4742 #define QM_REG_WFQVPWEIGHT_RT_SIZE                              512
4743 #define QM_REG_WFQVPCRD_RT_OFFSET                               37233
4744 #define QM_REG_WFQVPCRD_RT_SIZE                                 512
4745 #define QM_REG_WFQVPMAP_RT_OFFSET                               37745
4746 #define QM_REG_WFQVPMAP_RT_SIZE                                 512
4747 #define QM_REG_PTRTBLTX_RT_OFFSET                               38257
4748 #define QM_REG_PTRTBLTX_RT_SIZE                                 1024
4749 #define QM_REG_WFQPFCRD_MSB_RT_OFFSET                           39281
4750 #define QM_REG_WFQPFCRD_MSB_RT_SIZE                             320
4751 #define QM_REG_VOQCRDLINE_RT_OFFSET                             39601
4752 #define QM_REG_VOQCRDLINE_RT_SIZE                               36
4753 #define QM_REG_VOQINITCRDLINE_RT_OFFSET                         39637
4754 #define QM_REG_VOQINITCRDLINE_RT_SIZE                           36
4755 #define QM_REG_RLPFVOQENABLE_MSB_RT_OFFSET                      39673
4756 #define NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET                       39674
4757 #define NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET                  39675
4758 #define NIG_REG_OUTER_TAG_VALUE_LIST0_RT_OFFSET                 39676
4759 #define NIG_REG_OUTER_TAG_VALUE_LIST1_RT_OFFSET                 39677
4760 #define NIG_REG_OUTER_TAG_VALUE_LIST2_RT_OFFSET                 39678
4761 #define NIG_REG_OUTER_TAG_VALUE_LIST3_RT_OFFSET                 39679
4762 #define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET              39680
4763 #define NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET                       39681
4764 #define NIG_REG_LLH_FUNC_TAG_EN_RT_SIZE                         4
4765 #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET                    39685
4766 #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_SIZE                      4
4767 #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_OFFSET                 39689
4768 #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_SIZE                   32
4769 #define NIG_REG_LLH_FUNC_FILTER_EN_RT_OFFSET                    39721
4770 #define NIG_REG_LLH_FUNC_FILTER_EN_RT_SIZE                      16
4771 #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_OFFSET                  39737
4772 #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_SIZE                    16
4773 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET         39753
4774 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE           16
4775 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET               39769
4776 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_SIZE                 16
4777 #define NIG_REG_TX_EDPM_CTRL_RT_OFFSET                          39785
4778 #define NIG_REG_ROCE_DUPLICATE_TO_HOST_RT_OFFSET                39786
4779 #define NIG_REG_PPF_TO_ENGINE_SEL_RT_OFFSET                     39787
4780 #define NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE                       8
4781 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_VALUE_RT_OFFSET          39795
4782 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_VALUE_RT_SIZE            1024
4783 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_EN_RT_OFFSET             40819
4784 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_EN_RT_SIZE               512
4785 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_MODE_RT_OFFSET           41331
4786 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_MODE_RT_SIZE             512
4787 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET  41843
4788 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE    512
4789 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_HDR_SEL_RT_OFFSET        42355
4790 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_HDR_SEL_RT_SIZE          512
4791 #define NIG_REG_LLH_PF_CLS_FILTERS_MAP_RT_OFFSET                42867
4792 #define NIG_REG_LLH_PF_CLS_FILTERS_MAP_RT_SIZE                  32
4793 #define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET                       42899
4794 #define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET                       42900
4795 #define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET                       42901
4796 #define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET                   42902
4797 #define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET                   42903
4798 #define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET                   42904
4799 #define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET                   42905
4800 #define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET                42906
4801 #define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET                42907
4802 #define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET                42908
4803 #define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET                42909
4804 #define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET                    42910
4805 #define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET                 42911
4806 #define PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET                       42912
4807 #define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET                  42913
4808 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET                42914
4809 #define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET                   42915
4810 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET            42916
4811 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET                42917
4812 #define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET                   42918
4813 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET            42919
4814 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET                42920
4815 #define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET                   42921
4816 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET            42922
4817 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET                42923
4818 #define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET                   42924
4819 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET            42925
4820 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET                42926
4821 #define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET                   42927
4822 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET            42928
4823 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET                42929
4824 #define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET                   42930
4825 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET            42931
4826 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET                42932
4827 #define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET                   42933
4828 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET            42934
4829 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET                42935
4830 #define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET                   42936
4831 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET            42937
4832 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET                42938
4833 #define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET                   42939
4834 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET            42940
4835 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET                42941
4836 #define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET                   42942
4837 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET            42943
4838 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET               42944
4839 #define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET                  42945
4840 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET           42946
4841 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET               42947
4842 #define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET                  42948
4843 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET           42949
4844 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET               42950
4845 #define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET                  42951
4846 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET           42952
4847 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET               42953
4848 #define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET                  42954
4849 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET           42955
4850 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET               42956
4851 #define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET                  42957
4852 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET           42958
4853 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET               42959
4854 #define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET                  42960
4855 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET           42961
4856 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET               42962
4857 #define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET                  42963
4858 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET           42964
4859 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET               42965
4860 #define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET                  42966
4861 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET           42967
4862 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET               42968
4863 #define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET                  42969
4864 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET           42970
4865 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET               42971
4866 #define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET                  42972
4867 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET           42973
4868 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ20_RT_OFFSET               42974
4869 #define PBF_REG_BTB_GUARANTEED_VOQ20_RT_OFFSET                  42975
4870 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ20_RT_OFFSET           42976
4871 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ21_RT_OFFSET               42977
4872 #define PBF_REG_BTB_GUARANTEED_VOQ21_RT_OFFSET                  42978
4873 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ21_RT_OFFSET           42979
4874 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ22_RT_OFFSET               42980
4875 #define PBF_REG_BTB_GUARANTEED_VOQ22_RT_OFFSET                  42981
4876 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ22_RT_OFFSET           42982
4877 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ23_RT_OFFSET               42983
4878 #define PBF_REG_BTB_GUARANTEED_VOQ23_RT_OFFSET                  42984
4879 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ23_RT_OFFSET           42985
4880 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ24_RT_OFFSET               42986
4881 #define PBF_REG_BTB_GUARANTEED_VOQ24_RT_OFFSET                  42987
4882 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ24_RT_OFFSET           42988
4883 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ25_RT_OFFSET               42989
4884 #define PBF_REG_BTB_GUARANTEED_VOQ25_RT_OFFSET                  42990
4885 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ25_RT_OFFSET           42991
4886 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ26_RT_OFFSET               42992
4887 #define PBF_REG_BTB_GUARANTEED_VOQ26_RT_OFFSET                  42993
4888 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ26_RT_OFFSET           42994
4889 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ27_RT_OFFSET               42995
4890 #define PBF_REG_BTB_GUARANTEED_VOQ27_RT_OFFSET                  42996
4891 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ27_RT_OFFSET           42997
4892 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ28_RT_OFFSET               42998
4893 #define PBF_REG_BTB_GUARANTEED_VOQ28_RT_OFFSET                  42999
4894 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ28_RT_OFFSET           43000
4895 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ29_RT_OFFSET               43001
4896 #define PBF_REG_BTB_GUARANTEED_VOQ29_RT_OFFSET                  43002
4897 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ29_RT_OFFSET           43003
4898 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ30_RT_OFFSET               43004
4899 #define PBF_REG_BTB_GUARANTEED_VOQ30_RT_OFFSET                  43005
4900 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ30_RT_OFFSET           43006
4901 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ31_RT_OFFSET               43007
4902 #define PBF_REG_BTB_GUARANTEED_VOQ31_RT_OFFSET                  43008
4903 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ31_RT_OFFSET           43009
4904 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ32_RT_OFFSET               43010
4905 #define PBF_REG_BTB_GUARANTEED_VOQ32_RT_OFFSET                  43011
4906 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ32_RT_OFFSET           43012
4907 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ33_RT_OFFSET               43013
4908 #define PBF_REG_BTB_GUARANTEED_VOQ33_RT_OFFSET                  43014
4909 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ33_RT_OFFSET           43015
4910 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ34_RT_OFFSET               43016
4911 #define PBF_REG_BTB_GUARANTEED_VOQ34_RT_OFFSET                  43017
4912 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ34_RT_OFFSET           43018
4913 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ35_RT_OFFSET               43019
4914 #define PBF_REG_BTB_GUARANTEED_VOQ35_RT_OFFSET                  43020
4915 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ35_RT_OFFSET           43021
4916 #define XCM_REG_CON_PHY_Q3_RT_OFFSET                            43022
4917
4918 #define RUNTIME_ARRAY_SIZE      43023
4919
4920 /* Init Callbacks */
4921 #define DMAE_READY_CB   0
4922
4923 /* The eth storm context for the Tstorm */
4924 struct tstorm_eth_conn_st_ctx {
4925         __le32 reserved[4];
4926 };
4927
4928 /* The eth storm context for the Pstorm */
4929 struct pstorm_eth_conn_st_ctx {
4930         __le32 reserved[8];
4931 };
4932
4933 /* The eth storm context for the Xstorm */
4934 struct xstorm_eth_conn_st_ctx {
4935         __le32 reserved[60];
4936 };
4937
4938 struct e4_xstorm_eth_conn_ag_ctx {
4939         u8 reserved0;
4940         u8 state;
4941         u8 flags0;
4942 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK     0x1
4943 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT    0
4944 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK        0x1
4945 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED1_SHIFT       1
4946 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK        0x1
4947 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED2_SHIFT       2
4948 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK     0x1
4949 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_SHIFT    3
4950 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK        0x1
4951 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED3_SHIFT       4
4952 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK        0x1
4953 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED4_SHIFT       5
4954 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK        0x1
4955 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED5_SHIFT       6
4956 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK        0x1
4957 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED6_SHIFT       7
4958                 u8 flags1;
4959 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK        0x1
4960 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED7_SHIFT       0
4961 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK        0x1
4962 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED8_SHIFT       1
4963 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED9_MASK        0x1
4964 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED9_SHIFT       2
4965 #define E4_XSTORM_ETH_CONN_AG_CTX_BIT11_MASK            0x1
4966 #define E4_XSTORM_ETH_CONN_AG_CTX_BIT11_SHIFT           3
4967 #define E4_XSTORM_ETH_CONN_AG_CTX_E5_RESERVED2_MASK     0x1
4968 #define E4_XSTORM_ETH_CONN_AG_CTX_E5_RESERVED2_SHIFT    4
4969 #define E4_XSTORM_ETH_CONN_AG_CTX_E5_RESERVED3_MASK     0x1
4970 #define E4_XSTORM_ETH_CONN_AG_CTX_E5_RESERVED3_SHIFT    5
4971 #define E4_XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_MASK   0x1
4972 #define E4_XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT  6
4973 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_MASK     0x1
4974 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT    7
4975         u8 flags2;
4976 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0_MASK      0x3
4977 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0_SHIFT     0
4978 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1_MASK      0x3
4979 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1_SHIFT     2
4980 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2_MASK      0x3
4981 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2_SHIFT     4
4982 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3_MASK      0x3
4983 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3_SHIFT     6
4984         u8 flags3;
4985 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4_MASK      0x3
4986 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4_SHIFT     0
4987 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5_MASK      0x3
4988 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5_SHIFT     2
4989 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6_MASK      0x3
4990 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6_SHIFT     4
4991 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7_MASK      0x3
4992 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7_SHIFT     6
4993                 u8 flags4;
4994 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8_MASK      0x3
4995 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8_SHIFT     0
4996 #define E4_XSTORM_ETH_CONN_AG_CTX_CF9_MASK      0x3
4997 #define E4_XSTORM_ETH_CONN_AG_CTX_CF9_SHIFT     2
4998 #define E4_XSTORM_ETH_CONN_AG_CTX_CF10_MASK     0x3
4999 #define E4_XSTORM_ETH_CONN_AG_CTX_CF10_SHIFT    4
5000 #define E4_XSTORM_ETH_CONN_AG_CTX_CF11_MASK     0x3
5001 #define E4_XSTORM_ETH_CONN_AG_CTX_CF11_SHIFT    6
5002         u8 flags5;
5003 #define E4_XSTORM_ETH_CONN_AG_CTX_CF12_MASK     0x3
5004 #define E4_XSTORM_ETH_CONN_AG_CTX_CF12_SHIFT    0
5005 #define E4_XSTORM_ETH_CONN_AG_CTX_CF13_MASK     0x3
5006 #define E4_XSTORM_ETH_CONN_AG_CTX_CF13_SHIFT    2
5007 #define E4_XSTORM_ETH_CONN_AG_CTX_CF14_MASK     0x3
5008 #define E4_XSTORM_ETH_CONN_AG_CTX_CF14_SHIFT    4
5009 #define E4_XSTORM_ETH_CONN_AG_CTX_CF15_MASK     0x3
5010 #define E4_XSTORM_ETH_CONN_AG_CTX_CF15_SHIFT    6
5011         u8 flags6;
5012 #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK         0x3
5013 #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT        0
5014 #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_MASK         0x3
5015 #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT        2
5016 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_MASK                    0x3
5017 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_SHIFT                   4
5018 #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_MASK             0x3
5019 #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_SHIFT            6
5020         u8 flags7;
5021 #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_MASK         0x3
5022 #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_SHIFT        0
5023 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED10_MASK       0x3
5024 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED10_SHIFT      2
5025 #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_MASK        0x3
5026 #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_SHIFT       4
5027 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0EN_MASK            0x1
5028 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT           6
5029 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1EN_MASK            0x1
5030 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT           7
5031         u8 flags8;
5032 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2EN_MASK    0x1
5033 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT   0
5034 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3EN_MASK    0x1
5035 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT   1
5036 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4EN_MASK    0x1
5037 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT   2
5038 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5EN_MASK    0x1
5039 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT   3
5040 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6EN_MASK    0x1
5041 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT   4
5042 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7EN_MASK    0x1
5043 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT   5
5044 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8EN_MASK    0x1
5045 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT   6
5046 #define E4_XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK    0x1
5047 #define E4_XSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT   7
5048         u8 flags9;
5049 #define E4_XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK                   0x1
5050 #define E4_XSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT                  0
5051 #define E4_XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK                   0x1
5052 #define E4_XSTORM_ETH_CONN_AG_CTX_CF11EN_SHIFT                  1
5053 #define E4_XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK                   0x1
5054 #define E4_XSTORM_ETH_CONN_AG_CTX_CF12EN_SHIFT                  2
5055 #define E4_XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK                   0x1
5056 #define E4_XSTORM_ETH_CONN_AG_CTX_CF13EN_SHIFT                  3
5057 #define E4_XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK                   0x1
5058 #define E4_XSTORM_ETH_CONN_AG_CTX_CF14EN_SHIFT                  4
5059 #define E4_XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK                   0x1
5060 #define E4_XSTORM_ETH_CONN_AG_CTX_CF15EN_SHIFT                  5
5061 #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK      0x1
5062 #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT     6
5063 #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK      0x1
5064 #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT     7
5065         u8 flags10;
5066 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK                 0x1
5067 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_SHIFT                0
5068 #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK          0x1
5069 #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT         1
5070 #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK              0x1
5071 #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT             2
5072 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK               0x1
5073 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED11_SHIFT              3
5074 #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK             0x1
5075 #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_SHIFT            4
5076 #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK   0x1
5077 #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT  5
5078 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK               0x1
5079 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED12_SHIFT              6
5080 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK               0x1
5081 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED13_SHIFT              7
5082         u8 flags11;
5083 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK       0x1
5084 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED14_SHIFT      0
5085 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED15_MASK       0x1
5086 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED15_SHIFT      1
5087 #define E4_XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_MASK   0x1
5088 #define E4_XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT  2
5089 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK          0x1
5090 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT         3
5091 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE6EN_MASK          0x1
5092 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT         4
5093 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK          0x1
5094 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT         5
5095 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_MASK     0x1
5096 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_SHIFT    6
5097 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE9EN_MASK          0x1
5098 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE9EN_SHIFT         7
5099         u8 flags12;
5100 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE10EN_MASK         0x1
5101 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE10EN_SHIFT        0
5102 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE11EN_MASK         0x1
5103 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE11EN_SHIFT        1
5104 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_MASK     0x1
5105 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_SHIFT    2
5106 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_MASK     0x1
5107 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_SHIFT    3
5108 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE14EN_MASK         0x1
5109 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE14EN_SHIFT        4
5110 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE15EN_MASK         0x1
5111 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE15EN_SHIFT        5
5112 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE16EN_MASK         0x1
5113 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE16EN_SHIFT        6
5114 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE17EN_MASK         0x1
5115 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE17EN_SHIFT        7
5116         u8 flags13;
5117 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE18EN_MASK         0x1
5118 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE18EN_SHIFT        0
5119 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE19EN_MASK         0x1
5120 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE19EN_SHIFT        1
5121 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_MASK     0x1
5122 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_SHIFT    2
5123 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_MASK     0x1
5124 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_SHIFT    3
5125 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_MASK     0x1
5126 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_SHIFT    4
5127 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_MASK     0x1
5128 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_SHIFT    5
5129 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_MASK     0x1
5130 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_SHIFT    6
5131 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK     0x1
5132 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_SHIFT    7
5133         u8 flags14;
5134 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK         0x1
5135 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT        0
5136 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK       0x1
5137 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT      1
5138 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK     0x1
5139 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT    2
5140 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK     0x1
5141 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT    3
5142 #define E4_XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK           0x1
5143 #define E4_XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT          4
5144 #define E4_XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK         0x1
5145 #define E4_XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT        5
5146 #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK               0x3
5147 #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_SHIFT              6
5148         u8 edpm_event_id;
5149         __le16 physical_q0;
5150         __le16 e5_reserved1;
5151         __le16 edpm_num_bds;
5152         __le16 tx_bd_cons;
5153         __le16 tx_bd_prod;
5154         __le16 tx_class;
5155         __le16 conn_dpi;
5156         u8 byte3;
5157         u8 byte4;
5158         u8 byte5;
5159         u8 byte6;
5160         __le32 reg0;
5161         __le32 reg1;
5162         __le32 reg2;
5163         __le32 reg3;
5164         __le32 reg4;
5165         __le32 reg5;
5166         __le32 reg6;
5167         __le16 word7;
5168         __le16 word8;
5169         __le16 word9;
5170         __le16 word10;
5171         __le32 reg7;
5172         __le32 reg8;
5173         __le32 reg9;
5174         u8 byte7;
5175         u8 byte8;
5176         u8 byte9;
5177         u8 byte10;
5178         u8 byte11;
5179         u8 byte12;
5180         u8 byte13;
5181         u8 byte14;
5182         u8 byte15;
5183         u8 e5_reserved;
5184         __le16 word11;
5185         __le32 reg10;
5186         __le32 reg11;
5187         __le32 reg12;
5188         __le32 reg13;
5189         __le32 reg14;
5190         __le32 reg15;
5191         __le32 reg16;
5192         __le32 reg17;
5193         __le32 reg18;
5194         __le32 reg19;
5195         __le16 word12;
5196         __le16 word13;
5197         __le16 word14;
5198         __le16 word15;
5199 };
5200
5201 /* The eth storm context for the Ystorm */
5202 struct ystorm_eth_conn_st_ctx {
5203         __le32 reserved[8];
5204 };
5205
5206 struct e4_ystorm_eth_conn_ag_ctx {
5207         u8 byte0;
5208         u8 state;
5209         u8 flags0;
5210 #define E4_YSTORM_ETH_CONN_AG_CTX_BIT0_MASK                     0x1
5211 #define E4_YSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT                    0
5212 #define E4_YSTORM_ETH_CONN_AG_CTX_BIT1_MASK                     0x1
5213 #define E4_YSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT                    1
5214 #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK        0x3
5215 #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT       2
5216 #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_MASK         0x3
5217 #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_SHIFT        4
5218 #define E4_YSTORM_ETH_CONN_AG_CTX_CF2_MASK                      0x3
5219 #define E4_YSTORM_ETH_CONN_AG_CTX_CF2_SHIFT                     6
5220         u8 flags1;
5221 #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK     0x1
5222 #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT    0
5223 #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_MASK      0x1
5224 #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_SHIFT     1
5225 #define E4_YSTORM_ETH_CONN_AG_CTX_CF2EN_MASK                    0x1
5226 #define E4_YSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT                   2
5227 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK                  0x1
5228 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT                 3
5229 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK                  0x1
5230 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT                 4
5231 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK                  0x1
5232 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT                 5
5233 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK                  0x1
5234 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT                 6
5235 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK                  0x1
5236 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT                 7
5237         u8 tx_q0_int_coallecing_timeset;
5238         u8 byte3;
5239         __le16 word0;
5240         __le32 terminate_spqe;
5241         __le32 reg1;
5242         __le16 tx_bd_cons_upd;
5243         __le16 word2;
5244         __le16 word3;
5245         __le16 word4;
5246         __le32 reg2;
5247         __le32 reg3;
5248 };
5249
5250 struct e4_tstorm_eth_conn_ag_ctx {
5251         u8 byte0;
5252         u8 byte1;
5253         u8 flags0;
5254 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT0_MASK     0x1
5255 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT    0
5256 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT1_MASK     0x1
5257 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT    1
5258 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT2_MASK     0x1
5259 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT2_SHIFT    2
5260 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT3_MASK     0x1
5261 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT3_SHIFT    3
5262 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT4_MASK     0x1
5263 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT4_SHIFT    4
5264 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT5_MASK     0x1
5265 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT5_SHIFT    5
5266 #define E4_TSTORM_ETH_CONN_AG_CTX_CF0_MASK      0x3
5267 #define E4_TSTORM_ETH_CONN_AG_CTX_CF0_SHIFT     6
5268         u8 flags1;
5269 #define E4_TSTORM_ETH_CONN_AG_CTX_CF1_MASK      0x3
5270 #define E4_TSTORM_ETH_CONN_AG_CTX_CF1_SHIFT     0
5271 #define E4_TSTORM_ETH_CONN_AG_CTX_CF2_MASK      0x3
5272 #define E4_TSTORM_ETH_CONN_AG_CTX_CF2_SHIFT     2
5273 #define E4_TSTORM_ETH_CONN_AG_CTX_CF3_MASK      0x3
5274 #define E4_TSTORM_ETH_CONN_AG_CTX_CF3_SHIFT     4
5275 #define E4_TSTORM_ETH_CONN_AG_CTX_CF4_MASK      0x3
5276 #define E4_TSTORM_ETH_CONN_AG_CTX_CF4_SHIFT     6
5277         u8 flags2;
5278 #define E4_TSTORM_ETH_CONN_AG_CTX_CF5_MASK      0x3
5279 #define E4_TSTORM_ETH_CONN_AG_CTX_CF5_SHIFT     0
5280 #define E4_TSTORM_ETH_CONN_AG_CTX_CF6_MASK      0x3
5281 #define E4_TSTORM_ETH_CONN_AG_CTX_CF6_SHIFT     2
5282 #define E4_TSTORM_ETH_CONN_AG_CTX_CF7_MASK      0x3
5283 #define E4_TSTORM_ETH_CONN_AG_CTX_CF7_SHIFT     4
5284 #define E4_TSTORM_ETH_CONN_AG_CTX_CF8_MASK      0x3
5285 #define E4_TSTORM_ETH_CONN_AG_CTX_CF8_SHIFT     6
5286         u8 flags3;
5287 #define E4_TSTORM_ETH_CONN_AG_CTX_CF9_MASK      0x3
5288 #define E4_TSTORM_ETH_CONN_AG_CTX_CF9_SHIFT     0
5289 #define E4_TSTORM_ETH_CONN_AG_CTX_CF10_MASK     0x3
5290 #define E4_TSTORM_ETH_CONN_AG_CTX_CF10_SHIFT    2
5291 #define E4_TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK    0x1
5292 #define E4_TSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT   4
5293 #define E4_TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK    0x1
5294 #define E4_TSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT   5
5295 #define E4_TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK    0x1
5296 #define E4_TSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT   6
5297 #define E4_TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK    0x1
5298 #define E4_TSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT   7
5299         u8 flags4;
5300 #define E4_TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK    0x1
5301 #define E4_TSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT   0
5302 #define E4_TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK    0x1
5303 #define E4_TSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT   1
5304 #define E4_TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK    0x1
5305 #define E4_TSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT   2
5306 #define E4_TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK    0x1
5307 #define E4_TSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT   3
5308 #define E4_TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK    0x1
5309 #define E4_TSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT   4
5310 #define E4_TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK    0x1
5311 #define E4_TSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT   5
5312 #define E4_TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK   0x1
5313 #define E4_TSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT  6
5314 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK  0x1
5315 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7
5316         u8 flags5;
5317 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK          0x1
5318 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT         0
5319 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK          0x1
5320 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT         1
5321 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK          0x1
5322 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT         2
5323 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK          0x1
5324 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT         3
5325 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK          0x1
5326 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT         4
5327 #define E4_TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK         0x1
5328 #define E4_TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_SHIFT        5
5329 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK          0x1
5330 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT         6
5331 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK          0x1
5332 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT         7
5333         __le32 reg0;
5334         __le32 reg1;
5335         __le32 reg2;
5336         __le32 reg3;
5337         __le32 reg4;
5338         __le32 reg5;
5339         __le32 reg6;
5340         __le32 reg7;
5341         __le32 reg8;
5342         u8 byte2;
5343         u8 byte3;
5344         __le16 rx_bd_cons;
5345         u8 byte4;
5346         u8 byte5;
5347         __le16 rx_bd_prod;
5348         __le16 word2;
5349         __le16 word3;
5350         __le32 reg9;
5351         __le32 reg10;
5352 };
5353
5354 struct e4_ustorm_eth_conn_ag_ctx {
5355         u8 byte0;
5356         u8 byte1;
5357         u8 flags0;
5358 #define E4_USTORM_ETH_CONN_AG_CTX_BIT0_MASK                     0x1
5359 #define E4_USTORM_ETH_CONN_AG_CTX_BIT0_SHIFT                    0
5360 #define E4_USTORM_ETH_CONN_AG_CTX_BIT1_MASK                     0x1
5361 #define E4_USTORM_ETH_CONN_AG_CTX_BIT1_SHIFT                    1
5362 #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_MASK      0x3
5363 #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_SHIFT     2
5364 #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_MASK      0x3
5365 #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_SHIFT     4
5366 #define E4_USTORM_ETH_CONN_AG_CTX_CF2_MASK                      0x3
5367 #define E4_USTORM_ETH_CONN_AG_CTX_CF2_SHIFT                     6
5368         u8 flags1;
5369 #define E4_USTORM_ETH_CONN_AG_CTX_CF3_MASK                      0x3
5370 #define E4_USTORM_ETH_CONN_AG_CTX_CF3_SHIFT                     0
5371 #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK                0x3
5372 #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_SHIFT               2
5373 #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK                0x3
5374 #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_SHIFT               4
5375 #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK        0x3
5376 #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT       6
5377         u8 flags2;
5378 #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_MASK   0x1
5379 #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_SHIFT  0
5380 #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_MASK   0x1
5381 #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_SHIFT  1
5382 #define E4_USTORM_ETH_CONN_AG_CTX_CF2EN_MASK                    0x1
5383 #define E4_USTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT                   2
5384 #define E4_USTORM_ETH_CONN_AG_CTX_CF3EN_MASK                    0x1
5385 #define E4_USTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT                   3
5386 #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_MASK             0x1
5387 #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_SHIFT            4
5388 #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_MASK             0x1
5389 #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_SHIFT            5
5390 #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK     0x1
5391 #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT    6
5392 #define E4_USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK                  0x1
5393 #define E4_USTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT                 7
5394         u8 flags3;
5395 #define E4_USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK  0x1
5396 #define E4_USTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0
5397 #define E4_USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK  0x1
5398 #define E4_USTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1
5399 #define E4_USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK  0x1
5400 #define E4_USTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2
5401 #define E4_USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK  0x1
5402 #define E4_USTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3
5403 #define E4_USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK  0x1
5404 #define E4_USTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4
5405 #define E4_USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK  0x1
5406 #define E4_USTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 5
5407 #define E4_USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK  0x1
5408 #define E4_USTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6
5409 #define E4_USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK  0x1
5410 #define E4_USTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7
5411         u8 byte2;
5412         u8 byte3;
5413         __le16 word0;
5414         __le16 tx_bd_cons;
5415         __le32 reg0;
5416         __le32 reg1;
5417         __le32 reg2;
5418         __le32 tx_int_coallecing_timeset;
5419         __le16 tx_drv_bd_cons;
5420         __le16 rx_drv_cqe_cons;
5421 };
5422
5423 /* The eth storm context for the Ustorm */
5424 struct ustorm_eth_conn_st_ctx {
5425         __le32 reserved[40];
5426 };
5427
5428 /* The eth storm context for the Mstorm */
5429 struct mstorm_eth_conn_st_ctx {
5430         __le32 reserved[8];
5431 };
5432
5433 /* eth connection context */
5434 struct e4_eth_conn_context {
5435         struct tstorm_eth_conn_st_ctx tstorm_st_context;
5436         struct regpair tstorm_st_padding[2];
5437         struct pstorm_eth_conn_st_ctx pstorm_st_context;
5438         struct xstorm_eth_conn_st_ctx xstorm_st_context;
5439         struct e4_xstorm_eth_conn_ag_ctx xstorm_ag_context;
5440         struct ystorm_eth_conn_st_ctx ystorm_st_context;
5441         struct e4_ystorm_eth_conn_ag_ctx ystorm_ag_context;
5442         struct e4_tstorm_eth_conn_ag_ctx tstorm_ag_context;
5443         struct e4_ustorm_eth_conn_ag_ctx ustorm_ag_context;
5444         struct ustorm_eth_conn_st_ctx ustorm_st_context;
5445         struct mstorm_eth_conn_st_ctx mstorm_st_context;
5446 };
5447
5448 /* Ethernet filter types: mac/vlan/pair */
5449 enum eth_error_code {
5450         ETH_OK = 0x00,
5451         ETH_FILTERS_MAC_ADD_FAIL_FULL,
5452         ETH_FILTERS_MAC_ADD_FAIL_FULL_MTT2,
5453         ETH_FILTERS_MAC_ADD_FAIL_DUP_MTT2,
5454         ETH_FILTERS_MAC_ADD_FAIL_DUP_STT2,
5455         ETH_FILTERS_MAC_DEL_FAIL_NOF,
5456         ETH_FILTERS_MAC_DEL_FAIL_NOF_MTT2,
5457         ETH_FILTERS_MAC_DEL_FAIL_NOF_STT2,
5458         ETH_FILTERS_MAC_ADD_FAIL_ZERO_MAC,
5459         ETH_FILTERS_VLAN_ADD_FAIL_FULL,
5460         ETH_FILTERS_VLAN_ADD_FAIL_DUP,
5461         ETH_FILTERS_VLAN_DEL_FAIL_NOF,
5462         ETH_FILTERS_VLAN_DEL_FAIL_NOF_TT1,
5463         ETH_FILTERS_PAIR_ADD_FAIL_DUP,
5464         ETH_FILTERS_PAIR_ADD_FAIL_FULL,
5465         ETH_FILTERS_PAIR_ADD_FAIL_FULL_MAC,
5466         ETH_FILTERS_PAIR_DEL_FAIL_NOF,
5467         ETH_FILTERS_PAIR_DEL_FAIL_NOF_TT1,
5468         ETH_FILTERS_PAIR_ADD_FAIL_ZERO_MAC,
5469         ETH_FILTERS_VNI_ADD_FAIL_FULL,
5470         ETH_FILTERS_VNI_ADD_FAIL_DUP,
5471         ETH_FILTERS_GFT_UPDATE_FAIL,
5472         MAX_ETH_ERROR_CODE
5473 };
5474
5475 /* Opcodes for the event ring */
5476 enum eth_event_opcode {
5477         ETH_EVENT_UNUSED,
5478         ETH_EVENT_VPORT_START,
5479         ETH_EVENT_VPORT_UPDATE,
5480         ETH_EVENT_VPORT_STOP,
5481         ETH_EVENT_TX_QUEUE_START,
5482         ETH_EVENT_TX_QUEUE_STOP,
5483         ETH_EVENT_RX_QUEUE_START,
5484         ETH_EVENT_RX_QUEUE_UPDATE,
5485         ETH_EVENT_RX_QUEUE_STOP,
5486         ETH_EVENT_FILTERS_UPDATE,
5487         ETH_EVENT_RX_ADD_OPENFLOW_FILTER,
5488         ETH_EVENT_RX_DELETE_OPENFLOW_FILTER,
5489         ETH_EVENT_RX_CREATE_OPENFLOW_ACTION,
5490         ETH_EVENT_RX_ADD_UDP_FILTER,
5491         ETH_EVENT_RX_DELETE_UDP_FILTER,
5492         ETH_EVENT_RX_CREATE_GFT_ACTION,
5493         ETH_EVENT_RX_GFT_UPDATE_FILTER,
5494         ETH_EVENT_TX_QUEUE_UPDATE,
5495         MAX_ETH_EVENT_OPCODE
5496 };
5497
5498 /* Classify rule types in E2/E3 */
5499 enum eth_filter_action {
5500         ETH_FILTER_ACTION_UNUSED,
5501         ETH_FILTER_ACTION_REMOVE,
5502         ETH_FILTER_ACTION_ADD,
5503         ETH_FILTER_ACTION_REMOVE_ALL,
5504         MAX_ETH_FILTER_ACTION
5505 };
5506
5507 /* Command for adding/removing a classification rule $$KEEP_ENDIANNESS$$ */
5508 struct eth_filter_cmd {
5509         u8 type;
5510         u8 vport_id;
5511         u8 action;
5512         u8 reserved0;
5513         __le32 vni;
5514         __le16 mac_lsb;
5515         __le16 mac_mid;
5516         __le16 mac_msb;
5517         __le16 vlan_id;
5518 };
5519
5520 /*      $$KEEP_ENDIANNESS$$ */
5521 struct eth_filter_cmd_header {
5522         u8 rx;
5523         u8 tx;
5524         u8 cmd_cnt;
5525         u8 assert_on_error;
5526         u8 reserved1[4];
5527 };
5528
5529 /* Ethernet filter types: mac/vlan/pair */
5530 enum eth_filter_type {
5531         ETH_FILTER_TYPE_UNUSED,
5532         ETH_FILTER_TYPE_MAC,
5533         ETH_FILTER_TYPE_VLAN,
5534         ETH_FILTER_TYPE_PAIR,
5535         ETH_FILTER_TYPE_INNER_MAC,
5536         ETH_FILTER_TYPE_INNER_VLAN,
5537         ETH_FILTER_TYPE_INNER_PAIR,
5538         ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR,
5539         ETH_FILTER_TYPE_MAC_VNI_PAIR,
5540         ETH_FILTER_TYPE_VNI,
5541         MAX_ETH_FILTER_TYPE
5542 };
5543
5544 /* Eth IPv4 Fragment Type */
5545 enum eth_ipv4_frag_type {
5546         ETH_IPV4_NOT_FRAG,
5547         ETH_IPV4_FIRST_FRAG,
5548         ETH_IPV4_NON_FIRST_FRAG,
5549         MAX_ETH_IPV4_FRAG_TYPE
5550 };
5551
5552 /* eth IPv4 Fragment Type */
5553 enum eth_ip_type {
5554         ETH_IPV4,
5555         ETH_IPV6,
5556         MAX_ETH_IP_TYPE
5557 };
5558
5559 /* Ethernet Ramrod Command IDs */
5560 enum eth_ramrod_cmd_id {
5561         ETH_RAMROD_UNUSED,
5562         ETH_RAMROD_VPORT_START,
5563         ETH_RAMROD_VPORT_UPDATE,
5564         ETH_RAMROD_VPORT_STOP,
5565         ETH_RAMROD_RX_QUEUE_START,
5566         ETH_RAMROD_RX_QUEUE_STOP,
5567         ETH_RAMROD_TX_QUEUE_START,
5568         ETH_RAMROD_TX_QUEUE_STOP,
5569         ETH_RAMROD_FILTERS_UPDATE,
5570         ETH_RAMROD_RX_QUEUE_UPDATE,
5571         ETH_RAMROD_RX_CREATE_OPENFLOW_ACTION,
5572         ETH_RAMROD_RX_ADD_OPENFLOW_FILTER,
5573         ETH_RAMROD_RX_DELETE_OPENFLOW_FILTER,
5574         ETH_RAMROD_RX_ADD_UDP_FILTER,
5575         ETH_RAMROD_RX_DELETE_UDP_FILTER,
5576         ETH_RAMROD_RX_CREATE_GFT_ACTION,
5577         ETH_RAMROD_GFT_UPDATE_FILTER,
5578         ETH_RAMROD_TX_QUEUE_UPDATE,
5579         MAX_ETH_RAMROD_CMD_ID
5580 };
5581
5582 /* Return code from eth sp ramrods */
5583 struct eth_return_code {
5584         u8 value;
5585 #define ETH_RETURN_CODE_ERR_CODE_MASK   0x1F
5586 #define ETH_RETURN_CODE_ERR_CODE_SHIFT  0
5587 #define ETH_RETURN_CODE_RESERVED_MASK   0x3
5588 #define ETH_RETURN_CODE_RESERVED_SHIFT  5
5589 #define ETH_RETURN_CODE_RX_TX_MASK      0x1
5590 #define ETH_RETURN_CODE_RX_TX_SHIFT     7
5591 };
5592
5593 /* What to do in case an error occurs */
5594 enum eth_tx_err {
5595         ETH_TX_ERR_DROP,
5596         ETH_TX_ERR_ASSERT_MALICIOUS,
5597         MAX_ETH_TX_ERR
5598 };
5599
5600 /* Array of the different error type behaviors */
5601 struct eth_tx_err_vals {
5602         __le16 values;
5603 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_MASK                  0x1
5604 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_SHIFT                 0
5605 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_MASK                   0x1
5606 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_SHIFT                  1
5607 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_MASK                  0x1
5608 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_SHIFT                 2
5609 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_MASK                0x1
5610 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_SHIFT               3
5611 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_MASK        0x1
5612 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_SHIFT       4
5613 #define ETH_TX_ERR_VALS_MTU_VIOLATION_MASK                      0x1
5614 #define ETH_TX_ERR_VALS_MTU_VIOLATION_SHIFT                     5
5615 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_MASK              0x1
5616 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_SHIFT             6
5617 #define ETH_TX_ERR_VALS_RESERVED_MASK                           0x1FF
5618 #define ETH_TX_ERR_VALS_RESERVED_SHIFT                          7
5619 };
5620
5621 /* vport rss configuration data */
5622 struct eth_vport_rss_config {
5623         __le16 capabilities;
5624 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_MASK               0x1
5625 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_SHIFT              0
5626 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_MASK               0x1
5627 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_SHIFT              1
5628 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_MASK           0x1
5629 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_SHIFT          2
5630 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_MASK           0x1
5631 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_SHIFT          3
5632 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_MASK           0x1
5633 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_SHIFT          4
5634 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_MASK           0x1
5635 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_SHIFT          5
5636 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_MASK         0x1
5637 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_SHIFT        6
5638 #define ETH_VPORT_RSS_CONFIG_RESERVED0_MASK                     0x1FF
5639 #define ETH_VPORT_RSS_CONFIG_RESERVED0_SHIFT                    7
5640         u8 rss_id;
5641         u8 rss_mode;
5642         u8 update_rss_key;
5643         u8 update_rss_ind_table;
5644         u8 update_rss_capabilities;
5645         u8 tbl_size;
5646         __le32 reserved2[2];
5647         __le16 indirection_table[ETH_RSS_IND_TABLE_ENTRIES_NUM];
5648
5649         __le32 rss_key[ETH_RSS_KEY_SIZE_REGS];
5650         __le32 reserved3[2];
5651 };
5652
5653 /* eth vport RSS mode */
5654 enum eth_vport_rss_mode {
5655         ETH_VPORT_RSS_MODE_DISABLED,
5656         ETH_VPORT_RSS_MODE_REGULAR,
5657         MAX_ETH_VPORT_RSS_MODE
5658 };
5659
5660 /* Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$ */
5661 struct eth_vport_rx_mode {
5662         __le16 state;
5663 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_MASK           0x1
5664 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_SHIFT          0
5665 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_MASK         0x1
5666 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_SHIFT        1
5667 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_MASK   0x1
5668 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_SHIFT  2
5669 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_MASK           0x1
5670 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_SHIFT          3
5671 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_MASK         0x1
5672 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_SHIFT        4
5673 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_MASK         0x1
5674 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_SHIFT        5
5675 #define ETH_VPORT_RX_MODE_RESERVED1_MASK                0x3FF
5676 #define ETH_VPORT_RX_MODE_RESERVED1_SHIFT               6
5677         __le16 reserved2[3];
5678 };
5679
5680 /* Command for setting tpa parameters */
5681 struct eth_vport_tpa_param {
5682         u8 tpa_ipv4_en_flg;
5683         u8 tpa_ipv6_en_flg;
5684         u8 tpa_ipv4_tunn_en_flg;
5685         u8 tpa_ipv6_tunn_en_flg;
5686         u8 tpa_pkt_split_flg;
5687         u8 tpa_hdr_data_split_flg;
5688         u8 tpa_gro_consistent_flg;
5689
5690         u8 tpa_max_aggs_num;
5691
5692         __le16 tpa_max_size;
5693         __le16 tpa_min_size_to_start;
5694
5695         __le16 tpa_min_size_to_cont;
5696         u8 max_buff_num;
5697         u8 reserved;
5698 };
5699
5700 /* Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$ */
5701 struct eth_vport_tx_mode {
5702         __le16 state;
5703 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_MASK           0x1
5704 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_SHIFT          0
5705 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_MASK         0x1
5706 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_SHIFT        1
5707 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_MASK           0x1
5708 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_SHIFT          2
5709 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_MASK         0x1
5710 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_SHIFT        3
5711 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_MASK         0x1
5712 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_SHIFT        4
5713 #define ETH_VPORT_TX_MODE_RESERVED1_MASK                0x7FF
5714 #define ETH_VPORT_TX_MODE_RESERVED1_SHIFT               5
5715         __le16 reserved2[3];
5716 };
5717
5718 /* GFT filter update action type */
5719 enum gft_filter_update_action {
5720         GFT_ADD_FILTER,
5721         GFT_DELETE_FILTER,
5722         MAX_GFT_FILTER_UPDATE_ACTION
5723 };
5724
5725 /* Ramrod data for rx add openflow filter */
5726 struct rx_add_openflow_filter_data {
5727         __le16 action_icid;
5728         u8 priority;
5729         u8 reserved0;
5730         __le32 tenant_id;
5731         __le16 dst_mac_hi;
5732         __le16 dst_mac_mid;
5733         __le16 dst_mac_lo;
5734         __le16 src_mac_hi;
5735         __le16 src_mac_mid;
5736         __le16 src_mac_lo;
5737         __le16 vlan_id;
5738         __le16 l2_eth_type;
5739         u8 ipv4_dscp;
5740         u8 ipv4_frag_type;
5741         u8 ipv4_over_ip;
5742         u8 tenant_id_exists;
5743         __le32 ipv4_dst_addr;
5744         __le32 ipv4_src_addr;
5745         __le16 l4_dst_port;
5746         __le16 l4_src_port;
5747 };
5748
5749 /* Ramrod data for rx create gft action */
5750 struct rx_create_gft_action_data {
5751         u8 vport_id;
5752         u8 reserved[7];
5753 };
5754
5755 /* Ramrod data for rx create openflow action */
5756 struct rx_create_openflow_action_data {
5757         u8 vport_id;
5758         u8 reserved[7];
5759 };
5760
5761 /* Ramrod data for rx queue start ramrod */
5762 struct rx_queue_start_ramrod_data {
5763         __le16 rx_queue_id;
5764         __le16 num_of_pbl_pages;
5765         __le16 bd_max_bytes;
5766         __le16 sb_id;
5767         u8 sb_index;
5768         u8 vport_id;
5769         u8 default_rss_queue_flg;
5770         u8 complete_cqe_flg;
5771         u8 complete_event_flg;
5772         u8 stats_counter_id;
5773         u8 pin_context;
5774         u8 pxp_tph_valid_bd;
5775         u8 pxp_tph_valid_pkt;
5776         u8 pxp_st_hint;
5777
5778         __le16 pxp_st_index;
5779         u8 pmd_mode;
5780
5781         u8 notify_en;
5782         u8 toggle_val;
5783
5784         u8 vf_rx_prod_index;
5785         u8 vf_rx_prod_use_zone_a;
5786         u8 reserved[5];
5787         __le16 reserved1;
5788         struct regpair cqe_pbl_addr;
5789         struct regpair bd_base;
5790         struct regpair reserved2;
5791 };
5792
5793 /* Ramrod data for rx queue stop ramrod */
5794 struct rx_queue_stop_ramrod_data {
5795         __le16 rx_queue_id;
5796         u8 complete_cqe_flg;
5797         u8 complete_event_flg;
5798         u8 vport_id;
5799         u8 reserved[3];
5800 };
5801
5802 /* Ramrod data for rx queue update ramrod */
5803 struct rx_queue_update_ramrod_data {
5804         __le16 rx_queue_id;
5805         u8 complete_cqe_flg;
5806         u8 complete_event_flg;
5807         u8 vport_id;
5808         u8 reserved[4];
5809         u8 reserved1;
5810         u8 reserved2;
5811         u8 reserved3;
5812         __le16 reserved4;
5813         __le16 reserved5;
5814         struct regpair reserved6;
5815 };
5816
5817 /* Ramrod data for rx Add UDP Filter */
5818 struct rx_udp_filter_data {
5819         __le16 action_icid;
5820         __le16 vlan_id;
5821         u8 ip_type;
5822         u8 tenant_id_exists;
5823         __le16 reserved1;
5824         __le32 ip_dst_addr[4];
5825         __le32 ip_src_addr[4];
5826         __le16 udp_dst_port;
5827         __le16 udp_src_port;
5828         __le32 tenant_id;
5829 };
5830
5831 /* Add or delete GFT filter - filter is packet header of type of packet wished
5832  * to pass certain FW flow.
5833  */
5834 struct rx_update_gft_filter_data {
5835         struct regpair pkt_hdr_addr;
5836         __le16 pkt_hdr_length;
5837         __le16 action_icid;
5838         __le16 rx_qid;
5839         __le16 flow_id;
5840         __le16 vport_id;
5841         u8 action_icid_valid;
5842         u8 rx_qid_valid;
5843         u8 flow_id_valid;
5844         u8 filter_action;
5845         u8 assert_on_error;
5846         u8 reserved;
5847 };
5848
5849 /* Ramrod data for rx queue start ramrod */
5850 struct tx_queue_start_ramrod_data {
5851         __le16 sb_id;
5852         u8 sb_index;
5853         u8 vport_id;
5854         u8 reserved0;
5855         u8 stats_counter_id;
5856         __le16 qm_pq_id;
5857         u8 flags;
5858 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_MASK   0x1
5859 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_SHIFT  0
5860 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_MASK       0x1
5861 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_SHIFT      1
5862 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_MASK       0x1
5863 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_SHIFT      2
5864 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_MASK                0x1
5865 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_SHIFT               3
5866 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_MASK               0x1
5867 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_SHIFT              4
5868 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_MASK             0x1
5869 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_SHIFT            5
5870 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_MASK               0x3
5871 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_SHIFT              6
5872         u8 pxp_st_hint;
5873         u8 pxp_tph_valid_bd;
5874         u8 pxp_tph_valid_pkt;
5875         __le16 pxp_st_index;
5876         __le16 comp_agg_size;
5877         __le16 queue_zone_id;
5878         __le16 reserved2;
5879         __le16 pbl_size;
5880         __le16 tx_queue_id;
5881         __le16 same_as_last_id;
5882         __le16 reserved[3];
5883         struct regpair pbl_base_addr;
5884         struct regpair bd_cons_address;
5885 };
5886
5887 /* Ramrod data for tx queue stop ramrod */
5888 struct tx_queue_stop_ramrod_data {
5889         __le16 reserved[4];
5890 };
5891
5892 /* Ramrod data for tx queue update ramrod */
5893 struct tx_queue_update_ramrod_data {
5894         __le16 update_qm_pq_id_flg;
5895         __le16 qm_pq_id;
5896         __le32 reserved0;
5897         struct regpair reserved1[5];
5898 };
5899
5900 /* Ramrod data for vport update ramrod */
5901 struct vport_filter_update_ramrod_data {
5902         struct eth_filter_cmd_header filter_cmd_hdr;
5903         struct eth_filter_cmd filter_cmds[ETH_FILTER_RULES_COUNT];
5904 };
5905
5906 /* Ramrod data for vport start ramrod */
5907 struct vport_start_ramrod_data {
5908         u8 vport_id;
5909         u8 sw_fid;
5910         __le16 mtu;
5911         u8 drop_ttl0_en;
5912         u8 inner_vlan_removal_en;
5913         struct eth_vport_rx_mode rx_mode;
5914         struct eth_vport_tx_mode tx_mode;
5915         struct eth_vport_tpa_param tpa_param;
5916         __le16 default_vlan;
5917         u8 tx_switching_en;
5918         u8 anti_spoofing_en;
5919
5920         u8 default_vlan_en;
5921
5922         u8 handle_ptp_pkts;
5923         u8 silent_vlan_removal_en;
5924         u8 untagged;
5925         struct eth_tx_err_vals tx_err_behav;
5926
5927         u8 zero_placement_offset;
5928         u8 ctl_frame_mac_check_en;
5929         u8 ctl_frame_ethtype_check_en;
5930         u8 reserved[5];
5931 };
5932
5933 /* Ramrod data for vport stop ramrod */
5934 struct vport_stop_ramrod_data {
5935         u8 vport_id;
5936         u8 reserved[7];
5937 };
5938
5939 /* Ramrod data for vport update ramrod */
5940 struct vport_update_ramrod_data_cmn {
5941         u8 vport_id;
5942         u8 update_rx_active_flg;
5943         u8 rx_active_flg;
5944         u8 update_tx_active_flg;
5945         u8 tx_active_flg;
5946         u8 update_rx_mode_flg;
5947         u8 update_tx_mode_flg;
5948         u8 update_approx_mcast_flg;
5949
5950         u8 update_rss_flg;
5951         u8 update_inner_vlan_removal_en_flg;
5952
5953         u8 inner_vlan_removal_en;
5954         u8 update_tpa_param_flg;
5955         u8 update_tpa_en_flg;
5956         u8 update_tx_switching_en_flg;
5957
5958         u8 tx_switching_en;
5959         u8 update_anti_spoofing_en_flg;
5960
5961         u8 anti_spoofing_en;
5962         u8 update_handle_ptp_pkts;
5963
5964         u8 handle_ptp_pkts;
5965         u8 update_default_vlan_en_flg;
5966
5967         u8 default_vlan_en;
5968
5969         u8 update_default_vlan_flg;
5970
5971         __le16 default_vlan;
5972         u8 update_accept_any_vlan_flg;
5973
5974         u8 accept_any_vlan;
5975         u8 silent_vlan_removal_en;
5976         u8 update_mtu_flg;
5977
5978         __le16 mtu;
5979         u8 update_ctl_frame_checks_en_flg;
5980         u8 ctl_frame_mac_check_en;
5981         u8 ctl_frame_ethtype_check_en;
5982         u8 reserved[15];
5983 };
5984
5985 struct vport_update_ramrod_mcast {
5986         __le32 bins[ETH_MULTICAST_MAC_BINS_IN_REGS];
5987 };
5988
5989 /* Ramrod data for vport update ramrod */
5990 struct vport_update_ramrod_data {
5991         struct vport_update_ramrod_data_cmn common;
5992
5993         struct eth_vport_rx_mode rx_mode;
5994         struct eth_vport_tx_mode tx_mode;
5995         struct eth_vport_tpa_param tpa_param;
5996         struct vport_update_ramrod_mcast approx_mcast;
5997         struct eth_vport_rss_config rss_config;
5998 };
5999
6000 struct e4_xstorm_eth_conn_ag_ctx_dq_ext_ldpart {
6001         u8 reserved0;
6002         u8 state;
6003         u8 flags0;
6004 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK       0x1
6005 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT      0
6006 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_MASK          0x1
6007 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_SHIFT         1
6008 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_MASK          0x1
6009 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_SHIFT         2
6010 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK       0x1
6011 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT      3
6012 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_MASK          0x1
6013 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_SHIFT         4
6014 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_MASK          0x1
6015 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_SHIFT         5
6016 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_MASK          0x1
6017 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_SHIFT         6
6018 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_MASK          0x1
6019 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_SHIFT         7
6020         u8 flags1;
6021 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_MASK          0x1
6022 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_SHIFT         0
6023 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_MASK          0x1
6024 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_SHIFT         1
6025 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_MASK          0x1
6026 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_SHIFT         2
6027 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_MASK              0x1
6028 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_SHIFT             3
6029 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED2_MASK       0x1
6030 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED2_SHIFT      4
6031 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED3_MASK       0x1
6032 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED3_SHIFT      5
6033 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_MASK     0x1
6034 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_SHIFT    6
6035 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_MASK       0x1
6036 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_SHIFT      7
6037         u8 flags2;
6038 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0_MASK        0x3
6039 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0_SHIFT       0
6040 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1_MASK        0x3
6041 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1_SHIFT       2
6042 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2_MASK        0x3
6043 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2_SHIFT       4
6044 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3_MASK        0x3
6045 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3_SHIFT       6
6046         u8 flags3;
6047 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4_MASK        0x3
6048 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4_SHIFT       0
6049 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5_MASK        0x3
6050 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5_SHIFT       2
6051 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6_MASK        0x3
6052 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6_SHIFT       4
6053 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7_MASK        0x3
6054 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7_SHIFT       6
6055         u8 flags4;
6056 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8_MASK        0x3
6057 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8_SHIFT       0
6058 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9_MASK        0x3
6059 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9_SHIFT       2
6060 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10_MASK       0x3
6061 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10_SHIFT      4
6062 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11_MASK       0x3
6063 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11_SHIFT      6
6064         u8 flags5;
6065 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12_MASK       0x3
6066 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12_SHIFT      0
6067 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13_MASK       0x3
6068 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13_SHIFT      2
6069 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14_MASK       0x3
6070 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14_SHIFT      4
6071 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15_MASK       0x3
6072 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15_SHIFT      6
6073         u8 flags6;
6074 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_MASK   0x3
6075 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_SHIFT  0
6076 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_MASK   0x3
6077 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_SHIFT  2
6078 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_MASK              0x3
6079 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_SHIFT             4
6080 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_MASK       0x3
6081 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_SHIFT      6
6082         u8 flags7;
6083 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_MASK           0x3
6084 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_SHIFT          0
6085 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_MASK         0x3
6086 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_SHIFT        2
6087 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_MASK          0x3
6088 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT         4
6089 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_MASK              0x1
6090 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_SHIFT             6
6091 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_MASK              0x1
6092 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_SHIFT             7
6093         u8 flags8;
6094 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_MASK      0x1
6095 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_SHIFT     0
6096 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_MASK      0x1
6097 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_SHIFT     1
6098 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_MASK      0x1
6099 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_SHIFT     2
6100 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_MASK      0x1
6101 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_SHIFT     3
6102 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_MASK      0x1
6103 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_SHIFT     4
6104 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_MASK      0x1
6105 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_SHIFT     5
6106 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_MASK      0x1
6107 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_SHIFT     6
6108 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_MASK      0x1
6109 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_SHIFT     7
6110         u8 flags9;
6111 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_MASK                     0x1
6112 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_SHIFT                    0
6113 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_MASK                     0x1
6114 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_SHIFT                    1
6115 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_MASK                     0x1
6116 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_SHIFT                    2
6117 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_MASK                     0x1
6118 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_SHIFT                    3
6119 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_MASK                     0x1
6120 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_SHIFT                    4
6121 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_MASK                     0x1
6122 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_SHIFT                    5
6123 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_MASK        0x1
6124 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_SHIFT       6
6125 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_MASK        0x1
6126 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_SHIFT       7
6127         u8 flags10;
6128 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_MASK                   0x1
6129 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_SHIFT                  0
6130 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_MASK            0x1
6131 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_SHIFT           1
6132 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_MASK                0x1
6133 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_SHIFT               2
6134 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_MASK                 0x1
6135 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_SHIFT                3
6136 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK               0x1
6137 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT              4
6138 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_MASK     0x1
6139 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_SHIFT    5
6140 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_MASK                 0x1
6141 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_SHIFT                6
6142 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_MASK                 0x1
6143 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_SHIFT                7
6144         u8 flags11;
6145 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_MASK         0x1
6146 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_SHIFT        0
6147 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_MASK         0x1
6148 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_SHIFT        1
6149 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_MASK     0x1
6150 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_SHIFT    2
6151 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_MASK            0x1
6152 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_SHIFT           3
6153 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_MASK            0x1
6154 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_SHIFT           4
6155 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_MASK            0x1
6156 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_SHIFT           5
6157 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK       0x1
6158 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT      6
6159 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_MASK            0x1
6160 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_SHIFT           7
6161         u8 flags12;
6162 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_MASK           0x1
6163 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_SHIFT          0
6164 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_MASK           0x1
6165 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_SHIFT          1
6166 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK       0x1
6167 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT      2
6168 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK       0x1
6169 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT      3
6170 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_MASK           0x1
6171 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_SHIFT          4
6172 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_MASK           0x1
6173 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_SHIFT          5
6174 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_MASK           0x1
6175 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_SHIFT          6
6176 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_MASK           0x1
6177 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_SHIFT          7
6178         u8 flags13;
6179 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_MASK           0x1
6180 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_SHIFT          0
6181 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_MASK           0x1
6182 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_SHIFT          1
6183 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK       0x1
6184 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT      2
6185 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK       0x1
6186 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT      3
6187 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK       0x1
6188 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT      4
6189 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK       0x1
6190 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT      5
6191 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK       0x1
6192 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT      6
6193 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK       0x1
6194 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT      7
6195         u8 flags14;
6196 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_MASK           0x1
6197 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_SHIFT          0
6198 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_MASK         0x1
6199 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_SHIFT        1
6200 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_MASK       0x1
6201 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_SHIFT      2
6202 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_MASK       0x1
6203 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_SHIFT      3
6204 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_MASK             0x1
6205 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_SHIFT            4
6206 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK           0x1
6207 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT          5
6208 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_MASK                 0x3
6209 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_SHIFT                6
6210         u8 edpm_event_id;
6211         __le16 physical_q0;
6212         __le16 e5_reserved1;
6213         __le16 edpm_num_bds;
6214         __le16 tx_bd_cons;
6215         __le16 tx_bd_prod;
6216         __le16 tx_class;
6217         __le16 conn_dpi;
6218         u8 byte3;
6219         u8 byte4;
6220         u8 byte5;
6221         u8 byte6;
6222         __le32 reg0;
6223         __le32 reg1;
6224         __le32 reg2;
6225         __le32 reg3;
6226         __le32 reg4;
6227 };
6228
6229 struct e4_mstorm_eth_conn_ag_ctx {
6230         u8 byte0;
6231         u8 byte1;
6232         u8 flags0;
6233 #define E4_MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK     0x1
6234 #define E4_MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT     0
6235 #define E4_MSTORM_ETH_CONN_AG_CTX_BIT1_MASK             0x1
6236 #define E4_MSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT            1
6237 #define E4_MSTORM_ETH_CONN_AG_CTX_CF0_MASK              0x3
6238 #define E4_MSTORM_ETH_CONN_AG_CTX_CF0_SHIFT             2
6239 #define E4_MSTORM_ETH_CONN_AG_CTX_CF1_MASK              0x3
6240 #define E4_MSTORM_ETH_CONN_AG_CTX_CF1_SHIFT             4
6241 #define E4_MSTORM_ETH_CONN_AG_CTX_CF2_MASK              0x3
6242 #define E4_MSTORM_ETH_CONN_AG_CTX_CF2_SHIFT             6
6243         u8 flags1;
6244 #define E4_MSTORM_ETH_CONN_AG_CTX_CF0EN_MASK    0x1
6245 #define E4_MSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT   0
6246 #define E4_MSTORM_ETH_CONN_AG_CTX_CF1EN_MASK    0x1
6247 #define E4_MSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT   1
6248 #define E4_MSTORM_ETH_CONN_AG_CTX_CF2EN_MASK    0x1
6249 #define E4_MSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT   2
6250 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK  0x1
6251 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3
6252 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK  0x1
6253 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4
6254 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK  0x1
6255 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5
6256 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK  0x1
6257 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6
6258 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK  0x1
6259 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7
6260         __le16 word0;
6261         __le16 word1;
6262         __le32 reg0;
6263         __le32 reg1;
6264 };
6265
6266 struct e4_xstorm_eth_hw_conn_ag_ctx {
6267         u8 reserved0;
6268         u8 state;
6269         u8 flags0;
6270 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_MASK  0x1
6271 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
6272 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_MASK     0x1
6273 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_SHIFT    1
6274 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_MASK     0x1
6275 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_SHIFT    2
6276 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_MASK  0x1
6277 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
6278 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_MASK     0x1
6279 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_SHIFT    4
6280 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_MASK     0x1
6281 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_SHIFT    5
6282 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_MASK     0x1
6283 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_SHIFT    6
6284 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_MASK     0x1
6285 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_SHIFT    7
6286         u8 flags1;
6287 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_MASK             0x1
6288 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_SHIFT            0
6289 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_MASK             0x1
6290 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_SHIFT            1
6291 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_MASK             0x1
6292 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_SHIFT            2
6293 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT11_MASK                 0x1
6294 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT11_SHIFT                3
6295 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED2_MASK          0x1
6296 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED2_SHIFT         4
6297 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED3_MASK          0x1
6298 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED3_SHIFT         5
6299 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_MASK        0x1
6300 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT       6
6301 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_MASK          0x1
6302 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT         7
6303         u8 flags2;
6304 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0_MASK   0x3
6305 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0_SHIFT  0
6306 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1_MASK   0x3
6307 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1_SHIFT  2
6308 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2_MASK   0x3
6309 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2_SHIFT  4
6310 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3_MASK   0x3
6311 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3_SHIFT  6
6312         u8 flags3;
6313 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4_MASK   0x3
6314 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4_SHIFT  0
6315 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5_MASK   0x3
6316 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5_SHIFT  2
6317 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6_MASK   0x3
6318 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6_SHIFT  4
6319 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7_MASK   0x3
6320 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7_SHIFT  6
6321         u8 flags4;
6322 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8_MASK   0x3
6323 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8_SHIFT  0
6324 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9_MASK   0x3
6325 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9_SHIFT  2
6326 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10_MASK  0x3
6327 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10_SHIFT 4
6328 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11_MASK  0x3
6329 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11_SHIFT 6
6330         u8 flags5;
6331 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12_MASK  0x3
6332 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12_SHIFT 0
6333 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13_MASK  0x3
6334 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13_SHIFT 2
6335 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14_MASK  0x3
6336 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14_SHIFT 4
6337 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15_MASK  0x3
6338 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15_SHIFT 6
6339         u8 flags6;
6340 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK      0x3
6341 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT     0
6342 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_MASK      0x3
6343 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT     2
6344 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_MASK                 0x3
6345 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_SHIFT                4
6346 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_MASK          0x3
6347 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_SHIFT         6
6348         u8 flags7;
6349 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_MASK      0x3
6350 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_SHIFT     0
6351 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_MASK    0x3
6352 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_SHIFT   2
6353 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_MASK     0x3
6354 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_SHIFT    4
6355 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_MASK         0x1
6356 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_SHIFT        6
6357 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_MASK         0x1
6358 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_SHIFT        7
6359         u8 flags8;
6360 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_MASK         0x1
6361 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_SHIFT        0
6362 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_MASK         0x1
6363 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_SHIFT        1
6364 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_MASK         0x1
6365 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_SHIFT        2
6366 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_MASK         0x1
6367 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_SHIFT        3
6368 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_MASK         0x1
6369 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_SHIFT        4
6370 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_MASK         0x1
6371 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_SHIFT        5
6372 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_MASK         0x1
6373 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_SHIFT        6
6374 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_MASK         0x1
6375 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_SHIFT        7
6376         u8 flags9;
6377 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_MASK                0x1
6378 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_SHIFT               0
6379 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_MASK                0x1
6380 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_SHIFT               1
6381 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_MASK                0x1
6382 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_SHIFT               2
6383 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_MASK                0x1
6384 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_SHIFT               3
6385 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_MASK                0x1
6386 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_SHIFT               4
6387 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_MASK                0x1
6388 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_SHIFT               5
6389 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK   0x1
6390 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT  6
6391 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK   0x1
6392 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT  7
6393         u8 flags10;
6394 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_MASK                      0x1
6395 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_SHIFT                     0
6396 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_MASK               0x1
6397 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT              1
6398 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_MASK                   0x1
6399 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT                  2
6400 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_MASK                    0x1
6401 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_SHIFT                   3
6402 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_MASK                  0x1
6403 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_SHIFT                 4
6404 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK        0x1
6405 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT       5
6406 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_MASK                    0x1
6407 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_SHIFT                   6
6408 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_MASK                    0x1
6409 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_SHIFT                   7
6410         u8 flags11;
6411 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_MASK            0x1
6412 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_SHIFT           0
6413 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_MASK            0x1
6414 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_SHIFT           1
6415 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_MASK        0x1
6416 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT       2
6417 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_MASK               0x1
6418 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_SHIFT              3
6419 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_MASK               0x1
6420 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_SHIFT              4
6421 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_MASK               0x1
6422 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_SHIFT              5
6423 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_MASK          0x1
6424 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_SHIFT         6
6425 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_MASK               0x1
6426 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_SHIFT              7
6427         u8 flags12;
6428 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_MASK      0x1
6429 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_SHIFT     0
6430 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_MASK      0x1
6431 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_SHIFT     1
6432 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_MASK  0x1
6433 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
6434 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_MASK  0x1
6435 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
6436 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_MASK      0x1
6437 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_SHIFT     4
6438 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_MASK      0x1
6439 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_SHIFT     5
6440 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_MASK      0x1
6441 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_SHIFT     6
6442 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_MASK      0x1
6443 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_SHIFT     7
6444         u8 flags13;
6445 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_MASK      0x1
6446 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_SHIFT     0
6447 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_MASK      0x1
6448 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_SHIFT     1
6449 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_MASK  0x1
6450 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
6451 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_MASK  0x1
6452 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
6453 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_MASK  0x1
6454 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
6455 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_MASK  0x1
6456 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
6457 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_MASK  0x1
6458 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
6459 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_MASK  0x1
6460 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
6461         u8 flags14;
6462 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK      0x1
6463 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT     0
6464 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK    0x1
6465 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT   1
6466 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK  0x1
6467 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2
6468 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK  0x1
6469 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3
6470 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_MASK        0x1
6471 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT       4
6472 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK      0x1
6473 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT     5
6474 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_MASK            0x3
6475 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_SHIFT           6
6476         u8 edpm_event_id;
6477         __le16 physical_q0;
6478         __le16 e5_reserved1;
6479         __le16 edpm_num_bds;
6480         __le16 tx_bd_cons;
6481         __le16 tx_bd_prod;
6482         __le16 tx_class;
6483         __le16 conn_dpi;
6484 };
6485
6486 /* GFT CAM line struct */
6487 struct gft_cam_line {
6488         __le32 camline;
6489 #define GFT_CAM_LINE_VALID_MASK         0x1
6490 #define GFT_CAM_LINE_VALID_SHIFT        0
6491 #define GFT_CAM_LINE_DATA_MASK          0x3FFF
6492 #define GFT_CAM_LINE_DATA_SHIFT         1
6493 #define GFT_CAM_LINE_MASK_BITS_MASK     0x3FFF
6494 #define GFT_CAM_LINE_MASK_BITS_SHIFT    15
6495 #define GFT_CAM_LINE_RESERVED1_MASK     0x7
6496 #define GFT_CAM_LINE_RESERVED1_SHIFT    29
6497 };
6498
6499 /* GFT CAM line struct with fields breakout */
6500 struct gft_cam_line_mapped {
6501         __le32 camline;
6502 #define GFT_CAM_LINE_MAPPED_VALID_MASK                          0x1
6503 #define GFT_CAM_LINE_MAPPED_VALID_SHIFT                         0
6504 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK                     0x1
6505 #define GFT_CAM_LINE_MAPPED_IP_VERSION_SHIFT                    1
6506 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK              0x1
6507 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_SHIFT             2
6508 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK            0xF
6509 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_SHIFT           3
6510 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK                    0xF
6511 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_SHIFT                   7
6512 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK                          0xF
6513 #define GFT_CAM_LINE_MAPPED_PF_ID_SHIFT                         11
6514 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_MASK                0x1
6515 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_SHIFT               15
6516 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_MASK         0x1
6517 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_SHIFT        16
6518 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_MASK       0xF
6519 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_SHIFT      17
6520 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_MASK               0xF
6521 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_SHIFT              21
6522 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK_MASK                     0xF
6523 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK_SHIFT                    25
6524 #define GFT_CAM_LINE_MAPPED_RESERVED1_MASK                      0x7
6525 #define GFT_CAM_LINE_MAPPED_RESERVED1_SHIFT                     29
6526 };
6527
6528 union gft_cam_line_union {
6529         struct gft_cam_line cam_line;
6530         struct gft_cam_line_mapped cam_line_mapped;
6531 };
6532
6533 /* Used in gft_profile_key: Indication for ip version */
6534 enum gft_profile_ip_version {
6535         GFT_PROFILE_IPV4 = 0,
6536         GFT_PROFILE_IPV6 = 1,
6537         MAX_GFT_PROFILE_IP_VERSION
6538 };
6539
6540 /* Profile key stucr fot GFT logic in Prs */
6541 struct gft_profile_key {
6542         __le16 profile_key;
6543 #define GFT_PROFILE_KEY_IP_VERSION_MASK                 0x1
6544 #define GFT_PROFILE_KEY_IP_VERSION_SHIFT                0
6545 #define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_MASK          0x1
6546 #define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_SHIFT         1
6547 #define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_MASK        0xF
6548 #define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_SHIFT       2
6549 #define GFT_PROFILE_KEY_TUNNEL_TYPE_MASK                0xF
6550 #define GFT_PROFILE_KEY_TUNNEL_TYPE_SHIFT               6
6551 #define GFT_PROFILE_KEY_PF_ID_MASK                      0xF
6552 #define GFT_PROFILE_KEY_PF_ID_SHIFT                     10
6553 #define GFT_PROFILE_KEY_RESERVED0_MASK                  0x3
6554 #define GFT_PROFILE_KEY_RESERVED0_SHIFT                 14
6555 };
6556
6557 /* Used in gft_profile_key: Indication for tunnel type */
6558 enum gft_profile_tunnel_type {
6559         GFT_PROFILE_NO_TUNNEL = 0,
6560         GFT_PROFILE_VXLAN_TUNNEL = 1,
6561         GFT_PROFILE_GRE_MAC_OR_NVGRE_TUNNEL = 2,
6562         GFT_PROFILE_GRE_IP_TUNNEL = 3,
6563         GFT_PROFILE_GENEVE_MAC_TUNNEL = 4,
6564         GFT_PROFILE_GENEVE_IP_TUNNEL = 5,
6565         MAX_GFT_PROFILE_TUNNEL_TYPE
6566 };
6567
6568 /* Used in gft_profile_key: Indication for protocol type */
6569 enum gft_profile_upper_protocol_type {
6570         GFT_PROFILE_ROCE_PROTOCOL = 0,
6571         GFT_PROFILE_RROCE_PROTOCOL = 1,
6572         GFT_PROFILE_FCOE_PROTOCOL = 2,
6573         GFT_PROFILE_ICMP_PROTOCOL = 3,
6574         GFT_PROFILE_ARP_PROTOCOL = 4,
6575         GFT_PROFILE_USER_TCP_SRC_PORT_1_INNER = 5,
6576         GFT_PROFILE_USER_TCP_DST_PORT_1_INNER = 6,
6577         GFT_PROFILE_TCP_PROTOCOL = 7,
6578         GFT_PROFILE_USER_UDP_DST_PORT_1_INNER = 8,
6579         GFT_PROFILE_USER_UDP_DST_PORT_2_OUTER = 9,
6580         GFT_PROFILE_UDP_PROTOCOL = 10,
6581         GFT_PROFILE_USER_IP_1_INNER = 11,
6582         GFT_PROFILE_USER_IP_2_OUTER = 12,
6583         GFT_PROFILE_USER_ETH_1_INNER = 13,
6584         GFT_PROFILE_USER_ETH_2_OUTER = 14,
6585         GFT_PROFILE_RAW = 15,
6586         MAX_GFT_PROFILE_UPPER_PROTOCOL_TYPE
6587 };
6588
6589 /* GFT RAM line struct */
6590 struct gft_ram_line {
6591         __le32 lo;
6592 #define GFT_RAM_LINE_VLAN_SELECT_MASK                   0x3
6593 #define GFT_RAM_LINE_VLAN_SELECT_SHIFT                  0
6594 #define GFT_RAM_LINE_TUNNEL_ENTROPHY_MASK               0x1
6595 #define GFT_RAM_LINE_TUNNEL_ENTROPHY_SHIFT              2
6596 #define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_MASK          0x1
6597 #define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_SHIFT         3
6598 #define GFT_RAM_LINE_TUNNEL_TTL_MASK                    0x1
6599 #define GFT_RAM_LINE_TUNNEL_TTL_SHIFT                   4
6600 #define GFT_RAM_LINE_TUNNEL_ETHERTYPE_MASK              0x1
6601 #define GFT_RAM_LINE_TUNNEL_ETHERTYPE_SHIFT             5
6602 #define GFT_RAM_LINE_TUNNEL_DST_PORT_MASK               0x1
6603 #define GFT_RAM_LINE_TUNNEL_DST_PORT_SHIFT              6
6604 #define GFT_RAM_LINE_TUNNEL_SRC_PORT_MASK               0x1
6605 #define GFT_RAM_LINE_TUNNEL_SRC_PORT_SHIFT              7
6606 #define GFT_RAM_LINE_TUNNEL_DSCP_MASK                   0x1
6607 #define GFT_RAM_LINE_TUNNEL_DSCP_SHIFT                  8
6608 #define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_MASK       0x1
6609 #define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_SHIFT      9
6610 #define GFT_RAM_LINE_TUNNEL_DST_IP_MASK                 0x1
6611 #define GFT_RAM_LINE_TUNNEL_DST_IP_SHIFT                10
6612 #define GFT_RAM_LINE_TUNNEL_SRC_IP_MASK                 0x1
6613 #define GFT_RAM_LINE_TUNNEL_SRC_IP_SHIFT                11
6614 #define GFT_RAM_LINE_TUNNEL_PRIORITY_MASK               0x1
6615 #define GFT_RAM_LINE_TUNNEL_PRIORITY_SHIFT              12
6616 #define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_MASK          0x1
6617 #define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_SHIFT         13
6618 #define GFT_RAM_LINE_TUNNEL_VLAN_MASK                   0x1
6619 #define GFT_RAM_LINE_TUNNEL_VLAN_SHIFT                  14
6620 #define GFT_RAM_LINE_TUNNEL_DST_MAC_MASK                0x1
6621 #define GFT_RAM_LINE_TUNNEL_DST_MAC_SHIFT               15
6622 #define GFT_RAM_LINE_TUNNEL_SRC_MAC_MASK                0x1
6623 #define GFT_RAM_LINE_TUNNEL_SRC_MAC_SHIFT               16
6624 #define GFT_RAM_LINE_TTL_EQUAL_ONE_MASK                 0x1
6625 #define GFT_RAM_LINE_TTL_EQUAL_ONE_SHIFT                17
6626 #define GFT_RAM_LINE_TTL_MASK                           0x1
6627 #define GFT_RAM_LINE_TTL_SHIFT                          18
6628 #define GFT_RAM_LINE_ETHERTYPE_MASK                     0x1
6629 #define GFT_RAM_LINE_ETHERTYPE_SHIFT                    19
6630 #define GFT_RAM_LINE_RESERVED0_MASK                     0x1
6631 #define GFT_RAM_LINE_RESERVED0_SHIFT                    20
6632 #define GFT_RAM_LINE_TCP_FLAG_FIN_MASK                  0x1
6633 #define GFT_RAM_LINE_TCP_FLAG_FIN_SHIFT                 21
6634 #define GFT_RAM_LINE_TCP_FLAG_SYN_MASK                  0x1
6635 #define GFT_RAM_LINE_TCP_FLAG_SYN_SHIFT                 22
6636 #define GFT_RAM_LINE_TCP_FLAG_RST_MASK                  0x1
6637 #define GFT_RAM_LINE_TCP_FLAG_RST_SHIFT                 23
6638 #define GFT_RAM_LINE_TCP_FLAG_PSH_MASK                  0x1
6639 #define GFT_RAM_LINE_TCP_FLAG_PSH_SHIFT                 24
6640 #define GFT_RAM_LINE_TCP_FLAG_ACK_MASK                  0x1
6641 #define GFT_RAM_LINE_TCP_FLAG_ACK_SHIFT                 25
6642 #define GFT_RAM_LINE_TCP_FLAG_URG_MASK                  0x1
6643 #define GFT_RAM_LINE_TCP_FLAG_URG_SHIFT                 26
6644 #define GFT_RAM_LINE_TCP_FLAG_ECE_MASK                  0x1
6645 #define GFT_RAM_LINE_TCP_FLAG_ECE_SHIFT                 27
6646 #define GFT_RAM_LINE_TCP_FLAG_CWR_MASK                  0x1
6647 #define GFT_RAM_LINE_TCP_FLAG_CWR_SHIFT                 28
6648 #define GFT_RAM_LINE_TCP_FLAG_NS_MASK                   0x1
6649 #define GFT_RAM_LINE_TCP_FLAG_NS_SHIFT                  29
6650 #define GFT_RAM_LINE_DST_PORT_MASK                      0x1
6651 #define GFT_RAM_LINE_DST_PORT_SHIFT                     30
6652 #define GFT_RAM_LINE_SRC_PORT_MASK                      0x1
6653 #define GFT_RAM_LINE_SRC_PORT_SHIFT                     31
6654         __le32 hi;
6655 #define GFT_RAM_LINE_DSCP_MASK                          0x1
6656 #define GFT_RAM_LINE_DSCP_SHIFT                         0
6657 #define GFT_RAM_LINE_OVER_IP_PROTOCOL_MASK              0x1
6658 #define GFT_RAM_LINE_OVER_IP_PROTOCOL_SHIFT             1
6659 #define GFT_RAM_LINE_DST_IP_MASK                        0x1
6660 #define GFT_RAM_LINE_DST_IP_SHIFT                       2
6661 #define GFT_RAM_LINE_SRC_IP_MASK                        0x1
6662 #define GFT_RAM_LINE_SRC_IP_SHIFT                       3
6663 #define GFT_RAM_LINE_PRIORITY_MASK                      0x1
6664 #define GFT_RAM_LINE_PRIORITY_SHIFT                     4
6665 #define GFT_RAM_LINE_PROVIDER_VLAN_MASK                 0x1
6666 #define GFT_RAM_LINE_PROVIDER_VLAN_SHIFT                5
6667 #define GFT_RAM_LINE_VLAN_MASK                          0x1
6668 #define GFT_RAM_LINE_VLAN_SHIFT                         6
6669 #define GFT_RAM_LINE_DST_MAC_MASK                       0x1
6670 #define GFT_RAM_LINE_DST_MAC_SHIFT                      7
6671 #define GFT_RAM_LINE_SRC_MAC_MASK                       0x1
6672 #define GFT_RAM_LINE_SRC_MAC_SHIFT                      8
6673 #define GFT_RAM_LINE_TENANT_ID_MASK                     0x1
6674 #define GFT_RAM_LINE_TENANT_ID_SHIFT                    9
6675 #define GFT_RAM_LINE_RESERVED1_MASK                     0x3FFFFF
6676 #define GFT_RAM_LINE_RESERVED1_SHIFT                    10
6677 };
6678
6679 /* Used in the first 2 bits for gft_ram_line: Indication for vlan mask */
6680 enum gft_vlan_select {
6681         INNER_PROVIDER_VLAN = 0,
6682         INNER_VLAN = 1,
6683         OUTER_PROVIDER_VLAN = 2,
6684         OUTER_VLAN = 3,
6685         MAX_GFT_VLAN_SELECT
6686 };
6687
6688 /* The rdma task context of Mstorm */
6689 struct ystorm_rdma_task_st_ctx {
6690         struct regpair temp[4];
6691 };
6692
6693 struct e4_ystorm_rdma_task_ag_ctx {
6694         u8 reserved;
6695         u8 byte1;
6696         __le16 msem_ctx_upd_seq;
6697         u8 flags0;
6698 #define E4_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK         0xF
6699 #define E4_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT        0
6700 #define E4_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK            0x1
6701 #define E4_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT           4
6702 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT1_MASK                    0x1
6703 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT                   5
6704 #define E4_YSTORM_RDMA_TASK_AG_CTX_VALID_MASK                   0x1
6705 #define E4_YSTORM_RDMA_TASK_AG_CTX_VALID_SHIFT                  6
6706 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT3_MASK                    0x1
6707 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT                   7
6708         u8 flags1;
6709 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0_MASK             0x3
6710 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT            0
6711 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1_MASK             0x3
6712 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT            2
6713 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_MASK      0x3
6714 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_SHIFT     4
6715 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK           0x1
6716 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT          6
6717 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK           0x1
6718 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT          7
6719         u8 flags2;
6720 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT4_MASK            0x1
6721 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT           0
6722 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK         0x1
6723 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT        1
6724 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK         0x1
6725 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT        2
6726 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK         0x1
6727 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT        3
6728 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK         0x1
6729 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT        4
6730 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK         0x1
6731 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT        5
6732 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK         0x1
6733 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT        6
6734 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK         0x1
6735 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT        7
6736         u8 key;
6737         __le32 mw_cnt;
6738         u8 ref_cnt_seq;
6739         u8 ctx_upd_seq;
6740         __le16 dif_flags;
6741         __le16 tx_ref_count;
6742         __le16 last_used_ltid;
6743         __le16 parent_mr_lo;
6744         __le16 parent_mr_hi;
6745         __le32 fbo_lo;
6746         __le32 fbo_hi;
6747 };
6748
6749 struct e4_mstorm_rdma_task_ag_ctx {
6750         u8 reserved;
6751         u8 byte1;
6752         __le16 icid;
6753         u8 flags0;
6754 #define E4_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK         0xF
6755 #define E4_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT        0
6756 #define E4_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK            0x1
6757 #define E4_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT           4
6758 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT1_MASK                    0x1
6759 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT                   5
6760 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT2_MASK                    0x1
6761 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT                   6
6762 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT3_MASK                    0x1
6763 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT                   7
6764         u8 flags1;
6765 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0_MASK     0x3
6766 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT    0
6767 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1_MASK     0x3
6768 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT    2
6769 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2_MASK     0x3
6770 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT    4
6771 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK   0x1
6772 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT  6
6773 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK   0x1
6774 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT  7
6775         u8 flags2;
6776 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK           0x1
6777 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT          0
6778 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK         0x1
6779 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT        1
6780 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK         0x1
6781 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT        2
6782 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK         0x1
6783 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT        3
6784 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK         0x1
6785 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT        4
6786 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK         0x1
6787 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT        5
6788 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK         0x1
6789 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT        6
6790 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK         0x1
6791 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT        7
6792         u8 key;
6793         __le32 mw_cnt;
6794         u8 ref_cnt_seq;
6795         u8 ctx_upd_seq;
6796         __le16 dif_flags;
6797         __le16 tx_ref_count;
6798         __le16 last_used_ltid;
6799         __le16 parent_mr_lo;
6800         __le16 parent_mr_hi;
6801         __le32 fbo_lo;
6802         __le32 fbo_hi;
6803 };
6804
6805 /* The roce task context of Mstorm */
6806 struct mstorm_rdma_task_st_ctx {
6807         struct regpair temp[4];
6808 };
6809
6810 /* The roce task context of Ustorm */
6811 struct ustorm_rdma_task_st_ctx {
6812         struct regpair temp[2];
6813 };
6814
6815 struct e4_ustorm_rdma_task_ag_ctx {
6816         u8 reserved;
6817         u8 byte1;
6818         __le16 icid;
6819         u8 flags0;
6820 #define E4_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK         0xF
6821 #define E4_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT        0
6822 #define E4_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK            0x1
6823 #define E4_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT           4
6824 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_MASK          0x1
6825 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_SHIFT         5
6826 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_MASK     0x3
6827 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_SHIFT    6
6828         u8 flags1;
6829 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_MASK   0x3
6830 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_SHIFT  0
6831 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_MASK           0x3
6832 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_SHIFT          2
6833 #define E4_USTORM_RDMA_TASK_AG_CTX_CF3_MASK                     0x3
6834 #define E4_USTORM_RDMA_TASK_AG_CTX_CF3_SHIFT                    4
6835 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_MASK            0x3
6836 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_SHIFT           6
6837         u8 flags2;
6838 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_MASK  0x1
6839 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_SHIFT 0
6840 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED2_MASK               0x1
6841 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED2_SHIFT              1
6842 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED3_MASK               0x1
6843 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED3_SHIFT              2
6844 #define E4_USTORM_RDMA_TASK_AG_CTX_CF3EN_MASK                   0x1
6845 #define E4_USTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT                  3
6846 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK         0x1
6847 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT        4
6848 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK                 0x1
6849 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT                5
6850 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK                 0x1
6851 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT                6
6852 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK                 0x1
6853 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT                7
6854         u8 flags3;
6855 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK         0x1
6856 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT        0
6857 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK         0x1
6858 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT        1
6859 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK         0x1
6860 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT        2
6861 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK         0x1
6862 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT        3
6863 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_MASK  0xF
6864 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4
6865         __le32 dif_err_intervals;
6866         __le32 dif_error_1st_interval;
6867         __le32 reg2;
6868         __le32 dif_runt_value;
6869         __le32 reg4;
6870         __le32 reg5;
6871 };
6872
6873 /* RDMA task context */
6874 struct e4_rdma_task_context {
6875         struct ystorm_rdma_task_st_ctx ystorm_st_context;
6876         struct e4_ystorm_rdma_task_ag_ctx ystorm_ag_context;
6877         struct tdif_task_context tdif_context;
6878         struct e4_mstorm_rdma_task_ag_ctx mstorm_ag_context;
6879         struct mstorm_rdma_task_st_ctx mstorm_st_context;
6880         struct rdif_task_context rdif_context;
6881         struct ustorm_rdma_task_st_ctx ustorm_st_context;
6882         struct regpair ustorm_st_padding[2];
6883         struct e4_ustorm_rdma_task_ag_ctx ustorm_ag_context;
6884 };
6885
6886 /* rdma function init ramrod data */
6887 struct rdma_close_func_ramrod_data {
6888         u8 cnq_start_offset;
6889         u8 num_cnqs;
6890         u8 vf_id;
6891         u8 vf_valid;
6892         u8 reserved[4];
6893 };
6894
6895 /* rdma function init CNQ parameters */
6896 struct rdma_cnq_params {
6897         __le16 sb_num;
6898         u8 sb_index;
6899         u8 num_pbl_pages;
6900         __le32 reserved;
6901         struct regpair pbl_base_addr;
6902         __le16 queue_zone_num;
6903         u8 reserved1[6];
6904 };
6905
6906 /* rdma create cq ramrod data */
6907 struct rdma_create_cq_ramrod_data {
6908         struct regpair cq_handle;
6909         struct regpair pbl_addr;
6910         __le32 max_cqes;
6911         __le16 pbl_num_pages;
6912         __le16 dpi;
6913         u8 is_two_level_pbl;
6914         u8 cnq_id;
6915         u8 pbl_log_page_size;
6916         u8 toggle_bit;
6917         __le16 int_timeout;
6918         __le16 reserved1;
6919 };
6920
6921 /* rdma deregister tid ramrod data */
6922 struct rdma_deregister_tid_ramrod_data {
6923         __le32 itid;
6924         __le32 reserved;
6925 };
6926
6927 /* rdma destroy cq output params */
6928 struct rdma_destroy_cq_output_params {
6929         __le16 cnq_num;
6930         __le16 reserved0;
6931         __le32 reserved1;
6932 };
6933
6934 /* rdma destroy cq ramrod data */
6935 struct rdma_destroy_cq_ramrod_data {
6936         struct regpair output_params_addr;
6937 };
6938
6939 /* RDMA slow path EQ cmd IDs */
6940 enum rdma_event_opcode {
6941         RDMA_EVENT_UNUSED,
6942         RDMA_EVENT_FUNC_INIT,
6943         RDMA_EVENT_FUNC_CLOSE,
6944         RDMA_EVENT_REGISTER_MR,
6945         RDMA_EVENT_DEREGISTER_MR,
6946         RDMA_EVENT_CREATE_CQ,
6947         RDMA_EVENT_RESIZE_CQ,
6948         RDMA_EVENT_DESTROY_CQ,
6949         RDMA_EVENT_CREATE_SRQ,
6950         RDMA_EVENT_MODIFY_SRQ,
6951         RDMA_EVENT_DESTROY_SRQ,
6952         MAX_RDMA_EVENT_OPCODE
6953 };
6954
6955 /* RDMA FW return code for slow path ramrods */
6956 enum rdma_fw_return_code {
6957         RDMA_RETURN_OK = 0,
6958         RDMA_RETURN_REGISTER_MR_BAD_STATE_ERR,
6959         RDMA_RETURN_DEREGISTER_MR_BAD_STATE_ERR,
6960         RDMA_RETURN_RESIZE_CQ_ERR,
6961         RDMA_RETURN_NIG_DRAIN_REQ,
6962         MAX_RDMA_FW_RETURN_CODE
6963 };
6964
6965 /* rdma function init header */
6966 struct rdma_init_func_hdr {
6967         u8 cnq_start_offset;
6968         u8 num_cnqs;
6969         u8 cq_ring_mode;
6970         u8 vf_id;
6971         u8 vf_valid;
6972         u8 relaxed_ordering;
6973         u8 reserved[2];
6974 };
6975
6976 /* rdma function init ramrod data */
6977 struct rdma_init_func_ramrod_data {
6978         struct rdma_init_func_hdr params_header;
6979         struct rdma_cnq_params cnq_params[NUM_OF_GLOBAL_QUEUES];
6980 };
6981
6982 /* RDMA ramrod command IDs */
6983 enum rdma_ramrod_cmd_id {
6984         RDMA_RAMROD_UNUSED,
6985         RDMA_RAMROD_FUNC_INIT,
6986         RDMA_RAMROD_FUNC_CLOSE,
6987         RDMA_RAMROD_REGISTER_MR,
6988         RDMA_RAMROD_DEREGISTER_MR,
6989         RDMA_RAMROD_CREATE_CQ,
6990         RDMA_RAMROD_RESIZE_CQ,
6991         RDMA_RAMROD_DESTROY_CQ,
6992         RDMA_RAMROD_CREATE_SRQ,
6993         RDMA_RAMROD_MODIFY_SRQ,
6994         RDMA_RAMROD_DESTROY_SRQ,
6995         MAX_RDMA_RAMROD_CMD_ID
6996 };
6997
6998 /* rdma register tid ramrod data */
6999 struct rdma_register_tid_ramrod_data {
7000         __le16 flags;
7001 #define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_MASK        0x1F
7002 #define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_SHIFT       0
7003 #define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_MASK        0x1
7004 #define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_SHIFT       5
7005 #define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_MASK           0x1
7006 #define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_SHIFT          6
7007 #define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_MASK               0x1
7008 #define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_SHIFT              7
7009 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_MASK          0x1
7010 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_SHIFT         8
7011 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_MASK         0x1
7012 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_SHIFT        9
7013 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_MASK        0x1
7014 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_SHIFT       10
7015 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_MASK          0x1
7016 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_SHIFT         11
7017 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_MASK           0x1
7018 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_SHIFT          12
7019 #define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_MASK       0x1
7020 #define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_SHIFT      13
7021 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED_MASK             0x3
7022 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED_SHIFT            14
7023         u8 flags1;
7024 #define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_MASK    0x1F
7025 #define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_SHIFT   0
7026 #define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_MASK             0x7
7027 #define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_SHIFT            5
7028         u8 flags2;
7029 #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_MASK               0x1
7030 #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_SHIFT              0
7031 #define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_MASK      0x1
7032 #define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_SHIFT     1
7033 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_MASK            0x3F
7034 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_SHIFT           2
7035         u8 key;
7036         u8 length_hi;
7037         u8 vf_id;
7038         u8 vf_valid;
7039         __le16 pd;
7040         __le16 reserved2;
7041         __le32 length_lo;
7042         __le32 itid;
7043         __le32 reserved3;
7044         struct regpair va;
7045         struct regpair pbl_base;
7046         struct regpair dif_error_addr;
7047         struct regpair dif_runt_addr;
7048         __le32 reserved4[2];
7049 };
7050
7051 /* rdma resize cq output params */
7052 struct rdma_resize_cq_output_params {
7053         __le32 old_cq_cons;
7054         __le32 old_cq_prod;
7055 };
7056
7057 /* rdma resize cq ramrod data */
7058 struct rdma_resize_cq_ramrod_data {
7059         u8 flags;
7060 #define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_MASK              0x1
7061 #define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_SHIFT             0
7062 #define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_MASK        0x1
7063 #define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_SHIFT       1
7064 #define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_MASK                0x3F
7065 #define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_SHIFT               2
7066         u8 pbl_log_page_size;
7067         __le16 pbl_num_pages;
7068         __le32 max_cqes;
7069         struct regpair pbl_addr;
7070         struct regpair output_params_addr;
7071 };
7072
7073 /* The rdma storm context of Mstorm */
7074 struct rdma_srq_context {
7075         struct regpair temp[8];
7076 };
7077
7078 /* rdma create qp requester ramrod data */
7079 struct rdma_srq_create_ramrod_data {
7080         struct regpair pbl_base_addr;
7081         __le16 pages_in_srq_pbl;
7082         __le16 pd_id;
7083         struct rdma_srq_id srq_id;
7084         __le16 page_size;
7085         __le16 reserved1;
7086         __le32 reserved2;
7087         struct regpair producers_addr;
7088 };
7089
7090 /* rdma create qp requester ramrod data */
7091 struct rdma_srq_destroy_ramrod_data {
7092         struct rdma_srq_id srq_id;
7093         __le32 reserved;
7094 };
7095
7096 /* rdma create qp requester ramrod data */
7097 struct rdma_srq_modify_ramrod_data {
7098         struct rdma_srq_id srq_id;
7099         __le32 wqe_limit;
7100 };
7101
7102 /* RDMA Tid type enumeration (for register_tid ramrod) */
7103 enum rdma_tid_type {
7104         RDMA_TID_REGISTERED_MR,
7105         RDMA_TID_FMR,
7106         RDMA_TID_MW_TYPE1,
7107         RDMA_TID_MW_TYPE2A,
7108         MAX_RDMA_TID_TYPE
7109 };
7110
7111 struct e4_xstorm_roce_conn_ag_ctx_dq_ext_ld_part {
7112         u8 reserved0;
7113         u8 state;
7114         u8 flags0;
7115 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK      0x1
7116 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT     0
7117 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_MASK              0x1
7118 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_SHIFT             1
7119 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_MASK              0x1
7120 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_SHIFT             2
7121 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK      0x1
7122 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT     3
7123 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_MASK              0x1
7124 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_SHIFT             4
7125 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_MASK              0x1
7126 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_SHIFT             5
7127 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_MASK              0x1
7128 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_SHIFT             6
7129 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_MASK              0x1
7130 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_SHIFT             7
7131         u8 flags1;
7132 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_MASK              0x1
7133 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_SHIFT             0
7134 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_MASK              0x1
7135 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_SHIFT             1
7136 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_MASK             0x1
7137 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_SHIFT            2
7138 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_MASK             0x1
7139 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_SHIFT            3
7140 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_MASK             0x1
7141 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_SHIFT            4
7142 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSTORM_FLUSH_MASK      0x1
7143 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSTORM_FLUSH_SHIFT     5
7144 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_MASK             0x1
7145 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_SHIFT            6
7146 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_MASK      0x1
7147 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_SHIFT     7
7148         u8 flags2;
7149 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_MASK       0x3
7150 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_SHIFT      0
7151 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_MASK       0x3
7152 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_SHIFT      2
7153 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_MASK       0x3
7154 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_SHIFT      4
7155 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_MASK       0x3
7156 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_SHIFT      6
7157         u8 flags3;
7158 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_MASK               0x3
7159 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_SHIFT              0
7160 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_MASK               0x3
7161 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_SHIFT              2
7162 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_MASK               0x3
7163 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_SHIFT              4
7164 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_MASK       0x3
7165 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_SHIFT      6
7166         u8 flags4;
7167 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_MASK       0x3
7168 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_SHIFT      0
7169 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_MASK       0x3
7170 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_SHIFT      2
7171 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_MASK      0x3
7172 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_SHIFT     4
7173 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_MASK      0x3
7174 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_SHIFT     6
7175         u8 flags5;
7176 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_MASK      0x3
7177 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_SHIFT     0
7178 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_MASK      0x3
7179 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_SHIFT     2
7180 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_MASK      0x3
7181 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_SHIFT     4
7182 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_MASK      0x3
7183 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_SHIFT     6
7184         u8 flags6;
7185 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_MASK      0x3
7186 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_SHIFT     0
7187 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_MASK      0x3
7188 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_SHIFT     2
7189 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_MASK      0x3
7190 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_SHIFT     4
7191 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_MASK      0x3
7192 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_SHIFT     6
7193         u8 flags7;
7194 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_MASK              0x3
7195 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_SHIFT             0
7196 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_MASK              0x3
7197 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_SHIFT             2
7198 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_MASK         0x3
7199 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT        4
7200 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_MASK             0x1
7201 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_SHIFT            6
7202 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_MASK             0x1
7203 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_SHIFT            7
7204         u8 flags8;
7205 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_MASK             0x1
7206 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_SHIFT            0
7207 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_MASK             0x1
7208 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_SHIFT            1
7209 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_MASK             0x1
7210 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_SHIFT            2
7211 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_MASK             0x1
7212 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_SHIFT            3
7213 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_MASK             0x1
7214 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_SHIFT            4
7215 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_MASK    0x1
7216 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_SHIFT   5
7217 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_MASK             0x1
7218 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_SHIFT            6
7219 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_MASK             0x1
7220 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_SHIFT            7
7221         u8 flags9;
7222 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_MASK    0x1
7223 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_SHIFT   0
7224 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_MASK    0x1
7225 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_SHIFT   1
7226 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_MASK    0x1
7227 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_SHIFT   2
7228 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_MASK    0x1
7229 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_SHIFT   3
7230 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_MASK    0x1
7231 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_SHIFT   4
7232 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_MASK    0x1
7233 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_SHIFT   5
7234 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_MASK    0x1
7235 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_SHIFT   6
7236 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_MASK    0x1
7237 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_SHIFT   7
7238         u8 flags10;
7239 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_MASK            0x1
7240 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_SHIFT           0
7241 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_MASK            0x1
7242 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_SHIFT           1
7243 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_MASK            0x1
7244 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_SHIFT           2
7245 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_MASK            0x1
7246 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_SHIFT           3
7247 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK      0x1
7248 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT     4
7249 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_MASK            0x1
7250 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_SHIFT           5
7251 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_MASK           0x1
7252 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_SHIFT          6
7253 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_MASK           0x1
7254 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_SHIFT          7
7255         u8 flags11;
7256 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_MASK           0x1
7257 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_SHIFT          0
7258 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_MASK           0x1
7259 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_SHIFT          1
7260 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_MASK           0x1
7261 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_SHIFT          2
7262 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_MASK           0x1
7263 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_SHIFT          3
7264 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_MASK           0x1
7265 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_SHIFT          4
7266 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_MASK           0x1
7267 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_SHIFT          5
7268 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK      0x1
7269 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT     6
7270 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_MASK           0x1
7271 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_SHIFT          7
7272         u8 flags12;
7273 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_MASK          0x1
7274 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_SHIFT         0
7275 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_MASK          0x1
7276 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_SHIFT         1
7277 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK      0x1
7278 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT     2
7279 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK      0x1
7280 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT     3
7281 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_MASK          0x1
7282 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_SHIFT         4
7283 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_MASK          0x1
7284 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_SHIFT         5
7285 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_MASK          0x1
7286 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_SHIFT         6
7287 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_MASK          0x1
7288 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_SHIFT         7
7289         u8 flags13;
7290 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_MASK          0x1
7291 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_SHIFT         0
7292 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_MASK          0x1
7293 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_SHIFT         1
7294 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK      0x1
7295 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT     2
7296 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK      0x1
7297 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT     3
7298 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK      0x1
7299 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT     4
7300 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK      0x1
7301 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT     5
7302 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK      0x1
7303 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT     6
7304 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK      0x1
7305 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT     7
7306         u8 flags14;
7307 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_MASK         0x1
7308 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_SHIFT        0
7309 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_MASK             0x1
7310 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_SHIFT            1
7311 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_MASK      0x3
7312 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_SHIFT     2
7313 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_MASK          0x1
7314 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_SHIFT         4
7315 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK  0x1
7316 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5
7317 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23_MASK              0x3
7318 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23_SHIFT             6
7319         u8 byte2;
7320         __le16 physical_q0;
7321         __le16 word1;
7322         __le16 word2;
7323         __le16 word3;
7324         __le16 word4;
7325         __le16 word5;
7326         __le16 conn_dpi;
7327         u8 byte3;
7328         u8 byte4;
7329         u8 byte5;
7330         u8 byte6;
7331         __le32 reg0;
7332         __le32 reg1;
7333         __le32 reg2;
7334         __le32 snd_nxt_psn;
7335         __le32 reg4;
7336 };
7337
7338 struct e4_mstorm_rdma_conn_ag_ctx {
7339         u8 byte0;
7340         u8 byte1;
7341         u8 flags0;
7342 #define E4_MSTORM_RDMA_CONN_AG_CTX_BIT0_MASK    0x1
7343 #define E4_MSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT   0
7344 #define E4_MSTORM_RDMA_CONN_AG_CTX_BIT1_MASK    0x1
7345 #define E4_MSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT   1
7346 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF0_MASK     0x3
7347 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT    2
7348 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF1_MASK     0x3
7349 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT    4
7350 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF2_MASK     0x3
7351 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT    6
7352         u8 flags1;
7353 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK           0x1
7354 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT          0
7355 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK           0x1
7356 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT          1
7357 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK           0x1
7358 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT          2
7359 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK         0x1
7360 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT        3
7361 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK         0x1
7362 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT        4
7363 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK         0x1
7364 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT        5
7365 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK         0x1
7366 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT        6
7367 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK         0x1
7368 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT        7
7369         __le16 word0;
7370         __le16 word1;
7371         __le32 reg0;
7372         __le32 reg1;
7373 };
7374
7375 struct e4_tstorm_rdma_conn_ag_ctx {
7376         u8 reserved0;
7377         u8 byte1;
7378         u8 flags0;
7379 #define E4_TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK    0x1
7380 #define E4_TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT   0
7381 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT1_MASK            0x1
7382 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT           1
7383 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT2_MASK            0x1
7384 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT           2
7385 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT3_MASK            0x1
7386 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT3_SHIFT           3
7387 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT4_MASK            0x1
7388 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT           4
7389 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT5_MASK            0x1
7390 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT           5
7391 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF0_MASK             0x3
7392 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT            6
7393         u8 flags1;
7394 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF1_MASK                     0x3
7395 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT                    0
7396 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF2_MASK                     0x3
7397 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT                    2
7398 #define E4_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK       0x3
7399 #define E4_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT      4
7400 #define E4_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK             0x3
7401 #define E4_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT            6
7402         u8 flags2;
7403 #define E4_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK         0x3
7404 #define E4_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT        0
7405 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF6_MASK                     0x3
7406 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT                    2
7407 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF7_MASK                     0x3
7408 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF7_SHIFT                    4
7409 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF8_MASK                     0x3
7410 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT                    6
7411         u8 flags3;
7412 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF9_MASK                     0x3
7413 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT                    0
7414 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF10_MASK                    0x3
7415 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT                   2
7416 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK                   0x1
7417 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT                  4
7418 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK                   0x1
7419 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT                  5
7420 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK                   0x1
7421 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT                  6
7422 #define E4_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK    0x1
7423 #define E4_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT   7
7424         u8 flags4;
7425 #define E4_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK          0x1
7426 #define E4_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT         0
7427 #define E4_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK      0x1
7428 #define E4_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT     1
7429 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK                   0x1
7430 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT                  2
7431 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF7EN_MASK                   0x1
7432 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF7EN_SHIFT                  3
7433 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK                   0x1
7434 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT                  4
7435 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK                   0x1
7436 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT                  5
7437 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK                  0x1
7438 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT                 6
7439 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK                 0x1
7440 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT                7
7441         u8 flags5;
7442 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK         0x1
7443 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT        0
7444 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK         0x1
7445 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT        1
7446 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK         0x1
7447 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT        2
7448 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK         0x1
7449 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT        3
7450 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK         0x1
7451 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT        4
7452 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK         0x1
7453 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT        5
7454 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK         0x1
7455 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT        6
7456 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK         0x1
7457 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT        7
7458         __le32 reg0;
7459         __le32 reg1;
7460         __le32 reg2;
7461         __le32 reg3;
7462         __le32 reg4;
7463         __le32 reg5;
7464         __le32 reg6;
7465         __le32 reg7;
7466         __le32 reg8;
7467         u8 byte2;
7468         u8 byte3;
7469         __le16 word0;
7470         u8 byte4;
7471         u8 byte5;
7472         __le16 word1;
7473         __le16 word2;
7474         __le16 word3;
7475         __le32 reg9;
7476         __le32 reg10;
7477 };
7478
7479 struct e4_tstorm_rdma_task_ag_ctx {
7480         u8 byte0;
7481         u8 byte1;
7482         __le16 word0;
7483         u8 flags0;
7484 #define E4_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_MASK         0xF
7485 #define E4_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_SHIFT        0
7486 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT0_MASK            0x1
7487 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT0_SHIFT           4
7488 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT1_MASK            0x1
7489 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT           5
7490 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT2_MASK            0x1
7491 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT           6
7492 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT3_MASK            0x1
7493 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT           7
7494         u8 flags1;
7495 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT4_MASK    0x1
7496 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT   0
7497 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT5_MASK    0x1
7498 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT5_SHIFT   1
7499 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0_MASK     0x3
7500 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT    2
7501 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1_MASK     0x3
7502 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT    4
7503 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2_MASK     0x3
7504 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT    6
7505         u8 flags2;
7506 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3_MASK     0x3
7507 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3_SHIFT    0
7508 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4_MASK     0x3
7509 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4_SHIFT    2
7510 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5_MASK     0x3
7511 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5_SHIFT    4
7512 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6_MASK     0x3
7513 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6_SHIFT    6
7514         u8 flags3;
7515 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7_MASK     0x3
7516 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7_SHIFT    0
7517 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK   0x1
7518 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT  2
7519 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK   0x1
7520 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT  3
7521 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK   0x1
7522 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT  4
7523 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3EN_MASK   0x1
7524 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT  5
7525 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4EN_MASK   0x1
7526 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4EN_SHIFT  6
7527 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5EN_MASK   0x1
7528 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5EN_SHIFT  7
7529         u8 flags4;
7530 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6EN_MASK           0x1
7531 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6EN_SHIFT          0
7532 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7EN_MASK           0x1
7533 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7EN_SHIFT          1
7534 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK         0x1
7535 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT        2
7536 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK         0x1
7537 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT        3
7538 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK         0x1
7539 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT        4
7540 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK         0x1
7541 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT        5
7542 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK         0x1
7543 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT        6
7544 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK         0x1
7545 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT        7
7546         u8 byte2;
7547         __le16 word1;
7548         __le32 reg0;
7549         u8 byte3;
7550         u8 byte4;
7551         __le16 word2;
7552         __le16 word3;
7553         __le16 word4;
7554         __le32 reg1;
7555         __le32 reg2;
7556 };
7557
7558 struct e4_ustorm_rdma_conn_ag_ctx {
7559         u8 reserved;
7560         u8 byte1;
7561         u8 flags0;
7562 #define E4_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK    0x1
7563 #define E4_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT   0
7564 #define E4_USTORM_RDMA_CONN_AG_CTX_BIT1_MASK            0x1
7565 #define E4_USTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT           1
7566 #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK     0x3
7567 #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT    2
7568 #define E4_USTORM_RDMA_CONN_AG_CTX_CF1_MASK             0x3
7569 #define E4_USTORM_RDMA_CONN_AG_CTX_CF1_SHIFT            4
7570 #define E4_USTORM_RDMA_CONN_AG_CTX_CF2_MASK             0x3
7571 #define E4_USTORM_RDMA_CONN_AG_CTX_CF2_SHIFT            6
7572         u8 flags1;
7573 #define E4_USTORM_RDMA_CONN_AG_CTX_CF3_MASK             0x3
7574 #define E4_USTORM_RDMA_CONN_AG_CTX_CF3_SHIFT            0
7575 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_MASK    0x3
7576 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT   2
7577 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_MASK       0x3
7578 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_SHIFT      4
7579 #define E4_USTORM_RDMA_CONN_AG_CTX_CF6_MASK             0x3
7580 #define E4_USTORM_RDMA_CONN_AG_CTX_CF6_SHIFT            6
7581         u8 flags2;
7582 #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK          0x1
7583 #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT         0
7584 #define E4_USTORM_RDMA_CONN_AG_CTX_CF1EN_MASK                   0x1
7585 #define E4_USTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT                  1
7586 #define E4_USTORM_RDMA_CONN_AG_CTX_CF2EN_MASK                   0x1
7587 #define E4_USTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT                  2
7588 #define E4_USTORM_RDMA_CONN_AG_CTX_CF3EN_MASK                   0x1
7589 #define E4_USTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT                  3
7590 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK         0x1
7591 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT        4
7592 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_MASK            0x1
7593 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT           5
7594 #define E4_USTORM_RDMA_CONN_AG_CTX_CF6EN_MASK                   0x1
7595 #define E4_USTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT                  6
7596 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_MASK                0x1
7597 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_SHIFT               7
7598         u8 flags3;
7599 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_EN_MASK           0x1
7600 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_EN_SHIFT          0
7601 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK         0x1
7602 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT        1
7603 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK         0x1
7604 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT        2
7605 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK         0x1
7606 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT        3
7607 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK         0x1
7608 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT        4
7609 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK         0x1
7610 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT        5
7611 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK         0x1
7612 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT        6
7613 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK         0x1
7614 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT        7
7615         u8 byte2;
7616         u8 byte3;
7617         __le16 conn_dpi;
7618         __le16 word1;
7619         __le32 cq_cons;
7620         __le32 cq_se_prod;
7621         __le32 cq_prod;
7622         __le32 reg3;
7623         __le16 int_timeout;
7624         __le16 word3;
7625 };
7626
7627 struct e4_xstorm_rdma_conn_ag_ctx {
7628         u8 reserved0;
7629         u8 state;
7630         u8 flags0;
7631 #define E4_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK    0x1
7632 #define E4_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT   0
7633 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT1_MASK            0x1
7634 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT           1
7635 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT2_MASK            0x1
7636 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT           2
7637 #define E4_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_MASK    0x1
7638 #define E4_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_SHIFT   3
7639 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT4_MASK            0x1
7640 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT           4
7641 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT5_MASK            0x1
7642 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT           5
7643 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT6_MASK            0x1
7644 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT6_SHIFT           6
7645 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT7_MASK            0x1
7646 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT7_SHIFT           7
7647         u8 flags1;
7648 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT8_MASK            0x1
7649 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT8_SHIFT           0
7650 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT9_MASK            0x1
7651 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT9_SHIFT           1
7652 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT10_MASK           0x1
7653 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT10_SHIFT          2
7654 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT11_MASK           0x1
7655 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT11_SHIFT          3
7656 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT12_MASK           0x1
7657 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT12_SHIFT          4
7658 #define E4_XSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_MASK    0x1
7659 #define E4_XSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_SHIFT   5
7660 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT14_MASK           0x1
7661 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT14_SHIFT          6
7662 #define E4_XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_MASK    0x1
7663 #define E4_XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_SHIFT   7
7664         u8 flags2;
7665 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF0_MASK     0x3
7666 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT    0
7667 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF1_MASK     0x3
7668 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT    2
7669 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF2_MASK     0x3
7670 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT    4
7671 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF3_MASK     0x3
7672 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF3_SHIFT    6
7673         u8 flags3;
7674 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF4_MASK             0x3
7675 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF4_SHIFT            0
7676 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF5_MASK             0x3
7677 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF5_SHIFT            2
7678 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF6_MASK             0x3
7679 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT            4
7680 #define E4_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK     0x3
7681 #define E4_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT    6
7682         u8 flags4;
7683 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF8_MASK     0x3
7684 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT    0
7685 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF9_MASK     0x3
7686 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT    2
7687 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF10_MASK    0x3
7688 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT   4
7689 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF11_MASK    0x3
7690 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF11_SHIFT   6
7691         u8 flags5;
7692 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF12_MASK    0x3
7693 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF12_SHIFT   0
7694 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF13_MASK    0x3
7695 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF13_SHIFT   2
7696 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF14_MASK    0x3
7697 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF14_SHIFT   4
7698 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF15_MASK    0x3
7699 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF15_SHIFT   6
7700         u8 flags6;
7701 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF16_MASK    0x3
7702 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF16_SHIFT   0
7703 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF17_MASK    0x3
7704 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF17_SHIFT   2
7705 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF18_MASK    0x3
7706 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF18_SHIFT   4
7707 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF19_MASK    0x3
7708 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF19_SHIFT   6
7709         u8 flags7;
7710 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF20_MASK            0x3
7711 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF20_SHIFT           0
7712 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF21_MASK            0x3
7713 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF21_SHIFT           2
7714 #define E4_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_MASK       0x3
7715 #define E4_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_SHIFT      4
7716 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK           0x1
7717 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT          6
7718 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK           0x1
7719 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT          7
7720         u8 flags8;
7721 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK           0x1
7722 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT          0
7723 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF3EN_MASK           0x1
7724 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT          1
7725 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF4EN_MASK           0x1
7726 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF4EN_SHIFT          2
7727 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF5EN_MASK           0x1
7728 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF5EN_SHIFT          3
7729 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK           0x1
7730 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT          4
7731 #define E4_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK  0x1
7732 #define E4_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
7733 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK           0x1
7734 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT          6
7735 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK           0x1
7736 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT          7
7737         u8 flags9;
7738 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK  0x1
7739 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT 0
7740 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF11EN_MASK  0x1
7741 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF11EN_SHIFT 1
7742 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF12EN_MASK  0x1
7743 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF12EN_SHIFT 2
7744 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF13EN_MASK  0x1
7745 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF13EN_SHIFT 3
7746 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF14EN_MASK  0x1
7747 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF14EN_SHIFT 4
7748 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF15EN_MASK  0x1
7749 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF15EN_SHIFT 5
7750 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF16EN_MASK  0x1
7751 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF16EN_SHIFT 6
7752 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF17EN_MASK  0x1
7753 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF17EN_SHIFT 7
7754         u8 flags10;
7755 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF18EN_MASK          0x1
7756 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF18EN_SHIFT         0
7757 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF19EN_MASK          0x1
7758 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF19EN_SHIFT         1
7759 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF20EN_MASK          0x1
7760 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF20EN_SHIFT         2
7761 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF21EN_MASK          0x1
7762 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF21EN_SHIFT         3
7763 #define E4_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_MASK    0x1
7764 #define E4_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_SHIFT   4
7765 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF23EN_MASK          0x1
7766 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF23EN_SHIFT         5
7767 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK         0x1
7768 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT        6
7769 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK         0x1
7770 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT        7
7771         u8 flags11;
7772 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK         0x1
7773 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT        0
7774 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK         0x1
7775 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT        1
7776 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK         0x1
7777 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT        2
7778 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK         0x1
7779 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT        3
7780 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK         0x1
7781 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT        4
7782 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK         0x1
7783 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT        5
7784 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_MASK    0x1
7785 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_SHIFT   6
7786 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE9EN_MASK         0x1
7787 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE9EN_SHIFT        7
7788         u8 flags12;
7789 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE10EN_MASK        0x1
7790 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE10EN_SHIFT       0
7791 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE11EN_MASK        0x1
7792 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE11EN_SHIFT       1
7793 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_MASK    0x1
7794 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_SHIFT   2
7795 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_MASK    0x1
7796 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_SHIFT   3
7797 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE14EN_MASK        0x1
7798 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE14EN_SHIFT       4
7799 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE15EN_MASK        0x1
7800 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE15EN_SHIFT       5
7801 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE16EN_MASK        0x1
7802 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE16EN_SHIFT       6
7803 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE17EN_MASK        0x1
7804 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE17EN_SHIFT       7
7805         u8 flags13;
7806 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE18EN_MASK        0x1
7807 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE18EN_SHIFT       0
7808 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE19EN_MASK        0x1
7809 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE19EN_SHIFT       1
7810 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_MASK    0x1
7811 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_SHIFT   2
7812 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_MASK    0x1
7813 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_SHIFT   3
7814 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_MASK    0x1
7815 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_SHIFT   4
7816 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_MASK    0x1
7817 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_SHIFT   5
7818 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_MASK    0x1
7819 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_SHIFT   6
7820 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_MASK    0x1
7821 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_SHIFT   7
7822         u8 flags14;
7823 #define E4_XSTORM_RDMA_CONN_AG_CTX_MIGRATION_MASK               0x1
7824 #define E4_XSTORM_RDMA_CONN_AG_CTX_MIGRATION_SHIFT              0
7825 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT17_MASK                   0x1
7826 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT17_SHIFT                  1
7827 #define E4_XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_MASK            0x3
7828 #define E4_XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_SHIFT           2
7829 #define E4_XSTORM_RDMA_CONN_AG_CTX_RESERVED_MASK                0x1
7830 #define E4_XSTORM_RDMA_CONN_AG_CTX_RESERVED_SHIFT               4
7831 #define E4_XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK        0x1
7832 #define E4_XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT       5
7833 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF23_MASK                    0x3
7834 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF23_SHIFT                   6
7835         u8 byte2;
7836         __le16 physical_q0;
7837         __le16 word1;
7838         __le16 word2;
7839         __le16 word3;
7840         __le16 word4;
7841         __le16 word5;
7842         __le16 conn_dpi;
7843         u8 byte3;
7844         u8 byte4;
7845         u8 byte5;
7846         u8 byte6;
7847         __le32 reg0;
7848         __le32 reg1;
7849         __le32 reg2;
7850         __le32 snd_nxt_psn;
7851         __le32 reg4;
7852         __le32 reg5;
7853         __le32 reg6;
7854 };
7855
7856 struct e4_ystorm_rdma_conn_ag_ctx {
7857         u8 byte0;
7858         u8 byte1;
7859         u8 flags0;
7860 #define E4_YSTORM_RDMA_CONN_AG_CTX_BIT0_MASK    0x1
7861 #define E4_YSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT   0
7862 #define E4_YSTORM_RDMA_CONN_AG_CTX_BIT1_MASK    0x1
7863 #define E4_YSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT   1
7864 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF0_MASK     0x3
7865 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT    2
7866 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF1_MASK     0x3
7867 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT    4
7868 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF2_MASK     0x3
7869 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT    6
7870         u8 flags1;
7871 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK           0x1
7872 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT          0
7873 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK           0x1
7874 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT          1
7875 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK           0x1
7876 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT          2
7877 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK         0x1
7878 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT        3
7879 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK         0x1
7880 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT        4
7881 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK         0x1
7882 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT        5
7883 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK         0x1
7884 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT        6
7885 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK         0x1
7886 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT        7
7887         u8 byte2;
7888         u8 byte3;
7889         __le16 word0;
7890         __le32 reg0;
7891         __le32 reg1;
7892         __le16 word1;
7893         __le16 word2;
7894         __le16 word3;
7895         __le16 word4;
7896         __le32 reg2;
7897         __le32 reg3;
7898 };
7899
7900 /* The roce storm context of Ystorm */
7901 struct ystorm_roce_conn_st_ctx {
7902         struct regpair temp[2];
7903 };
7904
7905 /* The roce storm context of Mstorm */
7906 struct pstorm_roce_conn_st_ctx {
7907         struct regpair temp[16];
7908 };
7909
7910 /* The roce storm context of Xstorm */
7911 struct xstorm_roce_conn_st_ctx {
7912         struct regpair temp[24];
7913 };
7914
7915 /* The roce storm context of Tstorm */
7916 struct tstorm_roce_conn_st_ctx {
7917         struct regpair temp[30];
7918 };
7919
7920 /* The roce storm context of Mstorm */
7921 struct mstorm_roce_conn_st_ctx {
7922         struct regpair temp[6];
7923 };
7924
7925 /* The roce storm context of Ystorm */
7926 struct ustorm_roce_conn_st_ctx {
7927         struct regpair temp[12];
7928 };
7929
7930 /* roce connection context */
7931 struct e4_roce_conn_context {
7932         struct ystorm_roce_conn_st_ctx ystorm_st_context;
7933         struct regpair ystorm_st_padding[2];
7934         struct pstorm_roce_conn_st_ctx pstorm_st_context;
7935         struct xstorm_roce_conn_st_ctx xstorm_st_context;
7936         struct regpair xstorm_st_padding[2];
7937         struct e4_xstorm_rdma_conn_ag_ctx xstorm_ag_context;
7938         struct e4_tstorm_rdma_conn_ag_ctx tstorm_ag_context;
7939         struct timers_context timer_context;
7940         struct e4_ustorm_rdma_conn_ag_ctx ustorm_ag_context;
7941         struct tstorm_roce_conn_st_ctx tstorm_st_context;
7942         struct mstorm_roce_conn_st_ctx mstorm_st_context;
7943         struct ustorm_roce_conn_st_ctx ustorm_st_context;
7944         struct regpair ustorm_st_padding[2];
7945 };
7946
7947 /* roce create qp requester ramrod data */
7948 struct roce_create_qp_req_ramrod_data {
7949         __le16 flags;
7950 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_MASK                 0x3
7951 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_SHIFT                0
7952 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK         0x1
7953 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT        2
7954 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_MASK               0x1
7955 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_SHIFT              3
7956 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_MASK                         0x7
7957 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_SHIFT                        4
7958 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_MASK                    0x1
7959 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_SHIFT                   7
7960 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK               0xF
7961 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT              8
7962 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK                 0xF
7963 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT                12
7964         u8 max_ord;
7965         u8 traffic_class;
7966         u8 hop_limit;
7967         u8 orq_num_pages;
7968         __le16 p_key;
7969         __le32 flow_label;
7970         __le32 dst_qp_id;
7971         __le32 ack_timeout_val;
7972         __le32 initial_psn;
7973         __le16 mtu;
7974         __le16 pd;
7975         __le16 sq_num_pages;
7976         __le16 low_latency_phy_queue;
7977         struct regpair sq_pbl_addr;
7978         struct regpair orq_pbl_addr;
7979         __le16 local_mac_addr[3];
7980         __le16 remote_mac_addr[3];
7981         __le16 vlan_id;
7982         __le16 udp_src_port;
7983         __le32 src_gid[4];
7984         __le32 dst_gid[4];
7985         struct regpair qp_handle_for_cqe;
7986         struct regpair qp_handle_for_async;
7987         u8 stats_counter_id;
7988         u8 reserved3[7];
7989         __le32 cq_cid;
7990         __le16 regular_latency_phy_queue;
7991         __le16 dpi;
7992 };
7993
7994 /* roce create qp responder ramrod data */
7995 struct roce_create_qp_resp_ramrod_data {
7996         __le16 flags;
7997 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_MASK                0x3
7998 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_SHIFT               0
7999 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK                 0x1
8000 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT                2
8001 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK                 0x1
8002 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT                3
8003 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK                  0x1
8004 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT                 4
8005 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_MASK                    0x1
8006 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_SHIFT                   5
8007 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_MASK        0x1
8008 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_SHIFT       6
8009 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_MASK            0x1
8010 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_SHIFT           7
8011 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_MASK                        0x7
8012 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_SHIFT                       8
8013 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK          0x1F
8014 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT         11
8015         u8 max_ird;
8016         u8 traffic_class;
8017         u8 hop_limit;
8018         u8 irq_num_pages;
8019         __le16 p_key;
8020         __le32 flow_label;
8021         __le32 dst_qp_id;
8022         u8 stats_counter_id;
8023         u8 reserved1;
8024         __le16 mtu;
8025         __le32 initial_psn;
8026         __le16 pd;
8027         __le16 rq_num_pages;
8028         struct rdma_srq_id srq_id;
8029         struct regpair rq_pbl_addr;
8030         struct regpair irq_pbl_addr;
8031         __le16 local_mac_addr[3];
8032         __le16 remote_mac_addr[3];
8033         __le16 vlan_id;
8034         __le16 udp_src_port;
8035         __le32 src_gid[4];
8036         __le32 dst_gid[4];
8037         struct regpair qp_handle_for_cqe;
8038         struct regpair qp_handle_for_async;
8039         __le16 low_latency_phy_queue;
8040         u8 reserved2[6];
8041         __le32 cq_cid;
8042         __le16 regular_latency_phy_queue;
8043         __le16 dpi;
8044 };
8045
8046 /* roce DCQCN received statistics */
8047 struct roce_dcqcn_received_stats {
8048         struct regpair ecn_pkt_rcv;
8049         struct regpair cnp_pkt_rcv;
8050 };
8051
8052 /* roce DCQCN sent statistics */
8053 struct roce_dcqcn_sent_stats {
8054         struct regpair cnp_pkt_sent;
8055 };
8056
8057 /* RoCE destroy qp requester output params */
8058 struct roce_destroy_qp_req_output_params {
8059         __le32 num_bound_mw;
8060         __le32 cq_prod;
8061 };
8062
8063 /* RoCE destroy qp requester ramrod data */
8064 struct roce_destroy_qp_req_ramrod_data {
8065         struct regpair output_params_addr;
8066 };
8067
8068 /* RoCE destroy qp responder output params */
8069 struct roce_destroy_qp_resp_output_params {
8070         __le32 num_invalidated_mw;
8071         __le32 cq_prod;
8072 };
8073
8074 /* RoCE destroy qp responder ramrod data */
8075 struct roce_destroy_qp_resp_ramrod_data {
8076         struct regpair output_params_addr;
8077 };
8078
8079 /* roce special events statistics */
8080 struct roce_events_stats {
8081         __le16 silent_drops;
8082         __le16 rnr_naks_sent;
8083         __le32 retransmit_count;
8084         __le32 icrc_error_count;
8085         __le32 reserved;
8086 };
8087
8088 /* ROCE slow path EQ cmd IDs */
8089 enum roce_event_opcode {
8090         ROCE_EVENT_CREATE_QP = 11,
8091         ROCE_EVENT_MODIFY_QP,
8092         ROCE_EVENT_QUERY_QP,
8093         ROCE_EVENT_DESTROY_QP,
8094         ROCE_EVENT_CREATE_UD_QP,
8095         ROCE_EVENT_DESTROY_UD_QP,
8096         MAX_ROCE_EVENT_OPCODE
8097 };
8098
8099 /* roce func init ramrod data */
8100 struct roce_init_func_params {
8101         u8 ll2_queue_id;
8102         u8 cnp_vlan_priority;
8103         u8 cnp_dscp;
8104         u8 reserved;
8105         __le32 cnp_send_timeout;
8106 };
8107
8108 /* roce func init ramrod data */
8109 struct roce_init_func_ramrod_data {
8110         struct rdma_init_func_ramrod_data rdma;
8111         struct roce_init_func_params roce;
8112 };
8113
8114 /* roce modify qp requester ramrod data */
8115 struct roce_modify_qp_req_ramrod_data {
8116         __le16 flags;
8117 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK             0x1
8118 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT            0
8119 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_MASK             0x1
8120 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_SHIFT            1
8121 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_MASK         0x1
8122 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_SHIFT        2
8123 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_MASK                   0x1
8124 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_SHIFT                  3
8125 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK          0x1
8126 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT         4
8127 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_MASK                 0x1
8128 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_SHIFT                5
8129 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_MASK             0x1
8130 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_SHIFT            6
8131 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_MASK           0x1
8132 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_SHIFT          7
8133 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_MASK             0x1
8134 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_SHIFT            8
8135 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_MASK                     0x1
8136 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_SHIFT                    9
8137 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_MASK                         0x7
8138 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_SHIFT                        10
8139 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PHYSICAL_QUEUES_FLG_MASK         0x1
8140 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PHYSICAL_QUEUES_FLG_SHIFT        13
8141 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_MASK                   0x3
8142 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_SHIFT                  14
8143         u8 fields;
8144 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK       0xF
8145 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT      0
8146 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK         0xF
8147 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT        4
8148         u8 max_ord;
8149         u8 traffic_class;
8150         u8 hop_limit;
8151         __le16 p_key;
8152         __le32 flow_label;
8153         __le32 ack_timeout_val;
8154         __le16 mtu;
8155         __le16 reserved2;
8156         __le32 reserved3[2];
8157         __le16 low_latency_phy_queue;
8158         __le16 regular_latency_phy_queue;
8159         __le32 src_gid[4];
8160         __le32 dst_gid[4];
8161 };
8162
8163 /* roce modify qp responder ramrod data */
8164 struct roce_modify_qp_resp_ramrod_data {
8165         __le16 flags;
8166 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK            0x1
8167 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT           0
8168 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK                 0x1
8169 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT                1
8170 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK                 0x1
8171 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT                2
8172 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK                  0x1
8173 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT                 3
8174 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_MASK                  0x1
8175 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_SHIFT                 4
8176 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK         0x1
8177 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT        5
8178 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_MASK                0x1
8179 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_SHIFT               6
8180 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_MASK                    0x1
8181 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_SHIFT                   7
8182 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_MASK      0x1
8183 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_SHIFT     8
8184 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK            0x1
8185 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT           9
8186 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PHYSICAL_QUEUES_FLG_MASK        0x1
8187 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PHYSICAL_QUEUES_FLG_SHIFT       10
8188 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_MASK                  0x1F
8189 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_SHIFT                 11
8190         u8 fields;
8191 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_MASK                0x7
8192 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_SHIFT               0
8193 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK  0x1F
8194 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT 3
8195         u8 max_ird;
8196         u8 traffic_class;
8197         u8 hop_limit;
8198         __le16 p_key;
8199         __le32 flow_label;
8200         __le16 mtu;
8201         __le16 low_latency_phy_queue;
8202         __le16 regular_latency_phy_queue;
8203         u8 reserved2[6];
8204         __le32 src_gid[4];
8205         __le32 dst_gid[4];
8206 };
8207
8208 /* RoCE query qp requester output params */
8209 struct roce_query_qp_req_output_params {
8210         __le32 psn;
8211         __le32 flags;
8212 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_MASK            0x1
8213 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_SHIFT           0
8214 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_MASK    0x1
8215 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_SHIFT   1
8216 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_MASK          0x3FFFFFFF
8217 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_SHIFT         2
8218 };
8219
8220 /* RoCE query qp requester ramrod data */
8221 struct roce_query_qp_req_ramrod_data {
8222         struct regpair output_params_addr;
8223 };
8224
8225 /* RoCE query qp responder output params */
8226 struct roce_query_qp_resp_output_params {
8227         __le32 psn;
8228         __le32 err_flag;
8229 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_MASK  0x1
8230 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_SHIFT 0
8231 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_MASK  0x7FFFFFFF
8232 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_SHIFT 1
8233 };
8234
8235 /* RoCE query qp responder ramrod data */
8236 struct roce_query_qp_resp_ramrod_data {
8237         struct regpair output_params_addr;
8238 };
8239
8240 /* ROCE ramrod command IDs */
8241 enum roce_ramrod_cmd_id {
8242         ROCE_RAMROD_CREATE_QP = 11,
8243         ROCE_RAMROD_MODIFY_QP,
8244         ROCE_RAMROD_QUERY_QP,
8245         ROCE_RAMROD_DESTROY_QP,
8246         ROCE_RAMROD_CREATE_UD_QP,
8247         ROCE_RAMROD_DESTROY_UD_QP,
8248         MAX_ROCE_RAMROD_CMD_ID
8249 };
8250
8251 struct e4_mstorm_roce_req_conn_ag_ctx {
8252         u8 byte0;
8253         u8 byte1;
8254         u8 flags0;
8255 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK        0x1
8256 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT       0
8257 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK        0x1
8258 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT       1
8259 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK         0x3
8260 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT        2
8261 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK         0x3
8262 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT        4
8263 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK         0x3
8264 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT        6
8265         u8 flags1;
8266 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK       0x1
8267 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT      0
8268 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK       0x1
8269 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT      1
8270 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK       0x1
8271 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT      2
8272 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK     0x1
8273 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT    3
8274 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK     0x1
8275 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT    4
8276 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK     0x1
8277 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT    5
8278 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK     0x1
8279 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT    6
8280 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK     0x1
8281 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT    7
8282         __le16 word0;
8283         __le16 word1;
8284         __le32 reg0;
8285         __le32 reg1;
8286 };
8287
8288 struct e4_mstorm_roce_resp_conn_ag_ctx {
8289         u8 byte0;
8290         u8 byte1;
8291         u8 flags0;
8292 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK       0x1
8293 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT      0
8294 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK       0x1
8295 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT      1
8296 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK        0x3
8297 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT       2
8298 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK        0x3
8299 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT       4
8300 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK        0x3
8301 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT       6
8302         u8 flags1;
8303 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK      0x1
8304 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT     0
8305 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK      0x1
8306 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT     1
8307 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK      0x1
8308 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT     2
8309 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK    0x1
8310 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT   3
8311 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK    0x1
8312 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT   4
8313 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK    0x1
8314 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT   5
8315 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK    0x1
8316 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT   6
8317 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK    0x1
8318 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT   7
8319         __le16 word0;
8320         __le16 word1;
8321         __le32 reg0;
8322         __le32 reg1;
8323 };
8324
8325 struct e4_tstorm_roce_req_conn_ag_ctx {
8326         u8 reserved0;
8327         u8 state;
8328         u8 flags0;
8329 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK                0x1
8330 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT               0
8331 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURRED_MASK           0x1
8332 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURRED_SHIFT          1
8333 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURRED_MASK       0x1
8334 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURRED_SHIFT      2
8335 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_MASK                        0x1
8336 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_SHIFT                       3
8337 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_MASK                0x1
8338 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_SHIFT               4
8339 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_MASK                  0x1
8340 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_SHIFT                 5
8341 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_MASK                    0x3
8342 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_SHIFT                   6
8343         u8 flags1;
8344 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK                         0x3
8345 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT                        0
8346 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_MASK                 0x3
8347 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_SHIFT                2
8348 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK           0x3
8349 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT          4
8350 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK                 0x3
8351 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT                6
8352         u8 flags2;
8353 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK     0x3
8354 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT    0
8355 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_MASK        0x3
8356 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_SHIFT       2
8357 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_MASK   0x3
8358 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_SHIFT  4
8359 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_MASK       0x3
8360 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_SHIFT      6
8361         u8 flags3;
8362 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_MASK     0x3
8363 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_SHIFT    0
8364 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_MASK       0x3
8365 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_SHIFT      2
8366 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_MASK                 0x1
8367 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_SHIFT                4
8368 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK                       0x1
8369 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT                      5
8370 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_MASK              0x1
8371 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_SHIFT             6
8372 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK        0x1
8373 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT       7
8374         u8 flags4;
8375 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK              0x1
8376 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT             0
8377 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK          0x1
8378 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT         1
8379 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_MASK             0x1
8380 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_SHIFT            2
8381 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_MASK        0x1
8382 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_SHIFT       3
8383 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_MASK            0x1
8384 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_SHIFT           4
8385 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_MASK  0x1
8386 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_SHIFT 5
8387 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_MASK    0x1
8388 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_SHIFT   6
8389 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK                     0x1
8390 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT                    7
8391         u8 flags5;
8392 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK             0x1
8393 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT            0
8394 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK             0x1
8395 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT            1
8396 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK             0x1
8397 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT            2
8398 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK             0x1
8399 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT            3
8400 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK             0x1
8401 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT            4
8402 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_MASK      0x1
8403 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_SHIFT     5
8404 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK             0x1
8405 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT            6
8406 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK             0x1
8407 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT            7
8408         __le32 reg0;
8409         __le32 snd_nxt_psn;
8410         __le32 snd_max_psn;
8411         __le32 orq_prod;
8412         __le32 reg4;
8413         __le32 reg5;
8414         __le32 reg6;
8415         __le32 reg7;
8416         __le32 reg8;
8417         u8 tx_cqe_error_type;
8418         u8 orq_cache_idx;
8419         __le16 snd_sq_cons_th;
8420         u8 byte4;
8421         u8 byte5;
8422         __le16 snd_sq_cons;
8423         __le16 conn_dpi;
8424         __le16 word3;
8425         __le32 reg9;
8426         __le32 reg10;
8427 };
8428
8429 struct e4_tstorm_roce_resp_conn_ag_ctx {
8430         u8 byte0;
8431         u8 state;
8432         u8 flags0;
8433 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK               0x1
8434 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT              0
8435 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_MASK  0x1
8436 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_SHIFT 1
8437 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_MASK                       0x1
8438 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_SHIFT                      2
8439 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_MASK                       0x1
8440 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_SHIFT                      3
8441 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_MASK               0x1
8442 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_SHIFT              4
8443 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_MASK                       0x1
8444 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_SHIFT                      5
8445 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK                        0x3
8446 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT                       6
8447         u8 flags1;
8448 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK        0x3
8449 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT       0
8450 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_MASK        0x3
8451 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_SHIFT       2
8452 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK                0x3
8453 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT               4
8454 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK        0x3
8455 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT       6
8456         u8 flags2;
8457 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK    0x3
8458 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT   0
8459 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK                0x3
8460 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT               2
8461 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_MASK                0x3
8462 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_SHIFT               4
8463 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK                0x3
8464 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT               6
8465         u8 flags3;
8466 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK                0x3
8467 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT               0
8468 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK               0x3
8469 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT              2
8470 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK              0x1
8471 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT             4
8472 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK     0x1
8473 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT    5
8474 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_MASK     0x1
8475 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_SHIFT    6
8476 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK              0x1
8477 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT             7
8478         u8 flags4;
8479 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK             0x1
8480 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT            0
8481 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK         0x1
8482 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT        1
8483 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK                      0x1
8484 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT                     2
8485 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_MASK                      0x1
8486 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_SHIFT                     3
8487 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK                      0x1
8488 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT                     4
8489 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK                      0x1
8490 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT                     5
8491 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK                     0x1
8492 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT                    6
8493 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK                    0x1
8494 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT                   7
8495         u8 flags5;
8496 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK            0x1
8497 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT           0
8498 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK            0x1
8499 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT           1
8500 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK            0x1
8501 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT           2
8502 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK            0x1
8503 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT           3
8504 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK            0x1
8505 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT           4
8506 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_MASK         0x1
8507 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_SHIFT        5
8508 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK            0x1
8509 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT           6
8510 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK            0x1
8511 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT           7
8512         __le32 psn_and_rxmit_id_echo;
8513         __le32 reg1;
8514         __le32 reg2;
8515         __le32 reg3;
8516         __le32 reg4;
8517         __le32 reg5;
8518         __le32 reg6;
8519         __le32 reg7;
8520         __le32 reg8;
8521         u8 tx_async_error_type;
8522         u8 byte3;
8523         __le16 rq_cons;
8524         u8 byte4;
8525         u8 byte5;
8526         __le16 rq_prod;
8527         __le16 conn_dpi;
8528         __le16 irq_cons;
8529         __le32 num_invlidated_mw;
8530         __le32 reg10;
8531 };
8532
8533 struct e4_ustorm_roce_req_conn_ag_ctx {
8534         u8 byte0;
8535         u8 byte1;
8536         u8 flags0;
8537 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK        0x1
8538 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT       0
8539 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK        0x1
8540 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT       1
8541 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK         0x3
8542 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT        2
8543 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK         0x3
8544 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT        4
8545 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK         0x3
8546 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT        6
8547         u8 flags1;
8548 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK         0x3
8549 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT        0
8550 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4_MASK         0x3
8551 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4_SHIFT        2
8552 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5_MASK         0x3
8553 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5_SHIFT        4
8554 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6_MASK         0x3
8555 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6_SHIFT        6
8556         u8 flags2;
8557 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK       0x1
8558 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT      0
8559 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK       0x1
8560 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT      1
8561 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK       0x1
8562 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT      2
8563 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK       0x1
8564 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT      3
8565 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_MASK       0x1
8566 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_SHIFT      4
8567 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_MASK       0x1
8568 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_SHIFT      5
8569 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_MASK       0x1
8570 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_SHIFT      6
8571 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK     0x1
8572 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT    7
8573         u8 flags3;
8574 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK     0x1
8575 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT    0
8576 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK     0x1
8577 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT    1
8578 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK     0x1
8579 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT    2
8580 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK     0x1
8581 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT    3
8582 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK     0x1
8583 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT    4
8584 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK     0x1
8585 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT    5
8586 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK     0x1
8587 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT    6
8588 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK     0x1
8589 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT    7
8590         u8 byte2;
8591         u8 byte3;
8592         __le16 word0;
8593         __le16 word1;
8594         __le32 reg0;
8595         __le32 reg1;
8596         __le32 reg2;
8597         __le32 reg3;
8598         __le16 word2;
8599         __le16 word3;
8600 };
8601
8602 struct e4_ustorm_roce_resp_conn_ag_ctx {
8603         u8 byte0;
8604         u8 byte1;
8605         u8 flags0;
8606 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK       0x1
8607 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT      0
8608 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK       0x1
8609 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT      1
8610 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK        0x3
8611 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT       2
8612 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK        0x3
8613 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT       4
8614 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK        0x3
8615 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT       6
8616         u8 flags1;
8617 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK        0x3
8618 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT       0
8619 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4_MASK        0x3
8620 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4_SHIFT       2
8621 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5_MASK        0x3
8622 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5_SHIFT       4
8623 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK        0x3
8624 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT       6
8625         u8 flags2;
8626 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK      0x1
8627 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT     0
8628 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK      0x1
8629 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT     1
8630 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK      0x1
8631 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT     2
8632 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK      0x1
8633 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT     3
8634 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_MASK      0x1
8635 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_SHIFT     4
8636 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_MASK      0x1
8637 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_SHIFT     5
8638 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK      0x1
8639 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT     6
8640 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK    0x1
8641 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT   7
8642         u8 flags3;
8643 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK    0x1
8644 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT   0
8645 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK    0x1
8646 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT   1
8647 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK    0x1
8648 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT   2
8649 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK    0x1
8650 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT   3
8651 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK    0x1
8652 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT   4
8653 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK    0x1
8654 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT   5
8655 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK    0x1
8656 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT   6
8657 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK    0x1
8658 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT   7
8659         u8 byte2;
8660         u8 byte3;
8661         __le16 word0;
8662         __le16 word1;
8663         __le32 reg0;
8664         __le32 reg1;
8665         __le32 reg2;
8666         __le32 reg3;
8667         __le16 word2;
8668         __le16 word3;
8669 };
8670
8671 struct e4_xstorm_roce_req_conn_ag_ctx {
8672         u8 reserved0;
8673         u8 state;
8674         u8 flags0;
8675 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK        0x1
8676 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT       0
8677 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_MASK           0x1
8678 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_SHIFT          1
8679 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_MASK           0x1
8680 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_SHIFT          2
8681 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_MASK        0x1
8682 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_SHIFT       3
8683 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_MASK           0x1
8684 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_SHIFT          4
8685 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_MASK           0x1
8686 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_SHIFT          5
8687 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_MASK           0x1
8688 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_SHIFT          6
8689 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_MASK           0x1
8690 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_SHIFT          7
8691         u8 flags1;
8692 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_MASK           0x1
8693 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_SHIFT          0
8694 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_MASK           0x1
8695 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_SHIFT          1
8696 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_MASK               0x1
8697 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_SHIFT              2
8698 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_MASK               0x1
8699 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_SHIFT              3
8700 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_MASK               0x1
8701 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_SHIFT              4
8702 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_MASK               0x1
8703 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_SHIFT              5
8704 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_MASK         0x1
8705 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_SHIFT        6
8706 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_MASK        0x1
8707 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_SHIFT       7
8708         u8 flags2;
8709 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK         0x3
8710 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT        0
8711 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK         0x3
8712 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT        2
8713 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK         0x3
8714 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT        4
8715 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK         0x3
8716 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT        6
8717         u8 flags3;
8718 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_MASK         0x3
8719 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT        0
8720 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_MASK         0x3
8721 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_SHIFT        2
8722 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_MASK        0x3
8723 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_SHIFT       4
8724 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK         0x3
8725 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT        6
8726         u8 flags4;
8727 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8_MASK         0x3
8728 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8_SHIFT        0
8729 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9_MASK         0x3
8730 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9_SHIFT        2
8731 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_MASK        0x3
8732 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_SHIFT       4
8733 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_MASK        0x3
8734 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_SHIFT       6
8735         u8 flags5;
8736 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_MASK                0x3
8737 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_SHIFT               0
8738 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_MASK                0x3
8739 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_SHIFT               2
8740 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_MASK        0x3
8741 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_SHIFT       4
8742 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_MASK                0x3
8743 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_SHIFT               6
8744         u8 flags6;
8745 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_MASK        0x3
8746 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_SHIFT       0
8747 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_MASK        0x3
8748 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_SHIFT       2
8749 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_MASK        0x3
8750 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_SHIFT       4
8751 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_MASK        0x3
8752 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_SHIFT       6
8753         u8 flags7;
8754 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_MASK        0x3
8755 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_SHIFT       0
8756 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_MASK        0x3
8757 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_SHIFT       2
8758 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_MASK   0x3
8759 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_SHIFT  4
8760 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK       0x1
8761 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT      6
8762 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK       0x1
8763 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT      7
8764         u8 flags8;
8765 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK               0x1
8766 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT              0
8767 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK               0x1
8768 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT              1
8769 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK      0x1
8770 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT     2
8771 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_MASK      0x1
8772 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT     3
8773 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_MASK     0x1
8774 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_SHIFT    4
8775 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK      0x1
8776 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT     5
8777 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8EN_MASK               0x1
8778 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8EN_SHIFT              6
8779 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9EN_MASK               0x1
8780 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9EN_SHIFT              7
8781         u8 flags9;
8782 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_MASK              0x1
8783 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_SHIFT             0
8784 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_MASK              0x1
8785 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_SHIFT             1
8786 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_MASK              0x1
8787 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_SHIFT             2
8788 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_MASK              0x1
8789 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_SHIFT             3
8790 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_MASK     0x1
8791 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_SHIFT    4
8792 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_MASK              0x1
8793 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_SHIFT             5
8794 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_MASK              0x1
8795 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_SHIFT             6
8796 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_MASK              0x1
8797 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_SHIFT             7
8798         u8 flags10;
8799 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_MASK              0x1
8800 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_SHIFT             0
8801 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_MASK              0x1
8802 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_SHIFT             1
8803 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_MASK              0x1
8804 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_SHIFT             2
8805 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_MASK              0x1
8806 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_SHIFT             3
8807 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_MASK        0x1
8808 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_SHIFT       4
8809 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_MASK              0x1
8810 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_SHIFT             5
8811 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK             0x1
8812 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT            6
8813 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK             0x1
8814 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT            7
8815         u8 flags11;
8816 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK             0x1
8817 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT            0
8818 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK             0x1
8819 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT            1
8820 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK             0x1
8821 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT            2
8822 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK             0x1
8823 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT            3
8824 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK             0x1
8825 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT            4
8826 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_MASK  0x1
8827 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_SHIFT 5
8828 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_MASK        0x1
8829 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_SHIFT       6
8830 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_MASK             0x1
8831 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_SHIFT            7
8832         u8 flags12;
8833 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_MASK          0x1
8834 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_SHIFT         0
8835 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_MASK            0x1
8836 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_SHIFT           1
8837 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_MASK        0x1
8838 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_SHIFT       2
8839 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_MASK        0x1
8840 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_SHIFT       3
8841 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_MASK   0x1
8842 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_SHIFT  4
8843 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_MASK            0x1
8844 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_SHIFT           5
8845 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_MASK   0x1
8846 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_SHIFT  6
8847 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_MASK     0x1
8848 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_SHIFT    7
8849         u8 flags13;
8850 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_MASK            0x1
8851 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_SHIFT           0
8852 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_MASK            0x1
8853 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_SHIFT           1
8854 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_MASK        0x1
8855 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_SHIFT       2
8856 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_MASK        0x1
8857 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_SHIFT       3
8858 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_MASK        0x1
8859 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_SHIFT       4
8860 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_MASK        0x1
8861 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_SHIFT       5
8862 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_MASK        0x1
8863 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_SHIFT       6
8864 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_MASK        0x1
8865 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_SHIFT       7
8866         u8 flags14;
8867 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_MASK      0x1
8868 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_SHIFT     0
8869 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_MASK               0x1
8870 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_SHIFT              1
8871 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_MASK        0x3
8872 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_SHIFT       2
8873 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_MASK            0x1
8874 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_SHIFT           4
8875 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK    0x1
8876 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT   5
8877 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_MASK                0x3
8878 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_SHIFT               6
8879         u8 byte2;
8880         __le16 physical_q0;
8881         __le16 word1;
8882         __le16 sq_cmp_cons;
8883         __le16 sq_cons;
8884         __le16 sq_prod;
8885         __le16 word5;
8886         __le16 conn_dpi;
8887         u8 byte3;
8888         u8 byte4;
8889         u8 byte5;
8890         u8 byte6;
8891         __le32 lsn;
8892         __le32 ssn;
8893         __le32 snd_una_psn;
8894         __le32 snd_nxt_psn;
8895         __le32 reg4;
8896         __le32 orq_cons_th;
8897         __le32 orq_cons;
8898 };
8899
8900 struct e4_xstorm_roce_resp_conn_ag_ctx {
8901         u8 reserved0;
8902         u8 state;
8903         u8 flags0;
8904 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK       0x1
8905 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT      0
8906 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_MASK          0x1
8907 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_SHIFT         1
8908 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_MASK          0x1
8909 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_SHIFT         2
8910 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_MASK       0x1
8911 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT      3
8912 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_MASK          0x1
8913 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_SHIFT         4
8914 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_MASK          0x1
8915 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_SHIFT         5
8916 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_MASK          0x1
8917 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_SHIFT         6
8918 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_MASK          0x1
8919 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_SHIFT         7
8920         u8 flags1;
8921 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_MASK          0x1
8922 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_SHIFT         0
8923 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_MASK          0x1
8924 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_SHIFT         1
8925 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_MASK              0x1
8926 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_SHIFT             2
8927 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_MASK              0x1
8928 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_SHIFT             3
8929 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_MASK              0x1
8930 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_SHIFT             4
8931 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_MASK              0x1
8932 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_SHIFT             5
8933 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_MASK        0x1
8934 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_SHIFT       6
8935 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_MASK       0x1
8936 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_SHIFT      7
8937         u8 flags2;
8938 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK        0x3
8939 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT       0
8940 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK        0x3
8941 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT       2
8942 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK        0x3
8943 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT       4
8944 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK        0x3
8945 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT       6
8946         u8 flags3;
8947 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_MASK           0x3
8948 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_SHIFT          0
8949 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK        0x3
8950 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT       2
8951 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_MASK       0x3
8952 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_SHIFT      4
8953 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK        0x3
8954 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT       6
8955         u8 flags4;
8956 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK        0x3
8957 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT       0
8958 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK        0x3
8959 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT       2
8960 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK       0x3
8961 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT      4
8962 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_MASK       0x3
8963 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_SHIFT      6
8964         u8 flags5;
8965 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_MASK       0x3
8966 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_SHIFT      0
8967 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_MASK       0x3
8968 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_SHIFT      2
8969 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_MASK       0x3
8970 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_SHIFT      4
8971 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_MASK       0x3
8972 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_SHIFT      6
8973         u8 flags6;
8974 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_MASK       0x3
8975 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_SHIFT      0
8976 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_MASK       0x3
8977 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_SHIFT      2
8978 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_MASK       0x3
8979 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_SHIFT      4
8980 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_MASK       0x3
8981 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_SHIFT      6
8982         u8 flags7;
8983 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_MASK       0x3
8984 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_SHIFT      0
8985 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_MASK       0x3
8986 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_SHIFT      2
8987 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_MASK  0x3
8988 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_SHIFT 4
8989 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK      0x1
8990 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT     6
8991 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK      0x1
8992 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT     7
8993         u8 flags8;
8994 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK              0x1
8995 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT             0
8996 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK              0x1
8997 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT             1
8998 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_MASK        0x1
8999 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_SHIFT       2
9000 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK     0x1
9001 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT    3
9002 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_MASK    0x1
9003 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_SHIFT   4
9004 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK     0x1
9005 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT    5
9006 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK              0x1
9007 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT             6
9008 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK              0x1
9009 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT             7
9010         u8 flags9;
9011 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK     0x1
9012 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT    0
9013 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_MASK     0x1
9014 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_SHIFT    1
9015 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_MASK     0x1
9016 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_SHIFT    2
9017 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_MASK     0x1
9018 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_SHIFT    3
9019 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_MASK     0x1
9020 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_SHIFT    4
9021 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_MASK     0x1
9022 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_SHIFT    5
9023 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_MASK     0x1
9024 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_SHIFT    6
9025 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_MASK     0x1
9026 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_SHIFT    7
9027         u8 flags10;
9028 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_MASK             0x1
9029 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_SHIFT            0
9030 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_MASK             0x1
9031 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_SHIFT            1
9032 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_MASK             0x1
9033 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_SHIFT            2
9034 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_MASK             0x1
9035 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_SHIFT            3
9036 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_MASK       0x1
9037 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT      4
9038 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_MASK             0x1
9039 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_SHIFT            5
9040 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK            0x1
9041 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT           6
9042 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK            0x1
9043 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT           7
9044         u8 flags11;
9045 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK            0x1
9046 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT           0
9047 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK            0x1
9048 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT           1
9049 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK            0x1
9050 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT           2
9051 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK            0x1
9052 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT           3
9053 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK            0x1
9054 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT           4
9055 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK            0x1
9056 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT           5
9057 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_MASK       0x1
9058 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_SHIFT      6
9059 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_MASK            0x1
9060 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_SHIFT           7
9061         u8 flags12;
9062 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_MASK   0x1
9063 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_SHIFT  0
9064 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE11EN_MASK           0x1
9065 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE11EN_SHIFT          1
9066 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_MASK       0x1
9067 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_SHIFT      2
9068 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_MASK       0x1
9069 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_SHIFT      3
9070 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_MASK           0x1
9071 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_SHIFT          4
9072 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_MASK           0x1
9073 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_SHIFT          5
9074 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_MASK           0x1
9075 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_SHIFT          6
9076 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_MASK           0x1
9077 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_SHIFT          7
9078         u8 flags13;
9079 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_MASK           0x1
9080 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_SHIFT          0
9081 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_MASK           0x1
9082 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_SHIFT          1
9083 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_MASK       0x1
9084 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_SHIFT      2
9085 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_MASK       0x1
9086 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_SHIFT      3
9087 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_MASK       0x1
9088 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_SHIFT      4
9089 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_MASK       0x1
9090 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_SHIFT      5
9091 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_MASK       0x1
9092 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_SHIFT      6
9093 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_MASK       0x1
9094 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_SHIFT      7
9095         u8 flags14;
9096 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_MASK      0x1
9097 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_SHIFT     0
9098 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_MASK      0x1
9099 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_SHIFT     1
9100 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_MASK      0x1
9101 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_SHIFT     2
9102 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_MASK      0x1
9103 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_SHIFT     3
9104 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_MASK      0x1
9105 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_SHIFT     4
9106 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_MASK      0x1
9107 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_SHIFT     5
9108 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_MASK       0x3
9109 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_SHIFT      6
9110         u8 byte2;
9111         __le16 physical_q0;
9112         __le16 irq_prod_shadow;
9113         __le16 word2;
9114         __le16 irq_cons;
9115         __le16 irq_prod;
9116         __le16 e5_reserved1;
9117         __le16 conn_dpi;
9118         u8 rxmit_opcode;
9119         u8 byte4;
9120         u8 byte5;
9121         u8 byte6;
9122         __le32 rxmit_psn_and_id;
9123         __le32 rxmit_bytes_length;
9124         __le32 psn;
9125         __le32 reg3;
9126         __le32 reg4;
9127         __le32 reg5;
9128         __le32 msn_and_syndrome;
9129 };
9130
9131 struct e4_ystorm_roce_req_conn_ag_ctx {
9132         u8 byte0;
9133         u8 byte1;
9134         u8 flags0;
9135 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK        0x1
9136 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT       0
9137 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK        0x1
9138 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT       1
9139 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK         0x3
9140 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT        2
9141 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK         0x3
9142 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT        4
9143 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK         0x3
9144 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT        6
9145         u8 flags1;
9146 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK       0x1
9147 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT      0
9148 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK       0x1
9149 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT      1
9150 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK       0x1
9151 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT      2
9152 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK     0x1
9153 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT    3
9154 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK     0x1
9155 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT    4
9156 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK     0x1
9157 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT    5
9158 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK     0x1
9159 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT    6
9160 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK     0x1
9161 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT    7
9162         u8 byte2;
9163         u8 byte3;
9164         __le16 word0;
9165         __le32 reg0;
9166         __le32 reg1;
9167         __le16 word1;
9168         __le16 word2;
9169         __le16 word3;
9170         __le16 word4;
9171         __le32 reg2;
9172         __le32 reg3;
9173 };
9174
9175 struct e4_ystorm_roce_resp_conn_ag_ctx {
9176         u8 byte0;
9177         u8 byte1;
9178         u8 flags0;
9179 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK       0x1
9180 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT      0
9181 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK       0x1
9182 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT      1
9183 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK        0x3
9184 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT       2
9185 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK        0x3
9186 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT       4
9187 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK        0x3
9188 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT       6
9189         u8 flags1;
9190 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK      0x1
9191 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT     0
9192 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK      0x1
9193 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT     1
9194 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK      0x1
9195 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT     2
9196 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK    0x1
9197 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT   3
9198 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK    0x1
9199 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT   4
9200 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK    0x1
9201 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT   5
9202 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK    0x1
9203 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT   6
9204 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK    0x1
9205 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT   7
9206         u8 byte2;
9207         u8 byte3;
9208         __le16 word0;
9209         __le32 reg0;
9210         __le32 reg1;
9211         __le16 word1;
9212         __le16 word2;
9213         __le16 word3;
9214         __le16 word4;
9215         __le32 reg2;
9216         __le32 reg3;
9217 };
9218
9219 /* Roce doorbell data */
9220 enum roce_flavor {
9221         PLAIN_ROCE,
9222         RROCE_IPV4,
9223         RROCE_IPV6,
9224         MAX_ROCE_FLAVOR
9225 };
9226
9227 /* The iwarp storm context of Ystorm */
9228 struct ystorm_iwarp_conn_st_ctx {
9229         __le32 reserved[4];
9230 };
9231
9232 /* The iwarp storm context of Pstorm */
9233 struct pstorm_iwarp_conn_st_ctx {
9234         __le32 reserved[36];
9235 };
9236
9237 /* The iwarp storm context of Xstorm */
9238 struct xstorm_iwarp_conn_st_ctx {
9239         __le32 reserved[44];
9240 };
9241
9242 struct e4_xstorm_iwarp_conn_ag_ctx {
9243         u8 reserved0;
9244         u8 state;
9245         u8 flags0;
9246 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK   0x1
9247 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT  0
9248 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_MASK   0x1
9249 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_SHIFT  1
9250 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM2_MASK   0x1
9251 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM2_SHIFT  2
9252 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_MASK   0x1
9253 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT  3
9254 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT4_MASK           0x1
9255 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT          4
9256 #define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED2_MASK      0x1
9257 #define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED2_SHIFT     5
9258 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT6_MASK           0x1
9259 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT6_SHIFT          6
9260 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT7_MASK           0x1
9261 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT7_SHIFT          7
9262         u8 flags1;
9263 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT8_MASK                           0x1
9264 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT8_SHIFT                          0
9265 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT9_MASK                           0x1
9266 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT9_SHIFT                          1
9267 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT10_MASK                          0x1
9268 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT10_SHIFT                         2
9269 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT11_MASK                          0x1
9270 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT11_SHIFT                         3
9271 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT12_MASK                          0x1
9272 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT12_SHIFT                         4
9273 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT13_MASK                          0x1
9274 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT13_SHIFT                         5
9275 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT14_MASK                          0x1
9276 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT14_SHIFT                         6
9277 #define E4_XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_MASK 0x1
9278 #define E4_XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_SHIFT 7
9279         u8 flags2;
9280 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF0_MASK                    0x3
9281 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT                   0
9282 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF1_MASK                    0x3
9283 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT                   2
9284 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF2_MASK                    0x3
9285 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT                   4
9286 #define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK         0x3
9287 #define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT        6
9288         u8 flags3;
9289 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF4_MASK    0x3
9290 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT   0
9291 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF5_MASK    0x3
9292 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT   2
9293 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF6_MASK    0x3
9294 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF6_SHIFT   4
9295 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF7_MASK    0x3
9296 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF7_SHIFT   6
9297         u8 flags4;
9298 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF8_MASK    0x3
9299 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT   0
9300 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF9_MASK    0x3
9301 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF9_SHIFT   2
9302 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF10_MASK   0x3
9303 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF10_SHIFT  4
9304 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF11_MASK   0x3
9305 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF11_SHIFT  6
9306         u8 flags5;
9307 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF12_MASK           0x3
9308 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF12_SHIFT          0
9309 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF13_MASK           0x3
9310 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF13_SHIFT          2
9311 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_MASK    0x3
9312 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT   4
9313 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF15_MASK           0x3
9314 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF15_SHIFT          6
9315         u8 flags6;
9316 #define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_MASK 0x3
9317 #define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_SHIFT 0
9318 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF17_MASK                           0x3
9319 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF17_SHIFT                          2
9320 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF18_MASK                           0x3
9321 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF18_SHIFT                          4
9322 #define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_MASK                       0x3
9323 #define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_SHIFT                      6
9324         u8 flags7;
9325 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_MASK       0x3
9326 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_SHIFT      0
9327 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_MASK       0x3
9328 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_SHIFT      2
9329 #define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_MASK      0x3
9330 #define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_SHIFT     4
9331 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK          0x1
9332 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT         6
9333 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK          0x1
9334 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT         7
9335         u8 flags8;
9336 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK                  0x1
9337 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT                 0
9338 #define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK      0x1
9339 #define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT     1
9340 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK                  0x1
9341 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT                 2
9342 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK                  0x1
9343 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF5EN_SHIFT                 3
9344 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK                  0x1
9345 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT                 4
9346 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK                  0x1
9347 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF7EN_SHIFT                 5
9348 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK                  0x1
9349 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF8EN_SHIFT                 6
9350 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF9EN_MASK                  0x1
9351 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF9EN_SHIFT                 7
9352         u8 flags9;
9353 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF10EN_MASK                         0x1
9354 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF10EN_SHIFT                        0
9355 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF11EN_MASK                         0x1
9356 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF11EN_SHIFT                        1
9357 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF12EN_MASK                         0x1
9358 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF12EN_SHIFT                        2
9359 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF13EN_MASK                         0x1
9360 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF13EN_SHIFT                        3
9361 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK                 0x1
9362 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT                4
9363 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF15EN_MASK                         0x1
9364 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF15EN_SHIFT                        5
9365 #define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_MASK 0x1
9366 #define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_SHIFT 6
9367 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF17EN_MASK                         0x1
9368 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF17EN_SHIFT                        7
9369         u8 flags10;
9370 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF18EN_MASK                 0x1
9371 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF18EN_SHIFT                0
9372 #define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_MASK            0x1
9373 #define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT           1
9374 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_MASK            0x1
9375 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT           2
9376 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_MASK            0x1
9377 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_SHIFT           3
9378 #define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_MASK           0x1
9379 #define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT          4
9380 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF23EN_MASK                 0x1
9381 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF23EN_SHIFT                5
9382 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK                0x1
9383 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT               6
9384 #define E4_XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_MASK   0x1
9385 #define E4_XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_SHIFT  7
9386         u8 flags11;
9387 #define E4_XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_MASK  0x1
9388 #define E4_XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT 0
9389 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK        0x1
9390 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT       1
9391 #define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED3_MASK      0x1
9392 #define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED3_SHIFT     2
9393 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK        0x1
9394 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT       3
9395 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK        0x1
9396 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE6EN_SHIFT       4
9397 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK        0x1
9398 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT       5
9399 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_MASK   0x1
9400 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_SHIFT  6
9401 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE9EN_MASK        0x1
9402 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE9EN_SHIFT       7
9403         u8 flags12;
9404 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_MASK   0x1
9405 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_SHIFT  0
9406 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE11EN_MASK               0x1
9407 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE11EN_SHIFT              1
9408 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_MASK           0x1
9409 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_SHIFT          2
9410 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_MASK           0x1
9411 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_SHIFT          3
9412 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_MASK       0x1
9413 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_SHIFT      4
9414 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE15EN_MASK               0x1
9415 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE15EN_SHIFT              5
9416 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE16EN_MASK               0x1
9417 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE16EN_SHIFT              6
9418 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE17EN_MASK               0x1
9419 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE17EN_SHIFT              7
9420         u8 flags13;
9421 #define E4_XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_MASK  0x1
9422 #define E4_XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_SHIFT 0
9423 #define E4_XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_MASK    0x1
9424 #define E4_XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_SHIFT   1
9425 #define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_MASK   0x1
9426 #define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_SHIFT  2
9427 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE21EN_MASK               0x1
9428 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE21EN_SHIFT              3
9429 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_MASK           0x1
9430 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_SHIFT          4
9431 #define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_MASK   0x1
9432 #define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_SHIFT  5
9433 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_MASK           0x1
9434 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_SHIFT          6
9435 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_MASK           0x1
9436 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_SHIFT          7
9437         u8 flags14;
9438 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT16_MASK          0x1
9439 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT16_SHIFT         0
9440 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT17_MASK          0x1
9441 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT17_SHIFT         1
9442 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT18_MASK          0x1
9443 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT18_SHIFT         2
9444 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED1_MASK   0x1
9445 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED1_SHIFT  3
9446 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED2_MASK   0x1
9447 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED2_SHIFT  4
9448 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED3_MASK   0x1
9449 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED3_SHIFT  5
9450 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF23_MASK           0x3
9451 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF23_SHIFT          6
9452         u8 byte2;
9453         __le16 physical_q0;
9454         __le16 physical_q1;
9455         __le16 sq_comp_cons;
9456         __le16 sq_tx_cons;
9457         __le16 sq_prod;
9458         __le16 word5;
9459         __le16 conn_dpi;
9460         u8 byte3;
9461         u8 byte4;
9462         u8 byte5;
9463         u8 byte6;
9464         __le32 reg0;
9465         __le32 reg1;
9466         __le32 reg2;
9467         __le32 more_to_send_seq;
9468         __le32 reg4;
9469         __le32 rewinded_snd_max;
9470         __le32 rd_msn;
9471         __le16 irq_prod_via_msdm;
9472         __le16 irq_cons;
9473         __le16 hq_cons_th_or_mpa_data;
9474         __le16 hq_cons;
9475         __le32 atom_msn;
9476         __le32 orq_cons;
9477         __le32 orq_cons_th;
9478         u8 byte7;
9479         u8 max_ord;
9480         u8 wqe_data_pad_bytes;
9481         u8 former_hq_prod;
9482         u8 irq_prod_via_msem;
9483         u8 byte12;
9484         u8 max_pkt_pdu_size_lo;
9485         u8 max_pkt_pdu_size_hi;
9486         u8 byte15;
9487         u8 e5_reserved;
9488         __le16 e5_reserved4;
9489         __le32 reg10;
9490         __le32 reg11;
9491         __le32 shared_queue_page_addr_lo;
9492         __le32 shared_queue_page_addr_hi;
9493         __le32 reg14;
9494         __le32 reg15;
9495         __le32 reg16;
9496         __le32 reg17;
9497 };
9498
9499 struct e4_tstorm_iwarp_conn_ag_ctx {
9500         u8 reserved0;
9501         u8 state;
9502         u8 flags0;
9503 #define E4_TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK   0x1
9504 #define E4_TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT  0
9505 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT1_MASK           0x1
9506 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT          1
9507 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT2_MASK           0x1
9508 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT2_SHIFT          2
9509 #define E4_TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_MASK   0x1
9510 #define E4_TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_SHIFT  3
9511 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT4_MASK           0x1
9512 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT          4
9513 #define E4_TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_MASK     0x1
9514 #define E4_TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_SHIFT    5
9515 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF0_MASK            0x3
9516 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT           6
9517         u8 flags1;
9518 #define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_MASK             0x3
9519 #define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_SHIFT            0
9520 #define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_MASK         0x3
9521 #define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_SHIFT        2
9522 #define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK         0x3
9523 #define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT        4
9524 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF4_MASK                    0x3
9525 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT                   6
9526         u8 flags2;
9527 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF5_MASK    0x3
9528 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT   0
9529 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF6_MASK    0x3
9530 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF6_SHIFT   2
9531 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF7_MASK    0x3
9532 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF7_SHIFT   4
9533 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF8_MASK    0x3
9534 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT   6
9535         u8 flags3;
9536 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPLETE_MASK 0x3
9537 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPLETE_SHIFT 0
9538 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_MASK        0x3
9539 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_SHIFT       2
9540 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK                          0x1
9541 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT                         4
9542 #define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_MASK                  0x1
9543 #define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_SHIFT                 5
9544 #define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_EN_MASK              0x1
9545 #define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_EN_SHIFT             6
9546 #define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK              0x1
9547 #define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT             7
9548         u8 flags4;
9549 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK                          0x1
9550 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT                         0
9551 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK                          0x1
9552 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF5EN_SHIFT                         1
9553 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK                          0x1
9554 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT                         2
9555 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK                          0x1
9556 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF7EN_SHIFT                         3
9557 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK                          0x1
9558 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF8EN_SHIFT                         4
9559 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPL_EN_MASK 0x1
9560 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPL_EN_SHIFT 5
9561 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_MASK     0x1
9562 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_SHIFT    6
9563 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK                        0x1
9564 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT                       7
9565         u8 flags5;
9566 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK                0x1
9567 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT               0
9568 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK                0x1
9569 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT               1
9570 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK                0x1
9571 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT               2
9572 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK                0x1
9573 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT               3
9574 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK                0x1
9575 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT               4
9576 #define E4_TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_MASK       0x1
9577 #define E4_TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_SHIFT      5
9578 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK                0x1
9579 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT               6
9580 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK                0x1
9581 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE8EN_SHIFT               7
9582         __le32 reg0;
9583         __le32 reg1;
9584         __le32 unaligned_nxt_seq;
9585         __le32 reg3;
9586         __le32 reg4;
9587         __le32 reg5;
9588         __le32 reg6;
9589         __le32 reg7;
9590         __le32 reg8;
9591         u8 orq_cache_idx;
9592         u8 hq_prod;
9593         __le16 sq_tx_cons_th;
9594         u8 orq_prod;
9595         u8 irq_cons;
9596         __le16 sq_tx_cons;
9597         __le16 conn_dpi;
9598         __le16 rq_prod;
9599         __le32 snd_seq;
9600         __le32 last_hq_sequence;
9601 };
9602
9603 /* The iwarp storm context of Tstorm */
9604 struct tstorm_iwarp_conn_st_ctx {
9605         __le32 reserved[60];
9606 };
9607
9608 /* The iwarp storm context of Mstorm */
9609 struct mstorm_iwarp_conn_st_ctx {
9610         __le32 reserved[32];
9611 };
9612
9613 /* The iwarp storm context of Ustorm */
9614 struct ustorm_iwarp_conn_st_ctx {
9615         __le32 reserved[24];
9616 };
9617
9618 /* iwarp connection context */
9619 struct e4_iwarp_conn_context {
9620         struct ystorm_iwarp_conn_st_ctx ystorm_st_context;
9621         struct regpair ystorm_st_padding[2];
9622         struct pstorm_iwarp_conn_st_ctx pstorm_st_context;
9623         struct regpair pstorm_st_padding[2];
9624         struct xstorm_iwarp_conn_st_ctx xstorm_st_context;
9625         struct regpair xstorm_st_padding[2];
9626         struct e4_xstorm_iwarp_conn_ag_ctx xstorm_ag_context;
9627         struct e4_tstorm_iwarp_conn_ag_ctx tstorm_ag_context;
9628         struct timers_context timer_context;
9629         struct e4_ustorm_rdma_conn_ag_ctx ustorm_ag_context;
9630         struct tstorm_iwarp_conn_st_ctx tstorm_st_context;
9631         struct regpair tstorm_st_padding[2];
9632         struct mstorm_iwarp_conn_st_ctx mstorm_st_context;
9633         struct ustorm_iwarp_conn_st_ctx ustorm_st_context;
9634 };
9635
9636 /* iWARP create QP params passed by driver to FW in CreateQP Request Ramrod */
9637 struct iwarp_create_qp_ramrod_data {
9638         u8 flags;
9639 #define IWARP_CREATE_QP_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK    0x1
9640 #define IWARP_CREATE_QP_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT   0
9641 #define IWARP_CREATE_QP_RAMROD_DATA_SIGNALED_COMP_MASK          0x1
9642 #define IWARP_CREATE_QP_RAMROD_DATA_SIGNALED_COMP_SHIFT         1
9643 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_RD_EN_MASK             0x1
9644 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_RD_EN_SHIFT            2
9645 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_WR_EN_MASK             0x1
9646 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_WR_EN_SHIFT            3
9647 #define IWARP_CREATE_QP_RAMROD_DATA_ATOMIC_EN_MASK              0x1
9648 #define IWARP_CREATE_QP_RAMROD_DATA_ATOMIC_EN_SHIFT             4
9649 #define IWARP_CREATE_QP_RAMROD_DATA_SRQ_FLG_MASK                0x1
9650 #define IWARP_CREATE_QP_RAMROD_DATA_SRQ_FLG_SHIFT               5
9651 #define IWARP_CREATE_QP_RAMROD_DATA_RESERVED0_MASK              0x3
9652 #define IWARP_CREATE_QP_RAMROD_DATA_RESERVED0_SHIFT             6
9653         u8 reserved1;
9654         __le16 pd;
9655         __le16 sq_num_pages;
9656         __le16 rq_num_pages;
9657         __le32 reserved3[2];
9658         struct regpair qp_handle_for_cqe;
9659         struct rdma_srq_id srq_id;
9660         __le32 cq_cid_for_sq;
9661         __le32 cq_cid_for_rq;
9662         __le16 dpi;
9663         __le16 physical_q0;
9664         __le16 physical_q1;
9665         u8 reserved2[6];
9666 };
9667
9668 /* iWARP completion queue types */
9669 enum iwarp_eqe_async_opcode {
9670         IWARP_EVENT_TYPE_ASYNC_CONNECT_COMPLETE,
9671         IWARP_EVENT_TYPE_ASYNC_ENHANCED_MPA_REPLY_ARRIVED,
9672         IWARP_EVENT_TYPE_ASYNC_MPA_HANDSHAKE_COMPLETE,
9673         IWARP_EVENT_TYPE_ASYNC_CID_CLEANED,
9674         IWARP_EVENT_TYPE_ASYNC_EXCEPTION_DETECTED,
9675         IWARP_EVENT_TYPE_ASYNC_QP_IN_ERROR_STATE,
9676         IWARP_EVENT_TYPE_ASYNC_CQ_OVERFLOW,
9677         MAX_IWARP_EQE_ASYNC_OPCODE
9678 };
9679
9680 struct iwarp_eqe_data_mpa_async_completion {
9681         __le16 ulp_data_len;
9682         u8 reserved[6];
9683 };
9684
9685 struct iwarp_eqe_data_tcp_async_completion {
9686         __le16 ulp_data_len;
9687         u8 mpa_handshake_mode;
9688         u8 reserved[5];
9689 };
9690
9691 /* iWARP completion queue types */
9692 enum iwarp_eqe_sync_opcode {
9693         IWARP_EVENT_TYPE_TCP_OFFLOAD =
9694         11,
9695         IWARP_EVENT_TYPE_MPA_OFFLOAD,
9696         IWARP_EVENT_TYPE_MPA_OFFLOAD_SEND_RTR,
9697         IWARP_EVENT_TYPE_CREATE_QP,
9698         IWARP_EVENT_TYPE_QUERY_QP,
9699         IWARP_EVENT_TYPE_MODIFY_QP,
9700         IWARP_EVENT_TYPE_DESTROY_QP,
9701         MAX_IWARP_EQE_SYNC_OPCODE
9702 };
9703
9704 /* iWARP EQE completion status */
9705 enum iwarp_fw_return_code {
9706         IWARP_CONN_ERROR_TCP_CONNECT_INVALID_PACKET = 5,
9707         IWARP_CONN_ERROR_TCP_CONNECTION_RST,
9708         IWARP_CONN_ERROR_TCP_CONNECT_TIMEOUT,
9709         IWARP_CONN_ERROR_MPA_ERROR_REJECT,
9710         IWARP_CONN_ERROR_MPA_NOT_SUPPORTED_VER,
9711         IWARP_CONN_ERROR_MPA_RST,
9712         IWARP_CONN_ERROR_MPA_FIN,
9713         IWARP_CONN_ERROR_MPA_RTR_MISMATCH,
9714         IWARP_CONN_ERROR_MPA_INSUF_IRD,
9715         IWARP_CONN_ERROR_MPA_INVALID_PACKET,
9716         IWARP_CONN_ERROR_MPA_LOCAL_ERROR,
9717         IWARP_CONN_ERROR_MPA_TIMEOUT,
9718         IWARP_CONN_ERROR_MPA_TERMINATE,
9719         IWARP_QP_IN_ERROR_GOOD_CLOSE,
9720         IWARP_QP_IN_ERROR_BAD_CLOSE,
9721         IWARP_EXCEPTION_DETECTED_LLP_CLOSED,
9722         IWARP_EXCEPTION_DETECTED_LLP_RESET,
9723         IWARP_EXCEPTION_DETECTED_IRQ_FULL,
9724         IWARP_EXCEPTION_DETECTED_RQ_EMPTY,
9725         IWARP_EXCEPTION_DETECTED_LLP_TIMEOUT,
9726         IWARP_EXCEPTION_DETECTED_REMOTE_PROTECTION_ERROR,
9727         IWARP_EXCEPTION_DETECTED_CQ_OVERFLOW,
9728         IWARP_EXCEPTION_DETECTED_LOCAL_CATASTROPHIC,
9729         IWARP_EXCEPTION_DETECTED_LOCAL_ACCESS_ERROR,
9730         IWARP_EXCEPTION_DETECTED_REMOTE_OPERATION_ERROR,
9731         IWARP_EXCEPTION_DETECTED_TERMINATE_RECEIVED,
9732         MAX_IWARP_FW_RETURN_CODE
9733 };
9734
9735 /* unaligned opaque data received from LL2 */
9736 struct iwarp_init_func_params {
9737         u8 ll2_ooo_q_index;
9738         u8 reserved1[7];
9739 };
9740
9741 /* iwarp func init ramrod data */
9742 struct iwarp_init_func_ramrod_data {
9743         struct rdma_init_func_ramrod_data rdma;
9744         struct tcp_init_params tcp;
9745         struct iwarp_init_func_params iwarp;
9746 };
9747
9748 /* iWARP QP - possible states to transition to */
9749 enum iwarp_modify_qp_new_state_type {
9750         IWARP_MODIFY_QP_STATE_CLOSING = 1,
9751         IWARP_MODIFY_QP_STATE_ERROR = 2,
9752         MAX_IWARP_MODIFY_QP_NEW_STATE_TYPE
9753 };
9754
9755 /* iwarp modify qp responder ramrod data */
9756 struct iwarp_modify_qp_ramrod_data {
9757         __le16 transition_to_state;
9758         __le16 flags;
9759 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_RD_EN_MASK             0x1
9760 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_RD_EN_SHIFT            0
9761 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_WR_EN_MASK             0x1
9762 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_WR_EN_SHIFT            1
9763 #define IWARP_MODIFY_QP_RAMROD_DATA_ATOMIC_EN_MASK              0x1
9764 #define IWARP_MODIFY_QP_RAMROD_DATA_ATOMIC_EN_SHIFT             2
9765 #define IWARP_MODIFY_QP_RAMROD_DATA_STATE_TRANS_EN_MASK         0x1
9766 #define IWARP_MODIFY_QP_RAMROD_DATA_STATE_TRANS_EN_SHIFT        3
9767 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK        0x1
9768 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT       4
9769 #define IWARP_MODIFY_QP_RAMROD_DATA_RESERVED_MASK               0x7FF
9770 #define IWARP_MODIFY_QP_RAMROD_DATA_RESERVED_SHIFT              5
9771         __le32 reserved3[3];
9772         __le32 reserved4[8];
9773 };
9774
9775 /* MPA params for Enhanced mode */
9776 struct mpa_rq_params {
9777         __le32 ird;
9778         __le32 ord;
9779 };
9780
9781 /* MPA host Address-Len for private data */
9782 struct mpa_ulp_buffer {
9783         struct regpair addr;
9784         __le16 len;
9785         __le16 reserved[3];
9786 };
9787
9788 /* iWARP MPA offload params common to Basic and Enhanced modes */
9789 struct mpa_outgoing_params {
9790         u8 crc_needed;
9791         u8 reject;
9792         u8 reserved[6];
9793         struct mpa_rq_params out_rq;
9794         struct mpa_ulp_buffer outgoing_ulp_buffer;
9795 };
9796
9797 /* iWARP MPA offload params passed by driver to FW in MPA Offload Request
9798  * Ramrod.
9799  */
9800 struct iwarp_mpa_offload_ramrod_data {
9801         struct mpa_outgoing_params common;
9802         __le32 tcp_cid;
9803         u8 mode;
9804         u8 tcp_connect_side;
9805         u8 rtr_pref;
9806 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RTR_SUPPORTED_MASK        0x7
9807 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RTR_SUPPORTED_SHIFT       0
9808 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RESERVED1_MASK            0x1F
9809 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RESERVED1_SHIFT           3
9810         u8 reserved2;
9811         struct mpa_ulp_buffer incoming_ulp_buffer;
9812         struct regpair async_eqe_output_buf;
9813         struct regpair handle_for_async;
9814         struct regpair shared_queue_addr;
9815         __le16 rcv_wnd;
9816         u8 stats_counter_id;
9817         u8 reserved3[13];
9818 };
9819
9820 /* iWARP TCP connection offload params passed by driver to FW */
9821 struct iwarp_offload_params {
9822         struct mpa_ulp_buffer incoming_ulp_buffer;
9823         struct regpair async_eqe_output_buf;
9824         struct regpair handle_for_async;
9825         __le16 physical_q0;
9826         __le16 physical_q1;
9827         u8 stats_counter_id;
9828         u8 mpa_mode;
9829         u8 reserved[10];
9830 };
9831
9832 /* iWARP query QP output params */
9833 struct iwarp_query_qp_output_params {
9834         __le32 flags;
9835 #define IWARP_QUERY_QP_OUTPUT_PARAMS_ERROR_FLG_MASK     0x1
9836 #define IWARP_QUERY_QP_OUTPUT_PARAMS_ERROR_FLG_SHIFT    0
9837 #define IWARP_QUERY_QP_OUTPUT_PARAMS_RESERVED0_MASK     0x7FFFFFFF
9838 #define IWARP_QUERY_QP_OUTPUT_PARAMS_RESERVED0_SHIFT    1
9839         u8 reserved1[4];
9840 };
9841
9842 /* iWARP query QP ramrod data */
9843 struct iwarp_query_qp_ramrod_data {
9844         struct regpair output_params_addr;
9845 };
9846
9847 /* iWARP Ramrod Command IDs */
9848 enum iwarp_ramrod_cmd_id {
9849         IWARP_RAMROD_CMD_ID_TCP_OFFLOAD = 11,
9850         IWARP_RAMROD_CMD_ID_MPA_OFFLOAD,
9851         IWARP_RAMROD_CMD_ID_MPA_OFFLOAD_SEND_RTR,
9852         IWARP_RAMROD_CMD_ID_CREATE_QP,
9853         IWARP_RAMROD_CMD_ID_QUERY_QP,
9854         IWARP_RAMROD_CMD_ID_MODIFY_QP,
9855         IWARP_RAMROD_CMD_ID_DESTROY_QP,
9856         MAX_IWARP_RAMROD_CMD_ID
9857 };
9858
9859 /* Per PF iWARP retransmit path statistics */
9860 struct iwarp_rxmit_stats_drv {
9861         struct regpair tx_go_to_slow_start_event_cnt;
9862         struct regpair tx_fast_retransmit_event_cnt;
9863 };
9864
9865 /* iWARP and TCP connection offload params passed by driver to FW in iWARP
9866  * offload ramrod.
9867  */
9868 struct iwarp_tcp_offload_ramrod_data {
9869         struct iwarp_offload_params iwarp;
9870         struct tcp_offload_params_opt2 tcp;
9871 };
9872
9873 /* iWARP MPA negotiation types */
9874 enum mpa_negotiation_mode {
9875         MPA_NEGOTIATION_TYPE_BASIC = 1,
9876         MPA_NEGOTIATION_TYPE_ENHANCED = 2,
9877         MAX_MPA_NEGOTIATION_MODE
9878 };
9879
9880 /* iWARP MPA Enhanced mode RTR types */
9881 enum mpa_rtr_type {
9882         MPA_RTR_TYPE_NONE = 0,
9883         MPA_RTR_TYPE_ZERO_SEND = 1,
9884         MPA_RTR_TYPE_ZERO_WRITE = 2,
9885         MPA_RTR_TYPE_ZERO_SEND_AND_WRITE = 3,
9886         MPA_RTR_TYPE_ZERO_READ = 4,
9887         MPA_RTR_TYPE_ZERO_SEND_AND_READ = 5,
9888         MPA_RTR_TYPE_ZERO_WRITE_AND_READ = 6,
9889         MPA_RTR_TYPE_ZERO_SEND_AND_WRITE_AND_READ = 7,
9890         MAX_MPA_RTR_TYPE
9891 };
9892
9893 /* unaligned opaque data received from LL2 */
9894 struct unaligned_opaque_data {
9895         __le16 first_mpa_offset;
9896         u8 tcp_payload_offset;
9897         u8 flags;
9898 #define UNALIGNED_OPAQUE_DATA_PKT_REACHED_WIN_RIGHT_EDGE_MASK   0x1
9899 #define UNALIGNED_OPAQUE_DATA_PKT_REACHED_WIN_RIGHT_EDGE_SHIFT  0
9900 #define UNALIGNED_OPAQUE_DATA_CONNECTION_CLOSED_MASK            0x1
9901 #define UNALIGNED_OPAQUE_DATA_CONNECTION_CLOSED_SHIFT           1
9902 #define UNALIGNED_OPAQUE_DATA_RESERVED_MASK                     0x3F
9903 #define UNALIGNED_OPAQUE_DATA_RESERVED_SHIFT                    2
9904         __le32 cid;
9905 };
9906
9907 struct e4_mstorm_iwarp_conn_ag_ctx {
9908         u8 reserved;
9909         u8 state;
9910         u8 flags0;
9911 #define E4_MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK           0x1
9912 #define E4_MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT          0
9913 #define E4_MSTORM_IWARP_CONN_AG_CTX_BIT1_MASK                   0x1
9914 #define E4_MSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT                  1
9915 #define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_MASK       0x3
9916 #define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_SHIFT      2
9917 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF1_MASK                    0x3
9918 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT                   4
9919 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF2_MASK                    0x3
9920 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT                   6
9921         u8 flags1;
9922 #define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_MASK    0x1
9923 #define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_SHIFT   0
9924 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK                  0x1
9925 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT                 1
9926 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK                  0x1
9927 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT                 2
9928 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK                0x1
9929 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT               3
9930 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK                0x1
9931 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT               4
9932 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK                0x1
9933 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT               5
9934 #define E4_MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_MASK            0x1
9935 #define E4_MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_SHIFT           6
9936 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK                0x1
9937 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT               7
9938         __le16 rcq_cons;
9939         __le16 rcq_cons_th;
9940         __le32 reg0;
9941         __le32 reg1;
9942 };
9943
9944 struct e4_ustorm_iwarp_conn_ag_ctx {
9945         u8 reserved;
9946         u8 byte1;
9947         u8 flags0;
9948 #define E4_USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK   0x1
9949 #define E4_USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT  0
9950 #define E4_USTORM_IWARP_CONN_AG_CTX_BIT1_MASK           0x1
9951 #define E4_USTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT          1
9952 #define E4_USTORM_IWARP_CONN_AG_CTX_CF0_MASK            0x3
9953 #define E4_USTORM_IWARP_CONN_AG_CTX_CF0_SHIFT           2
9954 #define E4_USTORM_IWARP_CONN_AG_CTX_CF1_MASK            0x3
9955 #define E4_USTORM_IWARP_CONN_AG_CTX_CF1_SHIFT           4
9956 #define E4_USTORM_IWARP_CONN_AG_CTX_CF2_MASK            0x3
9957 #define E4_USTORM_IWARP_CONN_AG_CTX_CF2_SHIFT           6
9958         u8 flags1;
9959 #define E4_USTORM_IWARP_CONN_AG_CTX_CF3_MASK            0x3
9960 #define E4_USTORM_IWARP_CONN_AG_CTX_CF3_SHIFT           0
9961 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_MASK   0x3
9962 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT  2
9963 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_MASK      0x3
9964 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_SHIFT     4
9965 #define E4_USTORM_IWARP_CONN_AG_CTX_CF6_MASK            0x3
9966 #define E4_USTORM_IWARP_CONN_AG_CTX_CF6_SHIFT           6
9967         u8 flags2;
9968 #define E4_USTORM_IWARP_CONN_AG_CTX_CF0EN_MASK                  0x1
9969 #define E4_USTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT                 0
9970 #define E4_USTORM_IWARP_CONN_AG_CTX_CF1EN_MASK                  0x1
9971 #define E4_USTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT                 1
9972 #define E4_USTORM_IWARP_CONN_AG_CTX_CF2EN_MASK                  0x1
9973 #define E4_USTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT                 2
9974 #define E4_USTORM_IWARP_CONN_AG_CTX_CF3EN_MASK                  0x1
9975 #define E4_USTORM_IWARP_CONN_AG_CTX_CF3EN_SHIFT                 3
9976 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK        0x1
9977 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT       4
9978 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_MASK           0x1
9979 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT          5
9980 #define E4_USTORM_IWARP_CONN_AG_CTX_CF6EN_MASK                  0x1
9981 #define E4_USTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT                 6
9982 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_MASK               0x1
9983 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_SHIFT              7
9984         u8 flags3;
9985 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_EN_MASK          0x1
9986 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_EN_SHIFT         0
9987 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK        0x1
9988 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT       1
9989 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK        0x1
9990 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT       2
9991 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK        0x1
9992 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT       3
9993 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK        0x1
9994 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT       4
9995 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK        0x1
9996 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE6EN_SHIFT       5
9997 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK        0x1
9998 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT       6
9999 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK        0x1
10000 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE8EN_SHIFT       7
10001         u8 byte2;
10002         u8 byte3;
10003         __le16 word0;
10004         __le16 word1;
10005         __le32 cq_cons;
10006         __le32 cq_se_prod;
10007         __le32 cq_prod;
10008         __le32 reg3;
10009         __le16 word2;
10010         __le16 word3;
10011 };
10012
10013 struct e4_ystorm_iwarp_conn_ag_ctx {
10014         u8 byte0;
10015         u8 byte1;
10016         u8 flags0;
10017 #define E4_YSTORM_IWARP_CONN_AG_CTX_BIT0_MASK   0x1
10018 #define E4_YSTORM_IWARP_CONN_AG_CTX_BIT0_SHIFT  0
10019 #define E4_YSTORM_IWARP_CONN_AG_CTX_BIT1_MASK   0x1
10020 #define E4_YSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT  1
10021 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF0_MASK    0x3
10022 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT   2
10023 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF1_MASK    0x3
10024 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT   4
10025 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF2_MASK    0x3
10026 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT   6
10027         u8 flags1;
10028 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK          0x1
10029 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT         0
10030 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK          0x1
10031 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT         1
10032 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK          0x1
10033 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT         2
10034 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK        0x1
10035 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT       3
10036 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK        0x1
10037 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT       4
10038 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK        0x1
10039 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT       5
10040 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK        0x1
10041 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT       6
10042 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK        0x1
10043 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT       7
10044         u8 byte2;
10045         u8 byte3;
10046         __le16 word0;
10047         __le32 reg0;
10048         __le32 reg1;
10049         __le16 word1;
10050         __le16 word2;
10051         __le16 word3;
10052         __le16 word4;
10053         __le32 reg2;
10054         __le32 reg3;
10055 };
10056
10057 /* The fcoe storm context of Ystorm */
10058 struct ystorm_fcoe_conn_st_ctx {
10059         u8 func_mode;
10060         u8 cos;
10061         u8 conf_version;
10062         u8 eth_hdr_size;
10063         __le16 stat_ram_addr;
10064         __le16 mtu;
10065         __le16 max_fc_payload_len;
10066         __le16 tx_max_fc_pay_len;
10067         u8 fcp_cmd_size;
10068         u8 fcp_rsp_size;
10069         __le16 mss;
10070         struct regpair reserved;
10071         __le16 min_frame_size;
10072         u8 protection_info_flags;
10073 #define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK         0x1
10074 #define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT        0
10075 #define YSTORM_FCOE_CONN_ST_CTX_VALID_MASK                      0x1
10076 #define YSTORM_FCOE_CONN_ST_CTX_VALID_SHIFT                     1
10077 #define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_MASK                  0x3F
10078 #define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_SHIFT                 2
10079         u8 dst_protection_per_mss;
10080         u8 src_protection_per_mss;
10081         u8 ptu_log_page_size;
10082         u8 flags;
10083 #define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK    0x1
10084 #define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT   0
10085 #define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK    0x1
10086 #define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_SHIFT   1
10087 #define YSTORM_FCOE_CONN_ST_CTX_RSRV_MASK               0x3F
10088 #define YSTORM_FCOE_CONN_ST_CTX_RSRV_SHIFT              2
10089         u8 fcp_xfer_size;
10090 };
10091
10092 /* FCoE 16-bits vlan structure */
10093 struct fcoe_vlan_fields {
10094         __le16 fields;
10095 #define FCOE_VLAN_FIELDS_VID_MASK       0xFFF
10096 #define FCOE_VLAN_FIELDS_VID_SHIFT      0
10097 #define FCOE_VLAN_FIELDS_CLI_MASK       0x1
10098 #define FCOE_VLAN_FIELDS_CLI_SHIFT      12
10099 #define FCOE_VLAN_FIELDS_PRI_MASK       0x7
10100 #define FCOE_VLAN_FIELDS_PRI_SHIFT      13
10101 };
10102
10103 /* FCoE 16-bits vlan union */
10104 union fcoe_vlan_field_union {
10105         struct fcoe_vlan_fields fields;
10106         __le16 val;
10107 };
10108
10109 /* FCoE 16-bits vlan, vif union */
10110 union fcoe_vlan_vif_field_union {
10111         union fcoe_vlan_field_union vlan;
10112         __le16 vif;
10113 };
10114
10115 /* Ethernet context section */
10116 struct pstorm_fcoe_eth_context_section {
10117         u8 remote_addr_3;
10118         u8 remote_addr_2;
10119         u8 remote_addr_1;
10120         u8 remote_addr_0;
10121         u8 local_addr_1;
10122         u8 local_addr_0;
10123         u8 remote_addr_5;
10124         u8 remote_addr_4;
10125         u8 local_addr_5;
10126         u8 local_addr_4;
10127         u8 local_addr_3;
10128         u8 local_addr_2;
10129         union fcoe_vlan_vif_field_union vif_outer_vlan;
10130         __le16 vif_outer_eth_type;
10131         union fcoe_vlan_vif_field_union inner_vlan;
10132         __le16 inner_eth_type;
10133 };
10134
10135 /* The fcoe storm context of Pstorm */
10136 struct pstorm_fcoe_conn_st_ctx {
10137         u8 func_mode;
10138         u8 cos;
10139         u8 conf_version;
10140         u8 rsrv;
10141         __le16 stat_ram_addr;
10142         __le16 mss;
10143         struct regpair abts_cleanup_addr;
10144         struct pstorm_fcoe_eth_context_section eth;
10145         u8 sid_2;
10146         u8 sid_1;
10147         u8 sid_0;
10148         u8 flags;
10149 #define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_MASK                 0x1
10150 #define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_SHIFT                0
10151 #define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_MASK         0x1
10152 #define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_SHIFT        1
10153 #define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK            0x1
10154 #define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT           2
10155 #define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK            0x1
10156 #define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_SHIFT           3
10157 #define PSTORM_FCOE_CONN_ST_CTX_SINGLE_VLAN_FLAG_MASK           0x1
10158 #define PSTORM_FCOE_CONN_ST_CTX_SINGLE_VLAN_FLAG_SHIFT          4
10159 #define PSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK                   0x7
10160 #define PSTORM_FCOE_CONN_ST_CTX_RESERVED_SHIFT                  5
10161         u8 did_2;
10162         u8 did_1;
10163         u8 did_0;
10164         u8 src_mac_index;
10165         __le16 rec_rr_tov_val;
10166         u8 q_relative_offset;
10167         u8 reserved1;
10168 };
10169
10170 /* The fcoe storm context of Xstorm */
10171 struct xstorm_fcoe_conn_st_ctx {
10172         u8 func_mode;
10173         u8 src_mac_index;
10174         u8 conf_version;
10175         u8 cached_wqes_avail;
10176         __le16 stat_ram_addr;
10177         u8 flags;
10178 #define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_MASK                0x1
10179 #define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_SHIFT               0
10180 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK            0x1
10181 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT           1
10182 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_MASK       0x1
10183 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_SHIFT      2
10184 #define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_MASK         0x3
10185 #define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_SHIFT        3
10186 #define XSTORM_FCOE_CONN_ST_CTX_RSRV_MASK                       0x7
10187 #define XSTORM_FCOE_CONN_ST_CTX_RSRV_SHIFT                      5
10188         u8 cached_wqes_offset;
10189         u8 reserved2;
10190         u8 eth_hdr_size;
10191         u8 seq_id;
10192         u8 max_conc_seqs;
10193         __le16 num_pages_in_pbl;
10194         __le16 reserved;
10195         struct regpair sq_pbl_addr;
10196         struct regpair sq_curr_page_addr;
10197         struct regpair sq_next_page_addr;
10198         struct regpair xferq_pbl_addr;
10199         struct regpair xferq_curr_page_addr;
10200         struct regpair xferq_next_page_addr;
10201         struct regpair respq_pbl_addr;
10202         struct regpair respq_curr_page_addr;
10203         struct regpair respq_next_page_addr;
10204         __le16 mtu;
10205         __le16 tx_max_fc_pay_len;
10206         __le16 max_fc_payload_len;
10207         __le16 min_frame_size;
10208         __le16 sq_pbl_next_index;
10209         __le16 respq_pbl_next_index;
10210         u8 fcp_cmd_byte_credit;
10211         u8 fcp_rsp_byte_credit;
10212         __le16 protection_info;
10213 #define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_MASK            0x1
10214 #define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_SHIFT           0
10215 #define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK         0x1
10216 #define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT        1
10217 #define XSTORM_FCOE_CONN_ST_CTX_VALID_MASK                      0x1
10218 #define XSTORM_FCOE_CONN_ST_CTX_VALID_SHIFT                     2
10219 #define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_MASK         0x1
10220 #define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_SHIFT        3
10221 #define XSTORM_FCOE_CONN_ST_CTX_RESERVED3_MASK                  0xF
10222 #define XSTORM_FCOE_CONN_ST_CTX_RESERVED3_SHIFT                 4
10223 #define XSTORM_FCOE_CONN_ST_CTX_DST_PROTECTION_PER_MSS_MASK     0xFF
10224 #define XSTORM_FCOE_CONN_ST_CTX_DST_PROTECTION_PER_MSS_SHIFT    8
10225         __le16 xferq_pbl_next_index;
10226         __le16 page_size;
10227         u8 mid_seq;
10228         u8 fcp_xfer_byte_credit;
10229         u8 reserved1[2];
10230         struct fcoe_wqe cached_wqes[16];
10231 };
10232
10233 struct e4_xstorm_fcoe_conn_ag_ctx {
10234         u8 reserved0;
10235         u8 state;
10236         u8 flags0;
10237 #define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK    0x1
10238 #define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT   0
10239 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED1_MASK       0x1
10240 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED1_SHIFT      1
10241 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED2_MASK       0x1
10242 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED2_SHIFT      2
10243 #define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_MASK    0x1
10244 #define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT   3
10245 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED3_MASK       0x1
10246 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED3_SHIFT      4
10247 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED4_MASK       0x1
10248 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED4_SHIFT      5
10249 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED5_MASK       0x1
10250 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED5_SHIFT      6
10251 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED6_MASK       0x1
10252 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED6_SHIFT      7
10253         u8 flags1;
10254 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED7_MASK       0x1
10255 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED7_SHIFT      0
10256 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED8_MASK       0x1
10257 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED8_SHIFT      1
10258 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED9_MASK       0x1
10259 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED9_SHIFT      2
10260 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT11_MASK           0x1
10261 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT11_SHIFT          3
10262 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT12_MASK           0x1
10263 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT12_SHIFT          4
10264 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT13_MASK           0x1
10265 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT13_SHIFT          5
10266 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT14_MASK           0x1
10267 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT14_SHIFT          6
10268 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT15_MASK           0x1
10269 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT15_SHIFT          7
10270         u8 flags2;
10271 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF0_MASK     0x3
10272 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT    0
10273 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF1_MASK     0x3
10274 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT    2
10275 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF2_MASK     0x3
10276 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT    4
10277 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF3_MASK     0x3
10278 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF3_SHIFT    6
10279         u8 flags3;
10280 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF4_MASK     0x3
10281 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT    0
10282 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF5_MASK     0x3
10283 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT    2
10284 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF6_MASK     0x3
10285 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT    4
10286 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF7_MASK     0x3
10287 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT    6
10288         u8 flags4;
10289 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF8_MASK     0x3
10290 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT    0
10291 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF9_MASK     0x3
10292 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT    2
10293 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF10_MASK    0x3
10294 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT   4
10295 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF11_MASK    0x3
10296 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF11_SHIFT   6
10297         u8 flags5;
10298 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF12_MASK    0x3
10299 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF12_SHIFT   0
10300 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF13_MASK    0x3
10301 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF13_SHIFT   2
10302 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF14_MASK    0x3
10303 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF14_SHIFT   4
10304 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF15_MASK    0x3
10305 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF15_SHIFT   6
10306         u8 flags6;
10307 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF16_MASK    0x3
10308 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF16_SHIFT   0
10309 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF17_MASK    0x3
10310 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF17_SHIFT   2
10311 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF18_MASK    0x3
10312 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF18_SHIFT   4
10313 #define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_MASK   0x3
10314 #define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_SHIFT  6
10315         u8 flags7;
10316 #define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_MASK        0x3
10317 #define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_SHIFT       0
10318 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED10_MASK      0x3
10319 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED10_SHIFT     2
10320 #define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_MASK       0x3
10321 #define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_SHIFT      4
10322 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK           0x1
10323 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT          6
10324 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK           0x1
10325 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT          7
10326         u8 flags8;
10327 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK   0x1
10328 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT  0
10329 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF3EN_MASK   0x1
10330 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT  1
10331 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK   0x1
10332 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT  2
10333 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK   0x1
10334 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT  3
10335 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK   0x1
10336 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT  4
10337 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK   0x1
10338 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT  5
10339 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK   0x1
10340 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT  6
10341 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK   0x1
10342 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT  7
10343         u8 flags9;
10344 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK  0x1
10345 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT 0
10346 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF11EN_MASK  0x1
10347 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF11EN_SHIFT 1
10348 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF12EN_MASK  0x1
10349 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF12EN_SHIFT 2
10350 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF13EN_MASK  0x1
10351 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF13EN_SHIFT 3
10352 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF14EN_MASK  0x1
10353 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF14EN_SHIFT 4
10354 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF15EN_MASK  0x1
10355 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF15EN_SHIFT 5
10356 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF16EN_MASK  0x1
10357 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF16EN_SHIFT 6
10358 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF17EN_MASK  0x1
10359 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF17EN_SHIFT 7
10360         u8 flags10;
10361 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF18EN_MASK          0x1
10362 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF18EN_SHIFT         0
10363 #define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_MASK        0x1
10364 #define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_SHIFT       1
10365 #define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_MASK     0x1
10366 #define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT    2
10367 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED11_MASK      0x1
10368 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED11_SHIFT     3
10369 #define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_MASK    0x1
10370 #define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT   4
10371 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF23EN_MASK          0x1
10372 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF23EN_SHIFT         5
10373 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED12_MASK      0x1
10374 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED12_SHIFT     6
10375 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED13_MASK      0x1
10376 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED13_SHIFT     7
10377         u8 flags11;
10378 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED14_MASK              0x1
10379 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED14_SHIFT             0
10380 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED15_MASK              0x1
10381 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED15_SHIFT             1
10382 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED16_MASK              0x1
10383 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED16_SHIFT             2
10384 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK                 0x1
10385 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT                3
10386 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK                 0x1
10387 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT                4
10388 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK                 0x1
10389 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT                5
10390 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_MASK            0x1
10391 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_SHIFT           6
10392 #define E4_XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_MASK       0x1
10393 #define E4_XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_SHIFT      7
10394         u8 flags12;
10395 #define E4_XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_MASK  0x1
10396 #define E4_XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_SHIFT 0
10397 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE11EN_MASK        0x1
10398 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE11EN_SHIFT       1
10399 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_MASK    0x1
10400 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_SHIFT   2
10401 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_MASK    0x1
10402 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_SHIFT   3
10403 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE14EN_MASK        0x1
10404 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE14EN_SHIFT       4
10405 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE15EN_MASK        0x1
10406 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE15EN_SHIFT       5
10407 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE16EN_MASK        0x1
10408 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE16EN_SHIFT       6
10409 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE17EN_MASK        0x1
10410 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE17EN_SHIFT       7
10411         u8 flags13;
10412 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_MASK       0x1
10413 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_SHIFT      0
10414 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE19EN_MASK                0x1
10415 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE19EN_SHIFT               1
10416 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_MASK            0x1
10417 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_SHIFT           2
10418 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_MASK            0x1
10419 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_SHIFT           3
10420 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_MASK            0x1
10421 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_SHIFT           4
10422 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_MASK            0x1
10423 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_SHIFT           5
10424 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_MASK            0x1
10425 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_SHIFT           6
10426 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_MASK            0x1
10427 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_SHIFT           7
10428         u8 flags14;
10429 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT16_MASK   0x1
10430 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT16_SHIFT  0
10431 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT17_MASK   0x1
10432 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT17_SHIFT  1
10433 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT18_MASK   0x1
10434 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT18_SHIFT  2
10435 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT19_MASK   0x1
10436 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT19_SHIFT  3
10437 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT20_MASK   0x1
10438 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT20_SHIFT  4
10439 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT21_MASK   0x1
10440 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT21_SHIFT  5
10441 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF23_MASK    0x3
10442 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF23_SHIFT   6
10443         u8 byte2;
10444         __le16 physical_q0;
10445         __le16 word1;
10446         __le16 word2;
10447         __le16 sq_cons;
10448         __le16 sq_prod;
10449         __le16 xferq_prod;
10450         __le16 xferq_cons;
10451         u8 byte3;
10452         u8 byte4;
10453         u8 byte5;
10454         u8 byte6;
10455         __le32 remain_io;
10456         __le32 reg1;
10457         __le32 reg2;
10458         __le32 reg3;
10459         __le32 reg4;
10460         __le32 reg5;
10461         __le32 reg6;
10462         __le16 respq_prod;
10463         __le16 respq_cons;
10464         __le16 word9;
10465         __le16 word10;
10466         __le32 reg7;
10467         __le32 reg8;
10468 };
10469
10470 /* The fcoe storm context of Ustorm */
10471 struct ustorm_fcoe_conn_st_ctx {
10472         struct regpair respq_pbl_addr;
10473         __le16 num_pages_in_pbl;
10474         u8 ptu_log_page_size;
10475         u8 log_page_size;
10476         __le16 respq_prod;
10477         u8 reserved[2];
10478 };
10479
10480 struct e4_tstorm_fcoe_conn_ag_ctx {
10481         u8 reserved0;
10482         u8 state;
10483         u8 flags0;
10484 #define E4_TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK    0x1
10485 #define E4_TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT   0
10486 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT1_MASK            0x1
10487 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT           1
10488 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT2_MASK            0x1
10489 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT2_SHIFT           2
10490 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT3_MASK            0x1
10491 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT3_SHIFT           3
10492 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT4_MASK            0x1
10493 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT4_SHIFT           4
10494 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT5_MASK            0x1
10495 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT5_SHIFT           5
10496 #define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_MASK  0x3
10497 #define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_SHIFT 6
10498         u8 flags1;
10499 #define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_MASK             0x3
10500 #define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT            0
10501 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF2_MASK                     0x3
10502 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT                    2
10503 #define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK       0x3
10504 #define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT      4
10505 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF4_MASK                     0x3
10506 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT                    6
10507         u8 flags2;
10508 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF5_MASK     0x3
10509 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT    0
10510 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF6_MASK     0x3
10511 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT    2
10512 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF7_MASK     0x3
10513 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT    4
10514 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF8_MASK     0x3
10515 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT    6
10516         u8 flags3;
10517 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF9_MASK                     0x3
10518 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT                    0
10519 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF10_MASK                    0x3
10520 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT                   2
10521 #define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_MASK       0x1
10522 #define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_SHIFT      4
10523 #define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK          0x1
10524 #define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT         5
10525 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK                   0x1
10526 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT                  6
10527 #define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK    0x1
10528 #define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT   7
10529         u8 flags4;
10530 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK           0x1
10531 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT          0
10532 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK           0x1
10533 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT          1
10534 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK           0x1
10535 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT          2
10536 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK           0x1
10537 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT          3
10538 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK           0x1
10539 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT          4
10540 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK           0x1
10541 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT          5
10542 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK          0x1
10543 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT         6
10544 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK         0x1
10545 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT        7
10546         u8 flags5;
10547 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK         0x1
10548 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT        0
10549 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK         0x1
10550 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT        1
10551 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK         0x1
10552 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT        2
10553 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK         0x1
10554 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT        3
10555 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK         0x1
10556 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT        4
10557 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK         0x1
10558 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT        5
10559 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK         0x1
10560 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT        6
10561 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK         0x1
10562 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT        7
10563         __le32 reg0;
10564         __le32 reg1;
10565 };
10566
10567 struct e4_ustorm_fcoe_conn_ag_ctx {
10568         u8 byte0;
10569         u8 byte1;
10570         u8 flags0;
10571 #define E4_USTORM_FCOE_CONN_AG_CTX_BIT0_MASK    0x1
10572 #define E4_USTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT   0
10573 #define E4_USTORM_FCOE_CONN_AG_CTX_BIT1_MASK    0x1
10574 #define E4_USTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT   1
10575 #define E4_USTORM_FCOE_CONN_AG_CTX_CF0_MASK     0x3
10576 #define E4_USTORM_FCOE_CONN_AG_CTX_CF0_SHIFT    2
10577 #define E4_USTORM_FCOE_CONN_AG_CTX_CF1_MASK     0x3
10578 #define E4_USTORM_FCOE_CONN_AG_CTX_CF1_SHIFT    4
10579 #define E4_USTORM_FCOE_CONN_AG_CTX_CF2_MASK     0x3
10580 #define E4_USTORM_FCOE_CONN_AG_CTX_CF2_SHIFT    6
10581         u8 flags1;
10582 #define E4_USTORM_FCOE_CONN_AG_CTX_CF3_MASK     0x3
10583 #define E4_USTORM_FCOE_CONN_AG_CTX_CF3_SHIFT    0
10584 #define E4_USTORM_FCOE_CONN_AG_CTX_CF4_MASK     0x3
10585 #define E4_USTORM_FCOE_CONN_AG_CTX_CF4_SHIFT    2
10586 #define E4_USTORM_FCOE_CONN_AG_CTX_CF5_MASK     0x3
10587 #define E4_USTORM_FCOE_CONN_AG_CTX_CF5_SHIFT    4
10588 #define E4_USTORM_FCOE_CONN_AG_CTX_CF6_MASK     0x3
10589 #define E4_USTORM_FCOE_CONN_AG_CTX_CF6_SHIFT    6
10590         u8 flags2;
10591 #define E4_USTORM_FCOE_CONN_AG_CTX_CF0EN_MASK           0x1
10592 #define E4_USTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT          0
10593 #define E4_USTORM_FCOE_CONN_AG_CTX_CF1EN_MASK           0x1
10594 #define E4_USTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT          1
10595 #define E4_USTORM_FCOE_CONN_AG_CTX_CF2EN_MASK           0x1
10596 #define E4_USTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT          2
10597 #define E4_USTORM_FCOE_CONN_AG_CTX_CF3EN_MASK           0x1
10598 #define E4_USTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT          3
10599 #define E4_USTORM_FCOE_CONN_AG_CTX_CF4EN_MASK           0x1
10600 #define E4_USTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT          4
10601 #define E4_USTORM_FCOE_CONN_AG_CTX_CF5EN_MASK           0x1
10602 #define E4_USTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT          5
10603 #define E4_USTORM_FCOE_CONN_AG_CTX_CF6EN_MASK           0x1
10604 #define E4_USTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT          6
10605 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK         0x1
10606 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT        7
10607         u8 flags3;
10608 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK         0x1
10609 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT        0
10610 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK         0x1
10611 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT        1
10612 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK         0x1
10613 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT        2
10614 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK         0x1
10615 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT        3
10616 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK         0x1
10617 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT        4
10618 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK         0x1
10619 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT        5
10620 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK         0x1
10621 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT        6
10622 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK         0x1
10623 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT        7
10624         u8 byte2;
10625         u8 byte3;
10626         __le16 word0;
10627         __le16 word1;
10628         __le32 reg0;
10629         __le32 reg1;
10630         __le32 reg2;
10631         __le32 reg3;
10632         __le16 word2;
10633         __le16 word3;
10634 };
10635
10636 /* The fcoe storm context of Tstorm */
10637 struct tstorm_fcoe_conn_st_ctx {
10638         __le16 stat_ram_addr;
10639         __le16 rx_max_fc_payload_len;
10640         __le16 e_d_tov_val;
10641         u8 flags;
10642 #define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_MASK        0x1
10643 #define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_SHIFT       0
10644 #define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_MASK       0x1
10645 #define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_SHIFT      1
10646 #define TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_MASK          0x3F
10647 #define TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_SHIFT         2
10648         u8 timers_cleanup_invocation_cnt;
10649         __le32 reserved1[2];
10650         __le32 dst_mac_address_bytes_0_to_3;
10651         __le16 dst_mac_address_bytes_4_to_5;
10652         __le16 ramrod_echo;
10653         u8 flags1;
10654 #define TSTORM_FCOE_CONN_ST_CTX_MODE_MASK       0x3
10655 #define TSTORM_FCOE_CONN_ST_CTX_MODE_SHIFT      0
10656 #define TSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK   0x3F
10657 #define TSTORM_FCOE_CONN_ST_CTX_RESERVED_SHIFT  2
10658         u8 cq_relative_offset;
10659         u8 cmdq_relative_offset;
10660         u8 bdq_resource_id;
10661         u8 reserved0[4];
10662 };
10663
10664 struct e4_mstorm_fcoe_conn_ag_ctx {
10665         u8 byte0;
10666         u8 byte1;
10667         u8 flags0;
10668 #define E4_MSTORM_FCOE_CONN_AG_CTX_BIT0_MASK    0x1
10669 #define E4_MSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT   0
10670 #define E4_MSTORM_FCOE_CONN_AG_CTX_BIT1_MASK    0x1
10671 #define E4_MSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT   1
10672 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF0_MASK     0x3
10673 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT    2
10674 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF1_MASK     0x3
10675 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT    4
10676 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF2_MASK     0x3
10677 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT    6
10678         u8 flags1;
10679 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK           0x1
10680 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT          0
10681 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK           0x1
10682 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT          1
10683 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK           0x1
10684 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT          2
10685 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK         0x1
10686 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT        3
10687 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK         0x1
10688 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT        4
10689 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK         0x1
10690 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT        5
10691 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK         0x1
10692 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT        6
10693 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK         0x1
10694 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT        7
10695         __le16 word0;
10696         __le16 word1;
10697         __le32 reg0;
10698         __le32 reg1;
10699 };
10700
10701 /* Fast path part of the fcoe storm context of Mstorm */
10702 struct fcoe_mstorm_fcoe_conn_st_ctx_fp {
10703         __le16 xfer_prod;
10704         u8 num_cqs;
10705         u8 reserved1;
10706         u8 protection_info;
10707 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_SUPPORT_PROTECTION_MASK  0x1
10708 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_SUPPORT_PROTECTION_SHIFT 0
10709 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_VALID_MASK               0x1
10710 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_VALID_SHIFT              1
10711 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_RESERVED0_MASK           0x3F
10712 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_RESERVED0_SHIFT          2
10713         u8 q_relative_offset;
10714         u8 reserved2[2];
10715 };
10716
10717 /* Non fast path part of the fcoe storm context of Mstorm */
10718 struct fcoe_mstorm_fcoe_conn_st_ctx_non_fp {
10719         __le16 conn_id;
10720         __le16 stat_ram_addr;
10721         __le16 num_pages_in_pbl;
10722         u8 ptu_log_page_size;
10723         u8 log_page_size;
10724         __le16 unsolicited_cq_count;
10725         __le16 cmdq_count;
10726         u8 bdq_resource_id;
10727         u8 reserved0[3];
10728         struct regpair xferq_pbl_addr;
10729         struct regpair reserved1;
10730         struct regpair reserved2[3];
10731 };
10732
10733 /* The fcoe storm context of Mstorm */
10734 struct mstorm_fcoe_conn_st_ctx {
10735         struct fcoe_mstorm_fcoe_conn_st_ctx_fp fp;
10736         struct fcoe_mstorm_fcoe_conn_st_ctx_non_fp non_fp;
10737 };
10738
10739 /* fcoe connection context */
10740 struct e4_fcoe_conn_context {
10741         struct ystorm_fcoe_conn_st_ctx ystorm_st_context;
10742         struct pstorm_fcoe_conn_st_ctx pstorm_st_context;
10743         struct regpair pstorm_st_padding[2];
10744         struct xstorm_fcoe_conn_st_ctx xstorm_st_context;
10745         struct e4_xstorm_fcoe_conn_ag_ctx xstorm_ag_context;
10746         struct regpair xstorm_ag_padding[6];
10747         struct ustorm_fcoe_conn_st_ctx ustorm_st_context;
10748         struct regpair ustorm_st_padding[2];
10749         struct e4_tstorm_fcoe_conn_ag_ctx tstorm_ag_context;
10750         struct regpair tstorm_ag_padding[2];
10751         struct timers_context timer_context;
10752         struct e4_ustorm_fcoe_conn_ag_ctx ustorm_ag_context;
10753         struct tstorm_fcoe_conn_st_ctx tstorm_st_context;
10754         struct e4_mstorm_fcoe_conn_ag_ctx mstorm_ag_context;
10755         struct mstorm_fcoe_conn_st_ctx mstorm_st_context;
10756 };
10757
10758 /* FCoE connection offload params passed by driver to FW in FCoE offload
10759  * ramrod.
10760  */
10761 struct fcoe_conn_offload_ramrod_params {
10762         struct fcoe_conn_offload_ramrod_data offload_ramrod_data;
10763 };
10764
10765 /* FCoE connection terminate params passed by driver to FW in FCoE terminate
10766  * conn ramrod.
10767  */
10768 struct fcoe_conn_terminate_ramrod_params {
10769         struct fcoe_conn_terminate_ramrod_data terminate_ramrod_data;
10770 };
10771
10772 /* FCoE event type */
10773 enum fcoe_event_type {
10774         FCOE_EVENT_INIT_FUNC,
10775         FCOE_EVENT_DESTROY_FUNC,
10776         FCOE_EVENT_STAT_FUNC,
10777         FCOE_EVENT_OFFLOAD_CONN,
10778         FCOE_EVENT_TERMINATE_CONN,
10779         FCOE_EVENT_ERROR,
10780         MAX_FCOE_EVENT_TYPE
10781 };
10782
10783 /* FCoE init params passed by driver to FW in FCoE init ramrod */
10784 struct fcoe_init_ramrod_params {
10785         struct fcoe_init_func_ramrod_data init_ramrod_data;
10786 };
10787
10788 /* FCoE ramrod Command IDs */
10789 enum fcoe_ramrod_cmd_id {
10790         FCOE_RAMROD_CMD_ID_INIT_FUNC,
10791         FCOE_RAMROD_CMD_ID_DESTROY_FUNC,
10792         FCOE_RAMROD_CMD_ID_STAT_FUNC,
10793         FCOE_RAMROD_CMD_ID_OFFLOAD_CONN,
10794         FCOE_RAMROD_CMD_ID_TERMINATE_CONN,
10795         MAX_FCOE_RAMROD_CMD_ID
10796 };
10797
10798 /* FCoE statistics params buffer passed by driver to FW in FCoE statistics
10799  * ramrod.
10800  */
10801 struct fcoe_stat_ramrod_params {
10802         struct fcoe_stat_ramrod_data stat_ramrod_data;
10803 };
10804
10805 struct e4_ystorm_fcoe_conn_ag_ctx {
10806         u8 byte0;
10807         u8 byte1;
10808         u8 flags0;
10809 #define E4_YSTORM_FCOE_CONN_AG_CTX_BIT0_MASK    0x1
10810 #define E4_YSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT   0
10811 #define E4_YSTORM_FCOE_CONN_AG_CTX_BIT1_MASK    0x1
10812 #define E4_YSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT   1
10813 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF0_MASK     0x3
10814 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT    2
10815 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF1_MASK     0x3
10816 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT    4
10817 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF2_MASK     0x3
10818 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT    6
10819         u8 flags1;
10820 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK           0x1
10821 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT          0
10822 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK           0x1
10823 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT          1
10824 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK           0x1
10825 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT          2
10826 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK         0x1
10827 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT        3
10828 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK         0x1
10829 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT        4
10830 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK         0x1
10831 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT        5
10832 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK         0x1
10833 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT        6
10834 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK         0x1
10835 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT        7
10836         u8 byte2;
10837         u8 byte3;
10838         __le16 word0;
10839         __le32 reg0;
10840         __le32 reg1;
10841         __le16 word1;
10842         __le16 word2;
10843         __le16 word3;
10844         __le16 word4;
10845         __le32 reg2;
10846         __le32 reg3;
10847 };
10848
10849 /* The iscsi storm connection context of Ystorm */
10850 struct ystorm_iscsi_conn_st_ctx {
10851         __le32 reserved[8];
10852 };
10853
10854 /* Combined iSCSI and TCP storm connection of Pstorm */
10855 struct pstorm_iscsi_tcp_conn_st_ctx {
10856         __le32 tcp[32];
10857         __le32 iscsi[4];
10858 };
10859
10860 /* The combined tcp and iscsi storm context of Xstorm */
10861 struct xstorm_iscsi_tcp_conn_st_ctx {
10862         __le32 reserved_tcp[4];
10863         __le32 reserved_iscsi[44];
10864 };
10865
10866 struct e4_xstorm_iscsi_conn_ag_ctx {
10867         u8 cdu_validation;
10868         u8 state;
10869         u8 flags0;
10870 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK   0x1
10871 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT  0
10872 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_MASK   0x1
10873 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_SHIFT  1
10874 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_MASK      0x1
10875 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_SHIFT     2
10876 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_MASK   0x1
10877 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_SHIFT  3
10878 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK           0x1
10879 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT4_SHIFT          4
10880 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_MASK      0x1
10881 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_SHIFT     5
10882 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT6_MASK           0x1
10883 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT6_SHIFT          6
10884 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT7_MASK           0x1
10885 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT7_SHIFT          7
10886         u8 flags1;
10887 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT8_MASK           0x1
10888 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT8_SHIFT          0
10889 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT9_MASK           0x1
10890 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT9_SHIFT          1
10891 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT10_MASK          0x1
10892 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT10_SHIFT         2
10893 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT11_MASK          0x1
10894 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT11_SHIFT         3
10895 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT12_MASK          0x1
10896 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT12_SHIFT         4
10897 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT13_MASK          0x1
10898 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT13_SHIFT         5
10899 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT14_MASK          0x1
10900 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT14_SHIFT         6
10901 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TX_TRUNCATE_MASK    0x1
10902 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TX_TRUNCATE_SHIFT   7
10903         u8 flags2;
10904 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF0_MASK                    0x3
10905 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT                   0
10906 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF1_MASK                    0x3
10907 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT                   2
10908 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF2_MASK                    0x3
10909 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT                   4
10910 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK         0x3
10911 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT        6
10912         u8 flags3;
10913 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF4_MASK    0x3
10914 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT   0
10915 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF5_MASK    0x3
10916 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT   2
10917 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF6_MASK    0x3
10918 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT   4
10919 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF7_MASK    0x3
10920 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF7_SHIFT   6
10921         u8 flags4;
10922 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF8_MASK    0x3
10923 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF8_SHIFT   0
10924 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF9_MASK    0x3
10925 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF9_SHIFT   2
10926 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF10_MASK   0x3
10927 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF10_SHIFT  4
10928 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF11_MASK   0x3
10929 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF11_SHIFT  6
10930         u8 flags5;
10931 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF12_MASK                           0x3
10932 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF12_SHIFT                          0
10933 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF13_MASK                           0x3
10934 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF13_SHIFT                          2
10935 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF14_MASK                           0x3
10936 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF14_SHIFT                          4
10937 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_MASK        0x3
10938 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_SHIFT       6
10939         u8 flags6;
10940 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF16_MASK           0x3
10941 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF16_SHIFT          0
10942 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF17_MASK           0x3
10943 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF17_SHIFT          2
10944 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF18_MASK           0x3
10945 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF18_SHIFT          4
10946 #define E4_XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_MASK       0x3
10947 #define E4_XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_SHIFT      6
10948         u8 flags7;
10949 #define E4_XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_MASK    0x3
10950 #define E4_XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_SHIFT   0
10951 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_MASK    0x3
10952 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_SHIFT   2
10953 #define E4_XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_MASK              0x3
10954 #define E4_XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_SHIFT             4
10955 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK                  0x1
10956 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT                 6
10957 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK                  0x1
10958 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT                 7
10959         u8 flags8;
10960 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK                  0x1
10961 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT                 0
10962 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK      0x1
10963 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT     1
10964 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK                  0x1
10965 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT                 2
10966 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK                  0x1
10967 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT                 3
10968 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK                  0x1
10969 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT                 4
10970 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK                  0x1
10971 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF7EN_SHIFT                 5
10972 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK                  0x1
10973 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF8EN_SHIFT                 6
10974 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF9EN_MASK                  0x1
10975 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF9EN_SHIFT                 7
10976         u8 flags9;
10977 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF10EN_MASK                         0x1
10978 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF10EN_SHIFT                        0
10979 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF11EN_MASK                         0x1
10980 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF11EN_SHIFT                        1
10981 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF12EN_MASK                         0x1
10982 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF12EN_SHIFT                        2
10983 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF13EN_MASK                         0x1
10984 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF13EN_SHIFT                        3
10985 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF14EN_MASK                         0x1
10986 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF14EN_SHIFT                        4
10987 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_EN_MASK     0x1
10988 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_EN_SHIFT    5
10989 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF16EN_MASK                         0x1
10990 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF16EN_SHIFT                        6
10991 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF17EN_MASK                         0x1
10992 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF17EN_SHIFT                        7
10993         u8 flags10;
10994 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF18EN_MASK                         0x1
10995 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF18EN_SHIFT                        0
10996 #define E4_XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_EN_MASK                    0x1
10997 #define E4_XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT                   1
10998 #define E4_XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_EN_MASK         0x1
10999 #define E4_XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_EN_SHIFT        2
11000 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_EN_MASK         0x1
11001 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_EN_SHIFT        3
11002 #define E4_XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_EN_MASK                   0x1
11003 #define E4_XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_EN_SHIFT                  4
11004 #define E4_XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_EN_MASK           0x1
11005 #define E4_XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_EN_SHIFT          5
11006 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK                        0x1
11007 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT                       6
11008 #define E4_XSTORM_ISCSI_CONN_AG_CTX_MORE_TO_SEND_DEC_RULE_EN_MASK       0x1
11009 #define E4_XSTORM_ISCSI_CONN_AG_CTX_MORE_TO_SEND_DEC_RULE_EN_SHIFT      7
11010         u8 flags11;
11011 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TX_BLOCKED_EN_MASK  0x1
11012 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT 0
11013 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK        0x1
11014 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT       1
11015 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED3_MASK      0x1
11016 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED3_SHIFT     2
11017 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK        0x1
11018 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT       3
11019 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK        0x1
11020 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT       4
11021 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK        0x1
11022 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT       5
11023 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED1_MASK   0x1
11024 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED1_SHIFT  6
11025 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE9EN_MASK        0x1
11026 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE9EN_SHIFT       7
11027         u8 flags12;
11028 #define E4_XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_MASK         0x1
11029 #define E4_XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_SHIFT        0
11030 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE11EN_MASK               0x1
11031 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE11EN_SHIFT              1
11032 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED2_MASK           0x1
11033 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED2_SHIFT          2
11034 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED3_MASK           0x1
11035 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED3_SHIFT          3
11036 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE14EN_MASK               0x1
11037 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE14EN_SHIFT              4
11038 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE15EN_MASK               0x1
11039 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE15EN_SHIFT              5
11040 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE16EN_MASK               0x1
11041 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE16EN_SHIFT              6
11042 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE17EN_MASK               0x1
11043 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE17EN_SHIFT              7
11044         u8 flags13;
11045 #define E4_XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_MASK       0x1
11046 #define E4_XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_SHIFT      0
11047 #define E4_XSTORM_ISCSI_CONN_AG_CTX_HQ_DEC_RULE_EN_MASK         0x1
11048 #define E4_XSTORM_ISCSI_CONN_AG_CTX_HQ_DEC_RULE_EN_SHIFT        1
11049 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED4_MASK           0x1
11050 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED4_SHIFT          2
11051 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED5_MASK           0x1
11052 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED5_SHIFT          3
11053 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED6_MASK           0x1
11054 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED6_SHIFT          4
11055 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED7_MASK           0x1
11056 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED7_SHIFT          5
11057 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED8_MASK           0x1
11058 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED8_SHIFT          6
11059 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED9_MASK           0x1
11060 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED9_SHIFT          7
11061         u8 flags14;
11062 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT16_MASK                  0x1
11063 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT16_SHIFT                 0
11064 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT17_MASK                  0x1
11065 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT17_SHIFT                 1
11066 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT18_MASK                  0x1
11067 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT18_SHIFT                 2
11068 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT19_MASK                  0x1
11069 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT19_SHIFT                 3
11070 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT20_MASK                  0x1
11071 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT20_SHIFT                 4
11072 #define E4_XSTORM_ISCSI_CONN_AG_CTX_DUMMY_READ_DONE_MASK        0x1
11073 #define E4_XSTORM_ISCSI_CONN_AG_CTX_DUMMY_READ_DONE_SHIFT       5
11074 #define E4_XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_MASK      0x3
11075 #define E4_XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_SHIFT     6
11076         u8 byte2;
11077         __le16 physical_q0;
11078         __le16 physical_q1;
11079         __le16 dummy_dorq_var;
11080         __le16 sq_cons;
11081         __le16 sq_prod;
11082         __le16 word5;
11083         __le16 slow_io_total_data_tx_update;
11084         u8 byte3;
11085         u8 byte4;
11086         u8 byte5;
11087         u8 byte6;
11088         __le32 reg0;
11089         __le32 reg1;
11090         __le32 reg2;
11091         __le32 more_to_send_seq;
11092         __le32 reg4;
11093         __le32 reg5;
11094         __le32 hq_scan_next_relevant_ack;
11095         __le16 r2tq_prod;
11096         __le16 r2tq_cons;
11097         __le16 hq_prod;
11098         __le16 hq_cons;
11099         __le32 remain_seq;
11100         __le32 bytes_to_next_pdu;
11101         __le32 hq_tcp_seq;
11102         u8 byte7;
11103         u8 byte8;
11104         u8 byte9;
11105         u8 byte10;
11106         u8 byte11;
11107         u8 byte12;
11108         u8 byte13;
11109         u8 byte14;
11110         u8 byte15;
11111         u8 e5_reserved;
11112         __le16 word11;
11113         __le32 reg10;
11114         __le32 reg11;
11115         __le32 exp_stat_sn;
11116         __le32 ongoing_fast_rxmit_seq;
11117         __le32 reg14;
11118         __le32 reg15;
11119         __le32 reg16;
11120         __le32 reg17;
11121 };
11122
11123 struct e4_tstorm_iscsi_conn_ag_ctx {
11124         u8 reserved0;
11125         u8 state;
11126         u8 flags0;
11127 #define E4_TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK   0x1
11128 #define E4_TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT  0
11129 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK           0x1
11130 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT          1
11131 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT2_MASK           0x1
11132 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT2_SHIFT          2
11133 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT3_MASK           0x1
11134 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT3_SHIFT          3
11135 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK           0x1
11136 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT4_SHIFT          4
11137 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT5_MASK           0x1
11138 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT5_SHIFT          5
11139 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF0_MASK            0x3
11140 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT           6
11141         u8 flags1;
11142 #define E4_TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_MASK           0x3
11143 #define E4_TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_SHIFT          0
11144 #define E4_TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_MASK           0x3
11145 #define E4_TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_SHIFT          2
11146 #define E4_TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK         0x3
11147 #define E4_TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT        4
11148 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF4_MASK                    0x3
11149 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT                   6
11150         u8 flags2;
11151 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF5_MASK    0x3
11152 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT   0
11153 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF6_MASK    0x3
11154 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT   2
11155 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF7_MASK    0x3
11156 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF7_SHIFT   4
11157 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF8_MASK    0x3
11158 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF8_SHIFT   6
11159         u8 flags3;
11160 #define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_MASK               0x3
11161 #define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_SHIFT              0
11162 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF10_MASK                   0x3
11163 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF10_SHIFT                  2
11164 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK                  0x1
11165 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT                 4
11166 #define E4_TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_EN_MASK        0x1
11167 #define E4_TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_EN_SHIFT       5
11168 #define E4_TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_EN_MASK        0x1
11169 #define E4_TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_EN_SHIFT       6
11170 #define E4_TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK      0x1
11171 #define E4_TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT     7
11172         u8 flags4;
11173 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK          0x1
11174 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT         0
11175 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK          0x1
11176 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT         1
11177 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK          0x1
11178 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT         2
11179 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK          0x1
11180 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF7EN_SHIFT         3
11181 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK          0x1
11182 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF8EN_SHIFT         4
11183 #define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_MASK    0x1
11184 #define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT   5
11185 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF10EN_MASK         0x1
11186 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF10EN_SHIFT        6
11187 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK        0x1
11188 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT       7
11189         u8 flags5;
11190 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK        0x1
11191 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT       0
11192 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK        0x1
11193 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT       1
11194 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK        0x1
11195 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT       2
11196 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK        0x1
11197 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT       3
11198 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK        0x1
11199 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT       4
11200 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK        0x1
11201 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT       5
11202 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK        0x1
11203 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT       6
11204 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK        0x1
11205 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE8EN_SHIFT       7
11206         __le32 reg0;
11207         __le32 reg1;
11208         __le32 reg2;
11209         __le32 reg3;
11210         __le32 reg4;
11211         __le32 reg5;
11212         __le32 reg6;
11213         __le32 reg7;
11214         __le32 reg8;
11215         u8 cid_offload_cnt;
11216         u8 byte3;
11217         __le16 word0;
11218 };
11219
11220 struct e4_ustorm_iscsi_conn_ag_ctx {
11221         u8 byte0;
11222         u8 byte1;
11223         u8 flags0;
11224 #define E4_USTORM_ISCSI_CONN_AG_CTX_BIT0_MASK   0x1
11225 #define E4_USTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT  0
11226 #define E4_USTORM_ISCSI_CONN_AG_CTX_BIT1_MASK   0x1
11227 #define E4_USTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT  1
11228 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF0_MASK    0x3
11229 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT   2
11230 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF1_MASK    0x3
11231 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT   4
11232 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF2_MASK    0x3
11233 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT   6
11234         u8 flags1;
11235 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF3_MASK    0x3
11236 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF3_SHIFT   0
11237 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF4_MASK    0x3
11238 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT   2
11239 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF5_MASK    0x3
11240 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT   4
11241 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF6_MASK    0x3
11242 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT   6
11243         u8 flags2;
11244 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK          0x1
11245 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT         0
11246 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK          0x1
11247 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT         1
11248 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK          0x1
11249 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT         2
11250 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF3EN_MASK          0x1
11251 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF3EN_SHIFT         3
11252 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK          0x1
11253 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT         4
11254 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK          0x1
11255 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT         5
11256 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK          0x1
11257 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT         6
11258 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK        0x1
11259 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT       7
11260         u8 flags3;
11261 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK        0x1
11262 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT       0
11263 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK        0x1
11264 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT       1
11265 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK        0x1
11266 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT       2
11267 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK        0x1
11268 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT       3
11269 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK        0x1
11270 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT       4
11271 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK        0x1
11272 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT       5
11273 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK        0x1
11274 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT       6
11275 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK        0x1
11276 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE8EN_SHIFT       7
11277         u8 byte2;
11278         u8 byte3;
11279         __le16 word0;
11280         __le16 word1;
11281         __le32 reg0;
11282         __le32 reg1;
11283         __le32 reg2;
11284         __le32 reg3;
11285         __le16 word2;
11286         __le16 word3;
11287 };
11288
11289 /* The iscsi storm connection context of Tstorm */
11290 struct tstorm_iscsi_conn_st_ctx {
11291         __le32 reserved[44];
11292 };
11293
11294 struct e4_mstorm_iscsi_conn_ag_ctx {
11295         u8 reserved;
11296         u8 state;
11297         u8 flags0;
11298 #define E4_MSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK   0x1
11299 #define E4_MSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT  0
11300 #define E4_MSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK   0x1
11301 #define E4_MSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT  1
11302 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF0_MASK    0x3
11303 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT   2
11304 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF1_MASK    0x3
11305 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT   4
11306 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF2_MASK    0x3
11307 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT   6
11308         u8 flags1;
11309 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK          0x1
11310 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT         0
11311 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK          0x1
11312 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT         1
11313 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK          0x1
11314 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT         2
11315 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK        0x1
11316 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT       3
11317 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK        0x1
11318 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT       4
11319 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK        0x1
11320 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT       5
11321 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK        0x1
11322 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT       6
11323 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK        0x1
11324 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT       7
11325         __le16 word0;
11326         __le16 word1;
11327         __le32 reg0;
11328         __le32 reg1;
11329 };
11330
11331 /* Combined iSCSI and TCP storm connection of Mstorm */
11332 struct mstorm_iscsi_tcp_conn_st_ctx {
11333         __le32 reserved_tcp[20];
11334         __le32 reserved_iscsi[12];
11335 };
11336
11337 /* The iscsi storm context of Ustorm */
11338 struct ustorm_iscsi_conn_st_ctx {
11339         __le32 reserved[52];
11340 };
11341
11342 /* iscsi connection context */
11343 struct e4_iscsi_conn_context {
11344         struct ystorm_iscsi_conn_st_ctx ystorm_st_context;
11345         struct pstorm_iscsi_tcp_conn_st_ctx pstorm_st_context;
11346         struct regpair pstorm_st_padding[2];
11347         struct pb_context xpb2_context;
11348         struct xstorm_iscsi_tcp_conn_st_ctx xstorm_st_context;
11349         struct regpair xstorm_st_padding[2];
11350         struct e4_xstorm_iscsi_conn_ag_ctx xstorm_ag_context;
11351         struct e4_tstorm_iscsi_conn_ag_ctx tstorm_ag_context;
11352         struct regpair tstorm_ag_padding[2];
11353         struct timers_context timer_context;
11354         struct e4_ustorm_iscsi_conn_ag_ctx ustorm_ag_context;
11355         struct pb_context upb_context;
11356         struct tstorm_iscsi_conn_st_ctx tstorm_st_context;
11357         struct regpair tstorm_st_padding[2];
11358         struct e4_mstorm_iscsi_conn_ag_ctx mstorm_ag_context;
11359         struct mstorm_iscsi_tcp_conn_st_ctx mstorm_st_context;
11360         struct ustorm_iscsi_conn_st_ctx ustorm_st_context;
11361 };
11362
11363 /* iSCSI init params passed by driver to FW in iSCSI init ramrod */
11364 struct iscsi_init_ramrod_params {
11365         struct iscsi_spe_func_init iscsi_init_spe;
11366         struct tcp_init_params tcp_init;
11367 };
11368
11369 struct e4_ystorm_iscsi_conn_ag_ctx {
11370         u8 byte0;
11371         u8 byte1;
11372         u8 flags0;
11373 #define E4_YSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK   0x1
11374 #define E4_YSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT  0
11375 #define E4_YSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK   0x1
11376 #define E4_YSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT  1
11377 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF0_MASK    0x3
11378 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT   2
11379 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF1_MASK    0x3
11380 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT   4
11381 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF2_MASK    0x3
11382 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT   6
11383         u8 flags1;
11384 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK          0x1
11385 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT         0
11386 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK          0x1
11387 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT         1
11388 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK          0x1
11389 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT         2
11390 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK        0x1
11391 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT       3
11392 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK        0x1
11393 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT       4
11394 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK        0x1
11395 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT       5
11396 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK        0x1
11397 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT       6
11398 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK        0x1
11399 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT       7
11400         u8 byte2;
11401         u8 byte3;
11402         __le16 word0;
11403         __le32 reg0;
11404         __le32 reg1;
11405         __le16 word1;
11406         __le16 word2;
11407         __le16 word3;
11408         __le16 word4;
11409         __le32 reg2;
11410         __le32 reg3;
11411 };
11412
11413 #define MFW_TRACE_SIGNATURE     0x25071946
11414
11415 /* The trace in the buffer */
11416 #define MFW_TRACE_EVENTID_MASK          0x00ffff
11417 #define MFW_TRACE_PRM_SIZE_MASK         0x0f0000
11418 #define MFW_TRACE_PRM_SIZE_SHIFT        16
11419 #define MFW_TRACE_ENTRY_SIZE            3
11420
11421 struct mcp_trace {
11422         u32 signature;          /* Help to identify that the trace is valid */
11423         u32 size;               /* the size of the trace buffer in bytes */
11424         u32 curr_level;         /* 2 - all will be written to the buffer
11425                                  * 1 - debug trace will not be written
11426                                  * 0 - just errors will be written to the buffer
11427                                  */
11428         u32 modules_mask[2];    /* a bit per module, 1 means write it, 0 means
11429                                  * mask it.
11430                                  */
11431
11432         /* Warning: the following pointers are assumed to be 32bits as they are
11433          * used only in the MFW.
11434          */
11435         u32 trace_prod; /* The next trace will be written to this offset */
11436         u32 trace_oldest; /* The oldest valid trace starts at this offset
11437                            * (usually very close after the current producer).
11438                            */
11439 };
11440
11441 #define VF_MAX_STATIC 192
11442
11443 #define MCP_GLOB_PATH_MAX       2
11444 #define MCP_PORT_MAX            2
11445 #define MCP_GLOB_PORT_MAX       4
11446 #define MCP_GLOB_FUNC_MAX       16
11447
11448 typedef u32 offsize_t;          /* In DWORDS !!! */
11449 /* Offset from the beginning of the MCP scratchpad */
11450 #define OFFSIZE_OFFSET_SHIFT    0
11451 #define OFFSIZE_OFFSET_MASK     0x0000ffff
11452 /* Size of specific element (not the whole array if any) */
11453 #define OFFSIZE_SIZE_SHIFT      16
11454 #define OFFSIZE_SIZE_MASK       0xffff0000
11455
11456 #define SECTION_OFFSET(_offsize) ((((_offsize &                 \
11457                                      OFFSIZE_OFFSET_MASK) >>    \
11458                                     OFFSIZE_OFFSET_SHIFT) << 2))
11459
11460 #define QED_SECTION_SIZE(_offsize) (((_offsize &                \
11461                                       OFFSIZE_SIZE_MASK) >>     \
11462                                      OFFSIZE_SIZE_SHIFT) << 2)
11463
11464 #define SECTION_ADDR(_offsize, idx) (MCP_REG_SCRATCH +                  \
11465                                      SECTION_OFFSET(_offsize) +         \
11466                                      (QED_SECTION_SIZE(_offsize) * idx))
11467
11468 #define SECTION_OFFSIZE_ADDR(_pub_base, _section)       \
11469         (_pub_base + offsetof(struct mcp_public_data, sections[_section]))
11470
11471 /* PHY configuration */
11472 struct eth_phy_cfg {
11473         u32 speed;
11474 #define ETH_SPEED_AUTONEG       0
11475 #define ETH_SPEED_SMARTLINQ     0x8
11476
11477         u32 pause;
11478 #define ETH_PAUSE_NONE          0x0
11479 #define ETH_PAUSE_AUTONEG       0x1
11480 #define ETH_PAUSE_RX            0x2
11481 #define ETH_PAUSE_TX            0x4
11482
11483         u32 adv_speed;
11484         u32 loopback_mode;
11485 #define ETH_LOOPBACK_NONE               (0)
11486 #define ETH_LOOPBACK_INT_PHY            (1)
11487 #define ETH_LOOPBACK_EXT_PHY            (2)
11488 #define ETH_LOOPBACK_EXT                (3)
11489 #define ETH_LOOPBACK_MAC                (4)
11490
11491         u32 eee_cfg;
11492 #define EEE_CFG_EEE_ENABLED                     BIT(0)
11493 #define EEE_CFG_TX_LPI                          BIT(1)
11494 #define EEE_CFG_ADV_SPEED_1G                    BIT(2)
11495 #define EEE_CFG_ADV_SPEED_10G                   BIT(3)
11496 #define EEE_TX_TIMER_USEC_MASK                  (0xfffffff0)
11497 #define EEE_TX_TIMER_USEC_OFFSET                4
11498 #define EEE_TX_TIMER_USEC_BALANCED_TIME         (0xa00)
11499 #define EEE_TX_TIMER_USEC_AGGRESSIVE_TIME       (0x100)
11500 #define EEE_TX_TIMER_USEC_LATENCY_TIME          (0x6000)
11501
11502         u32 feature_config_flags;
11503 #define ETH_EEE_MODE_ADV_LPI            (1 << 0)
11504 };
11505
11506 struct port_mf_cfg {
11507         u32 dynamic_cfg;
11508 #define PORT_MF_CFG_OV_TAG_MASK         0x0000ffff
11509 #define PORT_MF_CFG_OV_TAG_SHIFT        0
11510 #define PORT_MF_CFG_OV_TAG_DEFAULT      PORT_MF_CFG_OV_TAG_MASK
11511
11512         u32 reserved[1];
11513 };
11514
11515 struct eth_stats {
11516         u64 r64;
11517         u64 r127;
11518         u64 r255;
11519         u64 r511;
11520         u64 r1023;
11521         u64 r1518;
11522
11523         union {
11524                 struct {
11525                         u64 r1522;
11526                         u64 r2047;
11527                         u64 r4095;
11528                         u64 r9216;
11529                         u64 r16383;
11530                 } bb0;
11531                 struct {
11532                         u64 unused1;
11533                         u64 r1519_to_max;
11534                         u64 unused2;
11535                         u64 unused3;
11536                         u64 unused4;
11537                 } ah0;
11538         } u0;
11539
11540         u64 rfcs;
11541         u64 rxcf;
11542         u64 rxpf;
11543         u64 rxpp;
11544         u64 raln;
11545         u64 rfcr;
11546         u64 rovr;
11547         u64 rjbr;
11548         u64 rund;
11549         u64 rfrg;
11550         u64 t64;
11551         u64 t127;
11552         u64 t255;
11553         u64 t511;
11554         u64 t1023;
11555         u64 t1518;
11556
11557         union {
11558                 struct {
11559                         u64 t2047;
11560                         u64 t4095;
11561                         u64 t9216;
11562                         u64 t16383;
11563                 } bb1;
11564                 struct {
11565                         u64 t1519_to_max;
11566                         u64 unused6;
11567                         u64 unused7;
11568                         u64 unused8;
11569                 } ah1;
11570         } u1;
11571
11572         u64 txpf;
11573         u64 txpp;
11574
11575         union {
11576                 struct {
11577                         u64 tlpiec;
11578                         u64 tncl;
11579                 } bb2;
11580                 struct {
11581                         u64 unused9;
11582                         u64 unused10;
11583                 } ah2;
11584         } u2;
11585
11586         u64 rbyte;
11587         u64 rxuca;
11588         u64 rxmca;
11589         u64 rxbca;
11590         u64 rxpok;
11591         u64 tbyte;
11592         u64 txuca;
11593         u64 txmca;
11594         u64 txbca;
11595         u64 txcf;
11596 };
11597
11598 struct brb_stats {
11599         u64 brb_truncate[8];
11600         u64 brb_discard[8];
11601 };
11602
11603 struct port_stats {
11604         struct brb_stats brb;
11605         struct eth_stats eth;
11606 };
11607
11608 struct couple_mode_teaming {
11609         u8 port_cmt[MCP_GLOB_PORT_MAX];
11610 #define PORT_CMT_IN_TEAM        (1 << 0)
11611
11612 #define PORT_CMT_PORT_ROLE      (1 << 1)
11613 #define PORT_CMT_PORT_INACTIVE  (0 << 1)
11614 #define PORT_CMT_PORT_ACTIVE    (1 << 1)
11615
11616 #define PORT_CMT_TEAM_MASK      (1 << 2)
11617 #define PORT_CMT_TEAM0          (0 << 2)
11618 #define PORT_CMT_TEAM1          (1 << 2)
11619 };
11620
11621 #define LLDP_CHASSIS_ID_STAT_LEN        4
11622 #define LLDP_PORT_ID_STAT_LEN           4
11623 #define DCBX_MAX_APP_PROTOCOL           32
11624 #define MAX_SYSTEM_LLDP_TLV_DATA        32
11625
11626 enum _lldp_agent {
11627         LLDP_NEAREST_BRIDGE = 0,
11628         LLDP_NEAREST_NON_TPMR_BRIDGE,
11629         LLDP_NEAREST_CUSTOMER_BRIDGE,
11630         LLDP_MAX_LLDP_AGENTS
11631 };
11632
11633 struct lldp_config_params_s {
11634         u32 config;
11635 #define LLDP_CONFIG_TX_INTERVAL_MASK    0x000000ff
11636 #define LLDP_CONFIG_TX_INTERVAL_SHIFT   0
11637 #define LLDP_CONFIG_HOLD_MASK           0x00000f00
11638 #define LLDP_CONFIG_HOLD_SHIFT          8
11639 #define LLDP_CONFIG_MAX_CREDIT_MASK     0x0000f000
11640 #define LLDP_CONFIG_MAX_CREDIT_SHIFT    12
11641 #define LLDP_CONFIG_ENABLE_RX_MASK      0x40000000
11642 #define LLDP_CONFIG_ENABLE_RX_SHIFT     30
11643 #define LLDP_CONFIG_ENABLE_TX_MASK      0x80000000
11644 #define LLDP_CONFIG_ENABLE_TX_SHIFT     31
11645         u32 local_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];
11646         u32 local_port_id[LLDP_PORT_ID_STAT_LEN];
11647 };
11648
11649 struct lldp_status_params_s {
11650         u32 prefix_seq_num;
11651         u32 status;
11652         u32 peer_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];
11653         u32 peer_port_id[LLDP_PORT_ID_STAT_LEN];
11654         u32 suffix_seq_num;
11655 };
11656
11657 struct dcbx_ets_feature {
11658         u32 flags;
11659 #define DCBX_ETS_ENABLED_MASK   0x00000001
11660 #define DCBX_ETS_ENABLED_SHIFT  0
11661 #define DCBX_ETS_WILLING_MASK   0x00000002
11662 #define DCBX_ETS_WILLING_SHIFT  1
11663 #define DCBX_ETS_ERROR_MASK     0x00000004
11664 #define DCBX_ETS_ERROR_SHIFT    2
11665 #define DCBX_ETS_CBS_MASK       0x00000008
11666 #define DCBX_ETS_CBS_SHIFT      3
11667 #define DCBX_ETS_MAX_TCS_MASK   0x000000f0
11668 #define DCBX_ETS_MAX_TCS_SHIFT  4
11669 #define DCBX_OOO_TC_MASK        0x00000f00
11670 #define DCBX_OOO_TC_SHIFT       8
11671         u32 pri_tc_tbl[1];
11672 #define DCBX_TCP_OOO_TC         (4)
11673
11674 #define NIG_ETS_ISCSI_OOO_CLIENT_OFFSET (DCBX_TCP_OOO_TC + 1)
11675 #define DCBX_CEE_STRICT_PRIORITY        0xf
11676         u32 tc_bw_tbl[2];
11677         u32 tc_tsa_tbl[2];
11678 #define DCBX_ETS_TSA_STRICT     0
11679 #define DCBX_ETS_TSA_CBS        1
11680 #define DCBX_ETS_TSA_ETS        2
11681 };
11682
11683 #define DCBX_TCP_OOO_TC                 (4)
11684 #define DCBX_TCP_OOO_K2_4PORT_TC        (3)
11685
11686 struct dcbx_app_priority_entry {
11687         u32 entry;
11688 #define DCBX_APP_PRI_MAP_MASK           0x000000ff
11689 #define DCBX_APP_PRI_MAP_SHIFT          0
11690 #define DCBX_APP_PRI_0                  0x01
11691 #define DCBX_APP_PRI_1                  0x02
11692 #define DCBX_APP_PRI_2                  0x04
11693 #define DCBX_APP_PRI_3                  0x08
11694 #define DCBX_APP_PRI_4                  0x10
11695 #define DCBX_APP_PRI_5                  0x20
11696 #define DCBX_APP_PRI_6                  0x40
11697 #define DCBX_APP_PRI_7                  0x80
11698 #define DCBX_APP_SF_MASK                0x00000300
11699 #define DCBX_APP_SF_SHIFT               8
11700 #define DCBX_APP_SF_ETHTYPE             0
11701 #define DCBX_APP_SF_PORT                1
11702 #define DCBX_APP_SF_IEEE_MASK           0x0000f000
11703 #define DCBX_APP_SF_IEEE_SHIFT          12
11704 #define DCBX_APP_SF_IEEE_RESERVED       0
11705 #define DCBX_APP_SF_IEEE_ETHTYPE        1
11706 #define DCBX_APP_SF_IEEE_TCP_PORT       2
11707 #define DCBX_APP_SF_IEEE_UDP_PORT       3
11708 #define DCBX_APP_SF_IEEE_TCP_UDP_PORT   4
11709
11710 #define DCBX_APP_PROTOCOL_ID_MASK       0xffff0000
11711 #define DCBX_APP_PROTOCOL_ID_SHIFT      16
11712 };
11713
11714 struct dcbx_app_priority_feature {
11715         u32 flags;
11716 #define DCBX_APP_ENABLED_MASK           0x00000001
11717 #define DCBX_APP_ENABLED_SHIFT          0
11718 #define DCBX_APP_WILLING_MASK           0x00000002
11719 #define DCBX_APP_WILLING_SHIFT          1
11720 #define DCBX_APP_ERROR_MASK             0x00000004
11721 #define DCBX_APP_ERROR_SHIFT            2
11722 #define DCBX_APP_MAX_TCS_MASK           0x0000f000
11723 #define DCBX_APP_MAX_TCS_SHIFT          12
11724 #define DCBX_APP_NUM_ENTRIES_MASK       0x00ff0000
11725 #define DCBX_APP_NUM_ENTRIES_SHIFT      16
11726         struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL];
11727 };
11728
11729 struct dcbx_features {
11730         struct dcbx_ets_feature ets;
11731         u32 pfc;
11732 #define DCBX_PFC_PRI_EN_BITMAP_MASK     0x000000ff
11733 #define DCBX_PFC_PRI_EN_BITMAP_SHIFT    0
11734 #define DCBX_PFC_PRI_EN_BITMAP_PRI_0    0x01
11735 #define DCBX_PFC_PRI_EN_BITMAP_PRI_1    0x02
11736 #define DCBX_PFC_PRI_EN_BITMAP_PRI_2    0x04
11737 #define DCBX_PFC_PRI_EN_BITMAP_PRI_3    0x08
11738 #define DCBX_PFC_PRI_EN_BITMAP_PRI_4    0x10
11739 #define DCBX_PFC_PRI_EN_BITMAP_PRI_5    0x20
11740 #define DCBX_PFC_PRI_EN_BITMAP_PRI_6    0x40
11741 #define DCBX_PFC_PRI_EN_BITMAP_PRI_7    0x80
11742
11743 #define DCBX_PFC_FLAGS_MASK             0x0000ff00
11744 #define DCBX_PFC_FLAGS_SHIFT            8
11745 #define DCBX_PFC_CAPS_MASK              0x00000f00
11746 #define DCBX_PFC_CAPS_SHIFT             8
11747 #define DCBX_PFC_MBC_MASK               0x00004000
11748 #define DCBX_PFC_MBC_SHIFT              14
11749 #define DCBX_PFC_WILLING_MASK           0x00008000
11750 #define DCBX_PFC_WILLING_SHIFT          15
11751 #define DCBX_PFC_ENABLED_MASK           0x00010000
11752 #define DCBX_PFC_ENABLED_SHIFT          16
11753 #define DCBX_PFC_ERROR_MASK             0x00020000
11754 #define DCBX_PFC_ERROR_SHIFT            17
11755
11756         struct dcbx_app_priority_feature app;
11757 };
11758
11759 struct dcbx_local_params {
11760         u32 config;
11761 #define DCBX_CONFIG_VERSION_MASK        0x00000007
11762 #define DCBX_CONFIG_VERSION_SHIFT       0
11763 #define DCBX_CONFIG_VERSION_DISABLED    0
11764 #define DCBX_CONFIG_VERSION_IEEE        1
11765 #define DCBX_CONFIG_VERSION_CEE         2
11766 #define DCBX_CONFIG_VERSION_STATIC      4
11767
11768         u32 flags;
11769         struct dcbx_features features;
11770 };
11771
11772 struct dcbx_mib {
11773         u32 prefix_seq_num;
11774         u32 flags;
11775         struct dcbx_features features;
11776         u32 suffix_seq_num;
11777 };
11778
11779 struct lldp_system_tlvs_buffer_s {
11780         u16 valid;
11781         u16 length;
11782         u32 data[MAX_SYSTEM_LLDP_TLV_DATA];
11783 };
11784
11785 struct dcb_dscp_map {
11786         u32 flags;
11787 #define DCB_DSCP_ENABLE_MASK    0x1
11788 #define DCB_DSCP_ENABLE_SHIFT   0
11789 #define DCB_DSCP_ENABLE 1
11790         u32 dscp_pri_map[8];
11791 };
11792
11793 struct public_global {
11794         u32 max_path;
11795         u32 max_ports;
11796 #define MODE_1P 1
11797 #define MODE_2P 2
11798 #define MODE_3P 3
11799 #define MODE_4P 4
11800         u32 debug_mb_offset;
11801         u32 phymod_dbg_mb_offset;
11802         struct couple_mode_teaming cmt;
11803         s32 internal_temperature;
11804         u32 mfw_ver;
11805         u32 running_bundle_id;
11806         s32 external_temperature;
11807         u32 mdump_reason;
11808 };
11809
11810 struct fw_flr_mb {
11811         u32 aggint;
11812         u32 opgen_addr;
11813         u32 accum_ack;
11814 };
11815
11816 struct public_path {
11817         struct fw_flr_mb flr_mb;
11818         u32 mcp_vf_disabled[VF_MAX_STATIC / 32];
11819
11820         u32 process_kill;
11821 #define PROCESS_KILL_COUNTER_MASK       0x0000ffff
11822 #define PROCESS_KILL_COUNTER_SHIFT      0
11823 #define PROCESS_KILL_GLOB_AEU_BIT_MASK  0xffff0000
11824 #define PROCESS_KILL_GLOB_AEU_BIT_SHIFT 16
11825 #define GLOBAL_AEU_BIT(aeu_reg_id, aeu_bit) (aeu_reg_id * 32 + aeu_bit)
11826 };
11827
11828 struct public_port {
11829         u32 validity_map;
11830
11831         u32 link_status;
11832 #define LINK_STATUS_LINK_UP                     0x00000001
11833 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK       0x0000001e
11834 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD    (1 << 1)
11835 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD    (2 << 1)
11836 #define LINK_STATUS_SPEED_AND_DUPLEX_10G        (3 << 1)
11837 #define LINK_STATUS_SPEED_AND_DUPLEX_20G        (4 << 1)
11838 #define LINK_STATUS_SPEED_AND_DUPLEX_40G        (5 << 1)
11839 #define LINK_STATUS_SPEED_AND_DUPLEX_50G        (6 << 1)
11840 #define LINK_STATUS_SPEED_AND_DUPLEX_100G       (7 << 1)
11841 #define LINK_STATUS_SPEED_AND_DUPLEX_25G        (8 << 1)
11842
11843 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED      0x00000020
11844
11845 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE     0x00000040
11846 #define LINK_STATUS_PARALLEL_DETECTION_USED     0x00000080
11847
11848 #define LINK_STATUS_PFC_ENABLED                         0x00000100
11849 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
11850 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
11851 #define LINK_STATUS_LINK_PARTNER_10G_CAPABLE            0x00000800
11852 #define LINK_STATUS_LINK_PARTNER_20G_CAPABLE            0x00001000
11853 #define LINK_STATUS_LINK_PARTNER_40G_CAPABLE            0x00002000
11854 #define LINK_STATUS_LINK_PARTNER_50G_CAPABLE            0x00004000
11855 #define LINK_STATUS_LINK_PARTNER_100G_CAPABLE           0x00008000
11856 #define LINK_STATUS_LINK_PARTNER_25G_CAPABLE            0x00010000
11857
11858 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK      0x000C0000
11859 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE      (0 << 18)
11860 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE        (1 << 18)
11861 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE       (2 << 18)
11862 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE             (3 << 18)
11863
11864 #define LINK_STATUS_SFP_TX_FAULT                        0x00100000
11865 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED             0x00200000
11866 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED             0x00400000
11867 #define LINK_STATUS_RX_SIGNAL_PRESENT                   0x00800000
11868 #define LINK_STATUS_MAC_LOCAL_FAULT                     0x01000000
11869 #define LINK_STATUS_MAC_REMOTE_FAULT                    0x02000000
11870 #define LINK_STATUS_UNSUPPORTED_SPD_REQ                 0x04000000
11871
11872         u32 link_status1;
11873         u32 ext_phy_fw_version;
11874         u32 drv_phy_cfg_addr;
11875
11876         u32 port_stx;
11877
11878         u32 stat_nig_timer;
11879
11880         struct port_mf_cfg port_mf_config;
11881         struct port_stats stats;
11882
11883         u32 media_type;
11884 #define MEDIA_UNSPECIFIED       0x0
11885 #define MEDIA_SFPP_10G_FIBER    0x1
11886 #define MEDIA_XFP_FIBER         0x2
11887 #define MEDIA_DA_TWINAX         0x3
11888 #define MEDIA_BASE_T            0x4
11889 #define MEDIA_SFP_1G_FIBER      0x5
11890 #define MEDIA_MODULE_FIBER      0x6
11891 #define MEDIA_KR                0xf0
11892 #define MEDIA_NOT_PRESENT       0xff
11893
11894         u32 lfa_status;
11895         u32 link_change_count;
11896
11897         struct lldp_config_params_s lldp_config_params[LLDP_MAX_LLDP_AGENTS];
11898         struct lldp_status_params_s lldp_status_params[LLDP_MAX_LLDP_AGENTS];
11899         struct lldp_system_tlvs_buffer_s system_lldp_tlvs_buf;
11900
11901         /* DCBX related MIB */
11902         struct dcbx_local_params local_admin_dcbx_mib;
11903         struct dcbx_mib remote_dcbx_mib;
11904         struct dcbx_mib operational_dcbx_mib;
11905
11906         u32 reserved[2];
11907         u32 transceiver_data;
11908 #define ETH_TRANSCEIVER_STATE_MASK      0x000000FF
11909 #define ETH_TRANSCEIVER_STATE_SHIFT     0x00000000
11910 #define ETH_TRANSCEIVER_STATE_UNPLUGGED 0x00000000
11911 #define ETH_TRANSCEIVER_STATE_PRESENT   0x00000001
11912 #define ETH_TRANSCEIVER_STATE_VALID     0x00000003
11913 #define ETH_TRANSCEIVER_STATE_UPDATING  0x00000008
11914
11915         u32 wol_info;
11916         u32 wol_pkt_len;
11917         u32 wol_pkt_details;
11918         struct dcb_dscp_map dcb_dscp_map;
11919
11920         u32 eee_status;
11921 #define EEE_ACTIVE_BIT                  BIT(0)
11922 #define EEE_LD_ADV_STATUS_MASK          0x000000f0
11923 #define EEE_LD_ADV_STATUS_OFFSET        4
11924 #define EEE_1G_ADV                      BIT(1)
11925 #define EEE_10G_ADV                     BIT(2)
11926 #define EEE_LP_ADV_STATUS_MASK          0x00000f00
11927 #define EEE_LP_ADV_STATUS_OFFSET        8
11928 #define EEE_SUPPORTED_SPEED_MASK        0x0000f000
11929 #define EEE_SUPPORTED_SPEED_OFFSET      12
11930 #define EEE_1G_SUPPORTED                BIT(1)
11931 #define EEE_10G_SUPPORTED               BIT(2)
11932
11933         u32 eee_remote;
11934 #define EEE_REMOTE_TW_TX_MASK   0x0000ffff
11935 #define EEE_REMOTE_TW_TX_OFFSET 0
11936 #define EEE_REMOTE_TW_RX_MASK   0xffff0000
11937 #define EEE_REMOTE_TW_RX_OFFSET 16
11938 };
11939
11940 struct public_func {
11941         u32 reserved0[2];
11942
11943         u32 mtu_size;
11944
11945         u32 reserved[7];
11946
11947         u32 config;
11948 #define FUNC_MF_CFG_FUNC_HIDE                   0x00000001
11949 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING          0x00000002
11950 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING_SHIFT    0x00000001
11951
11952 #define FUNC_MF_CFG_PROTOCOL_MASK       0x000000f0
11953 #define FUNC_MF_CFG_PROTOCOL_SHIFT      4
11954 #define FUNC_MF_CFG_PROTOCOL_ETHERNET   0x00000000
11955 #define FUNC_MF_CFG_PROTOCOL_ISCSI              0x00000010
11956 #define FUNC_MF_CFG_PROTOCOL_FCOE               0x00000020
11957 #define FUNC_MF_CFG_PROTOCOL_ROCE               0x00000030
11958 #define FUNC_MF_CFG_PROTOCOL_MAX        0x00000030
11959
11960 #define FUNC_MF_CFG_MIN_BW_MASK         0x0000ff00
11961 #define FUNC_MF_CFG_MIN_BW_SHIFT        8
11962 #define FUNC_MF_CFG_MIN_BW_DEFAULT      0x00000000
11963 #define FUNC_MF_CFG_MAX_BW_MASK         0x00ff0000
11964 #define FUNC_MF_CFG_MAX_BW_SHIFT        16
11965 #define FUNC_MF_CFG_MAX_BW_DEFAULT      0x00640000
11966
11967         u32 status;
11968 #define FUNC_STATUS_VLINK_DOWN          0x00000001
11969
11970         u32 mac_upper;
11971 #define FUNC_MF_CFG_UPPERMAC_MASK       0x0000ffff
11972 #define FUNC_MF_CFG_UPPERMAC_SHIFT      0
11973 #define FUNC_MF_CFG_UPPERMAC_DEFAULT    FUNC_MF_CFG_UPPERMAC_MASK
11974         u32 mac_lower;
11975 #define FUNC_MF_CFG_LOWERMAC_DEFAULT    0xffffffff
11976
11977         u32 fcoe_wwn_port_name_upper;
11978         u32 fcoe_wwn_port_name_lower;
11979
11980         u32 fcoe_wwn_node_name_upper;
11981         u32 fcoe_wwn_node_name_lower;
11982
11983         u32 ovlan_stag;
11984 #define FUNC_MF_CFG_OV_STAG_MASK        0x0000ffff
11985 #define FUNC_MF_CFG_OV_STAG_SHIFT       0
11986 #define FUNC_MF_CFG_OV_STAG_DEFAULT     FUNC_MF_CFG_OV_STAG_MASK
11987
11988         u32 pf_allocation;
11989
11990         u32 preserve_data;
11991
11992         u32 driver_last_activity_ts;
11993
11994         u32 drv_ack_vf_disabled[VF_MAX_STATIC / 32];
11995
11996         u32 drv_id;
11997 #define DRV_ID_PDA_COMP_VER_MASK        0x0000ffff
11998 #define DRV_ID_PDA_COMP_VER_SHIFT       0
11999
12000 #define LOAD_REQ_HSI_VERSION            2
12001 #define DRV_ID_MCP_HSI_VER_MASK         0x00ff0000
12002 #define DRV_ID_MCP_HSI_VER_SHIFT        16
12003 #define DRV_ID_MCP_HSI_VER_CURRENT      (LOAD_REQ_HSI_VERSION << \
12004                                          DRV_ID_MCP_HSI_VER_SHIFT)
12005
12006 #define DRV_ID_DRV_TYPE_MASK            0x7f000000
12007 #define DRV_ID_DRV_TYPE_SHIFT           24
12008 #define DRV_ID_DRV_TYPE_UNKNOWN         (0 << DRV_ID_DRV_TYPE_SHIFT)
12009 #define DRV_ID_DRV_TYPE_LINUX           (1 << DRV_ID_DRV_TYPE_SHIFT)
12010
12011 #define DRV_ID_DRV_INIT_HW_MASK         0x80000000
12012 #define DRV_ID_DRV_INIT_HW_SHIFT        31
12013 #define DRV_ID_DRV_INIT_HW_FLAG         (1 << DRV_ID_DRV_INIT_HW_SHIFT)
12014 };
12015
12016 struct mcp_mac {
12017         u32 mac_upper;
12018         u32 mac_lower;
12019 };
12020
12021 struct mcp_val64 {
12022         u32 lo;
12023         u32 hi;
12024 };
12025
12026 struct mcp_file_att {
12027         u32 nvm_start_addr;
12028         u32 len;
12029 };
12030
12031 struct bist_nvm_image_att {
12032         u32 return_code;
12033         u32 image_type;
12034         u32 nvm_start_addr;
12035         u32 len;
12036 };
12037
12038 #define MCP_DRV_VER_STR_SIZE 16
12039 #define MCP_DRV_VER_STR_SIZE_DWORD (MCP_DRV_VER_STR_SIZE / sizeof(u32))
12040 #define MCP_DRV_NVM_BUF_LEN 32
12041 struct drv_version_stc {
12042         u32 version;
12043         u8 name[MCP_DRV_VER_STR_SIZE - 4];
12044 };
12045
12046 struct lan_stats_stc {
12047         u64 ucast_rx_pkts;
12048         u64 ucast_tx_pkts;
12049         u32 fcs_err;
12050         u32 rserved;
12051 };
12052
12053 struct fcoe_stats_stc {
12054         u64 rx_pkts;
12055         u64 tx_pkts;
12056         u32 fcs_err;
12057         u32 login_failure;
12058 };
12059
12060 struct ocbb_data_stc {
12061         u32 ocbb_host_addr;
12062         u32 ocsd_host_addr;
12063         u32 ocsd_req_update_interval;
12064 };
12065
12066 #define MAX_NUM_OF_SENSORS 7
12067 struct temperature_status_stc {
12068         u32 num_of_sensors;
12069         u32 sensor[MAX_NUM_OF_SENSORS];
12070 };
12071
12072 /* crash dump configuration header */
12073 struct mdump_config_stc {
12074         u32 version;
12075         u32 config;
12076         u32 epoc;
12077         u32 num_of_logs;
12078         u32 valid_logs;
12079 };
12080
12081 enum resource_id_enum {
12082         RESOURCE_NUM_SB_E = 0,
12083         RESOURCE_NUM_L2_QUEUE_E = 1,
12084         RESOURCE_NUM_VPORT_E = 2,
12085         RESOURCE_NUM_VMQ_E = 3,
12086         RESOURCE_FACTOR_NUM_RSS_PF_E = 4,
12087         RESOURCE_FACTOR_RSS_PER_VF_E = 5,
12088         RESOURCE_NUM_RL_E = 6,
12089         RESOURCE_NUM_PQ_E = 7,
12090         RESOURCE_NUM_VF_E = 8,
12091         RESOURCE_VFC_FILTER_E = 9,
12092         RESOURCE_ILT_E = 10,
12093         RESOURCE_CQS_E = 11,
12094         RESOURCE_GFT_PROFILES_E = 12,
12095         RESOURCE_NUM_TC_E = 13,
12096         RESOURCE_NUM_RSS_ENGINES_E = 14,
12097         RESOURCE_LL2_QUEUE_E = 15,
12098         RESOURCE_RDMA_STATS_QUEUE_E = 16,
12099         RESOURCE_BDQ_E = 17,
12100         RESOURCE_MAX_NUM,
12101         RESOURCE_NUM_INVALID = 0xFFFFFFFF
12102 };
12103
12104 /* Resource ID is to be filled by the driver in the MB request
12105  * Size, offset & flags to be filled by the MFW in the MB response
12106  */
12107 struct resource_info {
12108         enum resource_id_enum res_id;
12109         u32 size;               /* number of allocated resources */
12110         u32 offset;             /* Offset of the 1st resource */
12111         u32 vf_size;
12112         u32 vf_offset;
12113         u32 flags;
12114 #define RESOURCE_ELEMENT_STRICT (1 << 0)
12115 };
12116
12117 #define DRV_ROLE_NONE           0
12118 #define DRV_ROLE_PREBOOT        1
12119 #define DRV_ROLE_OS             2
12120 #define DRV_ROLE_KDUMP          3
12121
12122 struct load_req_stc {
12123         u32 drv_ver_0;
12124         u32 drv_ver_1;
12125         u32 fw_ver;
12126         u32 misc0;
12127 #define LOAD_REQ_ROLE_MASK              0x000000FF
12128 #define LOAD_REQ_ROLE_SHIFT             0
12129 #define LOAD_REQ_LOCK_TO_MASK           0x0000FF00
12130 #define LOAD_REQ_LOCK_TO_SHIFT          8
12131 #define LOAD_REQ_LOCK_TO_DEFAULT        0
12132 #define LOAD_REQ_LOCK_TO_NONE           255
12133 #define LOAD_REQ_FORCE_MASK             0x000F0000
12134 #define LOAD_REQ_FORCE_SHIFT            16
12135 #define LOAD_REQ_FORCE_NONE             0
12136 #define LOAD_REQ_FORCE_PF               1
12137 #define LOAD_REQ_FORCE_ALL              2
12138 #define LOAD_REQ_FLAGS0_MASK            0x00F00000
12139 #define LOAD_REQ_FLAGS0_SHIFT           20
12140 #define LOAD_REQ_FLAGS0_AVOID_RESET     (0x1 << 0)
12141 };
12142
12143 struct load_rsp_stc {
12144         u32 drv_ver_0;
12145         u32 drv_ver_1;
12146         u32 fw_ver;
12147         u32 misc0;
12148 #define LOAD_RSP_ROLE_MASK              0x000000FF
12149 #define LOAD_RSP_ROLE_SHIFT             0
12150 #define LOAD_RSP_HSI_MASK               0x0000FF00
12151 #define LOAD_RSP_HSI_SHIFT              8
12152 #define LOAD_RSP_FLAGS0_MASK            0x000F0000
12153 #define LOAD_RSP_FLAGS0_SHIFT           16
12154 #define LOAD_RSP_FLAGS0_DRV_EXISTS      (0x1 << 0)
12155 };
12156
12157 union drv_union_data {
12158         u32 ver_str[MCP_DRV_VER_STR_SIZE_DWORD];
12159         struct mcp_mac wol_mac;
12160
12161         struct eth_phy_cfg drv_phy_cfg;
12162
12163         struct mcp_val64 val64;
12164
12165         u8 raw_data[MCP_DRV_NVM_BUF_LEN];
12166
12167         struct mcp_file_att file_att;
12168
12169         u32 ack_vf_disabled[VF_MAX_STATIC / 32];
12170
12171         struct drv_version_stc drv_version;
12172
12173         struct lan_stats_stc lan_stats;
12174         struct fcoe_stats_stc fcoe_stats;
12175         struct ocbb_data_stc ocbb_info;
12176         struct temperature_status_stc temp_info;
12177         struct resource_info resource;
12178         struct bist_nvm_image_att nvm_image_att;
12179         struct mdump_config_stc mdump_config;
12180 };
12181
12182 struct public_drv_mb {
12183         u32 drv_mb_header;
12184 #define DRV_MSG_CODE_MASK                       0xffff0000
12185 #define DRV_MSG_CODE_LOAD_REQ                   0x10000000
12186 #define DRV_MSG_CODE_LOAD_DONE                  0x11000000
12187 #define DRV_MSG_CODE_INIT_HW                    0x12000000
12188 #define DRV_MSG_CODE_CANCEL_LOAD_REQ            0x13000000
12189 #define DRV_MSG_CODE_UNLOAD_REQ                 0x20000000
12190 #define DRV_MSG_CODE_UNLOAD_DONE                0x21000000
12191 #define DRV_MSG_CODE_INIT_PHY                   0x22000000
12192 #define DRV_MSG_CODE_LINK_RESET                 0x23000000
12193 #define DRV_MSG_CODE_SET_DCBX                   0x25000000
12194 #define DRV_MSG_CODE_OV_UPDATE_CURR_CFG         0x26000000
12195 #define DRV_MSG_CODE_OV_UPDATE_BUS_NUM          0x27000000
12196 #define DRV_MSG_CODE_OV_UPDATE_BOOT_PROGRESS    0x28000000
12197 #define DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER     0x29000000
12198 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE     0x31000000
12199 #define DRV_MSG_CODE_BW_UPDATE_ACK              0x32000000
12200 #define DRV_MSG_CODE_OV_UPDATE_MTU              0x33000000
12201 #define DRV_MSG_GET_RESOURCE_ALLOC_MSG          0x34000000
12202 #define DRV_MSG_SET_RESOURCE_VALUE_MSG          0x35000000
12203 #define DRV_MSG_CODE_OV_UPDATE_WOL              0x38000000
12204 #define DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE     0x39000000
12205
12206 #define DRV_MSG_CODE_BW_UPDATE_ACK              0x32000000
12207 #define DRV_MSG_CODE_NIG_DRAIN                  0x30000000
12208 #define DRV_MSG_CODE_S_TAG_UPDATE_ACK           0x3b000000
12209 #define DRV_MSG_CODE_INITIATE_PF_FLR            0x02010000
12210 #define DRV_MSG_CODE_VF_DISABLED_DONE           0xc0000000
12211 #define DRV_MSG_CODE_CFG_VF_MSIX                0xc0010000
12212 #define DRV_MSG_CODE_CFG_PF_VFS_MSIX            0xc0020000
12213 #define DRV_MSG_CODE_NVM_GET_FILE_ATT           0x00030000
12214 #define DRV_MSG_CODE_NVM_READ_NVRAM             0x00050000
12215 #define DRV_MSG_CODE_MCP_RESET                  0x00090000
12216 #define DRV_MSG_CODE_SET_VERSION                0x000f0000
12217 #define DRV_MSG_CODE_MCP_HALT                   0x00100000
12218 #define DRV_MSG_CODE_SET_VMAC                   0x00110000
12219 #define DRV_MSG_CODE_GET_VMAC                   0x00120000
12220 #define DRV_MSG_CODE_VMAC_TYPE_SHIFT            4
12221 #define DRV_MSG_CODE_VMAC_TYPE_MASK             0x30
12222 #define DRV_MSG_CODE_VMAC_TYPE_MAC              1
12223 #define DRV_MSG_CODE_VMAC_TYPE_WWNN             2
12224 #define DRV_MSG_CODE_VMAC_TYPE_WWPN             3
12225
12226 #define DRV_MSG_CODE_GET_STATS                  0x00130000
12227 #define DRV_MSG_CODE_STATS_TYPE_LAN             1
12228 #define DRV_MSG_CODE_STATS_TYPE_FCOE            2
12229 #define DRV_MSG_CODE_STATS_TYPE_ISCSI           3
12230 #define DRV_MSG_CODE_STATS_TYPE_RDMA            4
12231
12232 #define DRV_MSG_CODE_MASK_PARITIES              0x001a0000
12233
12234 #define DRV_MSG_CODE_BIST_TEST                  0x001e0000
12235 #define DRV_MSG_CODE_SET_LED_MODE               0x00200000
12236 #define DRV_MSG_CODE_RESOURCE_CMD       0x00230000
12237
12238 #define RESOURCE_CMD_REQ_RESC_MASK              0x0000001F
12239 #define RESOURCE_CMD_REQ_RESC_SHIFT             0
12240 #define RESOURCE_CMD_REQ_OPCODE_MASK            0x000000E0
12241 #define RESOURCE_CMD_REQ_OPCODE_SHIFT           5
12242 #define RESOURCE_OPCODE_REQ                     1
12243 #define RESOURCE_OPCODE_REQ_WO_AGING            2
12244 #define RESOURCE_OPCODE_REQ_W_AGING             3
12245 #define RESOURCE_OPCODE_RELEASE                 4
12246 #define RESOURCE_OPCODE_FORCE_RELEASE           5
12247 #define RESOURCE_CMD_REQ_AGE_MASK               0x0000FF00
12248 #define RESOURCE_CMD_REQ_AGE_SHIFT              8
12249
12250 #define RESOURCE_CMD_RSP_OWNER_MASK             0x000000FF
12251 #define RESOURCE_CMD_RSP_OWNER_SHIFT            0
12252 #define RESOURCE_CMD_RSP_OPCODE_MASK            0x00000700
12253 #define RESOURCE_CMD_RSP_OPCODE_SHIFT           8
12254 #define RESOURCE_OPCODE_GNT                     1
12255 #define RESOURCE_OPCODE_BUSY                    2
12256 #define RESOURCE_OPCODE_RELEASED                3
12257 #define RESOURCE_OPCODE_RELEASED_PREVIOUS       4
12258 #define RESOURCE_OPCODE_WRONG_OWNER             5
12259 #define RESOURCE_OPCODE_UNKNOWN_CMD             255
12260
12261 #define RESOURCE_DUMP                           0
12262
12263 #define DRV_MSG_CODE_GET_PF_RDMA_PROTOCOL       0x002b0000
12264 #define DRV_MSG_CODE_OS_WOL                     0x002e0000
12265
12266 #define DRV_MSG_CODE_FEATURE_SUPPORT            0x00300000
12267 #define DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT    0x00310000
12268
12269 #define DRV_MSG_SEQ_NUMBER_MASK                 0x0000ffff
12270
12271         u32 drv_mb_param;
12272 #define DRV_MB_PARAM_UNLOAD_WOL_UNKNOWN         0x00000000
12273 #define DRV_MB_PARAM_UNLOAD_WOL_MCP             0x00000001
12274 #define DRV_MB_PARAM_UNLOAD_WOL_DISABLED        0x00000002
12275 #define DRV_MB_PARAM_UNLOAD_WOL_ENABLED         0x00000003
12276 #define DRV_MB_PARAM_DCBX_NOTIFY_MASK           0x000000FF
12277 #define DRV_MB_PARAM_DCBX_NOTIFY_SHIFT          3
12278
12279 #define DRV_MB_PARAM_NVM_LEN_OFFSET             24
12280
12281 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT    0
12282 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK     0x000000FF
12283 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT   8
12284 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK    0x0000FF00
12285 #define DRV_MB_PARAM_LLDP_SEND_MASK             0x00000001
12286 #define DRV_MB_PARAM_LLDP_SEND_SHIFT            0
12287
12288 #define DRV_MB_PARAM_OV_CURR_CFG_SHIFT          0
12289 #define DRV_MB_PARAM_OV_CURR_CFG_MASK           0x0000000F
12290 #define DRV_MB_PARAM_OV_CURR_CFG_NONE           0
12291 #define DRV_MB_PARAM_OV_CURR_CFG_OS             1
12292 #define DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC    2
12293 #define DRV_MB_PARAM_OV_CURR_CFG_OTHER          3
12294
12295 #define DRV_MB_PARAM_OV_STORM_FW_VER_SHIFT      0
12296 #define DRV_MB_PARAM_OV_STORM_FW_VER_MASK       0xFFFFFFFF
12297 #define DRV_MB_PARAM_OV_STORM_FW_VER_MAJOR_MASK 0xFF000000
12298 #define DRV_MB_PARAM_OV_STORM_FW_VER_MINOR_MASK 0x00FF0000
12299 #define DRV_MB_PARAM_OV_STORM_FW_VER_BUILD_MASK 0x0000FF00
12300 #define DRV_MB_PARAM_OV_STORM_FW_VER_DROP_MASK  0x000000FF
12301
12302 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_SHIFT       0
12303 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_MASK        0xF
12304 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_UNKNOWN     0x1
12305 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED  0x2
12306 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_LOADING     0x3
12307 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED    0x4
12308 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE      0x5
12309
12310 #define DRV_MB_PARAM_OV_MTU_SIZE_SHIFT  0
12311 #define DRV_MB_PARAM_OV_MTU_SIZE_MASK   0xFFFFFFFF
12312
12313 #define DRV_MB_PARAM_WOL_MASK   (DRV_MB_PARAM_WOL_DEFAULT | \
12314                                  DRV_MB_PARAM_WOL_DISABLED | \
12315                                  DRV_MB_PARAM_WOL_ENABLED)
12316 #define DRV_MB_PARAM_WOL_DEFAULT        DRV_MB_PARAM_UNLOAD_WOL_MCP
12317 #define DRV_MB_PARAM_WOL_DISABLED       DRV_MB_PARAM_UNLOAD_WOL_DISABLED
12318 #define DRV_MB_PARAM_WOL_ENABLED        DRV_MB_PARAM_UNLOAD_WOL_ENABLED
12319
12320 #define DRV_MB_PARAM_ESWITCH_MODE_MASK  (DRV_MB_PARAM_ESWITCH_MODE_NONE | \
12321                                          DRV_MB_PARAM_ESWITCH_MODE_VEB | \
12322                                          DRV_MB_PARAM_ESWITCH_MODE_VEPA)
12323 #define DRV_MB_PARAM_ESWITCH_MODE_NONE  0x0
12324 #define DRV_MB_PARAM_ESWITCH_MODE_VEB   0x1
12325 #define DRV_MB_PARAM_ESWITCH_MODE_VEPA  0x2
12326
12327 #define DRV_MB_PARAM_SET_LED_MODE_OPER          0x0
12328 #define DRV_MB_PARAM_SET_LED_MODE_ON            0x1
12329 #define DRV_MB_PARAM_SET_LED_MODE_OFF           0x2
12330
12331         /* Resource Allocation params - Driver version support */
12332 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK  0xFFFF0000
12333 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT 16
12334 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK  0x0000FFFF
12335 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT 0
12336
12337 #define DRV_MB_PARAM_BIST_REGISTER_TEST         1
12338 #define DRV_MB_PARAM_BIST_CLOCK_TEST            2
12339 #define DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES   3
12340 #define DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX       4
12341
12342 #define DRV_MB_PARAM_BIST_RC_UNKNOWN            0
12343 #define DRV_MB_PARAM_BIST_RC_PASSED             1
12344 #define DRV_MB_PARAM_BIST_RC_FAILED             2
12345 #define DRV_MB_PARAM_BIST_RC_INVALID_PARAMETER  3
12346
12347 #define DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT      0
12348 #define DRV_MB_PARAM_BIST_TEST_INDEX_MASK       0x000000FF
12349 #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT        8
12350 #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_MASK         0x0000FF00
12351
12352 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_MASK          0x0000FFFF
12353 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_OFFSET        0
12354 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE           0x00000002
12355
12356         u32 fw_mb_header;
12357 #define FW_MSG_CODE_MASK                        0xffff0000
12358 #define FW_MSG_CODE_UNSUPPORTED                 0x00000000
12359 #define FW_MSG_CODE_DRV_LOAD_ENGINE             0x10100000
12360 #define FW_MSG_CODE_DRV_LOAD_PORT               0x10110000
12361 #define FW_MSG_CODE_DRV_LOAD_FUNCTION           0x10120000
12362 #define FW_MSG_CODE_DRV_LOAD_REFUSED_PDA        0x10200000
12363 #define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1      0x10210000
12364 #define FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG       0x10220000
12365 #define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI        0x10230000
12366 #define FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE 0x10300000
12367 #define FW_MSG_CODE_DRV_LOAD_REFUSED_REJECT     0x10310000
12368 #define FW_MSG_CODE_DRV_LOAD_DONE               0x11100000
12369 #define FW_MSG_CODE_DRV_UNLOAD_ENGINE           0x20110000
12370 #define FW_MSG_CODE_DRV_UNLOAD_PORT             0x20120000
12371 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION         0x20130000
12372 #define FW_MSG_CODE_DRV_UNLOAD_DONE             0x21100000
12373 #define FW_MSG_CODE_RESOURCE_ALLOC_OK           0x34000000
12374 #define FW_MSG_CODE_RESOURCE_ALLOC_UNKNOWN      0x35000000
12375 #define FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED   0x36000000
12376 #define FW_MSG_CODE_S_TAG_UPDATE_ACK_DONE       0x3b000000
12377 #define FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE        0xb0010000
12378
12379 #define FW_MSG_CODE_NVM_OK                      0x00010000
12380 #define FW_MSG_CODE_OK                          0x00160000
12381
12382 #define FW_MSG_CODE_OS_WOL_SUPPORTED            0x00800000
12383 #define FW_MSG_CODE_OS_WOL_NOT_SUPPORTED        0x00810000
12384 #define FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE    0x00870000
12385 #define FW_MSG_SEQ_NUMBER_MASK                  0x0000ffff
12386
12387         u32 fw_mb_param;
12388 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK   0xFFFF0000
12389 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT  16
12390 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK   0x0000FFFF
12391 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT  0
12392
12393         /* get pf rdma protocol command responce */
12394 #define FW_MB_PARAM_GET_PF_RDMA_NONE            0x0
12395 #define FW_MB_PARAM_GET_PF_RDMA_ROCE            0x1
12396 #define FW_MB_PARAM_GET_PF_RDMA_IWARP           0x2
12397 #define FW_MB_PARAM_GET_PF_RDMA_BOTH            0x3
12398
12399 /* get MFW feature support response */
12400 #define FW_MB_PARAM_FEATURE_SUPPORT_EEE         0x00000002
12401
12402 #define FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR   (1 << 0)
12403
12404         u32 drv_pulse_mb;
12405 #define DRV_PULSE_SEQ_MASK                      0x00007fff
12406 #define DRV_PULSE_SYSTEM_TIME_MASK              0xffff0000
12407 #define DRV_PULSE_ALWAYS_ALIVE                  0x00008000
12408
12409         u32 mcp_pulse_mb;
12410 #define MCP_PULSE_SEQ_MASK                      0x00007fff
12411 #define MCP_PULSE_ALWAYS_ALIVE                  0x00008000
12412 #define MCP_EVENT_MASK                          0xffff0000
12413 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ        0x00010000
12414
12415         union drv_union_data union_data;
12416 };
12417
12418 enum MFW_DRV_MSG_TYPE {
12419         MFW_DRV_MSG_LINK_CHANGE,
12420         MFW_DRV_MSG_FLR_FW_ACK_FAILED,
12421         MFW_DRV_MSG_VF_DISABLED,
12422         MFW_DRV_MSG_LLDP_DATA_UPDATED,
12423         MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED,
12424         MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED,
12425         MFW_DRV_MSG_RESERVED4,
12426         MFW_DRV_MSG_BW_UPDATE,
12427         MFW_DRV_MSG_S_TAG_UPDATE,
12428         MFW_DRV_MSG_GET_LAN_STATS,
12429         MFW_DRV_MSG_GET_FCOE_STATS,
12430         MFW_DRV_MSG_GET_ISCSI_STATS,
12431         MFW_DRV_MSG_GET_RDMA_STATS,
12432         MFW_DRV_MSG_BW_UPDATE10,
12433         MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE,
12434         MFW_DRV_MSG_BW_UPDATE11,
12435         MFW_DRV_MSG_MAX
12436 };
12437
12438 #define MFW_DRV_MSG_MAX_DWORDS(msgs)    (((msgs - 1) >> 2) + 1)
12439 #define MFW_DRV_MSG_DWORD(msg_id)       (msg_id >> 2)
12440 #define MFW_DRV_MSG_OFFSET(msg_id)      ((msg_id & 0x3) << 3)
12441 #define MFW_DRV_MSG_MASK(msg_id)        (0xff << MFW_DRV_MSG_OFFSET(msg_id))
12442
12443 struct public_mfw_mb {
12444         u32 sup_msgs;
12445         u32 msg[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)];
12446         u32 ack[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)];
12447 };
12448
12449 enum public_sections {
12450         PUBLIC_DRV_MB,
12451         PUBLIC_MFW_MB,
12452         PUBLIC_GLOBAL,
12453         PUBLIC_PATH,
12454         PUBLIC_PORT,
12455         PUBLIC_FUNC,
12456         PUBLIC_MAX_SECTIONS
12457 };
12458
12459 struct mcp_public_data {
12460         u32 num_sections;
12461         u32 sections[PUBLIC_MAX_SECTIONS];
12462         struct public_drv_mb drv_mb[MCP_GLOB_FUNC_MAX];
12463         struct public_mfw_mb mfw_mb[MCP_GLOB_FUNC_MAX];
12464         struct public_global global;
12465         struct public_path path[MCP_GLOB_PATH_MAX];
12466         struct public_port port[MCP_GLOB_PORT_MAX];
12467         struct public_func func[MCP_GLOB_FUNC_MAX];
12468 };
12469
12470 struct nvm_cfg_mac_address {
12471         u32 mac_addr_hi;
12472 #define NVM_CFG_MAC_ADDRESS_HI_MASK     0x0000FFFF
12473 #define NVM_CFG_MAC_ADDRESS_HI_OFFSET   0
12474         u32 mac_addr_lo;
12475 };
12476
12477 struct nvm_cfg1_glob {
12478         u32 generic_cont0;
12479 #define NVM_CFG1_GLOB_MF_MODE_MASK              0x00000FF0
12480 #define NVM_CFG1_GLOB_MF_MODE_OFFSET            4
12481 #define NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED        0x0
12482 #define NVM_CFG1_GLOB_MF_MODE_DEFAULT           0x1
12483 #define NVM_CFG1_GLOB_MF_MODE_SPIO4             0x2
12484 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_0           0x3
12485 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_5           0x4
12486 #define NVM_CFG1_GLOB_MF_MODE_NPAR2_0           0x5
12487 #define NVM_CFG1_GLOB_MF_MODE_BD                0x6
12488 #define NVM_CFG1_GLOB_MF_MODE_UFP               0x7
12489         u32 engineering_change[3];
12490         u32 manufacturing_id;
12491         u32 serial_number[4];
12492         u32 pcie_cfg;
12493         u32 mgmt_traffic;
12494         u32 core_cfg;
12495 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK            0x000000FF
12496 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET          0
12497 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G        0x0
12498 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G           0x1
12499 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G       0x2
12500 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F         0x3
12501 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E      0x4
12502 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G        0x5
12503 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G           0xB
12504 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G           0xC
12505 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G           0xD
12506 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G           0xE
12507 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G           0xF
12508
12509         u32 e_lane_cfg1;
12510         u32 e_lane_cfg2;
12511         u32 f_lane_cfg1;
12512         u32 f_lane_cfg2;
12513         u32 mps10_preemphasis;
12514         u32 mps10_driver_current;
12515         u32 mps25_preemphasis;
12516         u32 mps25_driver_current;
12517         u32 pci_id;
12518         u32 pci_subsys_id;
12519         u32 bar;
12520         u32 mps10_txfir_main;
12521         u32 mps10_txfir_post;
12522         u32 mps25_txfir_main;
12523         u32 mps25_txfir_post;
12524         u32 manufacture_ver;
12525         u32 manufacture_time;
12526         u32 led_global_settings;
12527         u32 generic_cont1;
12528         u32 mbi_version;
12529 #define NVM_CFG1_GLOB_MBI_VERSION_0_MASK                0x000000FF
12530 #define NVM_CFG1_GLOB_MBI_VERSION_0_OFFSET              0
12531 #define NVM_CFG1_GLOB_MBI_VERSION_1_MASK                0x0000FF00
12532 #define NVM_CFG1_GLOB_MBI_VERSION_1_OFFSET              8
12533 #define NVM_CFG1_GLOB_MBI_VERSION_2_MASK                0x00FF0000
12534 #define NVM_CFG1_GLOB_MBI_VERSION_2_OFFSET              16
12535         u32 mbi_date;
12536         u32 misc_sig;
12537         u32 device_capabilities;
12538 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET      0x1
12539 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE          0x2
12540 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI         0x4
12541 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE          0x8
12542         u32 power_dissipated;
12543         u32 power_consumed;
12544         u32 efi_version;
12545         u32 multi_network_modes_capability;
12546         u32 reserved[41];
12547 };
12548
12549 struct nvm_cfg1_path {
12550         u32 reserved[30];
12551 };
12552
12553 struct nvm_cfg1_port {
12554         u32 reserved__m_relocated_to_option_123;
12555         u32 reserved__m_relocated_to_option_124;
12556         u32 generic_cont0;
12557 #define NVM_CFG1_PORT_DCBX_MODE_MASK                            0x000F0000
12558 #define NVM_CFG1_PORT_DCBX_MODE_OFFSET                          16
12559 #define NVM_CFG1_PORT_DCBX_MODE_DISABLED                        0x0
12560 #define NVM_CFG1_PORT_DCBX_MODE_IEEE                            0x1
12561 #define NVM_CFG1_PORT_DCBX_MODE_CEE                             0x2
12562 #define NVM_CFG1_PORT_DCBX_MODE_DYNAMIC                         0x3
12563 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_MASK            0x00F00000
12564 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_OFFSET          20
12565 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ETHERNET        0x1
12566 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_FCOE            0x2
12567 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ISCSI           0x4
12568         u32 pcie_cfg;
12569         u32 features;
12570         u32 speed_cap_mask;
12571 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK            0x0000FFFF
12572 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_OFFSET          0
12573 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G              0x1
12574 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G             0x2
12575 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G             0x8
12576 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G             0x10
12577 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G             0x20
12578 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G         0x40
12579         u32 link_settings;
12580 #define NVM_CFG1_PORT_DRV_LINK_SPEED_MASK                       0x0000000F
12581 #define NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET                     0
12582 #define NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG                    0x0
12583 #define NVM_CFG1_PORT_DRV_LINK_SPEED_1G                         0x1
12584 #define NVM_CFG1_PORT_DRV_LINK_SPEED_10G                        0x2
12585 #define NVM_CFG1_PORT_DRV_LINK_SPEED_25G                        0x4
12586 #define NVM_CFG1_PORT_DRV_LINK_SPEED_40G                        0x5
12587 #define NVM_CFG1_PORT_DRV_LINK_SPEED_50G                        0x6
12588 #define NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G                    0x7
12589 #define NVM_CFG1_PORT_DRV_LINK_SPEED_SMARTLINQ                  0x8
12590 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK                     0x00000070
12591 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET                   4
12592 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG                  0x1
12593 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX                       0x2
12594 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX                       0x4
12595         u32 phy_cfg;
12596         u32 mgmt_traffic;
12597
12598         u32 ext_phy;
12599         /* EEE power saving mode */
12600 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK                0x00FF0000
12601 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET              16
12602 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED            0x0
12603 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED            0x1
12604 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE          0x2
12605 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY         0x3
12606
12607         u32 mba_cfg1;
12608         u32 mba_cfg2;
12609         u32 vf_cfg;
12610         struct nvm_cfg_mac_address lldp_mac_address;
12611         u32 led_port_settings;
12612         u32 transceiver_00;
12613         u32 device_ids;
12614         u32 board_cfg;
12615         u32 mnm_10g_cap;
12616         u32 mnm_10g_ctrl;
12617         u32 mnm_10g_misc;
12618         u32 mnm_25g_cap;
12619         u32 mnm_25g_ctrl;
12620         u32 mnm_25g_misc;
12621         u32 mnm_40g_cap;
12622         u32 mnm_40g_ctrl;
12623         u32 mnm_40g_misc;
12624         u32 mnm_50g_cap;
12625         u32 mnm_50g_ctrl;
12626         u32 mnm_50g_misc;
12627         u32 mnm_100g_cap;
12628         u32 mnm_100g_ctrl;
12629         u32 mnm_100g_misc;
12630         u32 reserved[116];
12631 };
12632
12633 struct nvm_cfg1_func {
12634         struct nvm_cfg_mac_address mac_address;
12635         u32 rsrv1;
12636         u32 rsrv2;
12637         u32 device_id;
12638         u32 cmn_cfg;
12639         u32 pci_cfg;
12640         struct nvm_cfg_mac_address fcoe_node_wwn_mac_addr;
12641         struct nvm_cfg_mac_address fcoe_port_wwn_mac_addr;
12642         u32 preboot_generic_cfg;
12643         u32 reserved[8];
12644 };
12645
12646 struct nvm_cfg1 {
12647         struct nvm_cfg1_glob glob;
12648         struct nvm_cfg1_path path[MCP_GLOB_PATH_MAX];
12649         struct nvm_cfg1_port port[MCP_GLOB_PORT_MAX];
12650         struct nvm_cfg1_func func[MCP_GLOB_FUNC_MAX];
12651 };
12652
12653 enum spad_sections {
12654         SPAD_SECTION_TRACE,
12655         SPAD_SECTION_NVM_CFG,
12656         SPAD_SECTION_PUBLIC,
12657         SPAD_SECTION_PRIVATE,
12658         SPAD_SECTION_MAX
12659 };
12660
12661 #define MCP_TRACE_SIZE          2048    /* 2kb */
12662
12663 /* This section is located at a fixed location in the beginning of the
12664  * scratchpad, to ensure that the MCP trace is not run over during MFW upgrade.
12665  * All the rest of data has a floating location which differs from version to
12666  * version, and is pointed by the mcp_meta_data below.
12667  * Moreover, the spad_layout section is part of the MFW firmware, and is loaded
12668  * with it from nvram in order to clear this portion.
12669  */
12670 struct static_init {
12671         u32 num_sections;
12672         offsize_t sections[SPAD_SECTION_MAX];
12673 #define SECTION(_sec_) (*((offsize_t *)(STRUCT_OFFSET(sections[_sec_]))))
12674
12675         struct mcp_trace trace;
12676 #define MCP_TRACE_P ((struct mcp_trace *)(STRUCT_OFFSET(trace)))
12677         u8 trace_buffer[MCP_TRACE_SIZE];
12678 #define MCP_TRACE_BUF ((u8 *)(STRUCT_OFFSET(trace_buffer)))
12679         /* running_mfw has the same definition as in nvm_map.h.
12680          * This bit indicate both the running dir, and the running bundle.
12681          * It is set once when the LIM is loaded.
12682          */
12683         u32 running_mfw;
12684 #define RUNNING_MFW (*((u32 *)(STRUCT_OFFSET(running_mfw))))
12685         u32 build_time;
12686 #define MFW_BUILD_TIME (*((u32 *)(STRUCT_OFFSET(build_time))))
12687         u32 reset_type;
12688 #define RESET_TYPE (*((u32 *)(STRUCT_OFFSET(reset_type))))
12689         u32 mfw_secure_mode;
12690 #define MFW_SECURE_MODE (*((u32 *)(STRUCT_OFFSET(mfw_secure_mode))))
12691         u16 pme_status_pf_bitmap;
12692 #define PME_STATUS_PF_BITMAP (*((u16 *)(STRUCT_OFFSET(pme_status_pf_bitmap))))
12693         u16 pme_enable_pf_bitmap;
12694 #define PME_ENABLE_PF_BITMAP (*((u16 *)(STRUCT_OFFSET(pme_enable_pf_bitmap))))
12695         u32 mim_nvm_addr;
12696         u32 mim_start_addr;
12697         u32 ah_pcie_link_params;
12698 #define AH_PCIE_LINK_PARAMS_LINK_SPEED_MASK     (0x000000ff)
12699 #define AH_PCIE_LINK_PARAMS_LINK_SPEED_SHIFT    (0)
12700 #define AH_PCIE_LINK_PARAMS_LINK_WIDTH_MASK     (0x0000ff00)
12701 #define AH_PCIE_LINK_PARAMS_LINK_WIDTH_SHIFT    (8)
12702 #define AH_PCIE_LINK_PARAMS_ASPM_MODE_MASK      (0x00ff0000)
12703 #define AH_PCIE_LINK_PARAMS_ASPM_MODE_SHIFT     (16)
12704 #define AH_PCIE_LINK_PARAMS_ASPM_CAP_MASK       (0xff000000)
12705 #define AH_PCIE_LINK_PARAMS_ASPM_CAP_SHIFT      (24)
12706 #define AH_PCIE_LINK_PARAMS (*((u32 *)(STRUCT_OFFSET(ah_pcie_link_params))))
12707
12708         u32 rsrv_persist[5];    /* Persist reserved for MFW upgrades */
12709 };
12710
12711 #define NVM_MAGIC_VALUE         0x669955aa
12712
12713 enum nvm_image_type {
12714         NVM_TYPE_TIM1 = 0x01,
12715         NVM_TYPE_TIM2 = 0x02,
12716         NVM_TYPE_MIM1 = 0x03,
12717         NVM_TYPE_MIM2 = 0x04,
12718         NVM_TYPE_MBA = 0x05,
12719         NVM_TYPE_MODULES_PN = 0x06,
12720         NVM_TYPE_VPD = 0x07,
12721         NVM_TYPE_MFW_TRACE1 = 0x08,
12722         NVM_TYPE_MFW_TRACE2 = 0x09,
12723         NVM_TYPE_NVM_CFG1 = 0x0a,
12724         NVM_TYPE_L2B = 0x0b,
12725         NVM_TYPE_DIR1 = 0x0c,
12726         NVM_TYPE_EAGLE_FW1 = 0x0d,
12727         NVM_TYPE_FALCON_FW1 = 0x0e,
12728         NVM_TYPE_PCIE_FW1 = 0x0f,
12729         NVM_TYPE_HW_SET = 0x10,
12730         NVM_TYPE_LIM = 0x11,
12731         NVM_TYPE_AVS_FW1 = 0x12,
12732         NVM_TYPE_DIR2 = 0x13,
12733         NVM_TYPE_CCM = 0x14,
12734         NVM_TYPE_EAGLE_FW2 = 0x15,
12735         NVM_TYPE_FALCON_FW2 = 0x16,
12736         NVM_TYPE_PCIE_FW2 = 0x17,
12737         NVM_TYPE_AVS_FW2 = 0x18,
12738         NVM_TYPE_INIT_HW = 0x19,
12739         NVM_TYPE_DEFAULT_CFG = 0x1a,
12740         NVM_TYPE_MDUMP = 0x1b,
12741         NVM_TYPE_META = 0x1c,
12742         NVM_TYPE_ISCSI_CFG = 0x1d,
12743         NVM_TYPE_FCOE_CFG = 0x1f,
12744         NVM_TYPE_ETH_PHY_FW1 = 0x20,
12745         NVM_TYPE_ETH_PHY_FW2 = 0x21,
12746         NVM_TYPE_MAX,
12747 };
12748
12749 #define DIR_ID_1    (0)
12750
12751 #endif