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x86/topology: Fix function name in documentation
[cris-mirror.git] / drivers / net / ethernet / qlogic / qed / qed_init_fw_funcs.c
blob18fb5062a83d09c68ba962f88c1f41f31dd712ad
1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015-2017 QLogic Corporation
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/types.h>
34 #include <linux/crc8.h>
35 #include <linux/delay.h>
36 #include <linux/kernel.h>
37 #include <linux/slab.h>
38 #include <linux/string.h>
39 #include "qed_hsi.h"
40 #include "qed_hw.h"
41 #include "qed_init_ops.h"
42 #include "qed_reg_addr.h"
43
44 #define CDU_VALIDATION_DEFAULT_CFG 61
45
46 static u16 con_region_offsets[3][NUM_OF_CONNECTION_TYPES_E4] = {
47 {400, 336, 352, 304, 304, 384, 416, 352}, /* region 3 offsets */
48 {528, 496, 416, 448, 448, 512, 544, 480}, /* region 4 offsets */
49 {608, 544, 496, 512, 576, 592, 624, 560} /* region 5 offsets */
50 };
51
52 static u16 task_region_offsets[1][NUM_OF_CONNECTION_TYPES_E4] = {
53 {240, 240, 112, 0, 0, 0, 0, 96} /* region 1 offsets */
54 };
55
56 /* General constants */
57 #define QM_PQ_MEM_4KB(pq_size) (pq_size ? DIV_ROUND_UP((pq_size + 1) * \
58 QM_PQ_ELEMENT_SIZE, \
59 0x1000) : 0)
60 #define QM_PQ_SIZE_256B(pq_size) (pq_size ? DIV_ROUND_UP(pq_size, \
61 0x100) - 1 : 0)
62 #define QM_INVALID_PQ_ID 0xffff
63
64 /* Feature enable */
65 #define QM_BYPASS_EN 1
66 #define QM_BYTE_CRD_EN 1
67
68 /* Other PQ constants */
69 #define QM_OTHER_PQS_PER_PF 4
70
71 /* WFQ constants */
72
73 /* Upper bound in MB, 10 * burst size of 1ms in 50Gbps */
74 #define QM_WFQ_UPPER_BOUND 62500000
75
76 /* Bit of VOQ in WFQ VP PQ map */
77 #define QM_WFQ_VP_PQ_VOQ_SHIFT 0
78
79 /* Bit of PF in WFQ VP PQ map */
80 #define QM_WFQ_VP_PQ_PF_E4_SHIFT 5
81
82 /* 0x9000 = 4*9*1024 */
83 #define QM_WFQ_INC_VAL(weight) ((weight) * 0x9000)
84
85 /* Max WFQ increment value is 0.7 * upper bound */
86 #define QM_WFQ_MAX_INC_VAL ((QM_WFQ_UPPER_BOUND * 7) / 10)
87
88 /* RL constants */
89
90 /* Period in us */
91 #define QM_RL_PERIOD 5
92
93 /* Period in 25MHz cycles */
94 #define QM_RL_PERIOD_CLK_25M (25 * QM_RL_PERIOD)
95
96 /* RL increment value - rate is specified in mbps */
97 #define QM_RL_INC_VAL(rate) ({ \
98 typeof(rate) __rate = (rate); \
99 max_t(u32, \
100 (u32)(((__rate ? __rate : 1000000) * QM_RL_PERIOD * 101) / \
101 (8 * 100)), \
102 1); })
103
104 /* PF RL Upper bound is set to 10 * burst size of 1ms in 50Gbps */
105 #define QM_PF_RL_UPPER_BOUND 62500000
106
107 /* Max PF RL increment value is 0.7 * upper bound */
108 #define QM_PF_RL_MAX_INC_VAL ((QM_PF_RL_UPPER_BOUND * 7) / 10)
109
110 /* Vport RL Upper bound, link speed is in Mpbs */
111 #define QM_VP_RL_UPPER_BOUND(speed) ((u32)max_t(u32, \
112 QM_RL_INC_VAL(speed), \
113 9700 + 1000))
114
115 /* Max Vport RL increment value is the Vport RL upper bound */
116 #define QM_VP_RL_MAX_INC_VAL(speed) QM_VP_RL_UPPER_BOUND(speed)
117
118 /* Vport RL credit threshold in case of QM bypass */
119 #define QM_VP_RL_BYPASS_THRESH_SPEED (QM_VP_RL_UPPER_BOUND(10000) - 1)
120
121 /* AFullOprtnstcCrdMask constants */
122 #define QM_OPPOR_LINE_VOQ_DEF 1
123 #define QM_OPPOR_FW_STOP_DEF 0
124 #define QM_OPPOR_PQ_EMPTY_DEF 1
125
126 /* Command Queue constants */
127
128 /* Pure LB CmdQ lines (+spare) */
129 #define PBF_CMDQ_PURE_LB_LINES 150
130
131 #define PBF_CMDQ_LINES_E5_RSVD_RATIO 8
132
133 #define PBF_CMDQ_LINES_RT_OFFSET(ext_voq) \
134 (PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET + \
135 (ext_voq) * (PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET - \
136 PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET))
137
138 #define PBF_BTB_GUARANTEED_RT_OFFSET(ext_voq) \
139 (PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET + \
140 (ext_voq) * (PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET - \
141 PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET))
142
143 #define QM_VOQ_LINE_CRD(pbf_cmd_lines) \
144 ((((pbf_cmd_lines) - 4) * 2) | QM_LINE_CRD_REG_SIGN_BIT)
145
146 /* BTB: blocks constants (block size = 256B) */
147
148 /* 256B blocks in 9700B packet */
149 #define BTB_JUMBO_PKT_BLOCKS 38
150
151 /* Headroom per-port */
152 #define BTB_HEADROOM_BLOCKS BTB_JUMBO_PKT_BLOCKS
153 #define BTB_PURE_LB_FACTOR 10
154
155 /* Factored (hence really 0.7) */
156 #define BTB_PURE_LB_RATIO 7
157
158 /* QM stop command constants */
159 #define QM_STOP_PQ_MASK_WIDTH 32
160 #define QM_STOP_CMD_ADDR 2
161 #define QM_STOP_CMD_STRUCT_SIZE 2
162 #define QM_STOP_CMD_PAUSE_MASK_OFFSET 0
163 #define QM_STOP_CMD_PAUSE_MASK_SHIFT 0
164 #define QM_STOP_CMD_PAUSE_MASK_MASK -1
165 #define QM_STOP_CMD_GROUP_ID_OFFSET 1
166 #define QM_STOP_CMD_GROUP_ID_SHIFT 16
167 #define QM_STOP_CMD_GROUP_ID_MASK 15
168 #define QM_STOP_CMD_PQ_TYPE_OFFSET 1
169 #define QM_STOP_CMD_PQ_TYPE_SHIFT 24
170 #define QM_STOP_CMD_PQ_TYPE_MASK 1
171 #define QM_STOP_CMD_MAX_POLL_COUNT 100
172 #define QM_STOP_CMD_POLL_PERIOD_US 500
173
174 /* QM command macros */
175 #define QM_CMD_STRUCT_SIZE(cmd) cmd ## _STRUCT_SIZE
176 #define QM_CMD_SET_FIELD(var, cmd, field, value) \
177 SET_FIELD(var[cmd ## _ ## field ## _OFFSET], \
178 cmd ## _ ## field, \
179 value)
180
181 #define QM_INIT_TX_PQ_MAP(p_hwfn, map, chip, pq_id, rl_valid, vp_pq_id, rl_id, \
182 ext_voq, wrr) \
183 do { \
184 typeof(map) __map; \
185 memset(&__map, 0, sizeof(__map)); \
186 SET_FIELD(__map.reg, QM_RF_PQ_MAP_ ## chip ## _PQ_VALID, 1); \
187 SET_FIELD(__map.reg, QM_RF_PQ_MAP_ ## chip ## _RL_VALID, \
188 rl_valid); \
189 SET_FIELD(__map.reg, QM_RF_PQ_MAP_ ## chip ## _VP_PQ_ID, \
190 vp_pq_id); \
191 SET_FIELD(__map.reg, QM_RF_PQ_MAP_ ## chip ## _RL_ID, rl_id); \
192 SET_FIELD(__map.reg, QM_RF_PQ_MAP_ ## chip ## _VOQ, ext_voq); \
193 SET_FIELD(__map.reg, \
194 QM_RF_PQ_MAP_ ## chip ## _WRR_WEIGHT_GROUP, wrr); \
195 STORE_RT_REG(p_hwfn, QM_REG_TXPQMAP_RT_OFFSET + (pq_id), \
196 *((u32 *)&__map)); \
197 (map) = __map; \
198 } while (0)
199
200 #define WRITE_PQ_INFO_TO_RAM 1
201 #define PQ_INFO_ELEMENT(vp, pf, tc, port, rl_valid, rl) \
202 (((vp) << 0) | ((pf) << 12) | ((tc) << 16) | ((port) << 20) | \
203 ((rl_valid) << 22) | ((rl) << 24))
204 #define PQ_INFO_RAM_GRC_ADDRESS(pq_id) \
205 (XSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM + 21776 + (pq_id) * 4)
206
207 /******************** INTERNAL IMPLEMENTATION *********************/
208
209 /* Returns the external VOQ number */
210 static u8 qed_get_ext_voq(struct qed_hwfn *p_hwfn,
211 u8 port_id, u8 tc, u8 max_phys_tcs_per_port)
212 {
213 if (tc == PURE_LB_TC)
214 return NUM_OF_PHYS_TCS * MAX_NUM_PORTS_BB + port_id;
215 else
216 return port_id * max_phys_tcs_per_port + tc;
217 }
218
219 /* Prepare PF RL enable/disable runtime init values */
220 static void qed_enable_pf_rl(struct qed_hwfn *p_hwfn, bool pf_rl_en)
221 {
222 STORE_RT_REG(p_hwfn, QM_REG_RLPFENABLE_RT_OFFSET, pf_rl_en ? 1 : 0);
223 if (pf_rl_en) {
224 u8 num_ext_voqs = MAX_NUM_VOQS_E4;
225 u64 voq_bit_mask = ((u64)1 << num_ext_voqs) - 1;
226
227 /* Enable RLs for all VOQs */
228 STORE_RT_REG(p_hwfn,
229 QM_REG_RLPFVOQENABLE_RT_OFFSET,
230 (u32)voq_bit_mask);
231 if (num_ext_voqs >= 32)
232 STORE_RT_REG(p_hwfn, QM_REG_RLPFVOQENABLE_MSB_RT_OFFSET,
233 (u32)(voq_bit_mask >> 32));
234
235 /* Write RL period */
236 STORE_RT_REG(p_hwfn,
237 QM_REG_RLPFPERIOD_RT_OFFSET, QM_RL_PERIOD_CLK_25M);
238 STORE_RT_REG(p_hwfn,
239 QM_REG_RLPFPERIODTIMER_RT_OFFSET,
240 QM_RL_PERIOD_CLK_25M);
241
242 /* Set credit threshold for QM bypass flow */
243 if (QM_BYPASS_EN)
244 STORE_RT_REG(p_hwfn,
245 QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET,
246 QM_PF_RL_UPPER_BOUND);
247 }
248 }
249
250 /* Prepare PF WFQ enable/disable runtime init values */
251 static void qed_enable_pf_wfq(struct qed_hwfn *p_hwfn, bool pf_wfq_en)
252 {
253 STORE_RT_REG(p_hwfn, QM_REG_WFQPFENABLE_RT_OFFSET, pf_wfq_en ? 1 : 0);
254
255 /* Set credit threshold for QM bypass flow */
256 if (pf_wfq_en && QM_BYPASS_EN)
257 STORE_RT_REG(p_hwfn,
258 QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET,
259 QM_WFQ_UPPER_BOUND);
260 }
261
262 /* Prepare VPORT RL enable/disable runtime init values */
263 static void qed_enable_vport_rl(struct qed_hwfn *p_hwfn, bool vport_rl_en)
264 {
265 STORE_RT_REG(p_hwfn, QM_REG_RLGLBLENABLE_RT_OFFSET,
266 vport_rl_en ? 1 : 0);
267 if (vport_rl_en) {
268 /* Write RL period (use timer 0 only) */
269 STORE_RT_REG(p_hwfn,
270 QM_REG_RLGLBLPERIOD_0_RT_OFFSET,
271 QM_RL_PERIOD_CLK_25M);
272 STORE_RT_REG(p_hwfn,
273 QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET,
274 QM_RL_PERIOD_CLK_25M);
275
276 /* Set credit threshold for QM bypass flow */
277 if (QM_BYPASS_EN)
278 STORE_RT_REG(p_hwfn,
279 QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET,
280 QM_VP_RL_BYPASS_THRESH_SPEED);
281 }
282 }
283
284 /* Prepare VPORT WFQ enable/disable runtime init values */
285 static void qed_enable_vport_wfq(struct qed_hwfn *p_hwfn, bool vport_wfq_en)
286 {
287 STORE_RT_REG(p_hwfn, QM_REG_WFQVPENABLE_RT_OFFSET,
288 vport_wfq_en ? 1 : 0);
289
290 /* Set credit threshold for QM bypass flow */
291 if (vport_wfq_en && QM_BYPASS_EN)
292 STORE_RT_REG(p_hwfn,
293 QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET,
294 QM_WFQ_UPPER_BOUND);
295 }
296
297 /* Prepare runtime init values to allocate PBF command queue lines for
298 * the specified VOQ.
299 */
300 static void qed_cmdq_lines_voq_rt_init(struct qed_hwfn *p_hwfn,
301 u8 ext_voq, u16 cmdq_lines)
302 {
303 u32 qm_line_crd = QM_VOQ_LINE_CRD(cmdq_lines);
304
305 OVERWRITE_RT_REG(p_hwfn, PBF_CMDQ_LINES_RT_OFFSET(ext_voq),
306 (u32)cmdq_lines);
307 STORE_RT_REG(p_hwfn, QM_REG_VOQCRDLINE_RT_OFFSET + ext_voq,
308 qm_line_crd);
309 STORE_RT_REG(p_hwfn, QM_REG_VOQINITCRDLINE_RT_OFFSET + ext_voq,
310 qm_line_crd);
311 }
312
313 /* Prepare runtime init values to allocate PBF command queue lines. */
314 static void qed_cmdq_lines_rt_init(
315 struct qed_hwfn *p_hwfn,
316 u8 max_ports_per_engine,
317 u8 max_phys_tcs_per_port,
318 struct init_qm_port_params port_params[MAX_NUM_PORTS])
319 {
320 u8 tc, ext_voq, port_id, num_tcs_in_port;
321 u8 num_ext_voqs = MAX_NUM_VOQS_E4;
322
323 /* Clear PBF lines of all VOQs */
324 for (ext_voq = 0; ext_voq < num_ext_voqs; ext_voq++)
325 STORE_RT_REG(p_hwfn, PBF_CMDQ_LINES_RT_OFFSET(ext_voq), 0);
326
327 for (port_id = 0; port_id < max_ports_per_engine; port_id++) {
328 u16 phys_lines, phys_lines_per_tc;
329
330 if (!port_params[port_id].active)
331 continue;
332
333 /* Find number of command queue lines to divide between the
334 * active physical TCs. In E5, 1/8 of the lines are reserved.
335 * the lines for pure LB TC are subtracted.
336 */
337 phys_lines = port_params[port_id].num_pbf_cmd_lines;
338 phys_lines -= PBF_CMDQ_PURE_LB_LINES;
339
340 /* Find #lines per active physical TC */
341 num_tcs_in_port = 0;
342 for (tc = 0; tc < max_phys_tcs_per_port; tc++)
343 if (((port_params[port_id].active_phys_tcs >>
344 tc) & 0x1) == 1)
345 num_tcs_in_port++;
346 phys_lines_per_tc = phys_lines / num_tcs_in_port;
347
348 /* Init registers per active TC */
349 for (tc = 0; tc < max_phys_tcs_per_port; tc++) {
350 ext_voq = qed_get_ext_voq(p_hwfn,
351 port_id,
352 tc, max_phys_tcs_per_port);
353 if (((port_params[port_id].active_phys_tcs >>
354 tc) & 0x1) == 1)
355 qed_cmdq_lines_voq_rt_init(p_hwfn,
356 ext_voq,
357 phys_lines_per_tc);
358 }
359
360 /* Init registers for pure LB TC */
361 ext_voq = qed_get_ext_voq(p_hwfn,
362 port_id,
363 PURE_LB_TC, max_phys_tcs_per_port);
364 qed_cmdq_lines_voq_rt_init(p_hwfn,
365 ext_voq, PBF_CMDQ_PURE_LB_LINES);
366 }
367 }
368
369 static void qed_btb_blocks_rt_init(
370 struct qed_hwfn *p_hwfn,
371 u8 max_ports_per_engine,
372 u8 max_phys_tcs_per_port,
373 struct init_qm_port_params port_params[MAX_NUM_PORTS])
374 {
375 u32 usable_blocks, pure_lb_blocks, phys_blocks;
376 u8 tc, ext_voq, port_id, num_tcs_in_port;
377
378 for (port_id = 0; port_id < max_ports_per_engine; port_id++) {
379 if (!port_params[port_id].active)
380 continue;
381
382 /* Subtract headroom blocks */
383 usable_blocks = port_params[port_id].num_btb_blocks -
384 BTB_HEADROOM_BLOCKS;
385
386 /* Find blocks per physical TC. Use factor to avoid floating
387 * arithmethic.
388 */
389 num_tcs_in_port = 0;
390 for (tc = 0; tc < NUM_OF_PHYS_TCS; tc++)
391 if (((port_params[port_id].active_phys_tcs >>
392 tc) & 0x1) == 1)
393 num_tcs_in_port++;
394
395 pure_lb_blocks = (usable_blocks * BTB_PURE_LB_FACTOR) /
396 (num_tcs_in_port * BTB_PURE_LB_FACTOR +
397 BTB_PURE_LB_RATIO);
398 pure_lb_blocks = max_t(u32, BTB_JUMBO_PKT_BLOCKS,
399 pure_lb_blocks / BTB_PURE_LB_FACTOR);
400 phys_blocks = (usable_blocks - pure_lb_blocks) /
401 num_tcs_in_port;
402
403 /* Init physical TCs */
404 for (tc = 0; tc < NUM_OF_PHYS_TCS; tc++) {
405 if (((port_params[port_id].active_phys_tcs >>
406 tc) & 0x1) == 1) {
407 ext_voq =
408 qed_get_ext_voq(p_hwfn,
409 port_id,
410 tc,
411 max_phys_tcs_per_port);
412 STORE_RT_REG(p_hwfn,
413 PBF_BTB_GUARANTEED_RT_OFFSET
414 (ext_voq), phys_blocks);
415 }
416 }
417
418 /* Init pure LB TC */
419 ext_voq = qed_get_ext_voq(p_hwfn,
420 port_id,
421 PURE_LB_TC, max_phys_tcs_per_port);
422 STORE_RT_REG(p_hwfn, PBF_BTB_GUARANTEED_RT_OFFSET(ext_voq),
423 pure_lb_blocks);
424 }
425 }
426
427 /* Prepare Tx PQ mapping runtime init values for the specified PF */
428 static void qed_tx_pq_map_rt_init(struct qed_hwfn *p_hwfn,
429 struct qed_ptt *p_ptt,
430 struct qed_qm_pf_rt_init_params *p_params,
431 u32 base_mem_addr_4kb)
432 {
433 u32 tx_pq_vf_mask[MAX_QM_TX_QUEUES / QM_PF_QUEUE_GROUP_SIZE] = { 0 };
434 struct init_qm_vport_params *vport_params = p_params->vport_params;
435 u32 num_tx_pq_vf_masks = MAX_QM_TX_QUEUES / QM_PF_QUEUE_GROUP_SIZE;
436 u16 num_pqs, first_pq_group, last_pq_group, i, j, pq_id, pq_group;
437 struct init_qm_pq_params *pq_params = p_params->pq_params;
438 u32 pq_mem_4kb, vport_pq_mem_4kb, mem_addr_4kb;
439
440 num_pqs = p_params->num_pf_pqs + p_params->num_vf_pqs;
441
442 first_pq_group = p_params->start_pq / QM_PF_QUEUE_GROUP_SIZE;
443 last_pq_group = (p_params->start_pq + num_pqs - 1) /
444 QM_PF_QUEUE_GROUP_SIZE;
445
446 pq_mem_4kb = QM_PQ_MEM_4KB(p_params->num_pf_cids);
447 vport_pq_mem_4kb = QM_PQ_MEM_4KB(p_params->num_vf_cids);
448 mem_addr_4kb = base_mem_addr_4kb;
449
450 /* Set mapping from PQ group to PF */
451 for (pq_group = first_pq_group; pq_group <= last_pq_group; pq_group++)
452 STORE_RT_REG(p_hwfn, QM_REG_PQTX2PF_0_RT_OFFSET + pq_group,
453 (u32)(p_params->pf_id));
454
455 /* Set PQ sizes */
456 STORE_RT_REG(p_hwfn, QM_REG_MAXPQSIZE_0_RT_OFFSET,
457 QM_PQ_SIZE_256B(p_params->num_pf_cids));
458 STORE_RT_REG(p_hwfn, QM_REG_MAXPQSIZE_1_RT_OFFSET,
459 QM_PQ_SIZE_256B(p_params->num_vf_cids));
460
461 /* Go over all Tx PQs */
462 for (i = 0, pq_id = p_params->start_pq; i < num_pqs; i++, pq_id++) {
463 u8 ext_voq, vport_id_in_pf, tc_id = pq_params[i].tc_id;
464 u32 max_qm_global_rls = MAX_QM_GLOBAL_RLS;
465 struct qm_rf_pq_map_e4 tx_pq_map;
466 bool is_vf_pq, rl_valid;
467 u16 *p_first_tx_pq_id;
468
469 ext_voq = qed_get_ext_voq(p_hwfn,
470 p_params->port_id,
471 tc_id,
472 p_params->max_phys_tcs_per_port);
473 is_vf_pq = (i >= p_params->num_pf_pqs);
474 rl_valid = pq_params[i].rl_valid &&
475 pq_params[i].vport_id < max_qm_global_rls;
476
477 /* Update first Tx PQ of VPORT/TC */
478 vport_id_in_pf = pq_params[i].vport_id - p_params->start_vport;
479 p_first_tx_pq_id =
480 &vport_params[vport_id_in_pf].first_tx_pq_id[tc_id];
481 if (*p_first_tx_pq_id == QM_INVALID_PQ_ID) {
482 u32 map_val =
483 (ext_voq << QM_WFQ_VP_PQ_VOQ_SHIFT) |
484 (p_params->pf_id << QM_WFQ_VP_PQ_PF_E4_SHIFT);
485
486 /* Create new VP PQ */
487 *p_first_tx_pq_id = pq_id;
488
489 /* Map VP PQ to VOQ and PF */
490 STORE_RT_REG(p_hwfn,
491 QM_REG_WFQVPMAP_RT_OFFSET +
492 *p_first_tx_pq_id,
493 map_val);
494 }
495
496 /* Check RL ID */
497 if (pq_params[i].rl_valid && pq_params[i].vport_id >=
498 max_qm_global_rls)
499 DP_NOTICE(p_hwfn,
500 "Invalid VPORT ID for rate limiter configuration\n");
501
502 /* Prepare PQ map entry */
503 QM_INIT_TX_PQ_MAP(p_hwfn,
504 tx_pq_map,
505 E4,
506 pq_id,
507 rl_valid ? 1 : 0,
508 *p_first_tx_pq_id,
509 rl_valid ? pq_params[i].vport_id : 0,
510 ext_voq, pq_params[i].wrr_group);
511
512 /* Set PQ base address */
513 STORE_RT_REG(p_hwfn,
514 QM_REG_BASEADDRTXPQ_RT_OFFSET + pq_id,
515 mem_addr_4kb);
516
517 /* Clear PQ pointer table entry (64 bit) */
518 if (p_params->is_pf_loading)
519 for (j = 0; j < 2; j++)
520 STORE_RT_REG(p_hwfn,
521 QM_REG_PTRTBLTX_RT_OFFSET +
522 (pq_id * 2) + j, 0);
523
524 /* Write PQ info to RAM */
525 if (WRITE_PQ_INFO_TO_RAM != 0) {
526 u32 pq_info = 0;
527
528 pq_info = PQ_INFO_ELEMENT(*p_first_tx_pq_id,
529 p_params->pf_id,
530 tc_id,
531 p_params->port_id,
532 rl_valid ? 1 : 0,
533 rl_valid ?
534 pq_params[i].vport_id : 0);
535 qed_wr(p_hwfn, p_ptt, PQ_INFO_RAM_GRC_ADDRESS(pq_id),
536 pq_info);
537 }
538
539 /* If VF PQ, add indication to PQ VF mask */
540 if (is_vf_pq) {
541 tx_pq_vf_mask[pq_id /
542 QM_PF_QUEUE_GROUP_SIZE] |=
543 BIT((pq_id % QM_PF_QUEUE_GROUP_SIZE));
544 mem_addr_4kb += vport_pq_mem_4kb;
545 } else {
546 mem_addr_4kb += pq_mem_4kb;
547 }
548 }
549
550 /* Store Tx PQ VF mask to size select register */
551 for (i = 0; i < num_tx_pq_vf_masks; i++)
552 if (tx_pq_vf_mask[i])
553 STORE_RT_REG(p_hwfn,
554 QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET + i,
555 tx_pq_vf_mask[i]);
556 }
557
558 /* Prepare Other PQ mapping runtime init values for the specified PF */
559 static void qed_other_pq_map_rt_init(struct qed_hwfn *p_hwfn,
560 u8 pf_id,
561 bool is_pf_loading,
562 u32 num_pf_cids,
563 u32 num_tids, u32 base_mem_addr_4kb)
564 {
565 u32 pq_size, pq_mem_4kb, mem_addr_4kb;
566 u16 i, j, pq_id, pq_group;
567
568 /* A single other PQ group is used in each PF, where PQ group i is used
569 * in PF i.
570 */
571 pq_group = pf_id;
572 pq_size = num_pf_cids + num_tids;
573 pq_mem_4kb = QM_PQ_MEM_4KB(pq_size);
574 mem_addr_4kb = base_mem_addr_4kb;
575
576 /* Map PQ group to PF */
577 STORE_RT_REG(p_hwfn, QM_REG_PQOTHER2PF_0_RT_OFFSET + pq_group,
578 (u32)(pf_id));
579
580 /* Set PQ sizes */
581 STORE_RT_REG(p_hwfn, QM_REG_MAXPQSIZE_2_RT_OFFSET,
582 QM_PQ_SIZE_256B(pq_size));
583
584 for (i = 0, pq_id = pf_id * QM_PF_QUEUE_GROUP_SIZE;
585 i < QM_OTHER_PQS_PER_PF; i++, pq_id++) {
586 /* Set PQ base address */
587 STORE_RT_REG(p_hwfn,
588 QM_REG_BASEADDROTHERPQ_RT_OFFSET + pq_id,
589 mem_addr_4kb);
590
591 /* Clear PQ pointer table entry */
592 if (is_pf_loading)
593 for (j = 0; j < 2; j++)
594 STORE_RT_REG(p_hwfn,
595 QM_REG_PTRTBLOTHER_RT_OFFSET +
596 (pq_id * 2) + j, 0);
597
598 mem_addr_4kb += pq_mem_4kb;
599 }
600 }
601
602 /* Prepare PF WFQ runtime init values for the specified PF.
603 * Return -1 on error.
604 */
605 static int qed_pf_wfq_rt_init(struct qed_hwfn *p_hwfn,
606 struct qed_qm_pf_rt_init_params *p_params)
607 {
608 u16 num_tx_pqs = p_params->num_pf_pqs + p_params->num_vf_pqs;
609 struct init_qm_pq_params *pq_params = p_params->pq_params;
610 u32 inc_val, crd_reg_offset;
611 u8 ext_voq;
612 u16 i;
613
614 inc_val = QM_WFQ_INC_VAL(p_params->pf_wfq);
615 if (!inc_val || inc_val > QM_WFQ_MAX_INC_VAL) {
616 DP_NOTICE(p_hwfn, "Invalid PF WFQ weight configuration\n");
617 return -1;
618 }
619
620 for (i = 0; i < num_tx_pqs; i++) {
621 ext_voq = qed_get_ext_voq(p_hwfn,
622 p_params->port_id,
623 pq_params[i].tc_id,
624 p_params->max_phys_tcs_per_port);
625 crd_reg_offset =
626 (p_params->pf_id < MAX_NUM_PFS_BB ?
627 QM_REG_WFQPFCRD_RT_OFFSET :
628 QM_REG_WFQPFCRD_MSB_RT_OFFSET) +
629 ext_voq * MAX_NUM_PFS_BB +
630 (p_params->pf_id % MAX_NUM_PFS_BB);
631 OVERWRITE_RT_REG(p_hwfn,
632 crd_reg_offset, (u32)QM_WFQ_CRD_REG_SIGN_BIT);
633 }
634
635 STORE_RT_REG(p_hwfn,
636 QM_REG_WFQPFUPPERBOUND_RT_OFFSET + p_params->pf_id,
637 QM_WFQ_UPPER_BOUND | (u32)QM_WFQ_CRD_REG_SIGN_BIT);
638 STORE_RT_REG(p_hwfn, QM_REG_WFQPFWEIGHT_RT_OFFSET + p_params->pf_id,
639 inc_val);
640
641 return 0;
642 }
643
644 /* Prepare PF RL runtime init values for the specified PF.
645 * Return -1 on error.
646 */
647 static int qed_pf_rl_rt_init(struct qed_hwfn *p_hwfn, u8 pf_id, u32 pf_rl)
648 {
649 u32 inc_val = QM_RL_INC_VAL(pf_rl);
650
651 if (inc_val > QM_PF_RL_MAX_INC_VAL) {
652 DP_NOTICE(p_hwfn, "Invalid PF rate limit configuration\n");
653 return -1;
654 }
655
656 STORE_RT_REG(p_hwfn,
657 QM_REG_RLPFCRD_RT_OFFSET + pf_id,
658 (u32)QM_RL_CRD_REG_SIGN_BIT);
659 STORE_RT_REG(p_hwfn,
660 QM_REG_RLPFUPPERBOUND_RT_OFFSET + pf_id,
661 QM_PF_RL_UPPER_BOUND | (u32)QM_RL_CRD_REG_SIGN_BIT);
662 STORE_RT_REG(p_hwfn, QM_REG_RLPFINCVAL_RT_OFFSET + pf_id, inc_val);
663
664 return 0;
665 }
666
667 /* Prepare VPORT WFQ runtime init values for the specified VPORTs.
668 * Return -1 on error.
669 */
670 static int qed_vp_wfq_rt_init(struct qed_hwfn *p_hwfn,
671 u8 num_vports,
672 struct init_qm_vport_params *vport_params)
673 {
674 u16 vport_pq_id;
675 u32 inc_val;
676 u8 tc, i;
677
678 /* Go over all PF VPORTs */
679 for (i = 0; i < num_vports; i++) {
680 if (!vport_params[i].vport_wfq)
681 continue;
682
683 inc_val = QM_WFQ_INC_VAL(vport_params[i].vport_wfq);
684 if (inc_val > QM_WFQ_MAX_INC_VAL) {
685 DP_NOTICE(p_hwfn,
686 "Invalid VPORT WFQ weight configuration\n");
687 return -1;
688 }
689
690 /* Each VPORT can have several VPORT PQ IDs for various TCs */
691 for (tc = 0; tc < NUM_OF_TCS; tc++) {
692 vport_pq_id = vport_params[i].first_tx_pq_id[tc];
693 if (vport_pq_id != QM_INVALID_PQ_ID) {
694 STORE_RT_REG(p_hwfn,
695 QM_REG_WFQVPCRD_RT_OFFSET +
696 vport_pq_id,
697 (u32)QM_WFQ_CRD_REG_SIGN_BIT);
698 STORE_RT_REG(p_hwfn,
699 QM_REG_WFQVPWEIGHT_RT_OFFSET +
700 vport_pq_id, inc_val);
701 }
702 }
703 }
704
705 return 0;
706 }
707
708 /* Prepare VPORT RL runtime init values for the specified VPORTs.
709 * Return -1 on error.
710 */
711 static int qed_vport_rl_rt_init(struct qed_hwfn *p_hwfn,
712 u8 start_vport,
713 u8 num_vports,
714 u32 link_speed,
715 struct init_qm_vport_params *vport_params)
716 {
717 u8 i, vport_id;
718 u32 inc_val;
719
720 if (start_vport + num_vports >= MAX_QM_GLOBAL_RLS) {
721 DP_NOTICE(p_hwfn,
722 "Invalid VPORT ID for rate limiter configuration\n");
723 return -1;
724 }
725
726 /* Go over all PF VPORTs */
727 for (i = 0, vport_id = start_vport; i < num_vports; i++, vport_id++) {
728 inc_val = QM_RL_INC_VAL(vport_params[i].vport_rl ?
729 vport_params[i].vport_rl :
730 link_speed);
731 if (inc_val > QM_VP_RL_MAX_INC_VAL(link_speed)) {
732 DP_NOTICE(p_hwfn,
733 "Invalid VPORT rate-limit configuration\n");
734 return -1;
735 }
736
737 STORE_RT_REG(p_hwfn, QM_REG_RLGLBLCRD_RT_OFFSET + vport_id,
738 (u32)QM_RL_CRD_REG_SIGN_BIT);
739 STORE_RT_REG(p_hwfn,
740 QM_REG_RLGLBLUPPERBOUND_RT_OFFSET + vport_id,
741 QM_VP_RL_UPPER_BOUND(link_speed) |
742 (u32)QM_RL_CRD_REG_SIGN_BIT);
743 STORE_RT_REG(p_hwfn, QM_REG_RLGLBLINCVAL_RT_OFFSET + vport_id,
744 inc_val);
745 }
746
747 return 0;
748 }
749
750 static bool qed_poll_on_qm_cmd_ready(struct qed_hwfn *p_hwfn,
751 struct qed_ptt *p_ptt)
752 {
753 u32 reg_val, i;
754
755 for (i = 0, reg_val = 0; i < QM_STOP_CMD_MAX_POLL_COUNT && !reg_val;
756 i++) {
757 udelay(QM_STOP_CMD_POLL_PERIOD_US);
758 reg_val = qed_rd(p_hwfn, p_ptt, QM_REG_SDMCMDREADY);
759 }
760
761 /* Check if timeout while waiting for SDM command ready */
762 if (i == QM_STOP_CMD_MAX_POLL_COUNT) {
763 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
764 "Timeout when waiting for QM SDM command ready signal\n");
765 return false;
766 }
767
768 return true;
769 }
770
771 static bool qed_send_qm_cmd(struct qed_hwfn *p_hwfn,
772 struct qed_ptt *p_ptt,
773 u32 cmd_addr, u32 cmd_data_lsb, u32 cmd_data_msb)
774 {
775 if (!qed_poll_on_qm_cmd_ready(p_hwfn, p_ptt))
776 return false;
777
778 qed_wr(p_hwfn, p_ptt, QM_REG_SDMCMDADDR, cmd_addr);
779 qed_wr(p_hwfn, p_ptt, QM_REG_SDMCMDDATALSB, cmd_data_lsb);
780 qed_wr(p_hwfn, p_ptt, QM_REG_SDMCMDDATAMSB, cmd_data_msb);
781 qed_wr(p_hwfn, p_ptt, QM_REG_SDMCMDGO, 1);
782 qed_wr(p_hwfn, p_ptt, QM_REG_SDMCMDGO, 0);
783
784 return qed_poll_on_qm_cmd_ready(p_hwfn, p_ptt);
785 }
786
787 /******************** INTERFACE IMPLEMENTATION *********************/
788
789 u32 qed_qm_pf_mem_size(u32 num_pf_cids,
790 u32 num_vf_cids,
791 u32 num_tids, u16 num_pf_pqs, u16 num_vf_pqs)
792 {
793 return QM_PQ_MEM_4KB(num_pf_cids) * num_pf_pqs +
794 QM_PQ_MEM_4KB(num_vf_cids) * num_vf_pqs +
795 QM_PQ_MEM_4KB(num_pf_cids + num_tids) * QM_OTHER_PQS_PER_PF;
796 }
797
798 int qed_qm_common_rt_init(struct qed_hwfn *p_hwfn,
799 struct qed_qm_common_rt_init_params *p_params)
800 {
801 /* Init AFullOprtnstcCrdMask */
802 u32 mask = (QM_OPPOR_LINE_VOQ_DEF <<
803 QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_SHIFT) |
804 (QM_BYTE_CRD_EN << QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_SHIFT) |
805 (p_params->pf_wfq_en <<
806 QM_RF_OPPORTUNISTIC_MASK_PFWFQ_SHIFT) |
807 (p_params->vport_wfq_en <<
808 QM_RF_OPPORTUNISTIC_MASK_VPWFQ_SHIFT) |
809 (p_params->pf_rl_en <<
810 QM_RF_OPPORTUNISTIC_MASK_PFRL_SHIFT) |
811 (p_params->vport_rl_en <<
812 QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_SHIFT) |
813 (QM_OPPOR_FW_STOP_DEF <<
814 QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_SHIFT) |
815 (QM_OPPOR_PQ_EMPTY_DEF <<
816 QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_SHIFT);
817
818 STORE_RT_REG(p_hwfn, QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET, mask);
819
820 /* Enable/disable PF RL */
821 qed_enable_pf_rl(p_hwfn, p_params->pf_rl_en);
822
823 /* Enable/disable PF WFQ */
824 qed_enable_pf_wfq(p_hwfn, p_params->pf_wfq_en);
825
826 /* Enable/disable VPORT RL */
827 qed_enable_vport_rl(p_hwfn, p_params->vport_rl_en);
828
829 /* Enable/disable VPORT WFQ */
830 qed_enable_vport_wfq(p_hwfn, p_params->vport_wfq_en);
831
832 /* Init PBF CMDQ line credit */
833 qed_cmdq_lines_rt_init(p_hwfn,
834 p_params->max_ports_per_engine,
835 p_params->max_phys_tcs_per_port,
836 p_params->port_params);
837
838 /* Init BTB blocks in PBF */
839 qed_btb_blocks_rt_init(p_hwfn,
840 p_params->max_ports_per_engine,
841 p_params->max_phys_tcs_per_port,
842 p_params->port_params);
843
844 return 0;
845 }
846
847 int qed_qm_pf_rt_init(struct qed_hwfn *p_hwfn,
848 struct qed_ptt *p_ptt,
849 struct qed_qm_pf_rt_init_params *p_params)
850 {
851 struct init_qm_vport_params *vport_params = p_params->vport_params;
852 u32 other_mem_size_4kb = QM_PQ_MEM_4KB(p_params->num_pf_cids +
853 p_params->num_tids) *
854 QM_OTHER_PQS_PER_PF;
855 u8 tc, i;
856
857 /* Clear first Tx PQ ID array for each VPORT */
858 for (i = 0; i < p_params->num_vports; i++)
859 for (tc = 0; tc < NUM_OF_TCS; tc++)
860 vport_params[i].first_tx_pq_id[tc] = QM_INVALID_PQ_ID;
861
862 /* Map Other PQs (if any) */
863 qed_other_pq_map_rt_init(p_hwfn,
864 p_params->pf_id,
865 p_params->is_pf_loading, p_params->num_pf_cids,
866 p_params->num_tids, 0);
867
868 /* Map Tx PQs */
869 qed_tx_pq_map_rt_init(p_hwfn, p_ptt, p_params, other_mem_size_4kb);
870
871 /* Init PF WFQ */
872 if (p_params->pf_wfq)
873 if (qed_pf_wfq_rt_init(p_hwfn, p_params))
874 return -1;
875
876 /* Init PF RL */
877 if (qed_pf_rl_rt_init(p_hwfn, p_params->pf_id, p_params->pf_rl))
878 return -1;
879
880 /* Set VPORT WFQ */
881 if (qed_vp_wfq_rt_init(p_hwfn, p_params->num_vports, vport_params))
882 return -1;
883
884 /* Set VPORT RL */
885 if (qed_vport_rl_rt_init(p_hwfn, p_params->start_vport,
886 p_params->num_vports, p_params->link_speed,
887 vport_params))
888 return -1;
889
890 return 0;
891 }
892
893 int qed_init_pf_wfq(struct qed_hwfn *p_hwfn,
894 struct qed_ptt *p_ptt, u8 pf_id, u16 pf_wfq)
895 {
896 u32 inc_val = QM_WFQ_INC_VAL(pf_wfq);
897
898 if (!inc_val || inc_val > QM_WFQ_MAX_INC_VAL) {
899 DP_NOTICE(p_hwfn, "Invalid PF WFQ weight configuration\n");
900 return -1;
901 }
902
903 qed_wr(p_hwfn, p_ptt, QM_REG_WFQPFWEIGHT + pf_id * 4, inc_val);
904
905 return 0;
906 }
907
908 int qed_init_pf_rl(struct qed_hwfn *p_hwfn,
909 struct qed_ptt *p_ptt, u8 pf_id, u32 pf_rl)
910 {
911 u32 inc_val = QM_RL_INC_VAL(pf_rl);
912
913 if (inc_val > QM_PF_RL_MAX_INC_VAL) {
914 DP_NOTICE(p_hwfn, "Invalid PF rate limit configuration\n");
915 return -1;
916 }
917
918 qed_wr(p_hwfn,
919 p_ptt, QM_REG_RLPFCRD + pf_id * 4, (u32)QM_RL_CRD_REG_SIGN_BIT);
920 qed_wr(p_hwfn, p_ptt, QM_REG_RLPFINCVAL + pf_id * 4, inc_val);
921
922 return 0;
923 }
924
925 int qed_init_vport_wfq(struct qed_hwfn *p_hwfn,
926 struct qed_ptt *p_ptt,
927 u16 first_tx_pq_id[NUM_OF_TCS], u16 vport_wfq)
928 {
929 u16 vport_pq_id;
930 u32 inc_val;
931 u8 tc;
932
933 inc_val = QM_WFQ_INC_VAL(vport_wfq);
934 if (!inc_val || inc_val > QM_WFQ_MAX_INC_VAL) {
935 DP_NOTICE(p_hwfn, "Invalid VPORT WFQ weight configuration\n");
936 return -1;
937 }
938
939 for (tc = 0; tc < NUM_OF_TCS; tc++) {
940 vport_pq_id = first_tx_pq_id[tc];
941 if (vport_pq_id != QM_INVALID_PQ_ID)
942 qed_wr(p_hwfn,
943 p_ptt,
944 QM_REG_WFQVPWEIGHT + vport_pq_id * 4, inc_val);
945 }
946
947 return 0;
948 }
949
950 int qed_init_vport_rl(struct qed_hwfn *p_hwfn,
951 struct qed_ptt *p_ptt,
952 u8 vport_id, u32 vport_rl, u32 link_speed)
953 {
954 u32 inc_val, max_qm_global_rls = MAX_QM_GLOBAL_RLS;
955
956 if (vport_id >= max_qm_global_rls) {
957 DP_NOTICE(p_hwfn,
958 "Invalid VPORT ID for rate limiter configuration\n");
959 return -1;
960 }
961
962 inc_val = QM_RL_INC_VAL(vport_rl ? vport_rl : link_speed);
963 if (inc_val > QM_VP_RL_MAX_INC_VAL(link_speed)) {
964 DP_NOTICE(p_hwfn, "Invalid VPORT rate-limit configuration\n");
965 return -1;
966 }
967
968 qed_wr(p_hwfn,
969 p_ptt,
970 QM_REG_RLGLBLCRD + vport_id * 4, (u32)QM_RL_CRD_REG_SIGN_BIT);
971 qed_wr(p_hwfn, p_ptt, QM_REG_RLGLBLINCVAL + vport_id * 4, inc_val);
972
973 return 0;
974 }
975
976 bool qed_send_qm_stop_cmd(struct qed_hwfn *p_hwfn,
977 struct qed_ptt *p_ptt,
978 bool is_release_cmd,
979 bool is_tx_pq, u16 start_pq, u16 num_pqs)
980 {
981 u32 cmd_arr[QM_CMD_STRUCT_SIZE(QM_STOP_CMD)] = { 0 };
982 u32 pq_mask = 0, last_pq, pq_id;
983
984 last_pq = start_pq + num_pqs - 1;
985
986 /* Set command's PQ type */
987 QM_CMD_SET_FIELD(cmd_arr, QM_STOP_CMD, PQ_TYPE, is_tx_pq ? 0 : 1);
988
989 /* Go over requested PQs */
990 for (pq_id = start_pq; pq_id <= last_pq; pq_id++) {
991 /* Set PQ bit in mask (stop command only) */
992 if (!is_release_cmd)
993 pq_mask |= BIT((pq_id % QM_STOP_PQ_MASK_WIDTH));
994
995 /* If last PQ or end of PQ mask, write command */
996 if ((pq_id == last_pq) ||
997 (pq_id % QM_STOP_PQ_MASK_WIDTH ==
998 (QM_STOP_PQ_MASK_WIDTH - 1))) {
999 QM_CMD_SET_FIELD(cmd_arr,
1000 QM_STOP_CMD, PAUSE_MASK, pq_mask);
1001 QM_CMD_SET_FIELD(cmd_arr,
1002 QM_STOP_CMD,
1003 GROUP_ID,
1004 pq_id / QM_STOP_PQ_MASK_WIDTH);
1005 if (!qed_send_qm_cmd(p_hwfn, p_ptt, QM_STOP_CMD_ADDR,
1006 cmd_arr[0], cmd_arr[1]))
1007 return false;
1008 pq_mask = 0;
1009 }
1010 }
1011
1012 return true;
1013 }
1014
1015
1016 #define SET_TUNNEL_TYPE_ENABLE_BIT(var, offset, enable) \
1017 do { \
1018 typeof(var) *__p_var = &(var); \
1019 typeof(offset) __offset = offset; \
1020 *__p_var = (*__p_var & ~BIT(__offset)) | \
1021 ((enable) ? BIT(__offset) : 0); \
1022 } while (0)
1023 #define PRS_ETH_TUNN_FIC_FORMAT -188897008
1024
1025 void qed_set_vxlan_dest_port(struct qed_hwfn *p_hwfn,
1026 struct qed_ptt *p_ptt, u16 dest_port)
1027 {
1028 /* Update PRS register */
1029 qed_wr(p_hwfn, p_ptt, PRS_REG_VXLAN_PORT, dest_port);
1030
1031 /* Update NIG register */
1032 qed_wr(p_hwfn, p_ptt, NIG_REG_VXLAN_CTRL, dest_port);
1033
1034 /* Update PBF register */
1035 qed_wr(p_hwfn, p_ptt, PBF_REG_VXLAN_PORT, dest_port);
1036 }
1037
1038 void qed_set_vxlan_enable(struct qed_hwfn *p_hwfn,
1039 struct qed_ptt *p_ptt, bool vxlan_enable)
1040 {
1041 u32 reg_val;
1042 u8 shift;
1043
1044 /* Update PRS register */
1045 reg_val = qed_rd(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN);
1046 shift = PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_SHIFT;
1047 SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, shift, vxlan_enable);
1048 qed_wr(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN, reg_val);
1049 if (reg_val)
1050 qed_wr(p_hwfn,
1051 p_ptt,
1052 PRS_REG_OUTPUT_FORMAT_4_0_BB_K2,
1053 (u32)PRS_ETH_TUNN_FIC_FORMAT);
1054
1055 /* Update NIG register */
1056 reg_val = qed_rd(p_hwfn, p_ptt, NIG_REG_ENC_TYPE_ENABLE);
1057 shift = NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE_SHIFT;
1058 SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, shift, vxlan_enable);
1059 qed_wr(p_hwfn, p_ptt, NIG_REG_ENC_TYPE_ENABLE, reg_val);
1060
1061 /* Update DORQ register */
1062 qed_wr(p_hwfn,
1063 p_ptt, DORQ_REG_L2_EDPM_TUNNEL_VXLAN_EN, vxlan_enable ? 1 : 0);
1064 }
1065
1066 void qed_set_gre_enable(struct qed_hwfn *p_hwfn,
1067 struct qed_ptt *p_ptt,
1068 bool eth_gre_enable, bool ip_gre_enable)
1069 {
1070 u32 reg_val;
1071 u8 shift;
1072
1073 /* Update PRS register */
1074 reg_val = qed_rd(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN);
1075 shift = PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_SHIFT;
1076 SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, shift, eth_gre_enable);
1077 shift = PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_SHIFT;
1078 SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, shift, ip_gre_enable);
1079 qed_wr(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN, reg_val);
1080 if (reg_val)
1081 qed_wr(p_hwfn,
1082 p_ptt,
1083 PRS_REG_OUTPUT_FORMAT_4_0_BB_K2,
1084 (u32)PRS_ETH_TUNN_FIC_FORMAT);
1085
1086 /* Update NIG register */
1087 reg_val = qed_rd(p_hwfn, p_ptt, NIG_REG_ENC_TYPE_ENABLE);
1088 shift = NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE_SHIFT;
1089 SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, shift, eth_gre_enable);
1090 shift = NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE_SHIFT;
1091 SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, shift, ip_gre_enable);
1092 qed_wr(p_hwfn, p_ptt, NIG_REG_ENC_TYPE_ENABLE, reg_val);
1093
1094 /* Update DORQ registers */
1095 qed_wr(p_hwfn,
1096 p_ptt,
1097 DORQ_REG_L2_EDPM_TUNNEL_GRE_ETH_EN, eth_gre_enable ? 1 : 0);
1098 qed_wr(p_hwfn,
1099 p_ptt, DORQ_REG_L2_EDPM_TUNNEL_GRE_IP_EN, ip_gre_enable ? 1 : 0);
1100 }
1101
1102 void qed_set_geneve_dest_port(struct qed_hwfn *p_hwfn,
1103 struct qed_ptt *p_ptt, u16 dest_port)
1104 {
1105 /* Update PRS register */
1106 qed_wr(p_hwfn, p_ptt, PRS_REG_NGE_PORT, dest_port);
1107
1108 /* Update NIG register */
1109 qed_wr(p_hwfn, p_ptt, NIG_REG_NGE_PORT, dest_port);
1110
1111 /* Update PBF register */
1112 qed_wr(p_hwfn, p_ptt, PBF_REG_NGE_PORT, dest_port);
1113 }
1114
1115 void qed_set_geneve_enable(struct qed_hwfn *p_hwfn,
1116 struct qed_ptt *p_ptt,
1117 bool eth_geneve_enable, bool ip_geneve_enable)
1118 {
1119 u32 reg_val;
1120 u8 shift;
1121
1122 /* Update PRS register */
1123 reg_val = qed_rd(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN);
1124 shift = PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_SHIFT;
1125 SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, shift, eth_geneve_enable);
1126 shift = PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_SHIFT;
1127 SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, shift, ip_geneve_enable);
1128 qed_wr(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN, reg_val);
1129 if (reg_val)
1130 qed_wr(p_hwfn,
1131 p_ptt,
1132 PRS_REG_OUTPUT_FORMAT_4_0_BB_K2,
1133 (u32)PRS_ETH_TUNN_FIC_FORMAT);
1134
1135 /* Update NIG register */
1136 qed_wr(p_hwfn, p_ptt, NIG_REG_NGE_ETH_ENABLE,
1137 eth_geneve_enable ? 1 : 0);
1138 qed_wr(p_hwfn, p_ptt, NIG_REG_NGE_IP_ENABLE, ip_geneve_enable ? 1 : 0);
1139
1140 /* EDPM with geneve tunnel not supported in BB */
1141 if (QED_IS_BB_B0(p_hwfn->cdev))
1142 return;
1143
1144 /* Update DORQ registers */
1145 qed_wr(p_hwfn,
1146 p_ptt,
1147 DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN_K2_E5,
1148 eth_geneve_enable ? 1 : 0);
1149 qed_wr(p_hwfn,
1150 p_ptt,
1151 DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN_K2_E5,
1152 ip_geneve_enable ? 1 : 0);
1153 }
1154
1155 #define T_ETH_PACKET_ACTION_GFT_EVENTID 23
1156 #define PARSER_ETH_CONN_GFT_ACTION_CM_HDR 272
1157 #define T_ETH_PACKET_MATCH_RFS_EVENTID 25
1158 #define PARSER_ETH_CONN_CM_HDR 0
1159 #define CAM_LINE_SIZE sizeof(u32)
1160 #define RAM_LINE_SIZE sizeof(u64)
1161 #define REG_SIZE sizeof(u32)
1162
1163 void qed_gft_disable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u16 pf_id)
1164 {
1165 /* Disable gft search for PF */
1166 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_GFT, 0);
1167
1168 /* Clean ram & cam for next gft session */
1169
1170 /* Zero camline */
1171 qed_wr(p_hwfn, p_ptt, PRS_REG_GFT_CAM + CAM_LINE_SIZE * pf_id, 0);
1172
1173 /* Zero ramline */
1174 qed_wr(p_hwfn,
1175 p_ptt, PRS_REG_GFT_PROFILE_MASK_RAM + RAM_LINE_SIZE * pf_id, 0);
1176 qed_wr(p_hwfn,
1177 p_ptt,
1178 PRS_REG_GFT_PROFILE_MASK_RAM + RAM_LINE_SIZE * pf_id + REG_SIZE,
1179 0);
1180 }
1181
1182 void qed_set_gft_event_id_cm_hdr(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1183 {
1184 u32 rfs_cm_hdr_event_id;
1185
1186 /* Set RFS event ID to be awakened i Tstorm By Prs */
1187 rfs_cm_hdr_event_id = qed_rd(p_hwfn, p_ptt, PRS_REG_CM_HDR_GFT);
1188 rfs_cm_hdr_event_id |= T_ETH_PACKET_ACTION_GFT_EVENTID <<
1189 PRS_REG_CM_HDR_GFT_EVENT_ID_SHIFT;
1190 rfs_cm_hdr_event_id |= PARSER_ETH_CONN_GFT_ACTION_CM_HDR <<
1191 PRS_REG_CM_HDR_GFT_CM_HDR_SHIFT;
1192 qed_wr(p_hwfn, p_ptt, PRS_REG_CM_HDR_GFT, rfs_cm_hdr_event_id);
1193 }
1194
1195 void qed_gft_config(struct qed_hwfn *p_hwfn,
1196 struct qed_ptt *p_ptt,
1197 u16 pf_id,
1198 bool tcp,
1199 bool udp,
1200 bool ipv4, bool ipv6, enum gft_profile_type profile_type)
1201 {
1202 u32 reg_val, cam_line, ram_line_lo, ram_line_hi;
1203
1204 if (!ipv6 && !ipv4)
1205 DP_NOTICE(p_hwfn,
1206 "gft_config: must accept at least on of - ipv4 or ipv6'\n");
1207 if (!tcp && !udp)
1208 DP_NOTICE(p_hwfn,
1209 "gft_config: must accept at least on of - udp or tcp\n");
1210 if (profile_type >= MAX_GFT_PROFILE_TYPE)
1211 DP_NOTICE(p_hwfn, "gft_config: unsupported gft_profile_type\n");
1212
1213 /* Set RFS event ID to be awakened i Tstorm By Prs */
1214 reg_val = T_ETH_PACKET_MATCH_RFS_EVENTID <<
1215 PRS_REG_CM_HDR_GFT_EVENT_ID_SHIFT;
1216 reg_val |= PARSER_ETH_CONN_CM_HDR << PRS_REG_CM_HDR_GFT_CM_HDR_SHIFT;
1217 qed_wr(p_hwfn, p_ptt, PRS_REG_CM_HDR_GFT, reg_val);
1218
1219 /* Do not load context only cid in PRS on match. */
1220 qed_wr(p_hwfn, p_ptt, PRS_REG_LOAD_L2_FILTER, 0);
1221
1222 /* Do not use tenant ID exist bit for gft search */
1223 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TENANT_ID, 0);
1224
1225 /* Set Cam */
1226 cam_line = 0;
1227 SET_FIELD(cam_line, GFT_CAM_LINE_MAPPED_VALID, 1);
1228
1229 /* Filters are per PF!! */
1230 SET_FIELD(cam_line,
1231 GFT_CAM_LINE_MAPPED_PF_ID_MASK,
1232 GFT_CAM_LINE_MAPPED_PF_ID_MASK_MASK);
1233 SET_FIELD(cam_line, GFT_CAM_LINE_MAPPED_PF_ID, pf_id);
1234
1235 if (!(tcp && udp)) {
1236 SET_FIELD(cam_line,
1237 GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK,
1238 GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_MASK);
1239 if (tcp)
1240 SET_FIELD(cam_line,
1241 GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE,
1242 GFT_PROFILE_TCP_PROTOCOL);
1243 else
1244 SET_FIELD(cam_line,
1245 GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE,
1246 GFT_PROFILE_UDP_PROTOCOL);
1247 }
1248
1249 if (!(ipv4 && ipv6)) {
1250 SET_FIELD(cam_line, GFT_CAM_LINE_MAPPED_IP_VERSION_MASK, 1);
1251 if (ipv4)
1252 SET_FIELD(cam_line,
1253 GFT_CAM_LINE_MAPPED_IP_VERSION,
1254 GFT_PROFILE_IPV4);
1255 else
1256 SET_FIELD(cam_line,
1257 GFT_CAM_LINE_MAPPED_IP_VERSION,
1258 GFT_PROFILE_IPV6);
1259 }
1260
1261 /* Write characteristics to cam */
1262 qed_wr(p_hwfn, p_ptt, PRS_REG_GFT_CAM + CAM_LINE_SIZE * pf_id,
1263 cam_line);
1264 cam_line =
1265 qed_rd(p_hwfn, p_ptt, PRS_REG_GFT_CAM + CAM_LINE_SIZE * pf_id);
1266
1267 /* Write line to RAM - compare to filter 4 tuple */
1268 ram_line_lo = 0;
1269 ram_line_hi = 0;
1270
1271 if (profile_type == GFT_PROFILE_TYPE_4_TUPLE) {
1272 SET_FIELD(ram_line_hi, GFT_RAM_LINE_DST_IP, 1);
1273 SET_FIELD(ram_line_hi, GFT_RAM_LINE_SRC_IP, 1);
1274 SET_FIELD(ram_line_hi, GFT_RAM_LINE_OVER_IP_PROTOCOL, 1);
1275 SET_FIELD(ram_line_lo, GFT_RAM_LINE_ETHERTYPE, 1);
1276 SET_FIELD(ram_line_lo, GFT_RAM_LINE_SRC_PORT, 1);
1277 SET_FIELD(ram_line_lo, GFT_RAM_LINE_DST_PORT, 1);
1278 } else if (profile_type == GFT_PROFILE_TYPE_L4_DST_PORT) {
1279 SET_FIELD(ram_line_hi, GFT_RAM_LINE_OVER_IP_PROTOCOL, 1);
1280 SET_FIELD(ram_line_lo, GFT_RAM_LINE_ETHERTYPE, 1);
1281 SET_FIELD(ram_line_lo, GFT_RAM_LINE_DST_PORT, 1);
1282 } else if (profile_type == GFT_PROFILE_TYPE_IP_DST_PORT) {
1283 SET_FIELD(ram_line_hi, GFT_RAM_LINE_DST_IP, 1);
1284 SET_FIELD(ram_line_lo, GFT_RAM_LINE_ETHERTYPE, 1);
1285 }
1286
1287 qed_wr(p_hwfn,
1288 p_ptt,
1289 PRS_REG_GFT_PROFILE_MASK_RAM + RAM_LINE_SIZE * pf_id,
1290 ram_line_lo);
1291 qed_wr(p_hwfn,
1292 p_ptt,
1293 PRS_REG_GFT_PROFILE_MASK_RAM + RAM_LINE_SIZE * pf_id + REG_SIZE,
1294 ram_line_hi);
1295
1296 /* Set default profile so that no filter match will happen */
1297 qed_wr(p_hwfn,
1298 p_ptt,
1299 PRS_REG_GFT_PROFILE_MASK_RAM + RAM_LINE_SIZE *
1300 PRS_GFT_CAM_LINES_NO_MATCH, 0xffffffff);
1301 qed_wr(p_hwfn,
1302 p_ptt,
1303 PRS_REG_GFT_PROFILE_MASK_RAM + RAM_LINE_SIZE *
1304 PRS_GFT_CAM_LINES_NO_MATCH + REG_SIZE, 0x3ff);
1305
1306 /* Enable gft search */
1307 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_GFT, 1);
1308 }
1309
1310 DECLARE_CRC8_TABLE(cdu_crc8_table);
1311
1312 /* Calculate and return CDU validation byte per connection type/region/cid */
1313 static u8 qed_calc_cdu_validation_byte(u8 conn_type, u8 region, u32 cid)
1314 {
1315 const u8 validation_cfg = CDU_VALIDATION_DEFAULT_CFG;
1316 u8 crc, validation_byte = 0;
1317 static u8 crc8_table_valid; /* automatically initialized to 0 */
1318 u32 validation_string = 0;
1319 u32 data_to_crc;
1320
1321 if (!crc8_table_valid) {
1322 crc8_populate_msb(cdu_crc8_table, 0x07);
1323 crc8_table_valid = 1;
1324 }
1325
1326 /* The CRC is calculated on the String-to-compress:
1327 * [31:8] = {CID[31:20],CID[11:0]}
1328 * [7:4] = Region
1329 * [3:0] = Type
1330 */
1331 if ((validation_cfg >> CDU_CONTEXT_VALIDATION_CFG_USE_CID) & 1)
1332 validation_string |= (cid & 0xFFF00000) | ((cid & 0xFFF) << 8);
1333
1334 if ((validation_cfg >> CDU_CONTEXT_VALIDATION_CFG_USE_REGION) & 1)
1335 validation_string |= ((region & 0xF) << 4);
1336
1337 if ((validation_cfg >> CDU_CONTEXT_VALIDATION_CFG_USE_TYPE) & 1)
1338 validation_string |= (conn_type & 0xF);
1339
1340 /* Convert to big-endian and calculate CRC8 */
1341 data_to_crc = be32_to_cpu(validation_string);
1342
1343 crc = crc8(cdu_crc8_table,
1344 (u8 *)&data_to_crc, sizeof(data_to_crc), CRC8_INIT_VALUE);
1345
1346 /* The validation byte [7:0] is composed:
1347 * for type A validation
1348 * [7] = active configuration bit
1349 * [6:0] = crc[6:0]
1350 *
1351 * for type B validation
1352 * [7] = active configuration bit
1353 * [6:3] = connection_type[3:0]
1354 * [2:0] = crc[2:0]
1355 */
1356 validation_byte |=
1357 ((validation_cfg >>
1358 CDU_CONTEXT_VALIDATION_CFG_USE_ACTIVE) & 1) << 7;
1359
1360 if ((validation_cfg >>
1361 CDU_CONTEXT_VALIDATION_CFG_VALIDATION_TYPE_SHIFT) & 1)
1362 validation_byte |= ((conn_type & 0xF) << 3) | (crc & 0x7);
1363 else
1364 validation_byte |= crc & 0x7F;
1365
1366 return validation_byte;
1367 }
1368
1369 /* Calcualte and set validation bytes for session context */
1370 void qed_calc_session_ctx_validation(void *p_ctx_mem,
1371 u16 ctx_size, u8 ctx_type, u32 cid)
1372 {
1373 u8 *x_val_ptr, *t_val_ptr, *u_val_ptr, *p_ctx;
1374
1375 p_ctx = (u8 * const)p_ctx_mem;
1376 x_val_ptr = &p_ctx[con_region_offsets[0][ctx_type]];
1377 t_val_ptr = &p_ctx[con_region_offsets[1][ctx_type]];
1378 u_val_ptr = &p_ctx[con_region_offsets[2][ctx_type]];
1379
1380 memset(p_ctx, 0, ctx_size);
1381
1382 *x_val_ptr = qed_calc_cdu_validation_byte(ctx_type, 3, cid);
1383 *t_val_ptr = qed_calc_cdu_validation_byte(ctx_type, 4, cid);
1384 *u_val_ptr = qed_calc_cdu_validation_byte(ctx_type, 5, cid);
1385 }
1386
1387 /* Calcualte and set validation bytes for task context */
1388 void qed_calc_task_ctx_validation(void *p_ctx_mem,
1389 u16 ctx_size, u8 ctx_type, u32 tid)
1390 {
1391 u8 *p_ctx, *region1_val_ptr;
1392
1393 p_ctx = (u8 * const)p_ctx_mem;
1394 region1_val_ptr = &p_ctx[task_region_offsets[0][ctx_type]];
1395
1396 memset(p_ctx, 0, ctx_size);
1397
1398 *region1_val_ptr = qed_calc_cdu_validation_byte(ctx_type, 1, tid);
1399 }
1400
1401 /* Memset session context to 0 while preserving validation bytes */
1402 void qed_memset_session_ctx(void *p_ctx_mem, u32 ctx_size, u8 ctx_type)
1403 {
1404 u8 *x_val_ptr, *t_val_ptr, *u_val_ptr, *p_ctx;
1405 u8 x_val, t_val, u_val;
1406
1407 p_ctx = (u8 * const)p_ctx_mem;
1408 x_val_ptr = &p_ctx[con_region_offsets[0][ctx_type]];
1409 t_val_ptr = &p_ctx[con_region_offsets[1][ctx_type]];
1410 u_val_ptr = &p_ctx[con_region_offsets[2][ctx_type]];
1411
1412 x_val = *x_val_ptr;
1413 t_val = *t_val_ptr;
1414 u_val = *u_val_ptr;
1415
1416 memset(p_ctx, 0, ctx_size);
1417
1418 *x_val_ptr = x_val;
1419 *t_val_ptr = t_val;
1420 *u_val_ptr = u_val;
1421 }
1422
1423 /* Memset task context to 0 while preserving validation bytes */
1424 void qed_memset_task_ctx(void *p_ctx_mem, u32 ctx_size, u8 ctx_type)
1425 {
1426 u8 *p_ctx, *region1_val_ptr;
1427 u8 region1_val;
1428
1429 p_ctx = (u8 * const)p_ctx_mem;
1430 region1_val_ptr = &p_ctx[task_region_offsets[0][ctx_type]];
1431
1432 region1_val = *region1_val_ptr;
1433
1434 memset(p_ctx, 0, ctx_size);
1435
1436 *region1_val_ptr = region1_val;
1437 }
1438
1439 /* Enable and configure context validation */
1440 void qed_enable_context_validation(struct qed_hwfn *p_hwfn,
1441 struct qed_ptt *p_ptt)
1442 {
1443 u32 ctx_validation;
1444
1445 /* Enable validation for connection region 3: CCFC_CTX_VALID0[31:24] */
1446 ctx_validation = CDU_VALIDATION_DEFAULT_CFG << 24;
1447 qed_wr(p_hwfn, p_ptt, CDU_REG_CCFC_CTX_VALID0, ctx_validation);
1448
1449 /* Enable validation for connection region 5: CCFC_CTX_VALID1[15:8] */
1450 ctx_validation = CDU_VALIDATION_DEFAULT_CFG << 8;
1451 qed_wr(p_hwfn, p_ptt, CDU_REG_CCFC_CTX_VALID1, ctx_validation);
1452
1453 /* Enable validation for connection region 1: TCFC_CTX_VALID0[15:8] */
1454 ctx_validation = CDU_VALIDATION_DEFAULT_CFG << 8;
1455 qed_wr(p_hwfn, p_ptt, CDU_REG_TCFC_CTX_VALID0, ctx_validation);
1456 }
CRIS linux kernel tree