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x86/topology: Fix function name in documentation
[cris-mirror.git] / drivers / net / ethernet / realtek / r8169.c
blob0bf7d175925036644894aedf4835eece7c01877a
1 /*
2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
9 */
10
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
21 #include <linux/in.h>
22 #include <linux/ip.h>
23 #include <linux/tcp.h>
24 #include <linux/interrupt.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/firmware.h>
28 #include <linux/pci-aspm.h>
29 #include <linux/prefetch.h>
30 #include <linux/ipv6.h>
31 #include <net/ip6_checksum.h>
32
33 #include <asm/io.h>
34 #include <asm/irq.h>
35
36 #define RTL8169_VERSION "2.3LK-NAPI"
37 #define MODULENAME "r8169"
38 #define PFX MODULENAME ": "
39
40 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
41 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
42 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
43 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
44 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
45 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
46 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
47 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
48 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
49 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
50 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
51 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
52 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
53 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
54 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
55 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
56 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
57 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
58 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
59
60 #ifdef RTL8169_DEBUG
61 #define assert(expr) \
62 if (!(expr)) { \
63 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
64 #expr,__FILE__,__func__,__LINE__); \
65 }
66 #define dprintk(fmt, args...) \
67 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
68 #else
69 #define assert(expr) do {} while (0)
70 #define dprintk(fmt, args...) do {} while (0)
71 #endif /* RTL8169_DEBUG */
72
73 #define R8169_MSG_DEFAULT \
74 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
75
76 #define TX_SLOTS_AVAIL(tp) \
77 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
78
79 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
80 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
81 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
82
83 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
84 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
85 static const int multicast_filter_limit = 32;
86
87 #define MAX_READ_REQUEST_SHIFT 12
88 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
89 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
90
91 #define R8169_REGS_SIZE 256
92 #define R8169_NAPI_WEIGHT 64
93 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
94 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
95 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
96 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
97
98 #define RTL8169_TX_TIMEOUT (6*HZ)
99 #define RTL8169_PHY_TIMEOUT (10*HZ)
100
101 /* write/read MMIO register */
102 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
103 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
104 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
105 #define RTL_R8(reg) readb (ioaddr + (reg))
106 #define RTL_R16(reg) readw (ioaddr + (reg))
107 #define RTL_R32(reg) readl (ioaddr + (reg))
108
109 enum mac_version {
110 RTL_GIGA_MAC_VER_01 = 0,
111 RTL_GIGA_MAC_VER_02,
112 RTL_GIGA_MAC_VER_03,
113 RTL_GIGA_MAC_VER_04,
114 RTL_GIGA_MAC_VER_05,
115 RTL_GIGA_MAC_VER_06,
116 RTL_GIGA_MAC_VER_07,
117 RTL_GIGA_MAC_VER_08,
118 RTL_GIGA_MAC_VER_09,
119 RTL_GIGA_MAC_VER_10,
120 RTL_GIGA_MAC_VER_11,
121 RTL_GIGA_MAC_VER_12,
122 RTL_GIGA_MAC_VER_13,
123 RTL_GIGA_MAC_VER_14,
124 RTL_GIGA_MAC_VER_15,
125 RTL_GIGA_MAC_VER_16,
126 RTL_GIGA_MAC_VER_17,
127 RTL_GIGA_MAC_VER_18,
128 RTL_GIGA_MAC_VER_19,
129 RTL_GIGA_MAC_VER_20,
130 RTL_GIGA_MAC_VER_21,
131 RTL_GIGA_MAC_VER_22,
132 RTL_GIGA_MAC_VER_23,
133 RTL_GIGA_MAC_VER_24,
134 RTL_GIGA_MAC_VER_25,
135 RTL_GIGA_MAC_VER_26,
136 RTL_GIGA_MAC_VER_27,
137 RTL_GIGA_MAC_VER_28,
138 RTL_GIGA_MAC_VER_29,
139 RTL_GIGA_MAC_VER_30,
140 RTL_GIGA_MAC_VER_31,
141 RTL_GIGA_MAC_VER_32,
142 RTL_GIGA_MAC_VER_33,
143 RTL_GIGA_MAC_VER_34,
144 RTL_GIGA_MAC_VER_35,
145 RTL_GIGA_MAC_VER_36,
146 RTL_GIGA_MAC_VER_37,
147 RTL_GIGA_MAC_VER_38,
148 RTL_GIGA_MAC_VER_39,
149 RTL_GIGA_MAC_VER_40,
150 RTL_GIGA_MAC_VER_41,
151 RTL_GIGA_MAC_VER_42,
152 RTL_GIGA_MAC_VER_43,
153 RTL_GIGA_MAC_VER_44,
154 RTL_GIGA_MAC_VER_45,
155 RTL_GIGA_MAC_VER_46,
156 RTL_GIGA_MAC_VER_47,
157 RTL_GIGA_MAC_VER_48,
158 RTL_GIGA_MAC_VER_49,
159 RTL_GIGA_MAC_VER_50,
160 RTL_GIGA_MAC_VER_51,
161 RTL_GIGA_MAC_NONE = 0xff,
162 };
163
164 enum rtl_tx_desc_version {
165 RTL_TD_0 = 0,
166 RTL_TD_1 = 1,
167 };
168
169 #define JUMBO_1K ETH_DATA_LEN
170 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
171 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
172 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
173 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
174
175 #define _R(NAME,TD,FW,SZ,B) { \
176 .name = NAME, \
177 .txd_version = TD, \
178 .fw_name = FW, \
179 .jumbo_max = SZ, \
180 .jumbo_tx_csum = B \
181 }
182
183 static const struct {
184 const char *name;
185 enum rtl_tx_desc_version txd_version;
186 const char *fw_name;
187 u16 jumbo_max;
188 bool jumbo_tx_csum;
189 } rtl_chip_infos[] = {
190 /* PCI devices. */
191 [RTL_GIGA_MAC_VER_01] =
192 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
193 [RTL_GIGA_MAC_VER_02] =
194 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
195 [RTL_GIGA_MAC_VER_03] =
196 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
197 [RTL_GIGA_MAC_VER_04] =
198 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
199 [RTL_GIGA_MAC_VER_05] =
200 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
201 [RTL_GIGA_MAC_VER_06] =
202 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
203 /* PCI-E devices. */
204 [RTL_GIGA_MAC_VER_07] =
205 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
206 [RTL_GIGA_MAC_VER_08] =
207 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
208 [RTL_GIGA_MAC_VER_09] =
209 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
210 [RTL_GIGA_MAC_VER_10] =
211 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
212 [RTL_GIGA_MAC_VER_11] =
213 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
214 [RTL_GIGA_MAC_VER_12] =
215 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
216 [RTL_GIGA_MAC_VER_13] =
217 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
218 [RTL_GIGA_MAC_VER_14] =
219 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
220 [RTL_GIGA_MAC_VER_15] =
221 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
222 [RTL_GIGA_MAC_VER_16] =
223 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
224 [RTL_GIGA_MAC_VER_17] =
225 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
226 [RTL_GIGA_MAC_VER_18] =
227 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
228 [RTL_GIGA_MAC_VER_19] =
229 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
230 [RTL_GIGA_MAC_VER_20] =
231 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
232 [RTL_GIGA_MAC_VER_21] =
233 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
234 [RTL_GIGA_MAC_VER_22] =
235 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
236 [RTL_GIGA_MAC_VER_23] =
237 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
238 [RTL_GIGA_MAC_VER_24] =
239 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
240 [RTL_GIGA_MAC_VER_25] =
241 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
242 JUMBO_9K, false),
243 [RTL_GIGA_MAC_VER_26] =
244 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
245 JUMBO_9K, false),
246 [RTL_GIGA_MAC_VER_27] =
247 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
248 [RTL_GIGA_MAC_VER_28] =
249 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
250 [RTL_GIGA_MAC_VER_29] =
251 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
252 JUMBO_1K, true),
253 [RTL_GIGA_MAC_VER_30] =
254 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
255 JUMBO_1K, true),
256 [RTL_GIGA_MAC_VER_31] =
257 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
258 [RTL_GIGA_MAC_VER_32] =
259 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
260 JUMBO_9K, false),
261 [RTL_GIGA_MAC_VER_33] =
262 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
263 JUMBO_9K, false),
264 [RTL_GIGA_MAC_VER_34] =
265 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
266 JUMBO_9K, false),
267 [RTL_GIGA_MAC_VER_35] =
268 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
269 JUMBO_9K, false),
270 [RTL_GIGA_MAC_VER_36] =
271 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
272 JUMBO_9K, false),
273 [RTL_GIGA_MAC_VER_37] =
274 _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1,
275 JUMBO_1K, true),
276 [RTL_GIGA_MAC_VER_38] =
277 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_1,
278 JUMBO_9K, false),
279 [RTL_GIGA_MAC_VER_39] =
280 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_1,
281 JUMBO_1K, true),
282 [RTL_GIGA_MAC_VER_40] =
283 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_2,
284 JUMBO_9K, false),
285 [RTL_GIGA_MAC_VER_41] =
286 _R("RTL8168g/8111g", RTL_TD_1, NULL, JUMBO_9K, false),
287 [RTL_GIGA_MAC_VER_42] =
288 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_3,
289 JUMBO_9K, false),
290 [RTL_GIGA_MAC_VER_43] =
291 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_2,
292 JUMBO_1K, true),
293 [RTL_GIGA_MAC_VER_44] =
294 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_2,
295 JUMBO_9K, false),
296 [RTL_GIGA_MAC_VER_45] =
297 _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_1,
298 JUMBO_9K, false),
299 [RTL_GIGA_MAC_VER_46] =
300 _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_2,
301 JUMBO_9K, false),
302 [RTL_GIGA_MAC_VER_47] =
303 _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_1,
304 JUMBO_1K, false),
305 [RTL_GIGA_MAC_VER_48] =
306 _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_2,
307 JUMBO_1K, false),
308 [RTL_GIGA_MAC_VER_49] =
309 _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
310 JUMBO_9K, false),
311 [RTL_GIGA_MAC_VER_50] =
312 _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
313 JUMBO_9K, false),
314 [RTL_GIGA_MAC_VER_51] =
315 _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
316 JUMBO_9K, false),
317 };
318 #undef _R
319
320 enum cfg_version {
321 RTL_CFG_0 = 0x00,
322 RTL_CFG_1,
323 RTL_CFG_2
324 };
325
326 static const struct pci_device_id rtl8169_pci_tbl[] = {
327 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
328 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
329 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8161), 0, 0, RTL_CFG_1 },
330 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
331 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
332 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
333 { PCI_VENDOR_ID_DLINK, 0x4300,
334 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
335 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
336 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
337 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
338 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
339 { PCI_VENDOR_ID_LINKSYS, 0x1032,
340 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
341 { 0x0001, 0x8168,
342 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
343 {0,},
344 };
345
346 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
347
348 static int rx_buf_sz = 16383;
349 static int use_dac = -1;
350 static struct {
351 u32 msg_enable;
352 } debug = { -1 };
353
354 enum rtl_registers {
355 MAC0 = 0, /* Ethernet hardware address. */
356 MAC4 = 4,
357 MAR0 = 8, /* Multicast filter. */
358 CounterAddrLow = 0x10,
359 CounterAddrHigh = 0x14,
360 TxDescStartAddrLow = 0x20,
361 TxDescStartAddrHigh = 0x24,
362 TxHDescStartAddrLow = 0x28,
363 TxHDescStartAddrHigh = 0x2c,
364 FLASH = 0x30,
365 ERSR = 0x36,
366 ChipCmd = 0x37,
367 TxPoll = 0x38,
368 IntrMask = 0x3c,
369 IntrStatus = 0x3e,
370
371 TxConfig = 0x40,
372 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
373 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
374
375 RxConfig = 0x44,
376 #define RX128_INT_EN (1 << 15) /* 8111c and later */
377 #define RX_MULTI_EN (1 << 14) /* 8111c only */
378 #define RXCFG_FIFO_SHIFT 13
379 /* No threshold before first PCI xfer */
380 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
381 #define RX_EARLY_OFF (1 << 11)
382 #define RXCFG_DMA_SHIFT 8
383 /* Unlimited maximum PCI burst. */
384 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
385
386 RxMissed = 0x4c,
387 Cfg9346 = 0x50,
388 Config0 = 0x51,
389 Config1 = 0x52,
390 Config2 = 0x53,
391 #define PME_SIGNAL (1 << 5) /* 8168c and later */
392
393 Config3 = 0x54,
394 Config4 = 0x55,
395 Config5 = 0x56,
396 MultiIntr = 0x5c,
397 PHYAR = 0x60,
398 PHYstatus = 0x6c,
399 RxMaxSize = 0xda,
400 CPlusCmd = 0xe0,
401 IntrMitigate = 0xe2,
402
403 #define RTL_COALESCE_MASK 0x0f
404 #define RTL_COALESCE_SHIFT 4
405 #define RTL_COALESCE_T_MAX (RTL_COALESCE_MASK)
406 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_MASK << 2)
407
408 RxDescAddrLow = 0xe4,
409 RxDescAddrHigh = 0xe8,
410 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
411
412 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
413
414 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
415
416 #define TxPacketMax (8064 >> 7)
417 #define EarlySize 0x27
418
419 FuncEvent = 0xf0,
420 FuncEventMask = 0xf4,
421 FuncPresetState = 0xf8,
422 IBCR0 = 0xf8,
423 IBCR2 = 0xf9,
424 IBIMR0 = 0xfa,
425 IBISR0 = 0xfb,
426 FuncForceEvent = 0xfc,
427 };
428
429 enum rtl8110_registers {
430 TBICSR = 0x64,
431 TBI_ANAR = 0x68,
432 TBI_LPAR = 0x6a,
433 };
434
435 enum rtl8168_8101_registers {
436 CSIDR = 0x64,
437 CSIAR = 0x68,
438 #define CSIAR_FLAG 0x80000000
439 #define CSIAR_WRITE_CMD 0x80000000
440 #define CSIAR_BYTE_ENABLE 0x0f
441 #define CSIAR_BYTE_ENABLE_SHIFT 12
442 #define CSIAR_ADDR_MASK 0x0fff
443 #define CSIAR_FUNC_CARD 0x00000000
444 #define CSIAR_FUNC_SDIO 0x00010000
445 #define CSIAR_FUNC_NIC 0x00020000
446 #define CSIAR_FUNC_NIC2 0x00010000
447 PMCH = 0x6f,
448 EPHYAR = 0x80,
449 #define EPHYAR_FLAG 0x80000000
450 #define EPHYAR_WRITE_CMD 0x80000000
451 #define EPHYAR_REG_MASK 0x1f
452 #define EPHYAR_REG_SHIFT 16
453 #define EPHYAR_DATA_MASK 0xffff
454 DLLPR = 0xd0,
455 #define PFM_EN (1 << 6)
456 #define TX_10M_PS_EN (1 << 7)
457 DBG_REG = 0xd1,
458 #define FIX_NAK_1 (1 << 4)
459 #define FIX_NAK_2 (1 << 3)
460 TWSI = 0xd2,
461 MCU = 0xd3,
462 #define NOW_IS_OOB (1 << 7)
463 #define TX_EMPTY (1 << 5)
464 #define RX_EMPTY (1 << 4)
465 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
466 #define EN_NDP (1 << 3)
467 #define EN_OOB_RESET (1 << 2)
468 #define LINK_LIST_RDY (1 << 1)
469 EFUSEAR = 0xdc,
470 #define EFUSEAR_FLAG 0x80000000
471 #define EFUSEAR_WRITE_CMD 0x80000000
472 #define EFUSEAR_READ_CMD 0x00000000
473 #define EFUSEAR_REG_MASK 0x03ff
474 #define EFUSEAR_REG_SHIFT 8
475 #define EFUSEAR_DATA_MASK 0xff
476 MISC_1 = 0xf2,
477 #define PFM_D3COLD_EN (1 << 6)
478 };
479
480 enum rtl8168_registers {
481 LED_FREQ = 0x1a,
482 EEE_LED = 0x1b,
483 ERIDR = 0x70,
484 ERIAR = 0x74,
485 #define ERIAR_FLAG 0x80000000
486 #define ERIAR_WRITE_CMD 0x80000000
487 #define ERIAR_READ_CMD 0x00000000
488 #define ERIAR_ADDR_BYTE_ALIGN 4
489 #define ERIAR_TYPE_SHIFT 16
490 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
491 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
492 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
493 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
494 #define ERIAR_MASK_SHIFT 12
495 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
496 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
497 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
498 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
499 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
500 EPHY_RXER_NUM = 0x7c,
501 OCPDR = 0xb0, /* OCP GPHY access */
502 #define OCPDR_WRITE_CMD 0x80000000
503 #define OCPDR_READ_CMD 0x00000000
504 #define OCPDR_REG_MASK 0x7f
505 #define OCPDR_GPHY_REG_SHIFT 16
506 #define OCPDR_DATA_MASK 0xffff
507 OCPAR = 0xb4,
508 #define OCPAR_FLAG 0x80000000
509 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
510 #define OCPAR_GPHY_READ_CMD 0x0000f060
511 GPHY_OCP = 0xb8,
512 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
513 MISC = 0xf0, /* 8168e only. */
514 #define TXPLA_RST (1 << 29)
515 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
516 #define PWM_EN (1 << 22)
517 #define RXDV_GATED_EN (1 << 19)
518 #define EARLY_TALLY_EN (1 << 16)
519 };
520
521 enum rtl_register_content {
522 /* InterruptStatusBits */
523 SYSErr = 0x8000,
524 PCSTimeout = 0x4000,
525 SWInt = 0x0100,
526 TxDescUnavail = 0x0080,
527 RxFIFOOver = 0x0040,
528 LinkChg = 0x0020,
529 RxOverflow = 0x0010,
530 TxErr = 0x0008,
531 TxOK = 0x0004,
532 RxErr = 0x0002,
533 RxOK = 0x0001,
534
535 /* RxStatusDesc */
536 RxBOVF = (1 << 24),
537 RxFOVF = (1 << 23),
538 RxRWT = (1 << 22),
539 RxRES = (1 << 21),
540 RxRUNT = (1 << 20),
541 RxCRC = (1 << 19),
542
543 /* ChipCmdBits */
544 StopReq = 0x80,
545 CmdReset = 0x10,
546 CmdRxEnb = 0x08,
547 CmdTxEnb = 0x04,
548 RxBufEmpty = 0x01,
549
550 /* TXPoll register p.5 */
551 HPQ = 0x80, /* Poll cmd on the high prio queue */
552 NPQ = 0x40, /* Poll cmd on the low prio queue */
553 FSWInt = 0x01, /* Forced software interrupt */
554
555 /* Cfg9346Bits */
556 Cfg9346_Lock = 0x00,
557 Cfg9346_Unlock = 0xc0,
558
559 /* rx_mode_bits */
560 AcceptErr = 0x20,
561 AcceptRunt = 0x10,
562 AcceptBroadcast = 0x08,
563 AcceptMulticast = 0x04,
564 AcceptMyPhys = 0x02,
565 AcceptAllPhys = 0x01,
566 #define RX_CONFIG_ACCEPT_MASK 0x3f
567
568 /* TxConfigBits */
569 TxInterFrameGapShift = 24,
570 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
571
572 /* Config1 register p.24 */
573 LEDS1 = (1 << 7),
574 LEDS0 = (1 << 6),
575 Speed_down = (1 << 4),
576 MEMMAP = (1 << 3),
577 IOMAP = (1 << 2),
578 VPD = (1 << 1),
579 PMEnable = (1 << 0), /* Power Management Enable */
580
581 /* Config2 register p. 25 */
582 ClkReqEn = (1 << 7), /* Clock Request Enable */
583 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
584 PCI_Clock_66MHz = 0x01,
585 PCI_Clock_33MHz = 0x00,
586
587 /* Config3 register p.25 */
588 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
589 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
590 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
591 Rdy_to_L23 = (1 << 1), /* L23 Enable */
592 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
593
594 /* Config4 register */
595 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
596
597 /* Config5 register p.27 */
598 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
599 MWF = (1 << 5), /* Accept Multicast wakeup frame */
600 UWF = (1 << 4), /* Accept Unicast wakeup frame */
601 Spi_en = (1 << 3),
602 LanWake = (1 << 1), /* LanWake enable/disable */
603 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
604 ASPM_en = (1 << 0), /* ASPM enable */
605
606 /* TBICSR p.28 */
607 TBIReset = 0x80000000,
608 TBILoopback = 0x40000000,
609 TBINwEnable = 0x20000000,
610 TBINwRestart = 0x10000000,
611 TBILinkOk = 0x02000000,
612 TBINwComplete = 0x01000000,
613
614 /* CPlusCmd p.31 */
615 EnableBist = (1 << 15), // 8168 8101
616 Mac_dbgo_oe = (1 << 14), // 8168 8101
617 Normal_mode = (1 << 13), // unused
618 Force_half_dup = (1 << 12), // 8168 8101
619 Force_rxflow_en = (1 << 11), // 8168 8101
620 Force_txflow_en = (1 << 10), // 8168 8101
621 Cxpl_dbg_sel = (1 << 9), // 8168 8101
622 ASF = (1 << 8), // 8168 8101
623 PktCntrDisable = (1 << 7), // 8168 8101
624 Mac_dbgo_sel = 0x001c, // 8168
625 RxVlan = (1 << 6),
626 RxChkSum = (1 << 5),
627 PCIDAC = (1 << 4),
628 PCIMulRW = (1 << 3),
629 INTT_0 = 0x0000, // 8168
630 INTT_1 = 0x0001, // 8168
631 INTT_2 = 0x0002, // 8168
632 INTT_3 = 0x0003, // 8168
633
634 /* rtl8169_PHYstatus */
635 TBI_Enable = 0x80,
636 TxFlowCtrl = 0x40,
637 RxFlowCtrl = 0x20,
638 _1000bpsF = 0x10,
639 _100bps = 0x08,
640 _10bps = 0x04,
641 LinkStatus = 0x02,
642 FullDup = 0x01,
643
644 /* _TBICSRBit */
645 TBILinkOK = 0x02000000,
646
647 /* ResetCounterCommand */
648 CounterReset = 0x1,
649
650 /* DumpCounterCommand */
651 CounterDump = 0x8,
652
653 /* magic enable v2 */
654 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
655 };
656
657 enum rtl_desc_bit {
658 /* First doubleword. */
659 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
660 RingEnd = (1 << 30), /* End of descriptor ring */
661 FirstFrag = (1 << 29), /* First segment of a packet */
662 LastFrag = (1 << 28), /* Final segment of a packet */
663 };
664
665 /* Generic case. */
666 enum rtl_tx_desc_bit {
667 /* First doubleword. */
668 TD_LSO = (1 << 27), /* Large Send Offload */
669 #define TD_MSS_MAX 0x07ffu /* MSS value */
670
671 /* Second doubleword. */
672 TxVlanTag = (1 << 17), /* Add VLAN tag */
673 };
674
675 /* 8169, 8168b and 810x except 8102e. */
676 enum rtl_tx_desc_bit_0 {
677 /* First doubleword. */
678 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
679 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
680 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
681 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
682 };
683
684 /* 8102e, 8168c and beyond. */
685 enum rtl_tx_desc_bit_1 {
686 /* First doubleword. */
687 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
688 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
689 #define GTTCPHO_SHIFT 18
690 #define GTTCPHO_MAX 0x7fU
691
692 /* Second doubleword. */
693 #define TCPHO_SHIFT 18
694 #define TCPHO_MAX 0x3ffU
695 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
696 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
697 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
698 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
699 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
700 };
701
702 enum rtl_rx_desc_bit {
703 /* Rx private */
704 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
705 PID0 = (1 << 17), /* Protocol ID bit 0/2 */
706
707 #define RxProtoUDP (PID1)
708 #define RxProtoTCP (PID0)
709 #define RxProtoIP (PID1 | PID0)
710 #define RxProtoMask RxProtoIP
711
712 IPFail = (1 << 16), /* IP checksum failed */
713 UDPFail = (1 << 15), /* UDP/IP checksum failed */
714 TCPFail = (1 << 14), /* TCP/IP checksum failed */
715 RxVlanTag = (1 << 16), /* VLAN tag available */
716 };
717
718 #define RsvdMask 0x3fffc000
719
720 struct TxDesc {
721 __le32 opts1;
722 __le32 opts2;
723 __le64 addr;
724 };
725
726 struct RxDesc {
727 __le32 opts1;
728 __le32 opts2;
729 __le64 addr;
730 };
731
732 struct ring_info {
733 struct sk_buff *skb;
734 u32 len;
735 u8 __pad[sizeof(void *) - sizeof(u32)];
736 };
737
738 enum features {
739 RTL_FEATURE_WOL = (1 << 0),
740 RTL_FEATURE_MSI = (1 << 1),
741 RTL_FEATURE_GMII = (1 << 2),
742 };
743
744 struct rtl8169_counters {
745 __le64 tx_packets;
746 __le64 rx_packets;
747 __le64 tx_errors;
748 __le32 rx_errors;
749 __le16 rx_missed;
750 __le16 align_errors;
751 __le32 tx_one_collision;
752 __le32 tx_multi_collision;
753 __le64 rx_unicast;
754 __le64 rx_broadcast;
755 __le32 rx_multicast;
756 __le16 tx_aborted;
757 __le16 tx_underun;
758 };
759
760 struct rtl8169_tc_offsets {
761 bool inited;
762 __le64 tx_errors;
763 __le32 tx_multi_collision;
764 __le16 tx_aborted;
765 };
766
767 enum rtl_flag {
768 RTL_FLAG_TASK_ENABLED,
769 RTL_FLAG_TASK_SLOW_PENDING,
770 RTL_FLAG_TASK_RESET_PENDING,
771 RTL_FLAG_TASK_PHY_PENDING,
772 RTL_FLAG_MAX
773 };
774
775 struct rtl8169_stats {
776 u64 packets;
777 u64 bytes;
778 struct u64_stats_sync syncp;
779 };
780
781 struct rtl8169_private {
782 void __iomem *mmio_addr; /* memory map physical address */
783 struct pci_dev *pci_dev;
784 struct net_device *dev;
785 struct napi_struct napi;
786 u32 msg_enable;
787 u16 txd_version;
788 u16 mac_version;
789 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
790 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
791 u32 dirty_tx;
792 struct rtl8169_stats rx_stats;
793 struct rtl8169_stats tx_stats;
794 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
795 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
796 dma_addr_t TxPhyAddr;
797 dma_addr_t RxPhyAddr;
798 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
799 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
800 struct timer_list timer;
801 u16 cp_cmd;
802
803 u16 event_slow;
804 const struct rtl_coalesce_info *coalesce_info;
805
806 struct mdio_ops {
807 void (*write)(struct rtl8169_private *, int, int);
808 int (*read)(struct rtl8169_private *, int);
809 } mdio_ops;
810
811 struct pll_power_ops {
812 void (*down)(struct rtl8169_private *);
813 void (*up)(struct rtl8169_private *);
814 } pll_power_ops;
815
816 struct jumbo_ops {
817 void (*enable)(struct rtl8169_private *);
818 void (*disable)(struct rtl8169_private *);
819 } jumbo_ops;
820
821 struct csi_ops {
822 void (*write)(struct rtl8169_private *, int, int);
823 u32 (*read)(struct rtl8169_private *, int);
824 } csi_ops;
825
826 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
827 int (*get_link_ksettings)(struct net_device *,
828 struct ethtool_link_ksettings *);
829 void (*phy_reset_enable)(struct rtl8169_private *tp);
830 void (*hw_start)(struct net_device *);
831 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
832 unsigned int (*link_ok)(void __iomem *);
833 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
834 bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
835
836 struct {
837 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
838 struct mutex mutex;
839 struct work_struct work;
840 } wk;
841
842 unsigned features;
843
844 struct mii_if_info mii;
845 dma_addr_t counters_phys_addr;
846 struct rtl8169_counters *counters;
847 struct rtl8169_tc_offsets tc_offset;
848 u32 saved_wolopts;
849 u32 opts1_mask;
850
851 struct rtl_fw {
852 const struct firmware *fw;
853
854 #define RTL_VER_SIZE 32
855
856 char version[RTL_VER_SIZE];
857
858 struct rtl_fw_phy_action {
859 __le32 *code;
860 size_t size;
861 } phy_action;
862 } *rtl_fw;
863 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
864
865 u32 ocp_base;
866 };
867
868 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
869 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
870 module_param(use_dac, int, 0);
871 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
872 module_param_named(debug, debug.msg_enable, int, 0);
873 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
874 MODULE_LICENSE("GPL");
875 MODULE_VERSION(RTL8169_VERSION);
876 MODULE_FIRMWARE(FIRMWARE_8168D_1);
877 MODULE_FIRMWARE(FIRMWARE_8168D_2);
878 MODULE_FIRMWARE(FIRMWARE_8168E_1);
879 MODULE_FIRMWARE(FIRMWARE_8168E_2);
880 MODULE_FIRMWARE(FIRMWARE_8168E_3);
881 MODULE_FIRMWARE(FIRMWARE_8105E_1);
882 MODULE_FIRMWARE(FIRMWARE_8168F_1);
883 MODULE_FIRMWARE(FIRMWARE_8168F_2);
884 MODULE_FIRMWARE(FIRMWARE_8402_1);
885 MODULE_FIRMWARE(FIRMWARE_8411_1);
886 MODULE_FIRMWARE(FIRMWARE_8411_2);
887 MODULE_FIRMWARE(FIRMWARE_8106E_1);
888 MODULE_FIRMWARE(FIRMWARE_8106E_2);
889 MODULE_FIRMWARE(FIRMWARE_8168G_2);
890 MODULE_FIRMWARE(FIRMWARE_8168G_3);
891 MODULE_FIRMWARE(FIRMWARE_8168H_1);
892 MODULE_FIRMWARE(FIRMWARE_8168H_2);
893 MODULE_FIRMWARE(FIRMWARE_8107E_1);
894 MODULE_FIRMWARE(FIRMWARE_8107E_2);
895
896 static void rtl_lock_work(struct rtl8169_private *tp)
897 {
898 mutex_lock(&tp->wk.mutex);
899 }
900
901 static void rtl_unlock_work(struct rtl8169_private *tp)
902 {
903 mutex_unlock(&tp->wk.mutex);
904 }
905
906 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
907 {
908 pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
909 PCI_EXP_DEVCTL_READRQ, force);
910 }
911
912 struct rtl_cond {
913 bool (*check)(struct rtl8169_private *);
914 const char *msg;
915 };
916
917 static void rtl_udelay(unsigned int d)
918 {
919 udelay(d);
920 }
921
922 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
923 void (*delay)(unsigned int), unsigned int d, int n,
924 bool high)
925 {
926 int i;
927
928 for (i = 0; i < n; i++) {
929 delay(d);
930 if (c->check(tp) == high)
931 return true;
932 }
933 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
934 c->msg, !high, n, d);
935 return false;
936 }
937
938 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
939 const struct rtl_cond *c,
940 unsigned int d, int n)
941 {
942 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
943 }
944
945 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
946 const struct rtl_cond *c,
947 unsigned int d, int n)
948 {
949 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
950 }
951
952 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
953 const struct rtl_cond *c,
954 unsigned int d, int n)
955 {
956 return rtl_loop_wait(tp, c, msleep, d, n, true);
957 }
958
959 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
960 const struct rtl_cond *c,
961 unsigned int d, int n)
962 {
963 return rtl_loop_wait(tp, c, msleep, d, n, false);
964 }
965
966 #define DECLARE_RTL_COND(name) \
967 static bool name ## _check(struct rtl8169_private *); \
968 \
969 static const struct rtl_cond name = { \
970 .check = name ## _check, \
971 .msg = #name \
972 }; \
973 \
974 static bool name ## _check(struct rtl8169_private *tp)
975
976 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
977 {
978 if (reg & 0xffff0001) {
979 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
980 return true;
981 }
982 return false;
983 }
984
985 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
986 {
987 void __iomem *ioaddr = tp->mmio_addr;
988
989 return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
990 }
991
992 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
993 {
994 void __iomem *ioaddr = tp->mmio_addr;
995
996 if (rtl_ocp_reg_failure(tp, reg))
997 return;
998
999 RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
1000
1001 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
1002 }
1003
1004 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
1005 {
1006 void __iomem *ioaddr = tp->mmio_addr;
1007
1008 if (rtl_ocp_reg_failure(tp, reg))
1009 return 0;
1010
1011 RTL_W32(GPHY_OCP, reg << 15);
1012
1013 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1014 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
1015 }
1016
1017 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1018 {
1019 void __iomem *ioaddr = tp->mmio_addr;
1020
1021 if (rtl_ocp_reg_failure(tp, reg))
1022 return;
1023
1024 RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
1025 }
1026
1027 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1028 {
1029 void __iomem *ioaddr = tp->mmio_addr;
1030
1031 if (rtl_ocp_reg_failure(tp, reg))
1032 return 0;
1033
1034 RTL_W32(OCPDR, reg << 15);
1035
1036 return RTL_R32(OCPDR);
1037 }
1038
1039 #define OCP_STD_PHY_BASE 0xa400
1040
1041 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1042 {
1043 if (reg == 0x1f) {
1044 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1045 return;
1046 }
1047
1048 if (tp->ocp_base != OCP_STD_PHY_BASE)
1049 reg -= 0x10;
1050
1051 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1052 }
1053
1054 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1055 {
1056 if (tp->ocp_base != OCP_STD_PHY_BASE)
1057 reg -= 0x10;
1058
1059 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1060 }
1061
1062 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1063 {
1064 if (reg == 0x1f) {
1065 tp->ocp_base = value << 4;
1066 return;
1067 }
1068
1069 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1070 }
1071
1072 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1073 {
1074 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1075 }
1076
1077 DECLARE_RTL_COND(rtl_phyar_cond)
1078 {
1079 void __iomem *ioaddr = tp->mmio_addr;
1080
1081 return RTL_R32(PHYAR) & 0x80000000;
1082 }
1083
1084 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1085 {
1086 void __iomem *ioaddr = tp->mmio_addr;
1087
1088 RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1089
1090 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
1091 /*
1092 * According to hardware specs a 20us delay is required after write
1093 * complete indication, but before sending next command.
1094 */
1095 udelay(20);
1096 }
1097
1098 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1099 {
1100 void __iomem *ioaddr = tp->mmio_addr;
1101 int value;
1102
1103 RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1104
1105 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1106 RTL_R32(PHYAR) & 0xffff : ~0;
1107
1108 /*
1109 * According to hardware specs a 20us delay is required after read
1110 * complete indication, but before sending next command.
1111 */
1112 udelay(20);
1113
1114 return value;
1115 }
1116
1117 DECLARE_RTL_COND(rtl_ocpar_cond)
1118 {
1119 void __iomem *ioaddr = tp->mmio_addr;
1120
1121 return RTL_R32(OCPAR) & OCPAR_FLAG;
1122 }
1123
1124 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
1125 {
1126 void __iomem *ioaddr = tp->mmio_addr;
1127
1128 RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
1129 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1130 RTL_W32(EPHY_RXER_NUM, 0);
1131
1132 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
1133 }
1134
1135 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
1136 {
1137 r8168dp_1_mdio_access(tp, reg,
1138 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
1139 }
1140
1141 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
1142 {
1143 void __iomem *ioaddr = tp->mmio_addr;
1144
1145 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1146
1147 mdelay(1);
1148 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1149 RTL_W32(EPHY_RXER_NUM, 0);
1150
1151 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1152 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
1153 }
1154
1155 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1156
1157 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1158 {
1159 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1160 }
1161
1162 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1163 {
1164 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1165 }
1166
1167 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1168 {
1169 void __iomem *ioaddr = tp->mmio_addr;
1170
1171 r8168dp_2_mdio_start(ioaddr);
1172
1173 r8169_mdio_write(tp, reg, value);
1174
1175 r8168dp_2_mdio_stop(ioaddr);
1176 }
1177
1178 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1179 {
1180 void __iomem *ioaddr = tp->mmio_addr;
1181 int value;
1182
1183 r8168dp_2_mdio_start(ioaddr);
1184
1185 value = r8169_mdio_read(tp, reg);
1186
1187 r8168dp_2_mdio_stop(ioaddr);
1188
1189 return value;
1190 }
1191
1192 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1193 {
1194 tp->mdio_ops.write(tp, location, val);
1195 }
1196
1197 static int rtl_readphy(struct rtl8169_private *tp, int location)
1198 {
1199 return tp->mdio_ops.read(tp, location);
1200 }
1201
1202 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1203 {
1204 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1205 }
1206
1207 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1208 {
1209 int val;
1210
1211 val = rtl_readphy(tp, reg_addr);
1212 rtl_writephy(tp, reg_addr, (val & ~m) | p);
1213 }
1214
1215 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1216 int val)
1217 {
1218 struct rtl8169_private *tp = netdev_priv(dev);
1219
1220 rtl_writephy(tp, location, val);
1221 }
1222
1223 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1224 {
1225 struct rtl8169_private *tp = netdev_priv(dev);
1226
1227 return rtl_readphy(tp, location);
1228 }
1229
1230 DECLARE_RTL_COND(rtl_ephyar_cond)
1231 {
1232 void __iomem *ioaddr = tp->mmio_addr;
1233
1234 return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1235 }
1236
1237 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1238 {
1239 void __iomem *ioaddr = tp->mmio_addr;
1240
1241 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1242 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1243
1244 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1245
1246 udelay(10);
1247 }
1248
1249 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1250 {
1251 void __iomem *ioaddr = tp->mmio_addr;
1252
1253 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1254
1255 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1256 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
1257 }
1258
1259 DECLARE_RTL_COND(rtl_eriar_cond)
1260 {
1261 void __iomem *ioaddr = tp->mmio_addr;
1262
1263 return RTL_R32(ERIAR) & ERIAR_FLAG;
1264 }
1265
1266 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1267 u32 val, int type)
1268 {
1269 void __iomem *ioaddr = tp->mmio_addr;
1270
1271 BUG_ON((addr & 3) || (mask == 0));
1272 RTL_W32(ERIDR, val);
1273 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1274
1275 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1276 }
1277
1278 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1279 {
1280 void __iomem *ioaddr = tp->mmio_addr;
1281
1282 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1283
1284 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1285 RTL_R32(ERIDR) : ~0;
1286 }
1287
1288 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1289 u32 m, int type)
1290 {
1291 u32 val;
1292
1293 val = rtl_eri_read(tp, addr, type);
1294 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1295 }
1296
1297 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1298 {
1299 void __iomem *ioaddr = tp->mmio_addr;
1300
1301 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1302 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1303 RTL_R32(OCPDR) : ~0;
1304 }
1305
1306 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1307 {
1308 return rtl_eri_read(tp, reg, ERIAR_OOB);
1309 }
1310
1311 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1312 {
1313 switch (tp->mac_version) {
1314 case RTL_GIGA_MAC_VER_27:
1315 case RTL_GIGA_MAC_VER_28:
1316 case RTL_GIGA_MAC_VER_31:
1317 return r8168dp_ocp_read(tp, mask, reg);
1318 case RTL_GIGA_MAC_VER_49:
1319 case RTL_GIGA_MAC_VER_50:
1320 case RTL_GIGA_MAC_VER_51:
1321 return r8168ep_ocp_read(tp, mask, reg);
1322 default:
1323 BUG();
1324 return ~0;
1325 }
1326 }
1327
1328 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1329 u32 data)
1330 {
1331 void __iomem *ioaddr = tp->mmio_addr;
1332
1333 RTL_W32(OCPDR, data);
1334 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1335 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1336 }
1337
1338 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1339 u32 data)
1340 {
1341 rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1342 data, ERIAR_OOB);
1343 }
1344
1345 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
1346 {
1347 switch (tp->mac_version) {
1348 case RTL_GIGA_MAC_VER_27:
1349 case RTL_GIGA_MAC_VER_28:
1350 case RTL_GIGA_MAC_VER_31:
1351 r8168dp_ocp_write(tp, mask, reg, data);
1352 break;
1353 case RTL_GIGA_MAC_VER_49:
1354 case RTL_GIGA_MAC_VER_50:
1355 case RTL_GIGA_MAC_VER_51:
1356 r8168ep_ocp_write(tp, mask, reg, data);
1357 break;
1358 default:
1359 BUG();
1360 break;
1361 }
1362 }
1363
1364 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
1365 {
1366 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1367
1368 ocp_write(tp, 0x1, 0x30, 0x00000001);
1369 }
1370
1371 #define OOB_CMD_RESET 0x00
1372 #define OOB_CMD_DRIVER_START 0x05
1373 #define OOB_CMD_DRIVER_STOP 0x06
1374
1375 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1376 {
1377 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1378 }
1379
1380 DECLARE_RTL_COND(rtl_ocp_read_cond)
1381 {
1382 u16 reg;
1383
1384 reg = rtl8168_get_ocp_reg(tp);
1385
1386 return ocp_read(tp, 0x0f, reg) & 0x00000800;
1387 }
1388
1389 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1390 {
1391 return ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1392 }
1393
1394 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1395 {
1396 void __iomem *ioaddr = tp->mmio_addr;
1397
1398 return RTL_R8(IBISR0) & 0x20;
1399 }
1400
1401 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1402 {
1403 void __iomem *ioaddr = tp->mmio_addr;
1404
1405 RTL_W8(IBCR2, RTL_R8(IBCR2) & ~0x01);
1406 rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1407 RTL_W8(IBISR0, RTL_R8(IBISR0) | 0x20);
1408 RTL_W8(IBCR0, RTL_R8(IBCR0) & ~0x01);
1409 }
1410
1411 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1412 {
1413 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
1414 rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1415 }
1416
1417 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1418 {
1419 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1420 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1421 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1422 }
1423
1424 static void rtl8168_driver_start(struct rtl8169_private *tp)
1425 {
1426 switch (tp->mac_version) {
1427 case RTL_GIGA_MAC_VER_27:
1428 case RTL_GIGA_MAC_VER_28:
1429 case RTL_GIGA_MAC_VER_31:
1430 rtl8168dp_driver_start(tp);
1431 break;
1432 case RTL_GIGA_MAC_VER_49:
1433 case RTL_GIGA_MAC_VER_50:
1434 case RTL_GIGA_MAC_VER_51:
1435 rtl8168ep_driver_start(tp);
1436 break;
1437 default:
1438 BUG();
1439 break;
1440 }
1441 }
1442
1443 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1444 {
1445 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1446 rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1447 }
1448
1449 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1450 {
1451 rtl8168ep_stop_cmac(tp);
1452 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1453 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1454 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1455 }
1456
1457 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1458 {
1459 switch (tp->mac_version) {
1460 case RTL_GIGA_MAC_VER_27:
1461 case RTL_GIGA_MAC_VER_28:
1462 case RTL_GIGA_MAC_VER_31:
1463 rtl8168dp_driver_stop(tp);
1464 break;
1465 case RTL_GIGA_MAC_VER_49:
1466 case RTL_GIGA_MAC_VER_50:
1467 case RTL_GIGA_MAC_VER_51:
1468 rtl8168ep_driver_stop(tp);
1469 break;
1470 default:
1471 BUG();
1472 break;
1473 }
1474 }
1475
1476 static int r8168dp_check_dash(struct rtl8169_private *tp)
1477 {
1478 u16 reg = rtl8168_get_ocp_reg(tp);
1479
1480 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
1481 }
1482
1483 static int r8168ep_check_dash(struct rtl8169_private *tp)
1484 {
1485 return (ocp_read(tp, 0x0f, 0x128) & 0x00000001) ? 1 : 0;
1486 }
1487
1488 static int r8168_check_dash(struct rtl8169_private *tp)
1489 {
1490 switch (tp->mac_version) {
1491 case RTL_GIGA_MAC_VER_27:
1492 case RTL_GIGA_MAC_VER_28:
1493 case RTL_GIGA_MAC_VER_31:
1494 return r8168dp_check_dash(tp);
1495 case RTL_GIGA_MAC_VER_49:
1496 case RTL_GIGA_MAC_VER_50:
1497 case RTL_GIGA_MAC_VER_51:
1498 return r8168ep_check_dash(tp);
1499 default:
1500 return 0;
1501 }
1502 }
1503
1504 struct exgmac_reg {
1505 u16 addr;
1506 u16 mask;
1507 u32 val;
1508 };
1509
1510 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1511 const struct exgmac_reg *r, int len)
1512 {
1513 while (len-- > 0) {
1514 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1515 r++;
1516 }
1517 }
1518
1519 DECLARE_RTL_COND(rtl_efusear_cond)
1520 {
1521 void __iomem *ioaddr = tp->mmio_addr;
1522
1523 return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1524 }
1525
1526 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1527 {
1528 void __iomem *ioaddr = tp->mmio_addr;
1529
1530 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1531
1532 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1533 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1534 }
1535
1536 static u16 rtl_get_events(struct rtl8169_private *tp)
1537 {
1538 void __iomem *ioaddr = tp->mmio_addr;
1539
1540 return RTL_R16(IntrStatus);
1541 }
1542
1543 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1544 {
1545 void __iomem *ioaddr = tp->mmio_addr;
1546
1547 RTL_W16(IntrStatus, bits);
1548 mmiowb();
1549 }
1550
1551 static void rtl_irq_disable(struct rtl8169_private *tp)
1552 {
1553 void __iomem *ioaddr = tp->mmio_addr;
1554
1555 RTL_W16(IntrMask, 0);
1556 mmiowb();
1557 }
1558
1559 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1560 {
1561 void __iomem *ioaddr = tp->mmio_addr;
1562
1563 RTL_W16(IntrMask, bits);
1564 }
1565
1566 #define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1567 #define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1568 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1569
1570 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1571 {
1572 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1573 }
1574
1575 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1576 {
1577 void __iomem *ioaddr = tp->mmio_addr;
1578
1579 rtl_irq_disable(tp);
1580 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1581 RTL_R8(ChipCmd);
1582 }
1583
1584 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1585 {
1586 void __iomem *ioaddr = tp->mmio_addr;
1587
1588 return RTL_R32(TBICSR) & TBIReset;
1589 }
1590
1591 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1592 {
1593 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1594 }
1595
1596 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1597 {
1598 return RTL_R32(TBICSR) & TBILinkOk;
1599 }
1600
1601 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1602 {
1603 return RTL_R8(PHYstatus) & LinkStatus;
1604 }
1605
1606 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1607 {
1608 void __iomem *ioaddr = tp->mmio_addr;
1609
1610 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1611 }
1612
1613 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1614 {
1615 unsigned int val;
1616
1617 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1618 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1619 }
1620
1621 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1622 {
1623 void __iomem *ioaddr = tp->mmio_addr;
1624 struct net_device *dev = tp->dev;
1625
1626 if (!netif_running(dev))
1627 return;
1628
1629 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1630 tp->mac_version == RTL_GIGA_MAC_VER_38) {
1631 if (RTL_R8(PHYstatus) & _1000bpsF) {
1632 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1633 ERIAR_EXGMAC);
1634 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1635 ERIAR_EXGMAC);
1636 } else if (RTL_R8(PHYstatus) & _100bps) {
1637 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1638 ERIAR_EXGMAC);
1639 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1640 ERIAR_EXGMAC);
1641 } else {
1642 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1643 ERIAR_EXGMAC);
1644 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1645 ERIAR_EXGMAC);
1646 }
1647 /* Reset packet filter */
1648 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1649 ERIAR_EXGMAC);
1650 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1651 ERIAR_EXGMAC);
1652 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1653 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1654 if (RTL_R8(PHYstatus) & _1000bpsF) {
1655 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1656 ERIAR_EXGMAC);
1657 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1658 ERIAR_EXGMAC);
1659 } else {
1660 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1661 ERIAR_EXGMAC);
1662 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1663 ERIAR_EXGMAC);
1664 }
1665 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1666 if (RTL_R8(PHYstatus) & _10bps) {
1667 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1668 ERIAR_EXGMAC);
1669 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1670 ERIAR_EXGMAC);
1671 } else {
1672 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1673 ERIAR_EXGMAC);
1674 }
1675 }
1676 }
1677
1678 static void rtl8169_check_link_status(struct net_device *dev,
1679 struct rtl8169_private *tp,
1680 void __iomem *ioaddr)
1681 {
1682 if (tp->link_ok(ioaddr)) {
1683 rtl_link_chg_patch(tp);
1684 /* This is to cancel a scheduled suspend if there's one. */
1685 pm_request_resume(&tp->pci_dev->dev);
1686 netif_carrier_on(dev);
1687 if (net_ratelimit())
1688 netif_info(tp, ifup, dev, "link up\n");
1689 } else {
1690 netif_carrier_off(dev);
1691 netif_info(tp, ifdown, dev, "link down\n");
1692 pm_runtime_idle(&tp->pci_dev->dev);
1693 }
1694 }
1695
1696 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1697
1698 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1699 {
1700 void __iomem *ioaddr = tp->mmio_addr;
1701 u8 options;
1702 u32 wolopts = 0;
1703
1704 options = RTL_R8(Config1);
1705 if (!(options & PMEnable))
1706 return 0;
1707
1708 options = RTL_R8(Config3);
1709 if (options & LinkUp)
1710 wolopts |= WAKE_PHY;
1711 switch (tp->mac_version) {
1712 case RTL_GIGA_MAC_VER_34:
1713 case RTL_GIGA_MAC_VER_35:
1714 case RTL_GIGA_MAC_VER_36:
1715 case RTL_GIGA_MAC_VER_37:
1716 case RTL_GIGA_MAC_VER_38:
1717 case RTL_GIGA_MAC_VER_40:
1718 case RTL_GIGA_MAC_VER_41:
1719 case RTL_GIGA_MAC_VER_42:
1720 case RTL_GIGA_MAC_VER_43:
1721 case RTL_GIGA_MAC_VER_44:
1722 case RTL_GIGA_MAC_VER_45:
1723 case RTL_GIGA_MAC_VER_46:
1724 case RTL_GIGA_MAC_VER_47:
1725 case RTL_GIGA_MAC_VER_48:
1726 case RTL_GIGA_MAC_VER_49:
1727 case RTL_GIGA_MAC_VER_50:
1728 case RTL_GIGA_MAC_VER_51:
1729 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1730 wolopts |= WAKE_MAGIC;
1731 break;
1732 default:
1733 if (options & MagicPacket)
1734 wolopts |= WAKE_MAGIC;
1735 break;
1736 }
1737
1738 options = RTL_R8(Config5);
1739 if (options & UWF)
1740 wolopts |= WAKE_UCAST;
1741 if (options & BWF)
1742 wolopts |= WAKE_BCAST;
1743 if (options & MWF)
1744 wolopts |= WAKE_MCAST;
1745
1746 return wolopts;
1747 }
1748
1749 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1750 {
1751 struct rtl8169_private *tp = netdev_priv(dev);
1752 struct device *d = &tp->pci_dev->dev;
1753
1754 pm_runtime_get_noresume(d);
1755
1756 rtl_lock_work(tp);
1757
1758 wol->supported = WAKE_ANY;
1759 if (pm_runtime_active(d))
1760 wol->wolopts = __rtl8169_get_wol(tp);
1761 else
1762 wol->wolopts = tp->saved_wolopts;
1763
1764 rtl_unlock_work(tp);
1765
1766 pm_runtime_put_noidle(d);
1767 }
1768
1769 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1770 {
1771 void __iomem *ioaddr = tp->mmio_addr;
1772 unsigned int i, tmp;
1773 static const struct {
1774 u32 opt;
1775 u16 reg;
1776 u8 mask;
1777 } cfg[] = {
1778 { WAKE_PHY, Config3, LinkUp },
1779 { WAKE_UCAST, Config5, UWF },
1780 { WAKE_BCAST, Config5, BWF },
1781 { WAKE_MCAST, Config5, MWF },
1782 { WAKE_ANY, Config5, LanWake },
1783 { WAKE_MAGIC, Config3, MagicPacket }
1784 };
1785 u8 options;
1786
1787 RTL_W8(Cfg9346, Cfg9346_Unlock);
1788
1789 switch (tp->mac_version) {
1790 case RTL_GIGA_MAC_VER_34:
1791 case RTL_GIGA_MAC_VER_35:
1792 case RTL_GIGA_MAC_VER_36:
1793 case RTL_GIGA_MAC_VER_37:
1794 case RTL_GIGA_MAC_VER_38:
1795 case RTL_GIGA_MAC_VER_40:
1796 case RTL_GIGA_MAC_VER_41:
1797 case RTL_GIGA_MAC_VER_42:
1798 case RTL_GIGA_MAC_VER_43:
1799 case RTL_GIGA_MAC_VER_44:
1800 case RTL_GIGA_MAC_VER_45:
1801 case RTL_GIGA_MAC_VER_46:
1802 case RTL_GIGA_MAC_VER_47:
1803 case RTL_GIGA_MAC_VER_48:
1804 case RTL_GIGA_MAC_VER_49:
1805 case RTL_GIGA_MAC_VER_50:
1806 case RTL_GIGA_MAC_VER_51:
1807 tmp = ARRAY_SIZE(cfg) - 1;
1808 if (wolopts & WAKE_MAGIC)
1809 rtl_w0w1_eri(tp,
1810 0x0dc,
1811 ERIAR_MASK_0100,
1812 MagicPacket_v2,
1813 0x0000,
1814 ERIAR_EXGMAC);
1815 else
1816 rtl_w0w1_eri(tp,
1817 0x0dc,
1818 ERIAR_MASK_0100,
1819 0x0000,
1820 MagicPacket_v2,
1821 ERIAR_EXGMAC);
1822 break;
1823 default:
1824 tmp = ARRAY_SIZE(cfg);
1825 break;
1826 }
1827
1828 for (i = 0; i < tmp; i++) {
1829 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1830 if (wolopts & cfg[i].opt)
1831 options |= cfg[i].mask;
1832 RTL_W8(cfg[i].reg, options);
1833 }
1834
1835 switch (tp->mac_version) {
1836 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1837 options = RTL_R8(Config1) & ~PMEnable;
1838 if (wolopts)
1839 options |= PMEnable;
1840 RTL_W8(Config1, options);
1841 break;
1842 default:
1843 options = RTL_R8(Config2) & ~PME_SIGNAL;
1844 if (wolopts)
1845 options |= PME_SIGNAL;
1846 RTL_W8(Config2, options);
1847 break;
1848 }
1849
1850 RTL_W8(Cfg9346, Cfg9346_Lock);
1851 }
1852
1853 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1854 {
1855 struct rtl8169_private *tp = netdev_priv(dev);
1856 struct device *d = &tp->pci_dev->dev;
1857
1858 pm_runtime_get_noresume(d);
1859
1860 rtl_lock_work(tp);
1861
1862 if (wol->wolopts)
1863 tp->features |= RTL_FEATURE_WOL;
1864 else
1865 tp->features &= ~RTL_FEATURE_WOL;
1866 if (pm_runtime_active(d))
1867 __rtl8169_set_wol(tp, wol->wolopts);
1868 else
1869 tp->saved_wolopts = wol->wolopts;
1870
1871 rtl_unlock_work(tp);
1872
1873 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1874
1875 pm_runtime_put_noidle(d);
1876
1877 return 0;
1878 }
1879
1880 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1881 {
1882 return rtl_chip_infos[tp->mac_version].fw_name;
1883 }
1884
1885 static void rtl8169_get_drvinfo(struct net_device *dev,
1886 struct ethtool_drvinfo *info)
1887 {
1888 struct rtl8169_private *tp = netdev_priv(dev);
1889 struct rtl_fw *rtl_fw = tp->rtl_fw;
1890
1891 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1892 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1893 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1894 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1895 if (!IS_ERR_OR_NULL(rtl_fw))
1896 strlcpy(info->fw_version, rtl_fw->version,
1897 sizeof(info->fw_version));
1898 }
1899
1900 static int rtl8169_get_regs_len(struct net_device *dev)
1901 {
1902 return R8169_REGS_SIZE;
1903 }
1904
1905 static int rtl8169_set_speed_tbi(struct net_device *dev,
1906 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1907 {
1908 struct rtl8169_private *tp = netdev_priv(dev);
1909 void __iomem *ioaddr = tp->mmio_addr;
1910 int ret = 0;
1911 u32 reg;
1912
1913 reg = RTL_R32(TBICSR);
1914 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1915 (duplex == DUPLEX_FULL)) {
1916 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1917 } else if (autoneg == AUTONEG_ENABLE)
1918 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1919 else {
1920 netif_warn(tp, link, dev,
1921 "incorrect speed setting refused in TBI mode\n");
1922 ret = -EOPNOTSUPP;
1923 }
1924
1925 return ret;
1926 }
1927
1928 static int rtl8169_set_speed_xmii(struct net_device *dev,
1929 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1930 {
1931 struct rtl8169_private *tp = netdev_priv(dev);
1932 int giga_ctrl, bmcr;
1933 int rc = -EINVAL;
1934
1935 rtl_writephy(tp, 0x1f, 0x0000);
1936
1937 if (autoneg == AUTONEG_ENABLE) {
1938 int auto_nego;
1939
1940 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1941 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1942 ADVERTISE_100HALF | ADVERTISE_100FULL);
1943
1944 if (adv & ADVERTISED_10baseT_Half)
1945 auto_nego |= ADVERTISE_10HALF;
1946 if (adv & ADVERTISED_10baseT_Full)
1947 auto_nego |= ADVERTISE_10FULL;
1948 if (adv & ADVERTISED_100baseT_Half)
1949 auto_nego |= ADVERTISE_100HALF;
1950 if (adv & ADVERTISED_100baseT_Full)
1951 auto_nego |= ADVERTISE_100FULL;
1952
1953 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1954
1955 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1956 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1957
1958 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1959 if (tp->mii.supports_gmii) {
1960 if (adv & ADVERTISED_1000baseT_Half)
1961 giga_ctrl |= ADVERTISE_1000HALF;
1962 if (adv & ADVERTISED_1000baseT_Full)
1963 giga_ctrl |= ADVERTISE_1000FULL;
1964 } else if (adv & (ADVERTISED_1000baseT_Half |
1965 ADVERTISED_1000baseT_Full)) {
1966 netif_info(tp, link, dev,
1967 "PHY does not support 1000Mbps\n");
1968 goto out;
1969 }
1970
1971 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1972
1973 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1974 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1975 } else {
1976 if (speed == SPEED_10)
1977 bmcr = 0;
1978 else if (speed == SPEED_100)
1979 bmcr = BMCR_SPEED100;
1980 else
1981 goto out;
1982
1983 if (duplex == DUPLEX_FULL)
1984 bmcr |= BMCR_FULLDPLX;
1985 }
1986
1987 rtl_writephy(tp, MII_BMCR, bmcr);
1988
1989 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1990 tp->mac_version == RTL_GIGA_MAC_VER_03) {
1991 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1992 rtl_writephy(tp, 0x17, 0x2138);
1993 rtl_writephy(tp, 0x0e, 0x0260);
1994 } else {
1995 rtl_writephy(tp, 0x17, 0x2108);
1996 rtl_writephy(tp, 0x0e, 0x0000);
1997 }
1998 }
1999
2000 rc = 0;
2001 out:
2002 return rc;
2003 }
2004
2005 static int rtl8169_set_speed(struct net_device *dev,
2006 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
2007 {
2008 struct rtl8169_private *tp = netdev_priv(dev);
2009 int ret;
2010
2011 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
2012 if (ret < 0)
2013 goto out;
2014
2015 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
2016 (advertising & ADVERTISED_1000baseT_Full) &&
2017 !pci_is_pcie(tp->pci_dev)) {
2018 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
2019 }
2020 out:
2021 return ret;
2022 }
2023
2024 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
2025 netdev_features_t features)
2026 {
2027 struct rtl8169_private *tp = netdev_priv(dev);
2028
2029 if (dev->mtu > TD_MSS_MAX)
2030 features &= ~NETIF_F_ALL_TSO;
2031
2032 if (dev->mtu > JUMBO_1K &&
2033 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
2034 features &= ~NETIF_F_IP_CSUM;
2035
2036 return features;
2037 }
2038
2039 static void __rtl8169_set_features(struct net_device *dev,
2040 netdev_features_t features)
2041 {
2042 struct rtl8169_private *tp = netdev_priv(dev);
2043 void __iomem *ioaddr = tp->mmio_addr;
2044 u32 rx_config;
2045
2046 rx_config = RTL_R32(RxConfig);
2047 if (features & NETIF_F_RXALL)
2048 rx_config |= (AcceptErr | AcceptRunt);
2049 else
2050 rx_config &= ~(AcceptErr | AcceptRunt);
2051
2052 RTL_W32(RxConfig, rx_config);
2053
2054 if (features & NETIF_F_RXCSUM)
2055 tp->cp_cmd |= RxChkSum;
2056 else
2057 tp->cp_cmd &= ~RxChkSum;
2058
2059 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2060 tp->cp_cmd |= RxVlan;
2061 else
2062 tp->cp_cmd &= ~RxVlan;
2063
2064 tp->cp_cmd |= RTL_R16(CPlusCmd) & ~(RxVlan | RxChkSum);
2065
2066 RTL_W16(CPlusCmd, tp->cp_cmd);
2067 RTL_R16(CPlusCmd);
2068 }
2069
2070 static int rtl8169_set_features(struct net_device *dev,
2071 netdev_features_t features)
2072 {
2073 struct rtl8169_private *tp = netdev_priv(dev);
2074
2075 features &= NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX;
2076
2077 rtl_lock_work(tp);
2078 if (features ^ dev->features)
2079 __rtl8169_set_features(dev, features);
2080 rtl_unlock_work(tp);
2081
2082 return 0;
2083 }
2084
2085
2086 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
2087 {
2088 return (skb_vlan_tag_present(skb)) ?
2089 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
2090 }
2091
2092 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
2093 {
2094 u32 opts2 = le32_to_cpu(desc->opts2);
2095
2096 if (opts2 & RxVlanTag)
2097 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
2098 }
2099
2100 static int rtl8169_get_link_ksettings_tbi(struct net_device *dev,
2101 struct ethtool_link_ksettings *cmd)
2102 {
2103 struct rtl8169_private *tp = netdev_priv(dev);
2104 void __iomem *ioaddr = tp->mmio_addr;
2105 u32 status;
2106 u32 supported, advertising;
2107
2108 supported =
2109 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
2110 cmd->base.port = PORT_FIBRE;
2111
2112 status = RTL_R32(TBICSR);
2113 advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
2114 cmd->base.autoneg = !!(status & TBINwEnable);
2115
2116 cmd->base.speed = SPEED_1000;
2117 cmd->base.duplex = DUPLEX_FULL; /* Always set */
2118
2119 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
2120 supported);
2121 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
2122 advertising);
2123
2124 return 0;
2125 }
2126
2127 static int rtl8169_get_link_ksettings_xmii(struct net_device *dev,
2128 struct ethtool_link_ksettings *cmd)
2129 {
2130 struct rtl8169_private *tp = netdev_priv(dev);
2131
2132 mii_ethtool_get_link_ksettings(&tp->mii, cmd);
2133
2134 return 0;
2135 }
2136
2137 static int rtl8169_get_link_ksettings(struct net_device *dev,
2138 struct ethtool_link_ksettings *cmd)
2139 {
2140 struct rtl8169_private *tp = netdev_priv(dev);
2141 int rc;
2142
2143 rtl_lock_work(tp);
2144 rc = tp->get_link_ksettings(dev, cmd);
2145 rtl_unlock_work(tp);
2146
2147 return rc;
2148 }
2149
2150 static int rtl8169_set_link_ksettings(struct net_device *dev,
2151 const struct ethtool_link_ksettings *cmd)
2152 {
2153 struct rtl8169_private *tp = netdev_priv(dev);
2154 int rc;
2155 u32 advertising;
2156
2157 if (!ethtool_convert_link_mode_to_legacy_u32(&advertising,
2158 cmd->link_modes.advertising))
2159 return -EINVAL;
2160
2161 del_timer_sync(&tp->timer);
2162
2163 rtl_lock_work(tp);
2164 rc = rtl8169_set_speed(dev, cmd->base.autoneg, cmd->base.speed,
2165 cmd->base.duplex, advertising);
2166 rtl_unlock_work(tp);
2167
2168 return rc;
2169 }
2170
2171 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2172 void *p)
2173 {
2174 struct rtl8169_private *tp = netdev_priv(dev);
2175 u32 __iomem *data = tp->mmio_addr;
2176 u32 *dw = p;
2177 int i;
2178
2179 rtl_lock_work(tp);
2180 for (i = 0; i < R8169_REGS_SIZE; i += 4)
2181 memcpy_fromio(dw++, data++, 4);
2182 rtl_unlock_work(tp);
2183 }
2184
2185 static u32 rtl8169_get_msglevel(struct net_device *dev)
2186 {
2187 struct rtl8169_private *tp = netdev_priv(dev);
2188
2189 return tp->msg_enable;
2190 }
2191
2192 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
2193 {
2194 struct rtl8169_private *tp = netdev_priv(dev);
2195
2196 tp->msg_enable = value;
2197 }
2198
2199 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
2200 "tx_packets",
2201 "rx_packets",
2202 "tx_errors",
2203 "rx_errors",
2204 "rx_missed",
2205 "align_errors",
2206 "tx_single_collisions",
2207 "tx_multi_collisions",
2208 "unicast",
2209 "broadcast",
2210 "multicast",
2211 "tx_aborted",
2212 "tx_underrun",
2213 };
2214
2215 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
2216 {
2217 switch (sset) {
2218 case ETH_SS_STATS:
2219 return ARRAY_SIZE(rtl8169_gstrings);
2220 default:
2221 return -EOPNOTSUPP;
2222 }
2223 }
2224
2225 DECLARE_RTL_COND(rtl_counters_cond)
2226 {
2227 void __iomem *ioaddr = tp->mmio_addr;
2228
2229 return RTL_R32(CounterAddrLow) & (CounterReset | CounterDump);
2230 }
2231
2232 static bool rtl8169_do_counters(struct net_device *dev, u32 counter_cmd)
2233 {
2234 struct rtl8169_private *tp = netdev_priv(dev);
2235 void __iomem *ioaddr = tp->mmio_addr;
2236 dma_addr_t paddr = tp->counters_phys_addr;
2237 u32 cmd;
2238
2239 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
2240 RTL_R32(CounterAddrHigh);
2241 cmd = (u64)paddr & DMA_BIT_MASK(32);
2242 RTL_W32(CounterAddrLow, cmd);
2243 RTL_W32(CounterAddrLow, cmd | counter_cmd);
2244
2245 return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
2246 }
2247
2248 static bool rtl8169_reset_counters(struct net_device *dev)
2249 {
2250 struct rtl8169_private *tp = netdev_priv(dev);
2251
2252 /*
2253 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
2254 * tally counters.
2255 */
2256 if (tp->mac_version < RTL_GIGA_MAC_VER_19)
2257 return true;
2258
2259 return rtl8169_do_counters(dev, CounterReset);
2260 }
2261
2262 static bool rtl8169_update_counters(struct net_device *dev)
2263 {
2264 struct rtl8169_private *tp = netdev_priv(dev);
2265 void __iomem *ioaddr = tp->mmio_addr;
2266
2267 /*
2268 * Some chips are unable to dump tally counters when the receiver
2269 * is disabled.
2270 */
2271 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
2272 return true;
2273
2274 return rtl8169_do_counters(dev, CounterDump);
2275 }
2276
2277 static bool rtl8169_init_counter_offsets(struct net_device *dev)
2278 {
2279 struct rtl8169_private *tp = netdev_priv(dev);
2280 struct rtl8169_counters *counters = tp->counters;
2281 bool ret = false;
2282
2283 /*
2284 * rtl8169_init_counter_offsets is called from rtl_open. On chip
2285 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
2286 * reset by a power cycle, while the counter values collected by the
2287 * driver are reset at every driver unload/load cycle.
2288 *
2289 * To make sure the HW values returned by @get_stats64 match the SW
2290 * values, we collect the initial values at first open(*) and use them
2291 * as offsets to normalize the values returned by @get_stats64.
2292 *
2293 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
2294 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
2295 * set at open time by rtl_hw_start.
2296 */
2297
2298 if (tp->tc_offset.inited)
2299 return true;
2300
2301 /* If both, reset and update fail, propagate to caller. */
2302 if (rtl8169_reset_counters(dev))
2303 ret = true;
2304
2305 if (rtl8169_update_counters(dev))
2306 ret = true;
2307
2308 tp->tc_offset.tx_errors = counters->tx_errors;
2309 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
2310 tp->tc_offset.tx_aborted = counters->tx_aborted;
2311 tp->tc_offset.inited = true;
2312
2313 return ret;
2314 }
2315
2316 static void rtl8169_get_ethtool_stats(struct net_device *dev,
2317 struct ethtool_stats *stats, u64 *data)
2318 {
2319 struct rtl8169_private *tp = netdev_priv(dev);
2320 struct device *d = &tp->pci_dev->dev;
2321 struct rtl8169_counters *counters = tp->counters;
2322
2323 ASSERT_RTNL();
2324
2325 pm_runtime_get_noresume(d);
2326
2327 if (pm_runtime_active(d))
2328 rtl8169_update_counters(dev);
2329
2330 pm_runtime_put_noidle(d);
2331
2332 data[0] = le64_to_cpu(counters->tx_packets);
2333 data[1] = le64_to_cpu(counters->rx_packets);
2334 data[2] = le64_to_cpu(counters->tx_errors);
2335 data[3] = le32_to_cpu(counters->rx_errors);
2336 data[4] = le16_to_cpu(counters->rx_missed);
2337 data[5] = le16_to_cpu(counters->align_errors);
2338 data[6] = le32_to_cpu(counters->tx_one_collision);
2339 data[7] = le32_to_cpu(counters->tx_multi_collision);
2340 data[8] = le64_to_cpu(counters->rx_unicast);
2341 data[9] = le64_to_cpu(counters->rx_broadcast);
2342 data[10] = le32_to_cpu(counters->rx_multicast);
2343 data[11] = le16_to_cpu(counters->tx_aborted);
2344 data[12] = le16_to_cpu(counters->tx_underun);
2345 }
2346
2347 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2348 {
2349 switch(stringset) {
2350 case ETH_SS_STATS:
2351 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
2352 break;
2353 }
2354 }
2355
2356 static int rtl8169_nway_reset(struct net_device *dev)
2357 {
2358 struct rtl8169_private *tp = netdev_priv(dev);
2359
2360 return mii_nway_restart(&tp->mii);
2361 }
2362
2363 /*
2364 * Interrupt coalescing
2365 *
2366 * > 1 - the availability of the IntrMitigate (0xe2) register through the
2367 * > 8169, 8168 and 810x line of chipsets
2368 *
2369 * 8169, 8168, and 8136(810x) serial chipsets support it.
2370 *
2371 * > 2 - the Tx timer unit at gigabit speed
2372 *
2373 * The unit of the timer depends on both the speed and the setting of CPlusCmd
2374 * (0xe0) bit 1 and bit 0.
2375 *
2376 * For 8169
2377 * bit[1:0] \ speed 1000M 100M 10M
2378 * 0 0 320ns 2.56us 40.96us
2379 * 0 1 2.56us 20.48us 327.7us
2380 * 1 0 5.12us 40.96us 655.4us
2381 * 1 1 10.24us 81.92us 1.31ms
2382 *
2383 * For the other
2384 * bit[1:0] \ speed 1000M 100M 10M
2385 * 0 0 5us 2.56us 40.96us
2386 * 0 1 40us 20.48us 327.7us
2387 * 1 0 80us 40.96us 655.4us
2388 * 1 1 160us 81.92us 1.31ms
2389 */
2390
2391 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
2392 struct rtl_coalesce_scale {
2393 /* Rx / Tx */
2394 u32 nsecs[2];
2395 };
2396
2397 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
2398 struct rtl_coalesce_info {
2399 u32 speed;
2400 struct rtl_coalesce_scale scalev[4]; /* each CPlusCmd[0:1] case */
2401 };
2402
2403 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
2404 #define rxtx_x1822(r, t) { \
2405 {{(r), (t)}}, \
2406 {{(r)*8, (t)*8}}, \
2407 {{(r)*8*2, (t)*8*2}}, \
2408 {{(r)*8*2*2, (t)*8*2*2}}, \
2409 }
2410 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
2411 /* speed delays: rx00 tx00 */
2412 { SPEED_10, rxtx_x1822(40960, 40960) },
2413 { SPEED_100, rxtx_x1822( 2560, 2560) },
2414 { SPEED_1000, rxtx_x1822( 320, 320) },
2415 { 0 },
2416 };
2417
2418 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
2419 /* speed delays: rx00 tx00 */
2420 { SPEED_10, rxtx_x1822(40960, 40960) },
2421 { SPEED_100, rxtx_x1822( 2560, 2560) },
2422 { SPEED_1000, rxtx_x1822( 5000, 5000) },
2423 { 0 },
2424 };
2425 #undef rxtx_x1822
2426
2427 /* get rx/tx scale vector corresponding to current speed */
2428 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
2429 {
2430 struct rtl8169_private *tp = netdev_priv(dev);
2431 struct ethtool_link_ksettings ecmd;
2432 const struct rtl_coalesce_info *ci;
2433 int rc;
2434
2435 rc = rtl8169_get_link_ksettings(dev, &ecmd);
2436 if (rc < 0)
2437 return ERR_PTR(rc);
2438
2439 for (ci = tp->coalesce_info; ci->speed != 0; ci++) {
2440 if (ecmd.base.speed == ci->speed) {
2441 return ci;
2442 }
2443 }
2444
2445 return ERR_PTR(-ELNRNG);
2446 }
2447
2448 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
2449 {
2450 struct rtl8169_private *tp = netdev_priv(dev);
2451 void __iomem *ioaddr = tp->mmio_addr;
2452 const struct rtl_coalesce_info *ci;
2453 const struct rtl_coalesce_scale *scale;
2454 struct {
2455 u32 *max_frames;
2456 u32 *usecs;
2457 } coal_settings [] = {
2458 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
2459 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
2460 }, *p = coal_settings;
2461 int i;
2462 u16 w;
2463
2464 memset(ec, 0, sizeof(*ec));
2465
2466 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
2467 ci = rtl_coalesce_info(dev);
2468 if (IS_ERR(ci))
2469 return PTR_ERR(ci);
2470
2471 scale = &ci->scalev[RTL_R16(CPlusCmd) & 3];
2472
2473 /* read IntrMitigate and adjust according to scale */
2474 for (w = RTL_R16(IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
2475 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
2476 w >>= RTL_COALESCE_SHIFT;
2477 *p->usecs = w & RTL_COALESCE_MASK;
2478 }
2479
2480 for (i = 0; i < 2; i++) {
2481 p = coal_settings + i;
2482 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
2483
2484 /*
2485 * ethtool_coalesce says it is illegal to set both usecs and
2486 * max_frames to 0.
2487 */
2488 if (!*p->usecs && !*p->max_frames)
2489 *p->max_frames = 1;
2490 }
2491
2492 return 0;
2493 }
2494
2495 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
2496 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
2497 struct net_device *dev, u32 nsec, u16 *cp01)
2498 {
2499 const struct rtl_coalesce_info *ci;
2500 u16 i;
2501
2502 ci = rtl_coalesce_info(dev);
2503 if (IS_ERR(ci))
2504 return ERR_CAST(ci);
2505
2506 for (i = 0; i < 4; i++) {
2507 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
2508 ci->scalev[i].nsecs[1]);
2509 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
2510 *cp01 = i;
2511 return &ci->scalev[i];
2512 }
2513 }
2514
2515 return ERR_PTR(-EINVAL);
2516 }
2517
2518 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
2519 {
2520 struct rtl8169_private *tp = netdev_priv(dev);
2521 void __iomem *ioaddr = tp->mmio_addr;
2522 const struct rtl_coalesce_scale *scale;
2523 struct {
2524 u32 frames;
2525 u32 usecs;
2526 } coal_settings [] = {
2527 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
2528 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
2529 }, *p = coal_settings;
2530 u16 w = 0, cp01;
2531 int i;
2532
2533 scale = rtl_coalesce_choose_scale(dev,
2534 max(p[0].usecs, p[1].usecs) * 1000, &cp01);
2535 if (IS_ERR(scale))
2536 return PTR_ERR(scale);
2537
2538 for (i = 0; i < 2; i++, p++) {
2539 u32 units;
2540
2541 /*
2542 * accept max_frames=1 we returned in rtl_get_coalesce.
2543 * accept it not only when usecs=0 because of e.g. the following scenario:
2544 *
2545 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
2546 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
2547 * - then user does `ethtool -C eth0 rx-usecs 100`
2548 *
2549 * since ethtool sends to kernel whole ethtool_coalesce
2550 * settings, if we do not handle rx_usecs=!0, rx_frames=1
2551 * we'll reject it below in `frames % 4 != 0`.
2552 */
2553 if (p->frames == 1) {
2554 p->frames = 0;
2555 }
2556
2557 units = p->usecs * 1000 / scale->nsecs[i];
2558 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
2559 return -EINVAL;
2560
2561 w <<= RTL_COALESCE_SHIFT;
2562 w |= units;
2563 w <<= RTL_COALESCE_SHIFT;
2564 w |= p->frames >> 2;
2565 }
2566
2567 rtl_lock_work(tp);
2568
2569 RTL_W16(IntrMitigate, swab16(w));
2570
2571 tp->cp_cmd = (tp->cp_cmd & ~3) | cp01;
2572 RTL_W16(CPlusCmd, tp->cp_cmd);
2573 RTL_R16(CPlusCmd);
2574
2575 rtl_unlock_work(tp);
2576
2577 return 0;
2578 }
2579
2580 static const struct ethtool_ops rtl8169_ethtool_ops = {
2581 .get_drvinfo = rtl8169_get_drvinfo,
2582 .get_regs_len = rtl8169_get_regs_len,
2583 .get_link = ethtool_op_get_link,
2584 .get_coalesce = rtl_get_coalesce,
2585 .set_coalesce = rtl_set_coalesce,
2586 .get_msglevel = rtl8169_get_msglevel,
2587 .set_msglevel = rtl8169_set_msglevel,
2588 .get_regs = rtl8169_get_regs,
2589 .get_wol = rtl8169_get_wol,
2590 .set_wol = rtl8169_set_wol,
2591 .get_strings = rtl8169_get_strings,
2592 .get_sset_count = rtl8169_get_sset_count,
2593 .get_ethtool_stats = rtl8169_get_ethtool_stats,
2594 .get_ts_info = ethtool_op_get_ts_info,
2595 .nway_reset = rtl8169_nway_reset,
2596 .get_link_ksettings = rtl8169_get_link_ksettings,
2597 .set_link_ksettings = rtl8169_set_link_ksettings,
2598 };
2599
2600 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2601 struct net_device *dev, u8 default_version)
2602 {
2603 void __iomem *ioaddr = tp->mmio_addr;
2604 /*
2605 * The driver currently handles the 8168Bf and the 8168Be identically
2606 * but they can be identified more specifically through the test below
2607 * if needed:
2608 *
2609 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2610 *
2611 * Same thing for the 8101Eb and the 8101Ec:
2612 *
2613 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2614 */
2615 static const struct rtl_mac_info {
2616 u32 mask;
2617 u32 val;
2618 int mac_version;
2619 } mac_info[] = {
2620 /* 8168EP family. */
2621 { 0x7cf00000, 0x50200000, RTL_GIGA_MAC_VER_51 },
2622 { 0x7cf00000, 0x50100000, RTL_GIGA_MAC_VER_50 },
2623 { 0x7cf00000, 0x50000000, RTL_GIGA_MAC_VER_49 },
2624
2625 /* 8168H family. */
2626 { 0x7cf00000, 0x54100000, RTL_GIGA_MAC_VER_46 },
2627 { 0x7cf00000, 0x54000000, RTL_GIGA_MAC_VER_45 },
2628
2629 /* 8168G family. */
2630 { 0x7cf00000, 0x5c800000, RTL_GIGA_MAC_VER_44 },
2631 { 0x7cf00000, 0x50900000, RTL_GIGA_MAC_VER_42 },
2632 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
2633 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
2634
2635 /* 8168F family. */
2636 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
2637 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
2638 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
2639
2640 /* 8168E family. */
2641 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
2642 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
2643 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
2644 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
2645
2646 /* 8168D family. */
2647 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
2648 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
2649 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
2650
2651 /* 8168DP family. */
2652 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
2653 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
2654 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
2655
2656 /* 8168C family. */
2657 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
2658 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
2659 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
2660 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
2661 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
2662 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
2663 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
2664 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
2665 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
2666
2667 /* 8168B family. */
2668 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
2669 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
2670 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
2671 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
2672
2673 /* 8101 family. */
2674 { 0x7cf00000, 0x44900000, RTL_GIGA_MAC_VER_39 },
2675 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 },
2676 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
2677 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
2678 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
2679 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
2680 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2681 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
2682 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
2683 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
2684 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
2685 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
2686 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
2687 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2688 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
2689 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2690 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
2691 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
2692 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
2693 /* FIXME: where did these entries come from ? -- FR */
2694 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
2695 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
2696
2697 /* 8110 family. */
2698 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
2699 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
2700 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
2701 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
2702 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
2703 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
2704
2705 /* Catch-all */
2706 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
2707 };
2708 const struct rtl_mac_info *p = mac_info;
2709 u32 reg;
2710
2711 reg = RTL_R32(TxConfig);
2712 while ((reg & p->mask) != p->val)
2713 p++;
2714 tp->mac_version = p->mac_version;
2715
2716 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2717 netif_notice(tp, probe, dev,
2718 "unknown MAC, using family default\n");
2719 tp->mac_version = default_version;
2720 } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2721 tp->mac_version = tp->mii.supports_gmii ?
2722 RTL_GIGA_MAC_VER_42 :
2723 RTL_GIGA_MAC_VER_43;
2724 } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
2725 tp->mac_version = tp->mii.supports_gmii ?
2726 RTL_GIGA_MAC_VER_45 :
2727 RTL_GIGA_MAC_VER_47;
2728 } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
2729 tp->mac_version = tp->mii.supports_gmii ?
2730 RTL_GIGA_MAC_VER_46 :
2731 RTL_GIGA_MAC_VER_48;
2732 }
2733 }
2734
2735 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2736 {
2737 dprintk("mac_version = 0x%02x\n", tp->mac_version);
2738 }
2739
2740 struct phy_reg {
2741 u16 reg;
2742 u16 val;
2743 };
2744
2745 static void rtl_writephy_batch(struct rtl8169_private *tp,
2746 const struct phy_reg *regs, int len)
2747 {
2748 while (len-- > 0) {
2749 rtl_writephy(tp, regs->reg, regs->val);
2750 regs++;
2751 }
2752 }
2753
2754 #define PHY_READ 0x00000000
2755 #define PHY_DATA_OR 0x10000000
2756 #define PHY_DATA_AND 0x20000000
2757 #define PHY_BJMPN 0x30000000
2758 #define PHY_MDIO_CHG 0x40000000
2759 #define PHY_CLEAR_READCOUNT 0x70000000
2760 #define PHY_WRITE 0x80000000
2761 #define PHY_READCOUNT_EQ_SKIP 0x90000000
2762 #define PHY_COMP_EQ_SKIPN 0xa0000000
2763 #define PHY_COMP_NEQ_SKIPN 0xb0000000
2764 #define PHY_WRITE_PREVIOUS 0xc0000000
2765 #define PHY_SKIPN 0xd0000000
2766 #define PHY_DELAY_MS 0xe0000000
2767
2768 struct fw_info {
2769 u32 magic;
2770 char version[RTL_VER_SIZE];
2771 __le32 fw_start;
2772 __le32 fw_len;
2773 u8 chksum;
2774 } __packed;
2775
2776 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2777
2778 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2779 {
2780 const struct firmware *fw = rtl_fw->fw;
2781 struct fw_info *fw_info = (struct fw_info *)fw->data;
2782 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2783 char *version = rtl_fw->version;
2784 bool rc = false;
2785
2786 if (fw->size < FW_OPCODE_SIZE)
2787 goto out;
2788
2789 if (!fw_info->magic) {
2790 size_t i, size, start;
2791 u8 checksum = 0;
2792
2793 if (fw->size < sizeof(*fw_info))
2794 goto out;
2795
2796 for (i = 0; i < fw->size; i++)
2797 checksum += fw->data[i];
2798 if (checksum != 0)
2799 goto out;
2800
2801 start = le32_to_cpu(fw_info->fw_start);
2802 if (start > fw->size)
2803 goto out;
2804
2805 size = le32_to_cpu(fw_info->fw_len);
2806 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2807 goto out;
2808
2809 memcpy(version, fw_info->version, RTL_VER_SIZE);
2810
2811 pa->code = (__le32 *)(fw->data + start);
2812 pa->size = size;
2813 } else {
2814 if (fw->size % FW_OPCODE_SIZE)
2815 goto out;
2816
2817 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2818
2819 pa->code = (__le32 *)fw->data;
2820 pa->size = fw->size / FW_OPCODE_SIZE;
2821 }
2822 version[RTL_VER_SIZE - 1] = 0;
2823
2824 rc = true;
2825 out:
2826 return rc;
2827 }
2828
2829 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2830 struct rtl_fw_phy_action *pa)
2831 {
2832 bool rc = false;
2833 size_t index;
2834
2835 for (index = 0; index < pa->size; index++) {
2836 u32 action = le32_to_cpu(pa->code[index]);
2837 u32 regno = (action & 0x0fff0000) >> 16;
2838
2839 switch(action & 0xf0000000) {
2840 case PHY_READ:
2841 case PHY_DATA_OR:
2842 case PHY_DATA_AND:
2843 case PHY_MDIO_CHG:
2844 case PHY_CLEAR_READCOUNT:
2845 case PHY_WRITE:
2846 case PHY_WRITE_PREVIOUS:
2847 case PHY_DELAY_MS:
2848 break;
2849
2850 case PHY_BJMPN:
2851 if (regno > index) {
2852 netif_err(tp, ifup, tp->dev,
2853 "Out of range of firmware\n");
2854 goto out;
2855 }
2856 break;
2857 case PHY_READCOUNT_EQ_SKIP:
2858 if (index + 2 >= pa->size) {
2859 netif_err(tp, ifup, tp->dev,
2860 "Out of range of firmware\n");
2861 goto out;
2862 }
2863 break;
2864 case PHY_COMP_EQ_SKIPN:
2865 case PHY_COMP_NEQ_SKIPN:
2866 case PHY_SKIPN:
2867 if (index + 1 + regno >= pa->size) {
2868 netif_err(tp, ifup, tp->dev,
2869 "Out of range of firmware\n");
2870 goto out;
2871 }
2872 break;
2873
2874 default:
2875 netif_err(tp, ifup, tp->dev,
2876 "Invalid action 0x%08x\n", action);
2877 goto out;
2878 }
2879 }
2880 rc = true;
2881 out:
2882 return rc;
2883 }
2884
2885 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2886 {
2887 struct net_device *dev = tp->dev;
2888 int rc = -EINVAL;
2889
2890 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2891 netif_err(tp, ifup, dev, "invalid firmware\n");
2892 goto out;
2893 }
2894
2895 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2896 rc = 0;
2897 out:
2898 return rc;
2899 }
2900
2901 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2902 {
2903 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2904 struct mdio_ops org, *ops = &tp->mdio_ops;
2905 u32 predata, count;
2906 size_t index;
2907
2908 predata = count = 0;
2909 org.write = ops->write;
2910 org.read = ops->read;
2911
2912 for (index = 0; index < pa->size; ) {
2913 u32 action = le32_to_cpu(pa->code[index]);
2914 u32 data = action & 0x0000ffff;
2915 u32 regno = (action & 0x0fff0000) >> 16;
2916
2917 if (!action)
2918 break;
2919
2920 switch(action & 0xf0000000) {
2921 case PHY_READ:
2922 predata = rtl_readphy(tp, regno);
2923 count++;
2924 index++;
2925 break;
2926 case PHY_DATA_OR:
2927 predata |= data;
2928 index++;
2929 break;
2930 case PHY_DATA_AND:
2931 predata &= data;
2932 index++;
2933 break;
2934 case PHY_BJMPN:
2935 index -= regno;
2936 break;
2937 case PHY_MDIO_CHG:
2938 if (data == 0) {
2939 ops->write = org.write;
2940 ops->read = org.read;
2941 } else if (data == 1) {
2942 ops->write = mac_mcu_write;
2943 ops->read = mac_mcu_read;
2944 }
2945
2946 index++;
2947 break;
2948 case PHY_CLEAR_READCOUNT:
2949 count = 0;
2950 index++;
2951 break;
2952 case PHY_WRITE:
2953 rtl_writephy(tp, regno, data);
2954 index++;
2955 break;
2956 case PHY_READCOUNT_EQ_SKIP:
2957 index += (count == data) ? 2 : 1;
2958 break;
2959 case PHY_COMP_EQ_SKIPN:
2960 if (predata == data)
2961 index += regno;
2962 index++;
2963 break;
2964 case PHY_COMP_NEQ_SKIPN:
2965 if (predata != data)
2966 index += regno;
2967 index++;
2968 break;
2969 case PHY_WRITE_PREVIOUS:
2970 rtl_writephy(tp, regno, predata);
2971 index++;
2972 break;
2973 case PHY_SKIPN:
2974 index += regno + 1;
2975 break;
2976 case PHY_DELAY_MS:
2977 mdelay(data);
2978 index++;
2979 break;
2980
2981 default:
2982 BUG();
2983 }
2984 }
2985
2986 ops->write = org.write;
2987 ops->read = org.read;
2988 }
2989
2990 static void rtl_release_firmware(struct rtl8169_private *tp)
2991 {
2992 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2993 release_firmware(tp->rtl_fw->fw);
2994 kfree(tp->rtl_fw);
2995 }
2996 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2997 }
2998
2999 static void rtl_apply_firmware(struct rtl8169_private *tp)
3000 {
3001 struct rtl_fw *rtl_fw = tp->rtl_fw;
3002
3003 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
3004 if (!IS_ERR_OR_NULL(rtl_fw))
3005 rtl_phy_write_fw(tp, rtl_fw);
3006 }
3007
3008 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
3009 {
3010 if (rtl_readphy(tp, reg) != val)
3011 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
3012 else
3013 rtl_apply_firmware(tp);
3014 }
3015
3016 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
3017 {
3018 static const struct phy_reg phy_reg_init[] = {
3019 { 0x1f, 0x0001 },
3020 { 0x06, 0x006e },
3021 { 0x08, 0x0708 },
3022 { 0x15, 0x4000 },
3023 { 0x18, 0x65c7 },
3024
3025 { 0x1f, 0x0001 },
3026 { 0x03, 0x00a1 },
3027 { 0x02, 0x0008 },
3028 { 0x01, 0x0120 },
3029 { 0x00, 0x1000 },
3030 { 0x04, 0x0800 },
3031 { 0x04, 0x0000 },
3032
3033 { 0x03, 0xff41 },
3034 { 0x02, 0xdf60 },
3035 { 0x01, 0x0140 },
3036 { 0x00, 0x0077 },
3037 { 0x04, 0x7800 },
3038 { 0x04, 0x7000 },
3039
3040 { 0x03, 0x802f },
3041 { 0x02, 0x4f02 },
3042 { 0x01, 0x0409 },
3043 { 0x00, 0xf0f9 },
3044 { 0x04, 0x9800 },
3045 { 0x04, 0x9000 },
3046
3047 { 0x03, 0xdf01 },
3048 { 0x02, 0xdf20 },
3049 { 0x01, 0xff95 },
3050 { 0x00, 0xba00 },
3051 { 0x04, 0xa800 },
3052 { 0x04, 0xa000 },
3053
3054 { 0x03, 0xff41 },
3055 { 0x02, 0xdf20 },
3056 { 0x01, 0x0140 },
3057 { 0x00, 0x00bb },
3058 { 0x04, 0xb800 },
3059 { 0x04, 0xb000 },
3060
3061 { 0x03, 0xdf41 },
3062 { 0x02, 0xdc60 },
3063 { 0x01, 0x6340 },
3064 { 0x00, 0x007d },
3065 { 0x04, 0xd800 },
3066 { 0x04, 0xd000 },
3067
3068 { 0x03, 0xdf01 },
3069 { 0x02, 0xdf20 },
3070 { 0x01, 0x100a },
3071 { 0x00, 0xa0ff },
3072 { 0x04, 0xf800 },
3073 { 0x04, 0xf000 },
3074
3075 { 0x1f, 0x0000 },
3076 { 0x0b, 0x0000 },
3077 { 0x00, 0x9200 }
3078 };
3079
3080 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3081 }
3082
3083 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
3084 {
3085 static const struct phy_reg phy_reg_init[] = {
3086 { 0x1f, 0x0002 },
3087 { 0x01, 0x90d0 },
3088 { 0x1f, 0x0000 }
3089 };
3090
3091 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3092 }
3093
3094 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
3095 {
3096 struct pci_dev *pdev = tp->pci_dev;
3097
3098 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
3099 (pdev->subsystem_device != 0xe000))
3100 return;
3101
3102 rtl_writephy(tp, 0x1f, 0x0001);
3103 rtl_writephy(tp, 0x10, 0xf01b);
3104 rtl_writephy(tp, 0x1f, 0x0000);
3105 }
3106
3107 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
3108 {
3109 static const struct phy_reg phy_reg_init[] = {
3110 { 0x1f, 0x0001 },
3111 { 0x04, 0x0000 },
3112 { 0x03, 0x00a1 },
3113 { 0x02, 0x0008 },
3114 { 0x01, 0x0120 },
3115 { 0x00, 0x1000 },
3116 { 0x04, 0x0800 },
3117 { 0x04, 0x9000 },
3118 { 0x03, 0x802f },
3119 { 0x02, 0x4f02 },
3120 { 0x01, 0x0409 },
3121 { 0x00, 0xf099 },
3122 { 0x04, 0x9800 },
3123 { 0x04, 0xa000 },
3124 { 0x03, 0xdf01 },
3125 { 0x02, 0xdf20 },
3126 { 0x01, 0xff95 },
3127 { 0x00, 0xba00 },
3128 { 0x04, 0xa800 },
3129 { 0x04, 0xf000 },
3130 { 0x03, 0xdf01 },
3131 { 0x02, 0xdf20 },
3132 { 0x01, 0x101a },
3133 { 0x00, 0xa0ff },
3134 { 0x04, 0xf800 },
3135 { 0x04, 0x0000 },
3136 { 0x1f, 0x0000 },
3137
3138 { 0x1f, 0x0001 },
3139 { 0x10, 0xf41b },
3140 { 0x14, 0xfb54 },
3141 { 0x18, 0xf5c7 },
3142 { 0x1f, 0x0000 },
3143
3144 { 0x1f, 0x0001 },
3145 { 0x17, 0x0cc0 },
3146 { 0x1f, 0x0000 }
3147 };
3148
3149 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3150
3151 rtl8169scd_hw_phy_config_quirk(tp);
3152 }
3153
3154 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
3155 {
3156 static const struct phy_reg phy_reg_init[] = {
3157 { 0x1f, 0x0001 },
3158 { 0x04, 0x0000 },
3159 { 0x03, 0x00a1 },
3160 { 0x02, 0x0008 },
3161 { 0x01, 0x0120 },
3162 { 0x00, 0x1000 },
3163 { 0x04, 0x0800 },
3164 { 0x04, 0x9000 },
3165 { 0x03, 0x802f },
3166 { 0x02, 0x4f02 },
3167 { 0x01, 0x0409 },
3168 { 0x00, 0xf099 },
3169 { 0x04, 0x9800 },
3170 { 0x04, 0xa000 },
3171 { 0x03, 0xdf01 },
3172 { 0x02, 0xdf20 },
3173 { 0x01, 0xff95 },
3174 { 0x00, 0xba00 },
3175 { 0x04, 0xa800 },
3176 { 0x04, 0xf000 },
3177 { 0x03, 0xdf01 },
3178 { 0x02, 0xdf20 },
3179 { 0x01, 0x101a },
3180 { 0x00, 0xa0ff },
3181 { 0x04, 0xf800 },
3182 { 0x04, 0x0000 },
3183 { 0x1f, 0x0000 },
3184
3185 { 0x1f, 0x0001 },
3186 { 0x0b, 0x8480 },
3187 { 0x1f, 0x0000 },
3188
3189 { 0x1f, 0x0001 },
3190 { 0x18, 0x67c7 },
3191 { 0x04, 0x2000 },
3192 { 0x03, 0x002f },
3193 { 0x02, 0x4360 },
3194 { 0x01, 0x0109 },
3195 { 0x00, 0x3022 },
3196 { 0x04, 0x2800 },
3197 { 0x1f, 0x0000 },
3198
3199 { 0x1f, 0x0001 },
3200 { 0x17, 0x0cc0 },
3201 { 0x1f, 0x0000 }
3202 };
3203
3204 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3205 }
3206
3207 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
3208 {
3209 static const struct phy_reg phy_reg_init[] = {
3210 { 0x10, 0xf41b },
3211 { 0x1f, 0x0000 }
3212 };
3213
3214 rtl_writephy(tp, 0x1f, 0x0001);
3215 rtl_patchphy(tp, 0x16, 1 << 0);
3216
3217 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3218 }
3219
3220 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
3221 {
3222 static const struct phy_reg phy_reg_init[] = {
3223 { 0x1f, 0x0001 },
3224 { 0x10, 0xf41b },
3225 { 0x1f, 0x0000 }
3226 };
3227
3228 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3229 }
3230
3231 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
3232 {
3233 static const struct phy_reg phy_reg_init[] = {
3234 { 0x1f, 0x0000 },
3235 { 0x1d, 0x0f00 },
3236 { 0x1f, 0x0002 },
3237 { 0x0c, 0x1ec8 },
3238 { 0x1f, 0x0000 }
3239 };
3240
3241 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3242 }
3243
3244 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
3245 {
3246 static const struct phy_reg phy_reg_init[] = {
3247 { 0x1f, 0x0001 },
3248 { 0x1d, 0x3d98 },
3249 { 0x1f, 0x0000 }
3250 };
3251
3252 rtl_writephy(tp, 0x1f, 0x0000);
3253 rtl_patchphy(tp, 0x14, 1 << 5);
3254 rtl_patchphy(tp, 0x0d, 1 << 5);
3255
3256 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3257 }
3258
3259 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
3260 {
3261 static const struct phy_reg phy_reg_init[] = {
3262 { 0x1f, 0x0001 },
3263 { 0x12, 0x2300 },
3264 { 0x1f, 0x0002 },
3265 { 0x00, 0x88d4 },
3266 { 0x01, 0x82b1 },
3267 { 0x03, 0x7002 },
3268 { 0x08, 0x9e30 },
3269 { 0x09, 0x01f0 },
3270 { 0x0a, 0x5500 },
3271 { 0x0c, 0x00c8 },
3272 { 0x1f, 0x0003 },
3273 { 0x12, 0xc096 },
3274 { 0x16, 0x000a },
3275 { 0x1f, 0x0000 },
3276 { 0x1f, 0x0000 },
3277 { 0x09, 0x2000 },
3278 { 0x09, 0x0000 }
3279 };
3280
3281 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3282
3283 rtl_patchphy(tp, 0x14, 1 << 5);
3284 rtl_patchphy(tp, 0x0d, 1 << 5);
3285 rtl_writephy(tp, 0x1f, 0x0000);
3286 }
3287
3288 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
3289 {
3290 static const struct phy_reg phy_reg_init[] = {
3291 { 0x1f, 0x0001 },
3292 { 0x12, 0x2300 },
3293 { 0x03, 0x802f },
3294 { 0x02, 0x4f02 },
3295 { 0x01, 0x0409 },
3296 { 0x00, 0xf099 },
3297 { 0x04, 0x9800 },
3298 { 0x04, 0x9000 },
3299 { 0x1d, 0x3d98 },
3300 { 0x1f, 0x0002 },
3301 { 0x0c, 0x7eb8 },
3302 { 0x06, 0x0761 },
3303 { 0x1f, 0x0003 },
3304 { 0x16, 0x0f0a },
3305 { 0x1f, 0x0000 }
3306 };
3307
3308 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3309
3310 rtl_patchphy(tp, 0x16, 1 << 0);
3311 rtl_patchphy(tp, 0x14, 1 << 5);
3312 rtl_patchphy(tp, 0x0d, 1 << 5);
3313 rtl_writephy(tp, 0x1f, 0x0000);
3314 }
3315
3316 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
3317 {
3318 static const struct phy_reg phy_reg_init[] = {
3319 { 0x1f, 0x0001 },
3320 { 0x12, 0x2300 },
3321 { 0x1d, 0x3d98 },
3322 { 0x1f, 0x0002 },
3323 { 0x0c, 0x7eb8 },
3324 { 0x06, 0x5461 },
3325 { 0x1f, 0x0003 },
3326 { 0x16, 0x0f0a },
3327 { 0x1f, 0x0000 }
3328 };
3329
3330 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3331
3332 rtl_patchphy(tp, 0x16, 1 << 0);
3333 rtl_patchphy(tp, 0x14, 1 << 5);
3334 rtl_patchphy(tp, 0x0d, 1 << 5);
3335 rtl_writephy(tp, 0x1f, 0x0000);
3336 }
3337
3338 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
3339 {
3340 rtl8168c_3_hw_phy_config(tp);
3341 }
3342
3343 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
3344 {
3345 static const struct phy_reg phy_reg_init_0[] = {
3346 /* Channel Estimation */
3347 { 0x1f, 0x0001 },
3348 { 0x06, 0x4064 },
3349 { 0x07, 0x2863 },
3350 { 0x08, 0x059c },
3351 { 0x09, 0x26b4 },
3352 { 0x0a, 0x6a19 },
3353 { 0x0b, 0xdcc8 },
3354 { 0x10, 0xf06d },
3355 { 0x14, 0x7f68 },
3356 { 0x18, 0x7fd9 },
3357 { 0x1c, 0xf0ff },
3358 { 0x1d, 0x3d9c },
3359 { 0x1f, 0x0003 },
3360 { 0x12, 0xf49f },
3361 { 0x13, 0x070b },
3362 { 0x1a, 0x05ad },
3363 { 0x14, 0x94c0 },
3364
3365 /*
3366 * Tx Error Issue
3367 * Enhance line driver power
3368 */
3369 { 0x1f, 0x0002 },
3370 { 0x06, 0x5561 },
3371 { 0x1f, 0x0005 },
3372 { 0x05, 0x8332 },
3373 { 0x06, 0x5561 },
3374
3375 /*
3376 * Can not link to 1Gbps with bad cable
3377 * Decrease SNR threshold form 21.07dB to 19.04dB
3378 */
3379 { 0x1f, 0x0001 },
3380 { 0x17, 0x0cc0 },
3381
3382 { 0x1f, 0x0000 },
3383 { 0x0d, 0xf880 }
3384 };
3385
3386 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3387
3388 /*
3389 * Rx Error Issue
3390 * Fine Tune Switching regulator parameter
3391 */
3392 rtl_writephy(tp, 0x1f, 0x0002);
3393 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
3394 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
3395
3396 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3397 static const struct phy_reg phy_reg_init[] = {
3398 { 0x1f, 0x0002 },
3399 { 0x05, 0x669a },
3400 { 0x1f, 0x0005 },
3401 { 0x05, 0x8330 },
3402 { 0x06, 0x669a },
3403 { 0x1f, 0x0002 }
3404 };
3405 int val;
3406
3407 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3408
3409 val = rtl_readphy(tp, 0x0d);
3410
3411 if ((val & 0x00ff) != 0x006c) {
3412 static const u32 set[] = {
3413 0x0065, 0x0066, 0x0067, 0x0068,
3414 0x0069, 0x006a, 0x006b, 0x006c
3415 };
3416 int i;
3417
3418 rtl_writephy(tp, 0x1f, 0x0002);
3419
3420 val &= 0xff00;
3421 for (i = 0; i < ARRAY_SIZE(set); i++)
3422 rtl_writephy(tp, 0x0d, val | set[i]);
3423 }
3424 } else {
3425 static const struct phy_reg phy_reg_init[] = {
3426 { 0x1f, 0x0002 },
3427 { 0x05, 0x6662 },
3428 { 0x1f, 0x0005 },
3429 { 0x05, 0x8330 },
3430 { 0x06, 0x6662 }
3431 };
3432
3433 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3434 }
3435
3436 /* RSET couple improve */
3437 rtl_writephy(tp, 0x1f, 0x0002);
3438 rtl_patchphy(tp, 0x0d, 0x0300);
3439 rtl_patchphy(tp, 0x0f, 0x0010);
3440
3441 /* Fine tune PLL performance */
3442 rtl_writephy(tp, 0x1f, 0x0002);
3443 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3444 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3445
3446 rtl_writephy(tp, 0x1f, 0x0005);
3447 rtl_writephy(tp, 0x05, 0x001b);
3448
3449 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
3450
3451 rtl_writephy(tp, 0x1f, 0x0000);
3452 }
3453
3454 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
3455 {
3456 static const struct phy_reg phy_reg_init_0[] = {
3457 /* Channel Estimation */
3458 { 0x1f, 0x0001 },
3459 { 0x06, 0x4064 },
3460 { 0x07, 0x2863 },
3461 { 0x08, 0x059c },
3462 { 0x09, 0x26b4 },
3463 { 0x0a, 0x6a19 },
3464 { 0x0b, 0xdcc8 },
3465 { 0x10, 0xf06d },
3466 { 0x14, 0x7f68 },
3467 { 0x18, 0x7fd9 },
3468 { 0x1c, 0xf0ff },
3469 { 0x1d, 0x3d9c },
3470 { 0x1f, 0x0003 },
3471 { 0x12, 0xf49f },
3472 { 0x13, 0x070b },
3473 { 0x1a, 0x05ad },
3474 { 0x14, 0x94c0 },
3475
3476 /*
3477 * Tx Error Issue
3478 * Enhance line driver power
3479 */
3480 { 0x1f, 0x0002 },
3481 { 0x06, 0x5561 },
3482 { 0x1f, 0x0005 },
3483 { 0x05, 0x8332 },
3484 { 0x06, 0x5561 },
3485
3486 /*
3487 * Can not link to 1Gbps with bad cable
3488 * Decrease SNR threshold form 21.07dB to 19.04dB
3489 */
3490 { 0x1f, 0x0001 },
3491 { 0x17, 0x0cc0 },
3492
3493 { 0x1f, 0x0000 },
3494 { 0x0d, 0xf880 }
3495 };
3496
3497 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3498
3499 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3500 static const struct phy_reg phy_reg_init[] = {
3501 { 0x1f, 0x0002 },
3502 { 0x05, 0x669a },
3503 { 0x1f, 0x0005 },
3504 { 0x05, 0x8330 },
3505 { 0x06, 0x669a },
3506
3507 { 0x1f, 0x0002 }
3508 };
3509 int val;
3510
3511 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3512
3513 val = rtl_readphy(tp, 0x0d);
3514 if ((val & 0x00ff) != 0x006c) {
3515 static const u32 set[] = {
3516 0x0065, 0x0066, 0x0067, 0x0068,
3517 0x0069, 0x006a, 0x006b, 0x006c
3518 };
3519 int i;
3520
3521 rtl_writephy(tp, 0x1f, 0x0002);
3522
3523 val &= 0xff00;
3524 for (i = 0; i < ARRAY_SIZE(set); i++)
3525 rtl_writephy(tp, 0x0d, val | set[i]);
3526 }
3527 } else {
3528 static const struct phy_reg phy_reg_init[] = {
3529 { 0x1f, 0x0002 },
3530 { 0x05, 0x2642 },
3531 { 0x1f, 0x0005 },
3532 { 0x05, 0x8330 },
3533 { 0x06, 0x2642 }
3534 };
3535
3536 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3537 }
3538
3539 /* Fine tune PLL performance */
3540 rtl_writephy(tp, 0x1f, 0x0002);
3541 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3542 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3543
3544 /* Switching regulator Slew rate */
3545 rtl_writephy(tp, 0x1f, 0x0002);
3546 rtl_patchphy(tp, 0x0f, 0x0017);
3547
3548 rtl_writephy(tp, 0x1f, 0x0005);
3549 rtl_writephy(tp, 0x05, 0x001b);
3550
3551 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
3552
3553 rtl_writephy(tp, 0x1f, 0x0000);
3554 }
3555
3556 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
3557 {
3558 static const struct phy_reg phy_reg_init[] = {
3559 { 0x1f, 0x0002 },
3560 { 0x10, 0x0008 },
3561 { 0x0d, 0x006c },
3562
3563 { 0x1f, 0x0000 },
3564 { 0x0d, 0xf880 },
3565
3566 { 0x1f, 0x0001 },
3567 { 0x17, 0x0cc0 },
3568
3569 { 0x1f, 0x0001 },
3570 { 0x0b, 0xa4d8 },
3571 { 0x09, 0x281c },
3572 { 0x07, 0x2883 },
3573 { 0x0a, 0x6b35 },
3574 { 0x1d, 0x3da4 },
3575 { 0x1c, 0xeffd },
3576 { 0x14, 0x7f52 },
3577 { 0x18, 0x7fc6 },
3578 { 0x08, 0x0601 },
3579 { 0x06, 0x4063 },
3580 { 0x10, 0xf074 },
3581 { 0x1f, 0x0003 },
3582 { 0x13, 0x0789 },
3583 { 0x12, 0xf4bd },
3584 { 0x1a, 0x04fd },
3585 { 0x14, 0x84b0 },
3586 { 0x1f, 0x0000 },
3587 { 0x00, 0x9200 },
3588
3589 { 0x1f, 0x0005 },
3590 { 0x01, 0x0340 },
3591 { 0x1f, 0x0001 },
3592 { 0x04, 0x4000 },
3593 { 0x03, 0x1d21 },
3594 { 0x02, 0x0c32 },
3595 { 0x01, 0x0200 },
3596 { 0x00, 0x5554 },
3597 { 0x04, 0x4800 },
3598 { 0x04, 0x4000 },
3599 { 0x04, 0xf000 },
3600 { 0x03, 0xdf01 },
3601 { 0x02, 0xdf20 },
3602 { 0x01, 0x101a },
3603 { 0x00, 0xa0ff },
3604 { 0x04, 0xf800 },
3605 { 0x04, 0xf000 },
3606 { 0x1f, 0x0000 },
3607
3608 { 0x1f, 0x0007 },
3609 { 0x1e, 0x0023 },
3610 { 0x16, 0x0000 },
3611 { 0x1f, 0x0000 }
3612 };
3613
3614 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3615 }
3616
3617 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3618 {
3619 static const struct phy_reg phy_reg_init[] = {
3620 { 0x1f, 0x0001 },
3621 { 0x17, 0x0cc0 },
3622
3623 { 0x1f, 0x0007 },
3624 { 0x1e, 0x002d },
3625 { 0x18, 0x0040 },
3626 { 0x1f, 0x0000 }
3627 };
3628
3629 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3630 rtl_patchphy(tp, 0x0d, 1 << 5);
3631 }
3632
3633 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3634 {
3635 static const struct phy_reg phy_reg_init[] = {
3636 /* Enable Delay cap */
3637 { 0x1f, 0x0005 },
3638 { 0x05, 0x8b80 },
3639 { 0x06, 0xc896 },
3640 { 0x1f, 0x0000 },
3641
3642 /* Channel estimation fine tune */
3643 { 0x1f, 0x0001 },
3644 { 0x0b, 0x6c20 },
3645 { 0x07, 0x2872 },
3646 { 0x1c, 0xefff },
3647 { 0x1f, 0x0003 },
3648 { 0x14, 0x6420 },
3649 { 0x1f, 0x0000 },
3650
3651 /* Update PFM & 10M TX idle timer */
3652 { 0x1f, 0x0007 },
3653 { 0x1e, 0x002f },
3654 { 0x15, 0x1919 },
3655 { 0x1f, 0x0000 },
3656
3657 { 0x1f, 0x0007 },
3658 { 0x1e, 0x00ac },
3659 { 0x18, 0x0006 },
3660 { 0x1f, 0x0000 }
3661 };
3662
3663 rtl_apply_firmware(tp);
3664
3665 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3666
3667 /* DCO enable for 10M IDLE Power */
3668 rtl_writephy(tp, 0x1f, 0x0007);
3669 rtl_writephy(tp, 0x1e, 0x0023);
3670 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3671 rtl_writephy(tp, 0x1f, 0x0000);
3672
3673 /* For impedance matching */
3674 rtl_writephy(tp, 0x1f, 0x0002);
3675 rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3676 rtl_writephy(tp, 0x1f, 0x0000);
3677
3678 /* PHY auto speed down */
3679 rtl_writephy(tp, 0x1f, 0x0007);
3680 rtl_writephy(tp, 0x1e, 0x002d);
3681 rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3682 rtl_writephy(tp, 0x1f, 0x0000);
3683 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3684
3685 rtl_writephy(tp, 0x1f, 0x0005);
3686 rtl_writephy(tp, 0x05, 0x8b86);
3687 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3688 rtl_writephy(tp, 0x1f, 0x0000);
3689
3690 rtl_writephy(tp, 0x1f, 0x0005);
3691 rtl_writephy(tp, 0x05, 0x8b85);
3692 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3693 rtl_writephy(tp, 0x1f, 0x0007);
3694 rtl_writephy(tp, 0x1e, 0x0020);
3695 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3696 rtl_writephy(tp, 0x1f, 0x0006);
3697 rtl_writephy(tp, 0x00, 0x5a00);
3698 rtl_writephy(tp, 0x1f, 0x0000);
3699 rtl_writephy(tp, 0x0d, 0x0007);
3700 rtl_writephy(tp, 0x0e, 0x003c);
3701 rtl_writephy(tp, 0x0d, 0x4007);
3702 rtl_writephy(tp, 0x0e, 0x0000);
3703 rtl_writephy(tp, 0x0d, 0x0000);
3704 }
3705
3706 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3707 {
3708 const u16 w[] = {
3709 addr[0] | (addr[1] << 8),
3710 addr[2] | (addr[3] << 8),
3711 addr[4] | (addr[5] << 8)
3712 };
3713 const struct exgmac_reg e[] = {
3714 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3715 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3716 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3717 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3718 };
3719
3720 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3721 }
3722
3723 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3724 {
3725 static const struct phy_reg phy_reg_init[] = {
3726 /* Enable Delay cap */
3727 { 0x1f, 0x0004 },
3728 { 0x1f, 0x0007 },
3729 { 0x1e, 0x00ac },
3730 { 0x18, 0x0006 },
3731 { 0x1f, 0x0002 },
3732 { 0x1f, 0x0000 },
3733 { 0x1f, 0x0000 },
3734
3735 /* Channel estimation fine tune */
3736 { 0x1f, 0x0003 },
3737 { 0x09, 0xa20f },
3738 { 0x1f, 0x0000 },
3739 { 0x1f, 0x0000 },
3740
3741 /* Green Setting */
3742 { 0x1f, 0x0005 },
3743 { 0x05, 0x8b5b },
3744 { 0x06, 0x9222 },
3745 { 0x05, 0x8b6d },
3746 { 0x06, 0x8000 },
3747 { 0x05, 0x8b76 },
3748 { 0x06, 0x8000 },
3749 { 0x1f, 0x0000 }
3750 };
3751
3752 rtl_apply_firmware(tp);
3753
3754 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3755
3756 /* For 4-corner performance improve */
3757 rtl_writephy(tp, 0x1f, 0x0005);
3758 rtl_writephy(tp, 0x05, 0x8b80);
3759 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3760 rtl_writephy(tp, 0x1f, 0x0000);
3761
3762 /* PHY auto speed down */
3763 rtl_writephy(tp, 0x1f, 0x0004);
3764 rtl_writephy(tp, 0x1f, 0x0007);
3765 rtl_writephy(tp, 0x1e, 0x002d);
3766 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3767 rtl_writephy(tp, 0x1f, 0x0002);
3768 rtl_writephy(tp, 0x1f, 0x0000);
3769 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3770
3771 /* improve 10M EEE waveform */
3772 rtl_writephy(tp, 0x1f, 0x0005);
3773 rtl_writephy(tp, 0x05, 0x8b86);
3774 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3775 rtl_writephy(tp, 0x1f, 0x0000);
3776
3777 /* Improve 2-pair detection performance */
3778 rtl_writephy(tp, 0x1f, 0x0005);
3779 rtl_writephy(tp, 0x05, 0x8b85);
3780 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3781 rtl_writephy(tp, 0x1f, 0x0000);
3782
3783 /* EEE setting */
3784 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0003, 0x0000, ERIAR_EXGMAC);
3785 rtl_writephy(tp, 0x1f, 0x0005);
3786 rtl_writephy(tp, 0x05, 0x8b85);
3787 rtl_w0w1_phy(tp, 0x06, 0x2000, 0x0000);
3788 rtl_writephy(tp, 0x1f, 0x0004);
3789 rtl_writephy(tp, 0x1f, 0x0007);
3790 rtl_writephy(tp, 0x1e, 0x0020);
3791 rtl_w0w1_phy(tp, 0x15, 0x0100, 0x0000);
3792 rtl_writephy(tp, 0x1f, 0x0002);
3793 rtl_writephy(tp, 0x1f, 0x0000);
3794 rtl_writephy(tp, 0x0d, 0x0007);
3795 rtl_writephy(tp, 0x0e, 0x003c);
3796 rtl_writephy(tp, 0x0d, 0x4007);
3797 rtl_writephy(tp, 0x0e, 0x0006);
3798 rtl_writephy(tp, 0x0d, 0x0000);
3799
3800 /* Green feature */
3801 rtl_writephy(tp, 0x1f, 0x0003);
3802 rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3803 rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
3804 rtl_writephy(tp, 0x1f, 0x0000);
3805 rtl_writephy(tp, 0x1f, 0x0005);
3806 rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3807 rtl_writephy(tp, 0x1f, 0x0000);
3808 /* soft-reset phy */
3809 rtl_writephy(tp, MII_BMCR, BMCR_RESET | BMCR_ANENABLE | BMCR_ANRESTART);
3810
3811 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3812 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3813 }
3814
3815 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3816 {
3817 /* For 4-corner performance improve */
3818 rtl_writephy(tp, 0x1f, 0x0005);
3819 rtl_writephy(tp, 0x05, 0x8b80);
3820 rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3821 rtl_writephy(tp, 0x1f, 0x0000);
3822
3823 /* PHY auto speed down */
3824 rtl_writephy(tp, 0x1f, 0x0007);
3825 rtl_writephy(tp, 0x1e, 0x002d);
3826 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3827 rtl_writephy(tp, 0x1f, 0x0000);
3828 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3829
3830 /* Improve 10M EEE waveform */
3831 rtl_writephy(tp, 0x1f, 0x0005);
3832 rtl_writephy(tp, 0x05, 0x8b86);
3833 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3834 rtl_writephy(tp, 0x1f, 0x0000);
3835 }
3836
3837 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3838 {
3839 static const struct phy_reg phy_reg_init[] = {
3840 /* Channel estimation fine tune */
3841 { 0x1f, 0x0003 },
3842 { 0x09, 0xa20f },
3843 { 0x1f, 0x0000 },
3844
3845 /* Modify green table for giga & fnet */
3846 { 0x1f, 0x0005 },
3847 { 0x05, 0x8b55 },
3848 { 0x06, 0x0000 },
3849 { 0x05, 0x8b5e },
3850 { 0x06, 0x0000 },
3851 { 0x05, 0x8b67 },
3852 { 0x06, 0x0000 },
3853 { 0x05, 0x8b70 },
3854 { 0x06, 0x0000 },
3855 { 0x1f, 0x0000 },
3856 { 0x1f, 0x0007 },
3857 { 0x1e, 0x0078 },
3858 { 0x17, 0x0000 },
3859 { 0x19, 0x00fb },
3860 { 0x1f, 0x0000 },
3861
3862 /* Modify green table for 10M */
3863 { 0x1f, 0x0005 },
3864 { 0x05, 0x8b79 },
3865 { 0x06, 0xaa00 },
3866 { 0x1f, 0x0000 },
3867
3868 /* Disable hiimpedance detection (RTCT) */
3869 { 0x1f, 0x0003 },
3870 { 0x01, 0x328a },
3871 { 0x1f, 0x0000 }
3872 };
3873
3874 rtl_apply_firmware(tp);
3875
3876 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3877
3878 rtl8168f_hw_phy_config(tp);
3879
3880 /* Improve 2-pair detection performance */
3881 rtl_writephy(tp, 0x1f, 0x0005);
3882 rtl_writephy(tp, 0x05, 0x8b85);
3883 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3884 rtl_writephy(tp, 0x1f, 0x0000);
3885 }
3886
3887 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3888 {
3889 rtl_apply_firmware(tp);
3890
3891 rtl8168f_hw_phy_config(tp);
3892 }
3893
3894 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3895 {
3896 static const struct phy_reg phy_reg_init[] = {
3897 /* Channel estimation fine tune */
3898 { 0x1f, 0x0003 },
3899 { 0x09, 0xa20f },
3900 { 0x1f, 0x0000 },
3901
3902 /* Modify green table for giga & fnet */
3903 { 0x1f, 0x0005 },
3904 { 0x05, 0x8b55 },
3905 { 0x06, 0x0000 },
3906 { 0x05, 0x8b5e },
3907 { 0x06, 0x0000 },
3908 { 0x05, 0x8b67 },
3909 { 0x06, 0x0000 },
3910 { 0x05, 0x8b70 },
3911 { 0x06, 0x0000 },
3912 { 0x1f, 0x0000 },
3913 { 0x1f, 0x0007 },
3914 { 0x1e, 0x0078 },
3915 { 0x17, 0x0000 },
3916 { 0x19, 0x00aa },
3917 { 0x1f, 0x0000 },
3918
3919 /* Modify green table for 10M */
3920 { 0x1f, 0x0005 },
3921 { 0x05, 0x8b79 },
3922 { 0x06, 0xaa00 },
3923 { 0x1f, 0x0000 },
3924
3925 /* Disable hiimpedance detection (RTCT) */
3926 { 0x1f, 0x0003 },
3927 { 0x01, 0x328a },
3928 { 0x1f, 0x0000 }
3929 };
3930
3931
3932 rtl_apply_firmware(tp);
3933
3934 rtl8168f_hw_phy_config(tp);
3935
3936 /* Improve 2-pair detection performance */
3937 rtl_writephy(tp, 0x1f, 0x0005);
3938 rtl_writephy(tp, 0x05, 0x8b85);
3939 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3940 rtl_writephy(tp, 0x1f, 0x0000);
3941
3942 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3943
3944 /* Modify green table for giga */
3945 rtl_writephy(tp, 0x1f, 0x0005);
3946 rtl_writephy(tp, 0x05, 0x8b54);
3947 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3948 rtl_writephy(tp, 0x05, 0x8b5d);
3949 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3950 rtl_writephy(tp, 0x05, 0x8a7c);
3951 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3952 rtl_writephy(tp, 0x05, 0x8a7f);
3953 rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3954 rtl_writephy(tp, 0x05, 0x8a82);
3955 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3956 rtl_writephy(tp, 0x05, 0x8a85);
3957 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3958 rtl_writephy(tp, 0x05, 0x8a88);
3959 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3960 rtl_writephy(tp, 0x1f, 0x0000);
3961
3962 /* uc same-seed solution */
3963 rtl_writephy(tp, 0x1f, 0x0005);
3964 rtl_writephy(tp, 0x05, 0x8b85);
3965 rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3966 rtl_writephy(tp, 0x1f, 0x0000);
3967
3968 /* eee setting */
3969 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3970 rtl_writephy(tp, 0x1f, 0x0005);
3971 rtl_writephy(tp, 0x05, 0x8b85);
3972 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3973 rtl_writephy(tp, 0x1f, 0x0004);
3974 rtl_writephy(tp, 0x1f, 0x0007);
3975 rtl_writephy(tp, 0x1e, 0x0020);
3976 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3977 rtl_writephy(tp, 0x1f, 0x0000);
3978 rtl_writephy(tp, 0x0d, 0x0007);
3979 rtl_writephy(tp, 0x0e, 0x003c);
3980 rtl_writephy(tp, 0x0d, 0x4007);
3981 rtl_writephy(tp, 0x0e, 0x0000);
3982 rtl_writephy(tp, 0x0d, 0x0000);
3983
3984 /* Green feature */
3985 rtl_writephy(tp, 0x1f, 0x0003);
3986 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3987 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3988 rtl_writephy(tp, 0x1f, 0x0000);
3989 }
3990
3991 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3992 {
3993 rtl_apply_firmware(tp);
3994
3995 rtl_writephy(tp, 0x1f, 0x0a46);
3996 if (rtl_readphy(tp, 0x10) & 0x0100) {
3997 rtl_writephy(tp, 0x1f, 0x0bcc);
3998 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
3999 } else {
4000 rtl_writephy(tp, 0x1f, 0x0bcc);
4001 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
4002 }
4003
4004 rtl_writephy(tp, 0x1f, 0x0a46);
4005 if (rtl_readphy(tp, 0x13) & 0x0100) {
4006 rtl_writephy(tp, 0x1f, 0x0c41);
4007 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
4008 } else {
4009 rtl_writephy(tp, 0x1f, 0x0c41);
4010 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
4011 }
4012
4013 /* Enable PHY auto speed down */
4014 rtl_writephy(tp, 0x1f, 0x0a44);
4015 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
4016
4017 rtl_writephy(tp, 0x1f, 0x0bcc);
4018 rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
4019 rtl_writephy(tp, 0x1f, 0x0a44);
4020 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
4021 rtl_writephy(tp, 0x1f, 0x0a43);
4022 rtl_writephy(tp, 0x13, 0x8084);
4023 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
4024 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
4025
4026 /* EEE auto-fallback function */
4027 rtl_writephy(tp, 0x1f, 0x0a4b);
4028 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
4029
4030 /* Enable UC LPF tune function */
4031 rtl_writephy(tp, 0x1f, 0x0a43);
4032 rtl_writephy(tp, 0x13, 0x8012);
4033 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
4034
4035 rtl_writephy(tp, 0x1f, 0x0c42);
4036 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
4037
4038 /* Improve SWR Efficiency */
4039 rtl_writephy(tp, 0x1f, 0x0bcd);
4040 rtl_writephy(tp, 0x14, 0x5065);
4041 rtl_writephy(tp, 0x14, 0xd065);
4042 rtl_writephy(tp, 0x1f, 0x0bc8);
4043 rtl_writephy(tp, 0x11, 0x5655);
4044 rtl_writephy(tp, 0x1f, 0x0bcd);
4045 rtl_writephy(tp, 0x14, 0x1065);
4046 rtl_writephy(tp, 0x14, 0x9065);
4047 rtl_writephy(tp, 0x14, 0x1065);
4048
4049 /* Check ALDPS bit, disable it if enabled */
4050 rtl_writephy(tp, 0x1f, 0x0a43);
4051 if (rtl_readphy(tp, 0x10) & 0x0004)
4052 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4053
4054 rtl_writephy(tp, 0x1f, 0x0000);
4055 }
4056
4057 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
4058 {
4059 rtl_apply_firmware(tp);
4060 }
4061
4062 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
4063 {
4064 u16 dout_tapbin;
4065 u32 data;
4066
4067 rtl_apply_firmware(tp);
4068
4069 /* CHN EST parameters adjust - giga master */
4070 rtl_writephy(tp, 0x1f, 0x0a43);
4071 rtl_writephy(tp, 0x13, 0x809b);
4072 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
4073 rtl_writephy(tp, 0x13, 0x80a2);
4074 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
4075 rtl_writephy(tp, 0x13, 0x80a4);
4076 rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
4077 rtl_writephy(tp, 0x13, 0x809c);
4078 rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
4079 rtl_writephy(tp, 0x1f, 0x0000);
4080
4081 /* CHN EST parameters adjust - giga slave */
4082 rtl_writephy(tp, 0x1f, 0x0a43);
4083 rtl_writephy(tp, 0x13, 0x80ad);
4084 rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
4085 rtl_writephy(tp, 0x13, 0x80b4);
4086 rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
4087 rtl_writephy(tp, 0x13, 0x80ac);
4088 rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
4089 rtl_writephy(tp, 0x1f, 0x0000);
4090
4091 /* CHN EST parameters adjust - fnet */
4092 rtl_writephy(tp, 0x1f, 0x0a43);
4093 rtl_writephy(tp, 0x13, 0x808e);
4094 rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
4095 rtl_writephy(tp, 0x13, 0x8090);
4096 rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
4097 rtl_writephy(tp, 0x13, 0x8092);
4098 rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
4099 rtl_writephy(tp, 0x1f, 0x0000);
4100
4101 /* enable R-tune & PGA-retune function */
4102 dout_tapbin = 0;
4103 rtl_writephy(tp, 0x1f, 0x0a46);
4104 data = rtl_readphy(tp, 0x13);
4105 data &= 3;
4106 data <<= 2;
4107 dout_tapbin |= data;
4108 data = rtl_readphy(tp, 0x12);
4109 data &= 0xc000;
4110 data >>= 14;
4111 dout_tapbin |= data;
4112 dout_tapbin = ~(dout_tapbin^0x08);
4113 dout_tapbin <<= 12;
4114 dout_tapbin &= 0xf000;
4115 rtl_writephy(tp, 0x1f, 0x0a43);
4116 rtl_writephy(tp, 0x13, 0x827a);
4117 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
4118 rtl_writephy(tp, 0x13, 0x827b);
4119 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
4120 rtl_writephy(tp, 0x13, 0x827c);
4121 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
4122 rtl_writephy(tp, 0x13, 0x827d);
4123 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
4124
4125 rtl_writephy(tp, 0x1f, 0x0a43);
4126 rtl_writephy(tp, 0x13, 0x0811);
4127 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
4128 rtl_writephy(tp, 0x1f, 0x0a42);
4129 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
4130 rtl_writephy(tp, 0x1f, 0x0000);
4131
4132 /* enable GPHY 10M */
4133 rtl_writephy(tp, 0x1f, 0x0a44);
4134 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
4135 rtl_writephy(tp, 0x1f, 0x0000);
4136
4137 /* SAR ADC performance */
4138 rtl_writephy(tp, 0x1f, 0x0bca);
4139 rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
4140 rtl_writephy(tp, 0x1f, 0x0000);
4141
4142 rtl_writephy(tp, 0x1f, 0x0a43);
4143 rtl_writephy(tp, 0x13, 0x803f);
4144 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
4145 rtl_writephy(tp, 0x13, 0x8047);
4146 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
4147 rtl_writephy(tp, 0x13, 0x804f);
4148 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
4149 rtl_writephy(tp, 0x13, 0x8057);
4150 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
4151 rtl_writephy(tp, 0x13, 0x805f);
4152 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
4153 rtl_writephy(tp, 0x13, 0x8067);
4154 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
4155 rtl_writephy(tp, 0x13, 0x806f);
4156 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
4157 rtl_writephy(tp, 0x1f, 0x0000);
4158
4159 /* disable phy pfm mode */
4160 rtl_writephy(tp, 0x1f, 0x0a44);
4161 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
4162 rtl_writephy(tp, 0x1f, 0x0000);
4163
4164 /* Check ALDPS bit, disable it if enabled */
4165 rtl_writephy(tp, 0x1f, 0x0a43);
4166 if (rtl_readphy(tp, 0x10) & 0x0004)
4167 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4168
4169 rtl_writephy(tp, 0x1f, 0x0000);
4170 }
4171
4172 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
4173 {
4174 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
4175 u16 rlen;
4176 u32 data;
4177
4178 rtl_apply_firmware(tp);
4179
4180 /* CHIN EST parameter update */
4181 rtl_writephy(tp, 0x1f, 0x0a43);
4182 rtl_writephy(tp, 0x13, 0x808a);
4183 rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
4184 rtl_writephy(tp, 0x1f, 0x0000);
4185
4186 /* enable R-tune & PGA-retune function */
4187 rtl_writephy(tp, 0x1f, 0x0a43);
4188 rtl_writephy(tp, 0x13, 0x0811);
4189 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
4190 rtl_writephy(tp, 0x1f, 0x0a42);
4191 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
4192 rtl_writephy(tp, 0x1f, 0x0000);
4193
4194 /* enable GPHY 10M */
4195 rtl_writephy(tp, 0x1f, 0x0a44);
4196 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
4197 rtl_writephy(tp, 0x1f, 0x0000);
4198
4199 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
4200 data = r8168_mac_ocp_read(tp, 0xdd02);
4201 ioffset_p3 = ((data & 0x80)>>7);
4202 ioffset_p3 <<= 3;
4203
4204 data = r8168_mac_ocp_read(tp, 0xdd00);
4205 ioffset_p3 |= ((data & (0xe000))>>13);
4206 ioffset_p2 = ((data & (0x1e00))>>9);
4207 ioffset_p1 = ((data & (0x01e0))>>5);
4208 ioffset_p0 = ((data & 0x0010)>>4);
4209 ioffset_p0 <<= 3;
4210 ioffset_p0 |= (data & (0x07));
4211 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
4212
4213 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
4214 (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
4215 rtl_writephy(tp, 0x1f, 0x0bcf);
4216 rtl_writephy(tp, 0x16, data);
4217 rtl_writephy(tp, 0x1f, 0x0000);
4218 }
4219
4220 /* Modify rlen (TX LPF corner frequency) level */
4221 rtl_writephy(tp, 0x1f, 0x0bcd);
4222 data = rtl_readphy(tp, 0x16);
4223 data &= 0x000f;
4224 rlen = 0;
4225 if (data > 3)
4226 rlen = data - 3;
4227 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
4228 rtl_writephy(tp, 0x17, data);
4229 rtl_writephy(tp, 0x1f, 0x0bcd);
4230 rtl_writephy(tp, 0x1f, 0x0000);
4231
4232 /* disable phy pfm mode */
4233 rtl_writephy(tp, 0x1f, 0x0a44);
4234 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
4235 rtl_writephy(tp, 0x1f, 0x0000);
4236
4237 /* Check ALDPS bit, disable it if enabled */
4238 rtl_writephy(tp, 0x1f, 0x0a43);
4239 if (rtl_readphy(tp, 0x10) & 0x0004)
4240 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4241
4242 rtl_writephy(tp, 0x1f, 0x0000);
4243 }
4244
4245 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
4246 {
4247 /* Enable PHY auto speed down */
4248 rtl_writephy(tp, 0x1f, 0x0a44);
4249 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
4250 rtl_writephy(tp, 0x1f, 0x0000);
4251
4252 /* patch 10M & ALDPS */
4253 rtl_writephy(tp, 0x1f, 0x0bcc);
4254 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
4255 rtl_writephy(tp, 0x1f, 0x0a44);
4256 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
4257 rtl_writephy(tp, 0x1f, 0x0a43);
4258 rtl_writephy(tp, 0x13, 0x8084);
4259 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
4260 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
4261 rtl_writephy(tp, 0x1f, 0x0000);
4262
4263 /* Enable EEE auto-fallback function */
4264 rtl_writephy(tp, 0x1f, 0x0a4b);
4265 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
4266 rtl_writephy(tp, 0x1f, 0x0000);
4267
4268 /* Enable UC LPF tune function */
4269 rtl_writephy(tp, 0x1f, 0x0a43);
4270 rtl_writephy(tp, 0x13, 0x8012);
4271 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
4272 rtl_writephy(tp, 0x1f, 0x0000);
4273
4274 /* set rg_sel_sdm_rate */
4275 rtl_writephy(tp, 0x1f, 0x0c42);
4276 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
4277 rtl_writephy(tp, 0x1f, 0x0000);
4278
4279 /* Check ALDPS bit, disable it if enabled */
4280 rtl_writephy(tp, 0x1f, 0x0a43);
4281 if (rtl_readphy(tp, 0x10) & 0x0004)
4282 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4283
4284 rtl_writephy(tp, 0x1f, 0x0000);
4285 }
4286
4287 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
4288 {
4289 /* patch 10M & ALDPS */
4290 rtl_writephy(tp, 0x1f, 0x0bcc);
4291 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
4292 rtl_writephy(tp, 0x1f, 0x0a44);
4293 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
4294 rtl_writephy(tp, 0x1f, 0x0a43);
4295 rtl_writephy(tp, 0x13, 0x8084);
4296 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
4297 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
4298 rtl_writephy(tp, 0x1f, 0x0000);
4299
4300 /* Enable UC LPF tune function */
4301 rtl_writephy(tp, 0x1f, 0x0a43);
4302 rtl_writephy(tp, 0x13, 0x8012);
4303 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
4304 rtl_writephy(tp, 0x1f, 0x0000);
4305
4306 /* Set rg_sel_sdm_rate */
4307 rtl_writephy(tp, 0x1f, 0x0c42);
4308 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
4309 rtl_writephy(tp, 0x1f, 0x0000);
4310
4311 /* Channel estimation parameters */
4312 rtl_writephy(tp, 0x1f, 0x0a43);
4313 rtl_writephy(tp, 0x13, 0x80f3);
4314 rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
4315 rtl_writephy(tp, 0x13, 0x80f0);
4316 rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
4317 rtl_writephy(tp, 0x13, 0x80ef);
4318 rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
4319 rtl_writephy(tp, 0x13, 0x80f6);
4320 rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
4321 rtl_writephy(tp, 0x13, 0x80ec);
4322 rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
4323 rtl_writephy(tp, 0x13, 0x80ed);
4324 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4325 rtl_writephy(tp, 0x13, 0x80f2);
4326 rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
4327 rtl_writephy(tp, 0x13, 0x80f4);
4328 rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
4329 rtl_writephy(tp, 0x1f, 0x0a43);
4330 rtl_writephy(tp, 0x13, 0x8110);
4331 rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
4332 rtl_writephy(tp, 0x13, 0x810f);
4333 rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
4334 rtl_writephy(tp, 0x13, 0x8111);
4335 rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
4336 rtl_writephy(tp, 0x13, 0x8113);
4337 rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
4338 rtl_writephy(tp, 0x13, 0x8115);
4339 rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
4340 rtl_writephy(tp, 0x13, 0x810e);
4341 rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
4342 rtl_writephy(tp, 0x13, 0x810c);
4343 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4344 rtl_writephy(tp, 0x13, 0x810b);
4345 rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
4346 rtl_writephy(tp, 0x1f, 0x0a43);
4347 rtl_writephy(tp, 0x13, 0x80d1);
4348 rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
4349 rtl_writephy(tp, 0x13, 0x80cd);
4350 rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
4351 rtl_writephy(tp, 0x13, 0x80d3);
4352 rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
4353 rtl_writephy(tp, 0x13, 0x80d5);
4354 rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
4355 rtl_writephy(tp, 0x13, 0x80d7);
4356 rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
4357
4358 /* Force PWM-mode */
4359 rtl_writephy(tp, 0x1f, 0x0bcd);
4360 rtl_writephy(tp, 0x14, 0x5065);
4361 rtl_writephy(tp, 0x14, 0xd065);
4362 rtl_writephy(tp, 0x1f, 0x0bc8);
4363 rtl_writephy(tp, 0x12, 0x00ed);
4364 rtl_writephy(tp, 0x1f, 0x0bcd);
4365 rtl_writephy(tp, 0x14, 0x1065);
4366 rtl_writephy(tp, 0x14, 0x9065);
4367 rtl_writephy(tp, 0x14, 0x1065);
4368 rtl_writephy(tp, 0x1f, 0x0000);
4369
4370 /* Check ALDPS bit, disable it if enabled */
4371 rtl_writephy(tp, 0x1f, 0x0a43);
4372 if (rtl_readphy(tp, 0x10) & 0x0004)
4373 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4374
4375 rtl_writephy(tp, 0x1f, 0x0000);
4376 }
4377
4378 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
4379 {
4380 static const struct phy_reg phy_reg_init[] = {
4381 { 0x1f, 0x0003 },
4382 { 0x08, 0x441d },
4383 { 0x01, 0x9100 },
4384 { 0x1f, 0x0000 }
4385 };
4386
4387 rtl_writephy(tp, 0x1f, 0x0000);
4388 rtl_patchphy(tp, 0x11, 1 << 12);
4389 rtl_patchphy(tp, 0x19, 1 << 13);
4390 rtl_patchphy(tp, 0x10, 1 << 15);
4391
4392 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4393 }
4394
4395 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
4396 {
4397 static const struct phy_reg phy_reg_init[] = {
4398 { 0x1f, 0x0005 },
4399 { 0x1a, 0x0000 },
4400 { 0x1f, 0x0000 },
4401
4402 { 0x1f, 0x0004 },
4403 { 0x1c, 0x0000 },
4404 { 0x1f, 0x0000 },
4405
4406 { 0x1f, 0x0001 },
4407 { 0x15, 0x7701 },
4408 { 0x1f, 0x0000 }
4409 };
4410
4411 /* Disable ALDPS before ram code */
4412 rtl_writephy(tp, 0x1f, 0x0000);
4413 rtl_writephy(tp, 0x18, 0x0310);
4414 msleep(100);
4415
4416 rtl_apply_firmware(tp);
4417
4418 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4419 }
4420
4421 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
4422 {
4423 /* Disable ALDPS before setting firmware */
4424 rtl_writephy(tp, 0x1f, 0x0000);
4425 rtl_writephy(tp, 0x18, 0x0310);
4426 msleep(20);
4427
4428 rtl_apply_firmware(tp);
4429
4430 /* EEE setting */
4431 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4432 rtl_writephy(tp, 0x1f, 0x0004);
4433 rtl_writephy(tp, 0x10, 0x401f);
4434 rtl_writephy(tp, 0x19, 0x7030);
4435 rtl_writephy(tp, 0x1f, 0x0000);
4436 }
4437
4438 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
4439 {
4440 static const struct phy_reg phy_reg_init[] = {
4441 { 0x1f, 0x0004 },
4442 { 0x10, 0xc07f },
4443 { 0x19, 0x7030 },
4444 { 0x1f, 0x0000 }
4445 };
4446
4447 /* Disable ALDPS before ram code */
4448 rtl_writephy(tp, 0x1f, 0x0000);
4449 rtl_writephy(tp, 0x18, 0x0310);
4450 msleep(100);
4451
4452 rtl_apply_firmware(tp);
4453
4454 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4455 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4456
4457 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4458 }
4459
4460 static void rtl_hw_phy_config(struct net_device *dev)
4461 {
4462 struct rtl8169_private *tp = netdev_priv(dev);
4463
4464 rtl8169_print_mac_version(tp);
4465
4466 switch (tp->mac_version) {
4467 case RTL_GIGA_MAC_VER_01:
4468 break;
4469 case RTL_GIGA_MAC_VER_02:
4470 case RTL_GIGA_MAC_VER_03:
4471 rtl8169s_hw_phy_config(tp);
4472 break;
4473 case RTL_GIGA_MAC_VER_04:
4474 rtl8169sb_hw_phy_config(tp);
4475 break;
4476 case RTL_GIGA_MAC_VER_05:
4477 rtl8169scd_hw_phy_config(tp);
4478 break;
4479 case RTL_GIGA_MAC_VER_06:
4480 rtl8169sce_hw_phy_config(tp);
4481 break;
4482 case RTL_GIGA_MAC_VER_07:
4483 case RTL_GIGA_MAC_VER_08:
4484 case RTL_GIGA_MAC_VER_09:
4485 rtl8102e_hw_phy_config(tp);
4486 break;
4487 case RTL_GIGA_MAC_VER_11:
4488 rtl8168bb_hw_phy_config(tp);
4489 break;
4490 case RTL_GIGA_MAC_VER_12:
4491 rtl8168bef_hw_phy_config(tp);
4492 break;
4493 case RTL_GIGA_MAC_VER_17:
4494 rtl8168bef_hw_phy_config(tp);
4495 break;
4496 case RTL_GIGA_MAC_VER_18:
4497 rtl8168cp_1_hw_phy_config(tp);
4498 break;
4499 case RTL_GIGA_MAC_VER_19:
4500 rtl8168c_1_hw_phy_config(tp);
4501 break;
4502 case RTL_GIGA_MAC_VER_20:
4503 rtl8168c_2_hw_phy_config(tp);
4504 break;
4505 case RTL_GIGA_MAC_VER_21:
4506 rtl8168c_3_hw_phy_config(tp);
4507 break;
4508 case RTL_GIGA_MAC_VER_22:
4509 rtl8168c_4_hw_phy_config(tp);
4510 break;
4511 case RTL_GIGA_MAC_VER_23:
4512 case RTL_GIGA_MAC_VER_24:
4513 rtl8168cp_2_hw_phy_config(tp);
4514 break;
4515 case RTL_GIGA_MAC_VER_25:
4516 rtl8168d_1_hw_phy_config(tp);
4517 break;
4518 case RTL_GIGA_MAC_VER_26:
4519 rtl8168d_2_hw_phy_config(tp);
4520 break;
4521 case RTL_GIGA_MAC_VER_27:
4522 rtl8168d_3_hw_phy_config(tp);
4523 break;
4524 case RTL_GIGA_MAC_VER_28:
4525 rtl8168d_4_hw_phy_config(tp);
4526 break;
4527 case RTL_GIGA_MAC_VER_29:
4528 case RTL_GIGA_MAC_VER_30:
4529 rtl8105e_hw_phy_config(tp);
4530 break;
4531 case RTL_GIGA_MAC_VER_31:
4532 /* None. */
4533 break;
4534 case RTL_GIGA_MAC_VER_32:
4535 case RTL_GIGA_MAC_VER_33:
4536 rtl8168e_1_hw_phy_config(tp);
4537 break;
4538 case RTL_GIGA_MAC_VER_34:
4539 rtl8168e_2_hw_phy_config(tp);
4540 break;
4541 case RTL_GIGA_MAC_VER_35:
4542 rtl8168f_1_hw_phy_config(tp);
4543 break;
4544 case RTL_GIGA_MAC_VER_36:
4545 rtl8168f_2_hw_phy_config(tp);
4546 break;
4547
4548 case RTL_GIGA_MAC_VER_37:
4549 rtl8402_hw_phy_config(tp);
4550 break;
4551
4552 case RTL_GIGA_MAC_VER_38:
4553 rtl8411_hw_phy_config(tp);
4554 break;
4555
4556 case RTL_GIGA_MAC_VER_39:
4557 rtl8106e_hw_phy_config(tp);
4558 break;
4559
4560 case RTL_GIGA_MAC_VER_40:
4561 rtl8168g_1_hw_phy_config(tp);
4562 break;
4563 case RTL_GIGA_MAC_VER_42:
4564 case RTL_GIGA_MAC_VER_43:
4565 case RTL_GIGA_MAC_VER_44:
4566 rtl8168g_2_hw_phy_config(tp);
4567 break;
4568 case RTL_GIGA_MAC_VER_45:
4569 case RTL_GIGA_MAC_VER_47:
4570 rtl8168h_1_hw_phy_config(tp);
4571 break;
4572 case RTL_GIGA_MAC_VER_46:
4573 case RTL_GIGA_MAC_VER_48:
4574 rtl8168h_2_hw_phy_config(tp);
4575 break;
4576
4577 case RTL_GIGA_MAC_VER_49:
4578 rtl8168ep_1_hw_phy_config(tp);
4579 break;
4580 case RTL_GIGA_MAC_VER_50:
4581 case RTL_GIGA_MAC_VER_51:
4582 rtl8168ep_2_hw_phy_config(tp);
4583 break;
4584
4585 case RTL_GIGA_MAC_VER_41:
4586 default:
4587 break;
4588 }
4589 }
4590
4591 static void rtl_phy_work(struct rtl8169_private *tp)
4592 {
4593 struct timer_list *timer = &tp->timer;
4594 void __iomem *ioaddr = tp->mmio_addr;
4595 unsigned long timeout = RTL8169_PHY_TIMEOUT;
4596
4597 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
4598
4599 if (tp->phy_reset_pending(tp)) {
4600 /*
4601 * A busy loop could burn quite a few cycles on nowadays CPU.
4602 * Let's delay the execution of the timer for a few ticks.
4603 */
4604 timeout = HZ/10;
4605 goto out_mod_timer;
4606 }
4607
4608 if (tp->link_ok(ioaddr))
4609 return;
4610
4611 netif_dbg(tp, link, tp->dev, "PHY reset until link up\n");
4612
4613 tp->phy_reset_enable(tp);
4614
4615 out_mod_timer:
4616 mod_timer(timer, jiffies + timeout);
4617 }
4618
4619 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4620 {
4621 if (!test_and_set_bit(flag, tp->wk.flags))
4622 schedule_work(&tp->wk.work);
4623 }
4624
4625 static void rtl8169_phy_timer(struct timer_list *t)
4626 {
4627 struct rtl8169_private *tp = from_timer(tp, t, timer);
4628
4629 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
4630 }
4631
4632 DECLARE_RTL_COND(rtl_phy_reset_cond)
4633 {
4634 return tp->phy_reset_pending(tp);
4635 }
4636
4637 static void rtl8169_phy_reset(struct net_device *dev,
4638 struct rtl8169_private *tp)
4639 {
4640 tp->phy_reset_enable(tp);
4641 rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
4642 }
4643
4644 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4645 {
4646 void __iomem *ioaddr = tp->mmio_addr;
4647
4648 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
4649 (RTL_R8(PHYstatus) & TBI_Enable);
4650 }
4651
4652 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4653 {
4654 void __iomem *ioaddr = tp->mmio_addr;
4655
4656 rtl_hw_phy_config(dev);
4657
4658 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4659 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4660 RTL_W8(0x82, 0x01);
4661 }
4662
4663 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4664
4665 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4666 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4667
4668 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4669 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4670 RTL_W8(0x82, 0x01);
4671 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4672 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4673 }
4674
4675 rtl8169_phy_reset(dev, tp);
4676
4677 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4678 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4679 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4680 (tp->mii.supports_gmii ?
4681 ADVERTISED_1000baseT_Half |
4682 ADVERTISED_1000baseT_Full : 0));
4683
4684 if (rtl_tbi_enabled(tp))
4685 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4686 }
4687
4688 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4689 {
4690 void __iomem *ioaddr = tp->mmio_addr;
4691
4692 rtl_lock_work(tp);
4693
4694 RTL_W8(Cfg9346, Cfg9346_Unlock);
4695
4696 RTL_W32(MAC4, addr[4] | addr[5] << 8);
4697 RTL_R32(MAC4);
4698
4699 RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4700 RTL_R32(MAC0);
4701
4702 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4703 rtl_rar_exgmac_set(tp, addr);
4704
4705 RTL_W8(Cfg9346, Cfg9346_Lock);
4706
4707 rtl_unlock_work(tp);
4708 }
4709
4710 static int rtl_set_mac_address(struct net_device *dev, void *p)
4711 {
4712 struct rtl8169_private *tp = netdev_priv(dev);
4713 struct device *d = &tp->pci_dev->dev;
4714 struct sockaddr *addr = p;
4715
4716 if (!is_valid_ether_addr(addr->sa_data))
4717 return -EADDRNOTAVAIL;
4718
4719 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
4720
4721 pm_runtime_get_noresume(d);
4722
4723 if (pm_runtime_active(d))
4724 rtl_rar_set(tp, dev->dev_addr);
4725
4726 pm_runtime_put_noidle(d);
4727
4728 return 0;
4729 }
4730
4731 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4732 {
4733 struct rtl8169_private *tp = netdev_priv(dev);
4734 struct mii_ioctl_data *data = if_mii(ifr);
4735
4736 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
4737 }
4738
4739 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
4740 struct mii_ioctl_data *data, int cmd)
4741 {
4742 switch (cmd) {
4743 case SIOCGMIIPHY:
4744 data->phy_id = 32; /* Internal PHY */
4745 return 0;
4746
4747 case SIOCGMIIREG:
4748 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
4749 return 0;
4750
4751 case SIOCSMIIREG:
4752 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
4753 return 0;
4754 }
4755 return -EOPNOTSUPP;
4756 }
4757
4758 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
4759 {
4760 return -EOPNOTSUPP;
4761 }
4762
4763 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
4764 {
4765 struct mdio_ops *ops = &tp->mdio_ops;
4766
4767 switch (tp->mac_version) {
4768 case RTL_GIGA_MAC_VER_27:
4769 ops->write = r8168dp_1_mdio_write;
4770 ops->read = r8168dp_1_mdio_read;
4771 break;
4772 case RTL_GIGA_MAC_VER_28:
4773 case RTL_GIGA_MAC_VER_31:
4774 ops->write = r8168dp_2_mdio_write;
4775 ops->read = r8168dp_2_mdio_read;
4776 break;
4777 case RTL_GIGA_MAC_VER_40:
4778 case RTL_GIGA_MAC_VER_41:
4779 case RTL_GIGA_MAC_VER_42:
4780 case RTL_GIGA_MAC_VER_43:
4781 case RTL_GIGA_MAC_VER_44:
4782 case RTL_GIGA_MAC_VER_45:
4783 case RTL_GIGA_MAC_VER_46:
4784 case RTL_GIGA_MAC_VER_47:
4785 case RTL_GIGA_MAC_VER_48:
4786 case RTL_GIGA_MAC_VER_49:
4787 case RTL_GIGA_MAC_VER_50:
4788 case RTL_GIGA_MAC_VER_51:
4789 ops->write = r8168g_mdio_write;
4790 ops->read = r8168g_mdio_read;
4791 break;
4792 default:
4793 ops->write = r8169_mdio_write;
4794 ops->read = r8169_mdio_read;
4795 break;
4796 }
4797 }
4798
4799 static void rtl_speed_down(struct rtl8169_private *tp)
4800 {
4801 u32 adv;
4802 int lpa;
4803
4804 rtl_writephy(tp, 0x1f, 0x0000);
4805 lpa = rtl_readphy(tp, MII_LPA);
4806
4807 if (lpa & (LPA_10HALF | LPA_10FULL))
4808 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
4809 else if (lpa & (LPA_100HALF | LPA_100FULL))
4810 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4811 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4812 else
4813 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4814 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4815 (tp->mii.supports_gmii ?
4816 ADVERTISED_1000baseT_Half |
4817 ADVERTISED_1000baseT_Full : 0);
4818
4819 rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4820 adv);
4821 }
4822
4823 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4824 {
4825 void __iomem *ioaddr = tp->mmio_addr;
4826
4827 switch (tp->mac_version) {
4828 case RTL_GIGA_MAC_VER_25:
4829 case RTL_GIGA_MAC_VER_26:
4830 case RTL_GIGA_MAC_VER_29:
4831 case RTL_GIGA_MAC_VER_30:
4832 case RTL_GIGA_MAC_VER_32:
4833 case RTL_GIGA_MAC_VER_33:
4834 case RTL_GIGA_MAC_VER_34:
4835 case RTL_GIGA_MAC_VER_37:
4836 case RTL_GIGA_MAC_VER_38:
4837 case RTL_GIGA_MAC_VER_39:
4838 case RTL_GIGA_MAC_VER_40:
4839 case RTL_GIGA_MAC_VER_41:
4840 case RTL_GIGA_MAC_VER_42:
4841 case RTL_GIGA_MAC_VER_43:
4842 case RTL_GIGA_MAC_VER_44:
4843 case RTL_GIGA_MAC_VER_45:
4844 case RTL_GIGA_MAC_VER_46:
4845 case RTL_GIGA_MAC_VER_47:
4846 case RTL_GIGA_MAC_VER_48:
4847 case RTL_GIGA_MAC_VER_49:
4848 case RTL_GIGA_MAC_VER_50:
4849 case RTL_GIGA_MAC_VER_51:
4850 RTL_W32(RxConfig, RTL_R32(RxConfig) |
4851 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4852 break;
4853 default:
4854 break;
4855 }
4856 }
4857
4858 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4859 {
4860 if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
4861 return false;
4862
4863 rtl_speed_down(tp);
4864 rtl_wol_suspend_quirk(tp);
4865
4866 return true;
4867 }
4868
4869 static void r810x_phy_power_down(struct rtl8169_private *tp)
4870 {
4871 rtl_writephy(tp, 0x1f, 0x0000);
4872 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4873 }
4874
4875 static void r810x_phy_power_up(struct rtl8169_private *tp)
4876 {
4877 rtl_writephy(tp, 0x1f, 0x0000);
4878 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4879 }
4880
4881 static void r810x_pll_power_down(struct rtl8169_private *tp)
4882 {
4883 void __iomem *ioaddr = tp->mmio_addr;
4884
4885 if (rtl_wol_pll_power_down(tp))
4886 return;
4887
4888 r810x_phy_power_down(tp);
4889
4890 switch (tp->mac_version) {
4891 case RTL_GIGA_MAC_VER_07:
4892 case RTL_GIGA_MAC_VER_08:
4893 case RTL_GIGA_MAC_VER_09:
4894 case RTL_GIGA_MAC_VER_10:
4895 case RTL_GIGA_MAC_VER_13:
4896 case RTL_GIGA_MAC_VER_16:
4897 break;
4898 default:
4899 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4900 break;
4901 }
4902 }
4903
4904 static void r810x_pll_power_up(struct rtl8169_private *tp)
4905 {
4906 void __iomem *ioaddr = tp->mmio_addr;
4907
4908 r810x_phy_power_up(tp);
4909
4910 switch (tp->mac_version) {
4911 case RTL_GIGA_MAC_VER_07:
4912 case RTL_GIGA_MAC_VER_08:
4913 case RTL_GIGA_MAC_VER_09:
4914 case RTL_GIGA_MAC_VER_10:
4915 case RTL_GIGA_MAC_VER_13:
4916 case RTL_GIGA_MAC_VER_16:
4917 break;
4918 case RTL_GIGA_MAC_VER_47:
4919 case RTL_GIGA_MAC_VER_48:
4920 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4921 break;
4922 default:
4923 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4924 break;
4925 }
4926 }
4927
4928 static void r8168_phy_power_up(struct rtl8169_private *tp)
4929 {
4930 rtl_writephy(tp, 0x1f, 0x0000);
4931 switch (tp->mac_version) {
4932 case RTL_GIGA_MAC_VER_11:
4933 case RTL_GIGA_MAC_VER_12:
4934 case RTL_GIGA_MAC_VER_17:
4935 case RTL_GIGA_MAC_VER_18:
4936 case RTL_GIGA_MAC_VER_19:
4937 case RTL_GIGA_MAC_VER_20:
4938 case RTL_GIGA_MAC_VER_21:
4939 case RTL_GIGA_MAC_VER_22:
4940 case RTL_GIGA_MAC_VER_23:
4941 case RTL_GIGA_MAC_VER_24:
4942 case RTL_GIGA_MAC_VER_25:
4943 case RTL_GIGA_MAC_VER_26:
4944 case RTL_GIGA_MAC_VER_27:
4945 case RTL_GIGA_MAC_VER_28:
4946 case RTL_GIGA_MAC_VER_31:
4947 rtl_writephy(tp, 0x0e, 0x0000);
4948 break;
4949 default:
4950 break;
4951 }
4952 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4953 }
4954
4955 static void r8168_phy_power_down(struct rtl8169_private *tp)
4956 {
4957 rtl_writephy(tp, 0x1f, 0x0000);
4958 switch (tp->mac_version) {
4959 case RTL_GIGA_MAC_VER_32:
4960 case RTL_GIGA_MAC_VER_33:
4961 case RTL_GIGA_MAC_VER_40:
4962 case RTL_GIGA_MAC_VER_41:
4963 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
4964 break;
4965
4966 case RTL_GIGA_MAC_VER_11:
4967 case RTL_GIGA_MAC_VER_12:
4968 case RTL_GIGA_MAC_VER_17:
4969 case RTL_GIGA_MAC_VER_18:
4970 case RTL_GIGA_MAC_VER_19:
4971 case RTL_GIGA_MAC_VER_20:
4972 case RTL_GIGA_MAC_VER_21:
4973 case RTL_GIGA_MAC_VER_22:
4974 case RTL_GIGA_MAC_VER_23:
4975 case RTL_GIGA_MAC_VER_24:
4976 case RTL_GIGA_MAC_VER_25:
4977 case RTL_GIGA_MAC_VER_26:
4978 case RTL_GIGA_MAC_VER_27:
4979 case RTL_GIGA_MAC_VER_28:
4980 case RTL_GIGA_MAC_VER_31:
4981 rtl_writephy(tp, 0x0e, 0x0200);
4982 default:
4983 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4984 break;
4985 }
4986 }
4987
4988 static void r8168_pll_power_down(struct rtl8169_private *tp)
4989 {
4990 void __iomem *ioaddr = tp->mmio_addr;
4991
4992 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4993 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4994 tp->mac_version == RTL_GIGA_MAC_VER_31 ||
4995 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
4996 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
4997 tp->mac_version == RTL_GIGA_MAC_VER_51) &&
4998 r8168_check_dash(tp)) {
4999 return;
5000 }
5001
5002 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
5003 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
5004 (RTL_R16(CPlusCmd) & ASF)) {
5005 return;
5006 }
5007
5008 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
5009 tp->mac_version == RTL_GIGA_MAC_VER_33)
5010 rtl_ephy_write(tp, 0x19, 0xff64);
5011
5012 if (rtl_wol_pll_power_down(tp))
5013 return;
5014
5015 r8168_phy_power_down(tp);
5016
5017 switch (tp->mac_version) {
5018 case RTL_GIGA_MAC_VER_25:
5019 case RTL_GIGA_MAC_VER_26:
5020 case RTL_GIGA_MAC_VER_27:
5021 case RTL_GIGA_MAC_VER_28:
5022 case RTL_GIGA_MAC_VER_31:
5023 case RTL_GIGA_MAC_VER_32:
5024 case RTL_GIGA_MAC_VER_33:
5025 case RTL_GIGA_MAC_VER_44:
5026 case RTL_GIGA_MAC_VER_45:
5027 case RTL_GIGA_MAC_VER_46:
5028 case RTL_GIGA_MAC_VER_50:
5029 case RTL_GIGA_MAC_VER_51:
5030 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
5031 break;
5032 case RTL_GIGA_MAC_VER_40:
5033 case RTL_GIGA_MAC_VER_41:
5034 case RTL_GIGA_MAC_VER_49:
5035 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
5036 0xfc000000, ERIAR_EXGMAC);
5037 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
5038 break;
5039 }
5040 }
5041
5042 static void r8168_pll_power_up(struct rtl8169_private *tp)
5043 {
5044 void __iomem *ioaddr = tp->mmio_addr;
5045
5046 switch (tp->mac_version) {
5047 case RTL_GIGA_MAC_VER_25:
5048 case RTL_GIGA_MAC_VER_26:
5049 case RTL_GIGA_MAC_VER_27:
5050 case RTL_GIGA_MAC_VER_28:
5051 case RTL_GIGA_MAC_VER_31:
5052 case RTL_GIGA_MAC_VER_32:
5053 case RTL_GIGA_MAC_VER_33:
5054 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
5055 break;
5056 case RTL_GIGA_MAC_VER_44:
5057 case RTL_GIGA_MAC_VER_45:
5058 case RTL_GIGA_MAC_VER_46:
5059 case RTL_GIGA_MAC_VER_50:
5060 case RTL_GIGA_MAC_VER_51:
5061 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
5062 break;
5063 case RTL_GIGA_MAC_VER_40:
5064 case RTL_GIGA_MAC_VER_41:
5065 case RTL_GIGA_MAC_VER_49:
5066 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
5067 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
5068 0x00000000, ERIAR_EXGMAC);
5069 break;
5070 }
5071
5072 r8168_phy_power_up(tp);
5073 }
5074
5075 static void rtl_generic_op(struct rtl8169_private *tp,
5076 void (*op)(struct rtl8169_private *))
5077 {
5078 if (op)
5079 op(tp);
5080 }
5081
5082 static void rtl_pll_power_down(struct rtl8169_private *tp)
5083 {
5084 rtl_generic_op(tp, tp->pll_power_ops.down);
5085 }
5086
5087 static void rtl_pll_power_up(struct rtl8169_private *tp)
5088 {
5089 rtl_generic_op(tp, tp->pll_power_ops.up);
5090 }
5091
5092 static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
5093 {
5094 struct pll_power_ops *ops = &tp->pll_power_ops;
5095
5096 switch (tp->mac_version) {
5097 case RTL_GIGA_MAC_VER_07:
5098 case RTL_GIGA_MAC_VER_08:
5099 case RTL_GIGA_MAC_VER_09:
5100 case RTL_GIGA_MAC_VER_10:
5101 case RTL_GIGA_MAC_VER_16:
5102 case RTL_GIGA_MAC_VER_29:
5103 case RTL_GIGA_MAC_VER_30:
5104 case RTL_GIGA_MAC_VER_37:
5105 case RTL_GIGA_MAC_VER_39:
5106 case RTL_GIGA_MAC_VER_43:
5107 case RTL_GIGA_MAC_VER_47:
5108 case RTL_GIGA_MAC_VER_48:
5109 ops->down = r810x_pll_power_down;
5110 ops->up = r810x_pll_power_up;
5111 break;
5112
5113 case RTL_GIGA_MAC_VER_11:
5114 case RTL_GIGA_MAC_VER_12:
5115 case RTL_GIGA_MAC_VER_17:
5116 case RTL_GIGA_MAC_VER_18:
5117 case RTL_GIGA_MAC_VER_19:
5118 case RTL_GIGA_MAC_VER_20:
5119 case RTL_GIGA_MAC_VER_21:
5120 case RTL_GIGA_MAC_VER_22:
5121 case RTL_GIGA_MAC_VER_23:
5122 case RTL_GIGA_MAC_VER_24:
5123 case RTL_GIGA_MAC_VER_25:
5124 case RTL_GIGA_MAC_VER_26:
5125 case RTL_GIGA_MAC_VER_27:
5126 case RTL_GIGA_MAC_VER_28:
5127 case RTL_GIGA_MAC_VER_31:
5128 case RTL_GIGA_MAC_VER_32:
5129 case RTL_GIGA_MAC_VER_33:
5130 case RTL_GIGA_MAC_VER_34:
5131 case RTL_GIGA_MAC_VER_35:
5132 case RTL_GIGA_MAC_VER_36:
5133 case RTL_GIGA_MAC_VER_38:
5134 case RTL_GIGA_MAC_VER_40:
5135 case RTL_GIGA_MAC_VER_41:
5136 case RTL_GIGA_MAC_VER_42:
5137 case RTL_GIGA_MAC_VER_44:
5138 case RTL_GIGA_MAC_VER_45:
5139 case RTL_GIGA_MAC_VER_46:
5140 case RTL_GIGA_MAC_VER_49:
5141 case RTL_GIGA_MAC_VER_50:
5142 case RTL_GIGA_MAC_VER_51:
5143 ops->down = r8168_pll_power_down;
5144 ops->up = r8168_pll_power_up;
5145 break;
5146
5147 default:
5148 ops->down = NULL;
5149 ops->up = NULL;
5150 break;
5151 }
5152 }
5153
5154 static void rtl_init_rxcfg(struct rtl8169_private *tp)
5155 {
5156 void __iomem *ioaddr = tp->mmio_addr;
5157
5158 switch (tp->mac_version) {
5159 case RTL_GIGA_MAC_VER_01:
5160 case RTL_GIGA_MAC_VER_02:
5161 case RTL_GIGA_MAC_VER_03:
5162 case RTL_GIGA_MAC_VER_04:
5163 case RTL_GIGA_MAC_VER_05:
5164 case RTL_GIGA_MAC_VER_06:
5165 case RTL_GIGA_MAC_VER_10:
5166 case RTL_GIGA_MAC_VER_11:
5167 case RTL_GIGA_MAC_VER_12:
5168 case RTL_GIGA_MAC_VER_13:
5169 case RTL_GIGA_MAC_VER_14:
5170 case RTL_GIGA_MAC_VER_15:
5171 case RTL_GIGA_MAC_VER_16:
5172 case RTL_GIGA_MAC_VER_17:
5173 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
5174 break;
5175 case RTL_GIGA_MAC_VER_18:
5176 case RTL_GIGA_MAC_VER_19:
5177 case RTL_GIGA_MAC_VER_20:
5178 case RTL_GIGA_MAC_VER_21:
5179 case RTL_GIGA_MAC_VER_22:
5180 case RTL_GIGA_MAC_VER_23:
5181 case RTL_GIGA_MAC_VER_24:
5182 case RTL_GIGA_MAC_VER_34:
5183 case RTL_GIGA_MAC_VER_35:
5184 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
5185 break;
5186 case RTL_GIGA_MAC_VER_40:
5187 case RTL_GIGA_MAC_VER_41:
5188 case RTL_GIGA_MAC_VER_42:
5189 case RTL_GIGA_MAC_VER_43:
5190 case RTL_GIGA_MAC_VER_44:
5191 case RTL_GIGA_MAC_VER_45:
5192 case RTL_GIGA_MAC_VER_46:
5193 case RTL_GIGA_MAC_VER_47:
5194 case RTL_GIGA_MAC_VER_48:
5195 case RTL_GIGA_MAC_VER_49:
5196 case RTL_GIGA_MAC_VER_50:
5197 case RTL_GIGA_MAC_VER_51:
5198 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
5199 break;
5200 default:
5201 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
5202 break;
5203 }
5204 }
5205
5206 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
5207 {
5208 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
5209 }
5210
5211 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
5212 {
5213 void __iomem *ioaddr = tp->mmio_addr;
5214
5215 RTL_W8(Cfg9346, Cfg9346_Unlock);
5216 rtl_generic_op(tp, tp->jumbo_ops.enable);
5217 RTL_W8(Cfg9346, Cfg9346_Lock);
5218 }
5219
5220 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
5221 {
5222 void __iomem *ioaddr = tp->mmio_addr;
5223
5224 RTL_W8(Cfg9346, Cfg9346_Unlock);
5225 rtl_generic_op(tp, tp->jumbo_ops.disable);
5226 RTL_W8(Cfg9346, Cfg9346_Lock);
5227 }
5228
5229 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
5230 {
5231 void __iomem *ioaddr = tp->mmio_addr;
5232
5233 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
5234 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
5235 rtl_tx_performance_tweak(tp->pci_dev, PCI_EXP_DEVCTL_READRQ_512B);
5236 }
5237
5238 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
5239 {
5240 void __iomem *ioaddr = tp->mmio_addr;
5241
5242 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
5243 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
5244 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5245 }
5246
5247 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
5248 {
5249 void __iomem *ioaddr = tp->mmio_addr;
5250
5251 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
5252 }
5253
5254 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
5255 {
5256 void __iomem *ioaddr = tp->mmio_addr;
5257
5258 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
5259 }
5260
5261 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
5262 {
5263 void __iomem *ioaddr = tp->mmio_addr;
5264
5265 RTL_W8(MaxTxPacketSize, 0x3f);
5266 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
5267 RTL_W8(Config4, RTL_R8(Config4) | 0x01);
5268 rtl_tx_performance_tweak(tp->pci_dev, PCI_EXP_DEVCTL_READRQ_512B);
5269 }
5270
5271 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
5272 {
5273 void __iomem *ioaddr = tp->mmio_addr;
5274
5275 RTL_W8(MaxTxPacketSize, 0x0c);
5276 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
5277 RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
5278 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
5279 }
5280
5281 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
5282 {
5283 rtl_tx_performance_tweak(tp->pci_dev,
5284 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
5285 }
5286
5287 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
5288 {
5289 rtl_tx_performance_tweak(tp->pci_dev,
5290 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
5291 }
5292
5293 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
5294 {
5295 void __iomem *ioaddr = tp->mmio_addr;
5296
5297 r8168b_0_hw_jumbo_enable(tp);
5298
5299 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
5300 }
5301
5302 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
5303 {
5304 void __iomem *ioaddr = tp->mmio_addr;
5305
5306 r8168b_0_hw_jumbo_disable(tp);
5307
5308 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
5309 }
5310
5311 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
5312 {
5313 struct jumbo_ops *ops = &tp->jumbo_ops;
5314
5315 switch (tp->mac_version) {
5316 case RTL_GIGA_MAC_VER_11:
5317 ops->disable = r8168b_0_hw_jumbo_disable;
5318 ops->enable = r8168b_0_hw_jumbo_enable;
5319 break;
5320 case RTL_GIGA_MAC_VER_12:
5321 case RTL_GIGA_MAC_VER_17:
5322 ops->disable = r8168b_1_hw_jumbo_disable;
5323 ops->enable = r8168b_1_hw_jumbo_enable;
5324 break;
5325 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
5326 case RTL_GIGA_MAC_VER_19:
5327 case RTL_GIGA_MAC_VER_20:
5328 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
5329 case RTL_GIGA_MAC_VER_22:
5330 case RTL_GIGA_MAC_VER_23:
5331 case RTL_GIGA_MAC_VER_24:
5332 case RTL_GIGA_MAC_VER_25:
5333 case RTL_GIGA_MAC_VER_26:
5334 ops->disable = r8168c_hw_jumbo_disable;
5335 ops->enable = r8168c_hw_jumbo_enable;
5336 break;
5337 case RTL_GIGA_MAC_VER_27:
5338 case RTL_GIGA_MAC_VER_28:
5339 ops->disable = r8168dp_hw_jumbo_disable;
5340 ops->enable = r8168dp_hw_jumbo_enable;
5341 break;
5342 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
5343 case RTL_GIGA_MAC_VER_32:
5344 case RTL_GIGA_MAC_VER_33:
5345 case RTL_GIGA_MAC_VER_34:
5346 ops->disable = r8168e_hw_jumbo_disable;
5347 ops->enable = r8168e_hw_jumbo_enable;
5348 break;
5349
5350 /*
5351 * No action needed for jumbo frames with 8169.
5352 * No jumbo for 810x at all.
5353 */
5354 case RTL_GIGA_MAC_VER_40:
5355 case RTL_GIGA_MAC_VER_41:
5356 case RTL_GIGA_MAC_VER_42:
5357 case RTL_GIGA_MAC_VER_43:
5358 case RTL_GIGA_MAC_VER_44:
5359 case RTL_GIGA_MAC_VER_45:
5360 case RTL_GIGA_MAC_VER_46:
5361 case RTL_GIGA_MAC_VER_47:
5362 case RTL_GIGA_MAC_VER_48:
5363 case RTL_GIGA_MAC_VER_49:
5364 case RTL_GIGA_MAC_VER_50:
5365 case RTL_GIGA_MAC_VER_51:
5366 default:
5367 ops->disable = NULL;
5368 ops->enable = NULL;
5369 break;
5370 }
5371 }
5372
5373 DECLARE_RTL_COND(rtl_chipcmd_cond)
5374 {
5375 void __iomem *ioaddr = tp->mmio_addr;
5376
5377 return RTL_R8(ChipCmd) & CmdReset;
5378 }
5379
5380 static void rtl_hw_reset(struct rtl8169_private *tp)
5381 {
5382 void __iomem *ioaddr = tp->mmio_addr;
5383
5384 RTL_W8(ChipCmd, CmdReset);
5385
5386 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
5387 }
5388
5389 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
5390 {
5391 struct rtl_fw *rtl_fw;
5392 const char *name;
5393 int rc = -ENOMEM;
5394
5395 name = rtl_lookup_firmware_name(tp);
5396 if (!name)
5397 goto out_no_firmware;
5398
5399 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
5400 if (!rtl_fw)
5401 goto err_warn;
5402
5403 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
5404 if (rc < 0)
5405 goto err_free;
5406
5407 rc = rtl_check_firmware(tp, rtl_fw);
5408 if (rc < 0)
5409 goto err_release_firmware;
5410
5411 tp->rtl_fw = rtl_fw;
5412 out:
5413 return;
5414
5415 err_release_firmware:
5416 release_firmware(rtl_fw->fw);
5417 err_free:
5418 kfree(rtl_fw);
5419 err_warn:
5420 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
5421 name, rc);
5422 out_no_firmware:
5423 tp->rtl_fw = NULL;
5424 goto out;
5425 }
5426
5427 static void rtl_request_firmware(struct rtl8169_private *tp)
5428 {
5429 if (IS_ERR(tp->rtl_fw))
5430 rtl_request_uncached_firmware(tp);
5431 }
5432
5433 static void rtl_rx_close(struct rtl8169_private *tp)
5434 {
5435 void __iomem *ioaddr = tp->mmio_addr;
5436
5437 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
5438 }
5439
5440 DECLARE_RTL_COND(rtl_npq_cond)
5441 {
5442 void __iomem *ioaddr = tp->mmio_addr;
5443
5444 return RTL_R8(TxPoll) & NPQ;
5445 }
5446
5447 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
5448 {
5449 void __iomem *ioaddr = tp->mmio_addr;
5450
5451 return RTL_R32(TxConfig) & TXCFG_EMPTY;
5452 }
5453
5454 static void rtl8169_hw_reset(struct rtl8169_private *tp)
5455 {
5456 void __iomem *ioaddr = tp->mmio_addr;
5457
5458 /* Disable interrupts */
5459 rtl8169_irq_mask_and_ack(tp);
5460
5461 rtl_rx_close(tp);
5462
5463 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
5464 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
5465 tp->mac_version == RTL_GIGA_MAC_VER_31) {
5466 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
5467 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
5468 tp->mac_version == RTL_GIGA_MAC_VER_35 ||
5469 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
5470 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
5471 tp->mac_version == RTL_GIGA_MAC_VER_38 ||
5472 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
5473 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
5474 tp->mac_version == RTL_GIGA_MAC_VER_42 ||
5475 tp->mac_version == RTL_GIGA_MAC_VER_43 ||
5476 tp->mac_version == RTL_GIGA_MAC_VER_44 ||
5477 tp->mac_version == RTL_GIGA_MAC_VER_45 ||
5478 tp->mac_version == RTL_GIGA_MAC_VER_46 ||
5479 tp->mac_version == RTL_GIGA_MAC_VER_47 ||
5480 tp->mac_version == RTL_GIGA_MAC_VER_48 ||
5481 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
5482 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
5483 tp->mac_version == RTL_GIGA_MAC_VER_51) {
5484 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
5485 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
5486 } else {
5487 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
5488 udelay(100);
5489 }
5490
5491 rtl_hw_reset(tp);
5492 }
5493
5494 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
5495 {
5496 void __iomem *ioaddr = tp->mmio_addr;
5497
5498 /* Set DMA burst size and Interframe Gap Time */
5499 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
5500 (InterFrameGap << TxInterFrameGapShift));
5501 }
5502
5503 static void rtl_hw_start(struct net_device *dev)
5504 {
5505 struct rtl8169_private *tp = netdev_priv(dev);
5506
5507 tp->hw_start(dev);
5508
5509 rtl_irq_enable_all(tp);
5510 }
5511
5512 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
5513 void __iomem *ioaddr)
5514 {
5515 /*
5516 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
5517 * register to be written before TxDescAddrLow to work.
5518 * Switching from MMIO to I/O access fixes the issue as well.
5519 */
5520 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
5521 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
5522 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
5523 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
5524 }
5525
5526 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
5527 {
5528 u16 cmd;
5529
5530 cmd = RTL_R16(CPlusCmd);
5531 RTL_W16(CPlusCmd, cmd);
5532 return cmd;
5533 }
5534
5535 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
5536 {
5537 /* Low hurts. Let's disable the filtering. */
5538 RTL_W16(RxMaxSize, rx_buf_sz + 1);
5539 }
5540
5541 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
5542 {
5543 static const struct rtl_cfg2_info {
5544 u32 mac_version;
5545 u32 clk;
5546 u32 val;
5547 } cfg2_info [] = {
5548 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
5549 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
5550 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
5551 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
5552 };
5553 const struct rtl_cfg2_info *p = cfg2_info;
5554 unsigned int i;
5555 u32 clk;
5556
5557 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
5558 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
5559 if ((p->mac_version == mac_version) && (p->clk == clk)) {
5560 RTL_W32(0x7c, p->val);
5561 break;
5562 }
5563 }
5564 }
5565
5566 static void rtl_set_rx_mode(struct net_device *dev)
5567 {
5568 struct rtl8169_private *tp = netdev_priv(dev);
5569 void __iomem *ioaddr = tp->mmio_addr;
5570 u32 mc_filter[2]; /* Multicast hash filter */
5571 int rx_mode;
5572 u32 tmp = 0;
5573
5574 if (dev->flags & IFF_PROMISC) {
5575 /* Unconditionally log net taps. */
5576 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5577 rx_mode =
5578 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5579 AcceptAllPhys;
5580 mc_filter[1] = mc_filter[0] = 0xffffffff;
5581 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5582 (dev->flags & IFF_ALLMULTI)) {
5583 /* Too many to filter perfectly -- accept all multicasts. */
5584 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5585 mc_filter[1] = mc_filter[0] = 0xffffffff;
5586 } else {
5587 struct netdev_hw_addr *ha;
5588
5589 rx_mode = AcceptBroadcast | AcceptMyPhys;
5590 mc_filter[1] = mc_filter[0] = 0;
5591 netdev_for_each_mc_addr(ha, dev) {
5592 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5593 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5594 rx_mode |= AcceptMulticast;
5595 }
5596 }
5597
5598 if (dev->features & NETIF_F_RXALL)
5599 rx_mode |= (AcceptErr | AcceptRunt);
5600
5601 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
5602
5603 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5604 u32 data = mc_filter[0];
5605
5606 mc_filter[0] = swab32(mc_filter[1]);
5607 mc_filter[1] = swab32(data);
5608 }
5609
5610 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
5611 mc_filter[1] = mc_filter[0] = 0xffffffff;
5612
5613 RTL_W32(MAR0 + 4, mc_filter[1]);
5614 RTL_W32(MAR0 + 0, mc_filter[0]);
5615
5616 RTL_W32(RxConfig, tmp);
5617 }
5618
5619 static void rtl_hw_start_8169(struct net_device *dev)
5620 {
5621 struct rtl8169_private *tp = netdev_priv(dev);
5622 void __iomem *ioaddr = tp->mmio_addr;
5623 struct pci_dev *pdev = tp->pci_dev;
5624
5625 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
5626 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
5627 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
5628 }
5629
5630 RTL_W8(Cfg9346, Cfg9346_Unlock);
5631 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5632 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5633 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5634 tp->mac_version == RTL_GIGA_MAC_VER_04)
5635 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5636
5637 rtl_init_rxcfg(tp);
5638
5639 RTL_W8(EarlyTxThres, NoEarlyTx);
5640
5641 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5642
5643 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5644 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5645 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5646 tp->mac_version == RTL_GIGA_MAC_VER_04)
5647 rtl_set_rx_tx_config_registers(tp);
5648
5649 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
5650
5651 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5652 tp->mac_version == RTL_GIGA_MAC_VER_03) {
5653 dprintk("Set MAC Reg C+CR Offset 0xe0. "
5654 "Bit-3 and bit-14 MUST be 1\n");
5655 tp->cp_cmd |= (1 << 14);
5656 }
5657
5658 RTL_W16(CPlusCmd, tp->cp_cmd);
5659
5660 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
5661
5662 /*
5663 * Undocumented corner. Supposedly:
5664 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
5665 */
5666 RTL_W16(IntrMitigate, 0x0000);
5667
5668 rtl_set_rx_tx_desc_registers(tp, ioaddr);
5669
5670 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
5671 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
5672 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
5673 tp->mac_version != RTL_GIGA_MAC_VER_04) {
5674 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5675 rtl_set_rx_tx_config_registers(tp);
5676 }
5677
5678 RTL_W8(Cfg9346, Cfg9346_Lock);
5679
5680 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
5681 RTL_R8(IntrMask);
5682
5683 RTL_W32(RxMissed, 0);
5684
5685 rtl_set_rx_mode(dev);
5686
5687 /* no early-rx interrupts */
5688 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
5689 }
5690
5691 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
5692 {
5693 if (tp->csi_ops.write)
5694 tp->csi_ops.write(tp, addr, value);
5695 }
5696
5697 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
5698 {
5699 return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
5700 }
5701
5702 static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
5703 {
5704 u32 csi;
5705
5706 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
5707 rtl_csi_write(tp, 0x070c, csi | bits);
5708 }
5709
5710 static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
5711 {
5712 rtl_csi_access_enable(tp, 0x17000000);
5713 }
5714
5715 static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
5716 {
5717 rtl_csi_access_enable(tp, 0x27000000);
5718 }
5719
5720 DECLARE_RTL_COND(rtl_csiar_cond)
5721 {
5722 void __iomem *ioaddr = tp->mmio_addr;
5723
5724 return RTL_R32(CSIAR) & CSIAR_FLAG;
5725 }
5726
5727 static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
5728 {
5729 void __iomem *ioaddr = tp->mmio_addr;
5730
5731 RTL_W32(CSIDR, value);
5732 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5733 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5734
5735 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5736 }
5737
5738 static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
5739 {
5740 void __iomem *ioaddr = tp->mmio_addr;
5741
5742 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
5743 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5744
5745 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5746 RTL_R32(CSIDR) : ~0;
5747 }
5748
5749 static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
5750 {
5751 void __iomem *ioaddr = tp->mmio_addr;
5752
5753 RTL_W32(CSIDR, value);
5754 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5755 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5756 CSIAR_FUNC_NIC);
5757
5758 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5759 }
5760
5761 static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
5762 {
5763 void __iomem *ioaddr = tp->mmio_addr;
5764
5765 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
5766 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5767
5768 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5769 RTL_R32(CSIDR) : ~0;
5770 }
5771
5772 static void r8411_csi_write(struct rtl8169_private *tp, int addr, int value)
5773 {
5774 void __iomem *ioaddr = tp->mmio_addr;
5775
5776 RTL_W32(CSIDR, value);
5777 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5778 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5779 CSIAR_FUNC_NIC2);
5780
5781 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5782 }
5783
5784 static u32 r8411_csi_read(struct rtl8169_private *tp, int addr)
5785 {
5786 void __iomem *ioaddr = tp->mmio_addr;
5787
5788 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC2 |
5789 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5790
5791 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5792 RTL_R32(CSIDR) : ~0;
5793 }
5794
5795 static void rtl_init_csi_ops(struct rtl8169_private *tp)
5796 {
5797 struct csi_ops *ops = &tp->csi_ops;
5798
5799 switch (tp->mac_version) {
5800 case RTL_GIGA_MAC_VER_01:
5801 case RTL_GIGA_MAC_VER_02:
5802 case RTL_GIGA_MAC_VER_03:
5803 case RTL_GIGA_MAC_VER_04:
5804 case RTL_GIGA_MAC_VER_05:
5805 case RTL_GIGA_MAC_VER_06:
5806 case RTL_GIGA_MAC_VER_10:
5807 case RTL_GIGA_MAC_VER_11:
5808 case RTL_GIGA_MAC_VER_12:
5809 case RTL_GIGA_MAC_VER_13:
5810 case RTL_GIGA_MAC_VER_14:
5811 case RTL_GIGA_MAC_VER_15:
5812 case RTL_GIGA_MAC_VER_16:
5813 case RTL_GIGA_MAC_VER_17:
5814 ops->write = NULL;
5815 ops->read = NULL;
5816 break;
5817
5818 case RTL_GIGA_MAC_VER_37:
5819 case RTL_GIGA_MAC_VER_38:
5820 ops->write = r8402_csi_write;
5821 ops->read = r8402_csi_read;
5822 break;
5823
5824 case RTL_GIGA_MAC_VER_44:
5825 ops->write = r8411_csi_write;
5826 ops->read = r8411_csi_read;
5827 break;
5828
5829 default:
5830 ops->write = r8169_csi_write;
5831 ops->read = r8169_csi_read;
5832 break;
5833 }
5834 }
5835
5836 struct ephy_info {
5837 unsigned int offset;
5838 u16 mask;
5839 u16 bits;
5840 };
5841
5842 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
5843 int len)
5844 {
5845 u16 w;
5846
5847 while (len-- > 0) {
5848 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
5849 rtl_ephy_write(tp, e->offset, w);
5850 e++;
5851 }
5852 }
5853
5854 static void rtl_disable_clock_request(struct pci_dev *pdev)
5855 {
5856 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
5857 PCI_EXP_LNKCTL_CLKREQ_EN);
5858 }
5859
5860 static void rtl_enable_clock_request(struct pci_dev *pdev)
5861 {
5862 pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
5863 PCI_EXP_LNKCTL_CLKREQ_EN);
5864 }
5865
5866 static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
5867 {
5868 void __iomem *ioaddr = tp->mmio_addr;
5869 u8 data;
5870
5871 data = RTL_R8(Config3);
5872
5873 if (enable)
5874 data |= Rdy_to_L23;
5875 else
5876 data &= ~Rdy_to_L23;
5877
5878 RTL_W8(Config3, data);
5879 }
5880
5881 #define R8168_CPCMD_QUIRK_MASK (\
5882 EnableBist | \
5883 Mac_dbgo_oe | \
5884 Force_half_dup | \
5885 Force_rxflow_en | \
5886 Force_txflow_en | \
5887 Cxpl_dbg_sel | \
5888 ASF | \
5889 PktCntrDisable | \
5890 Mac_dbgo_sel)
5891
5892 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
5893 {
5894 void __iomem *ioaddr = tp->mmio_addr;
5895 struct pci_dev *pdev = tp->pci_dev;
5896
5897 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5898
5899 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5900
5901 if (tp->dev->mtu <= ETH_DATA_LEN) {
5902 rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) |
5903 PCI_EXP_DEVCTL_NOSNOOP_EN);
5904 }
5905 }
5906
5907 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
5908 {
5909 void __iomem *ioaddr = tp->mmio_addr;
5910
5911 rtl_hw_start_8168bb(tp);
5912
5913 RTL_W8(MaxTxPacketSize, TxPacketMax);
5914
5915 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
5916 }
5917
5918 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
5919 {
5920 void __iomem *ioaddr = tp->mmio_addr;
5921 struct pci_dev *pdev = tp->pci_dev;
5922
5923 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
5924
5925 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5926
5927 if (tp->dev->mtu <= ETH_DATA_LEN)
5928 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5929
5930 rtl_disable_clock_request(pdev);
5931
5932 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5933 }
5934
5935 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
5936 {
5937 static const struct ephy_info e_info_8168cp[] = {
5938 { 0x01, 0, 0x0001 },
5939 { 0x02, 0x0800, 0x1000 },
5940 { 0x03, 0, 0x0042 },
5941 { 0x06, 0x0080, 0x0000 },
5942 { 0x07, 0, 0x2000 }
5943 };
5944
5945 rtl_csi_access_enable_2(tp);
5946
5947 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
5948
5949 __rtl_hw_start_8168cp(tp);
5950 }
5951
5952 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
5953 {
5954 void __iomem *ioaddr = tp->mmio_addr;
5955 struct pci_dev *pdev = tp->pci_dev;
5956
5957 rtl_csi_access_enable_2(tp);
5958
5959 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5960
5961 if (tp->dev->mtu <= ETH_DATA_LEN)
5962 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5963
5964 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5965 }
5966
5967 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
5968 {
5969 void __iomem *ioaddr = tp->mmio_addr;
5970 struct pci_dev *pdev = tp->pci_dev;
5971
5972 rtl_csi_access_enable_2(tp);
5973
5974 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5975
5976 /* Magic. */
5977 RTL_W8(DBG_REG, 0x20);
5978
5979 RTL_W8(MaxTxPacketSize, TxPacketMax);
5980
5981 if (tp->dev->mtu <= ETH_DATA_LEN)
5982 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5983
5984 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5985 }
5986
5987 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
5988 {
5989 void __iomem *ioaddr = tp->mmio_addr;
5990 static const struct ephy_info e_info_8168c_1[] = {
5991 { 0x02, 0x0800, 0x1000 },
5992 { 0x03, 0, 0x0002 },
5993 { 0x06, 0x0080, 0x0000 }
5994 };
5995
5996 rtl_csi_access_enable_2(tp);
5997
5998 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
5999
6000 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
6001
6002 __rtl_hw_start_8168cp(tp);
6003 }
6004
6005 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
6006 {
6007 static const struct ephy_info e_info_8168c_2[] = {
6008 { 0x01, 0, 0x0001 },
6009 { 0x03, 0x0400, 0x0220 }
6010 };
6011
6012 rtl_csi_access_enable_2(tp);
6013
6014 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
6015
6016 __rtl_hw_start_8168cp(tp);
6017 }
6018
6019 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
6020 {
6021 rtl_hw_start_8168c_2(tp);
6022 }
6023
6024 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
6025 {
6026 rtl_csi_access_enable_2(tp);
6027
6028 __rtl_hw_start_8168cp(tp);
6029 }
6030
6031 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
6032 {
6033 void __iomem *ioaddr = tp->mmio_addr;
6034 struct pci_dev *pdev = tp->pci_dev;
6035
6036 rtl_csi_access_enable_2(tp);
6037
6038 rtl_disable_clock_request(pdev);
6039
6040 RTL_W8(MaxTxPacketSize, TxPacketMax);
6041
6042 if (tp->dev->mtu <= ETH_DATA_LEN)
6043 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6044
6045 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
6046 }
6047
6048 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
6049 {
6050 void __iomem *ioaddr = tp->mmio_addr;
6051 struct pci_dev *pdev = tp->pci_dev;
6052
6053 rtl_csi_access_enable_1(tp);
6054
6055 if (tp->dev->mtu <= ETH_DATA_LEN)
6056 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6057
6058 RTL_W8(MaxTxPacketSize, TxPacketMax);
6059
6060 rtl_disable_clock_request(pdev);
6061 }
6062
6063 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
6064 {
6065 void __iomem *ioaddr = tp->mmio_addr;
6066 struct pci_dev *pdev = tp->pci_dev;
6067 static const struct ephy_info e_info_8168d_4[] = {
6068 { 0x0b, 0x0000, 0x0048 },
6069 { 0x19, 0x0020, 0x0050 },
6070 { 0x0c, 0x0100, 0x0020 }
6071 };
6072
6073 rtl_csi_access_enable_1(tp);
6074
6075 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6076
6077 RTL_W8(MaxTxPacketSize, TxPacketMax);
6078
6079 rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4));
6080
6081 rtl_enable_clock_request(pdev);
6082 }
6083
6084 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
6085 {
6086 void __iomem *ioaddr = tp->mmio_addr;
6087 struct pci_dev *pdev = tp->pci_dev;
6088 static const struct ephy_info e_info_8168e_1[] = {
6089 { 0x00, 0x0200, 0x0100 },
6090 { 0x00, 0x0000, 0x0004 },
6091 { 0x06, 0x0002, 0x0001 },
6092 { 0x06, 0x0000, 0x0030 },
6093 { 0x07, 0x0000, 0x2000 },
6094 { 0x00, 0x0000, 0x0020 },
6095 { 0x03, 0x5800, 0x2000 },
6096 { 0x03, 0x0000, 0x0001 },
6097 { 0x01, 0x0800, 0x1000 },
6098 { 0x07, 0x0000, 0x4000 },
6099 { 0x1e, 0x0000, 0x2000 },
6100 { 0x19, 0xffff, 0xfe6c },
6101 { 0x0a, 0x0000, 0x0040 }
6102 };
6103
6104 rtl_csi_access_enable_2(tp);
6105
6106 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
6107
6108 if (tp->dev->mtu <= ETH_DATA_LEN)
6109 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6110
6111 RTL_W8(MaxTxPacketSize, TxPacketMax);
6112
6113 rtl_disable_clock_request(pdev);
6114
6115 /* Reset tx FIFO pointer */
6116 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
6117 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
6118
6119 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
6120 }
6121
6122 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
6123 {
6124 void __iomem *ioaddr = tp->mmio_addr;
6125 struct pci_dev *pdev = tp->pci_dev;
6126 static const struct ephy_info e_info_8168e_2[] = {
6127 { 0x09, 0x0000, 0x0080 },
6128 { 0x19, 0x0000, 0x0224 }
6129 };
6130
6131 rtl_csi_access_enable_1(tp);
6132
6133 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
6134
6135 if (tp->dev->mtu <= ETH_DATA_LEN)
6136 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6137
6138 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6139 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6140 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
6141 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6142 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
6143 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
6144 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
6145 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
6146
6147 RTL_W8(MaxTxPacketSize, EarlySize);
6148
6149 rtl_disable_clock_request(pdev);
6150
6151 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6152 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6153
6154 /* Adjust EEE LED frequency */
6155 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6156
6157 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
6158 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
6159 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
6160 }
6161
6162 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
6163 {
6164 void __iomem *ioaddr = tp->mmio_addr;
6165 struct pci_dev *pdev = tp->pci_dev;
6166
6167 rtl_csi_access_enable_2(tp);
6168
6169 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6170
6171 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6172 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6173 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
6174 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6175 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6176 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6177 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
6178 rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
6179 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
6180 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
6181
6182 RTL_W8(MaxTxPacketSize, EarlySize);
6183
6184 rtl_disable_clock_request(pdev);
6185
6186 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6187 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6188 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
6189 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
6190 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
6191 }
6192
6193 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
6194 {
6195 void __iomem *ioaddr = tp->mmio_addr;
6196 static const struct ephy_info e_info_8168f_1[] = {
6197 { 0x06, 0x00c0, 0x0020 },
6198 { 0x08, 0x0001, 0x0002 },
6199 { 0x09, 0x0000, 0x0080 },
6200 { 0x19, 0x0000, 0x0224 }
6201 };
6202
6203 rtl_hw_start_8168f(tp);
6204
6205 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
6206
6207 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
6208
6209 /* Adjust EEE LED frequency */
6210 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6211 }
6212
6213 static void rtl_hw_start_8411(struct rtl8169_private *tp)
6214 {
6215 static const struct ephy_info e_info_8168f_1[] = {
6216 { 0x06, 0x00c0, 0x0020 },
6217 { 0x0f, 0xffff, 0x5200 },
6218 { 0x1e, 0x0000, 0x4000 },
6219 { 0x19, 0x0000, 0x0224 }
6220 };
6221
6222 rtl_hw_start_8168f(tp);
6223 rtl_pcie_state_l2l3_enable(tp, false);
6224
6225 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
6226
6227 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
6228 }
6229
6230 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
6231 {
6232 void __iomem *ioaddr = tp->mmio_addr;
6233 struct pci_dev *pdev = tp->pci_dev;
6234
6235 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6236
6237 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
6238 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
6239 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
6240 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6241
6242 rtl_csi_access_enable_1(tp);
6243
6244 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6245
6246 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6247 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6248 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
6249
6250 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6251 RTL_W8(MaxTxPacketSize, EarlySize);
6252
6253 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6254 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6255
6256 /* Adjust EEE LED frequency */
6257 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6258
6259 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
6260 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6261
6262 rtl_pcie_state_l2l3_enable(tp, false);
6263 }
6264
6265 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
6266 {
6267 void __iomem *ioaddr = tp->mmio_addr;
6268 static const struct ephy_info e_info_8168g_1[] = {
6269 { 0x00, 0x0000, 0x0008 },
6270 { 0x0c, 0x37d0, 0x0820 },
6271 { 0x1e, 0x0000, 0x0001 },
6272 { 0x19, 0x8000, 0x0000 }
6273 };
6274
6275 rtl_hw_start_8168g(tp);
6276
6277 /* disable aspm and clock request before access ephy */
6278 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6279 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6280 rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
6281 }
6282
6283 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
6284 {
6285 void __iomem *ioaddr = tp->mmio_addr;
6286 static const struct ephy_info e_info_8168g_2[] = {
6287 { 0x00, 0x0000, 0x0008 },
6288 { 0x0c, 0x3df0, 0x0200 },
6289 { 0x19, 0xffff, 0xfc00 },
6290 { 0x1e, 0xffff, 0x20eb }
6291 };
6292
6293 rtl_hw_start_8168g(tp);
6294
6295 /* disable aspm and clock request before access ephy */
6296 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6297 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6298 rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
6299 }
6300
6301 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
6302 {
6303 void __iomem *ioaddr = tp->mmio_addr;
6304 static const struct ephy_info e_info_8411_2[] = {
6305 { 0x00, 0x0000, 0x0008 },
6306 { 0x0c, 0x3df0, 0x0200 },
6307 { 0x0f, 0xffff, 0x5200 },
6308 { 0x19, 0x0020, 0x0000 },
6309 { 0x1e, 0x0000, 0x2000 }
6310 };
6311
6312 rtl_hw_start_8168g(tp);
6313
6314 /* disable aspm and clock request before access ephy */
6315 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6316 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6317 rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
6318 }
6319
6320 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
6321 {
6322 void __iomem *ioaddr = tp->mmio_addr;
6323 struct pci_dev *pdev = tp->pci_dev;
6324 int rg_saw_cnt;
6325 u32 data;
6326 static const struct ephy_info e_info_8168h_1[] = {
6327 { 0x1e, 0x0800, 0x0001 },
6328 { 0x1d, 0x0000, 0x0800 },
6329 { 0x05, 0xffff, 0x2089 },
6330 { 0x06, 0xffff, 0x5881 },
6331 { 0x04, 0xffff, 0x154a },
6332 { 0x01, 0xffff, 0x068b }
6333 };
6334
6335 /* disable aspm and clock request before access ephy */
6336 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6337 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6338 rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
6339
6340 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6341
6342 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6343 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
6344 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
6345 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6346
6347 rtl_csi_access_enable_1(tp);
6348
6349 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6350
6351 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6352 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6353
6354 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
6355
6356 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
6357
6358 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6359
6360 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6361 RTL_W8(MaxTxPacketSize, EarlySize);
6362
6363 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6364 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6365
6366 /* Adjust EEE LED frequency */
6367 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6368
6369 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6370 RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6371
6372 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
6373
6374 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6375
6376 rtl_pcie_state_l2l3_enable(tp, false);
6377
6378 rtl_writephy(tp, 0x1f, 0x0c42);
6379 rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
6380 rtl_writephy(tp, 0x1f, 0x0000);
6381 if (rg_saw_cnt > 0) {
6382 u16 sw_cnt_1ms_ini;
6383
6384 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
6385 sw_cnt_1ms_ini &= 0x0fff;
6386 data = r8168_mac_ocp_read(tp, 0xd412);
6387 data &= ~0x0fff;
6388 data |= sw_cnt_1ms_ini;
6389 r8168_mac_ocp_write(tp, 0xd412, data);
6390 }
6391
6392 data = r8168_mac_ocp_read(tp, 0xe056);
6393 data &= ~0xf0;
6394 data |= 0x70;
6395 r8168_mac_ocp_write(tp, 0xe056, data);
6396
6397 data = r8168_mac_ocp_read(tp, 0xe052);
6398 data &= ~0x6000;
6399 data |= 0x8008;
6400 r8168_mac_ocp_write(tp, 0xe052, data);
6401
6402 data = r8168_mac_ocp_read(tp, 0xe0d6);
6403 data &= ~0x01ff;
6404 data |= 0x017f;
6405 r8168_mac_ocp_write(tp, 0xe0d6, data);
6406
6407 data = r8168_mac_ocp_read(tp, 0xd420);
6408 data &= ~0x0fff;
6409 data |= 0x047f;
6410 r8168_mac_ocp_write(tp, 0xd420, data);
6411
6412 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
6413 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
6414 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
6415 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
6416 }
6417
6418 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
6419 {
6420 void __iomem *ioaddr = tp->mmio_addr;
6421 struct pci_dev *pdev = tp->pci_dev;
6422
6423 rtl8168ep_stop_cmac(tp);
6424
6425 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6426
6427 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6428 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
6429 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
6430 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6431
6432 rtl_csi_access_enable_1(tp);
6433
6434 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6435
6436 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6437 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6438
6439 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
6440
6441 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6442
6443 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6444 RTL_W8(MaxTxPacketSize, EarlySize);
6445
6446 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6447 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6448
6449 /* Adjust EEE LED frequency */
6450 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6451
6452 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
6453
6454 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
6455
6456 rtl_pcie_state_l2l3_enable(tp, false);
6457 }
6458
6459 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
6460 {
6461 void __iomem *ioaddr = tp->mmio_addr;
6462 static const struct ephy_info e_info_8168ep_1[] = {
6463 { 0x00, 0xffff, 0x10ab },
6464 { 0x06, 0xffff, 0xf030 },
6465 { 0x08, 0xffff, 0x2006 },
6466 { 0x0d, 0xffff, 0x1666 },
6467 { 0x0c, 0x3ff0, 0x0000 }
6468 };
6469
6470 /* disable aspm and clock request before access ephy */
6471 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6472 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6473 rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
6474
6475 rtl_hw_start_8168ep(tp);
6476 }
6477
6478 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
6479 {
6480 void __iomem *ioaddr = tp->mmio_addr;
6481 static const struct ephy_info e_info_8168ep_2[] = {
6482 { 0x00, 0xffff, 0x10a3 },
6483 { 0x19, 0xffff, 0xfc00 },
6484 { 0x1e, 0xffff, 0x20ea }
6485 };
6486
6487 /* disable aspm and clock request before access ephy */
6488 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6489 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6490 rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
6491
6492 rtl_hw_start_8168ep(tp);
6493
6494 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6495 RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6496 }
6497
6498 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
6499 {
6500 void __iomem *ioaddr = tp->mmio_addr;
6501 u32 data;
6502 static const struct ephy_info e_info_8168ep_3[] = {
6503 { 0x00, 0xffff, 0x10a3 },
6504 { 0x19, 0xffff, 0x7c00 },
6505 { 0x1e, 0xffff, 0x20eb },
6506 { 0x0d, 0xffff, 0x1666 }
6507 };
6508
6509 /* disable aspm and clock request before access ephy */
6510 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6511 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6512 rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
6513
6514 rtl_hw_start_8168ep(tp);
6515
6516 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6517 RTL_W8(MISC_1, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6518
6519 data = r8168_mac_ocp_read(tp, 0xd3e2);
6520 data &= 0xf000;
6521 data |= 0x0271;
6522 r8168_mac_ocp_write(tp, 0xd3e2, data);
6523
6524 data = r8168_mac_ocp_read(tp, 0xd3e4);
6525 data &= 0xff00;
6526 r8168_mac_ocp_write(tp, 0xd3e4, data);
6527
6528 data = r8168_mac_ocp_read(tp, 0xe860);
6529 data |= 0x0080;
6530 r8168_mac_ocp_write(tp, 0xe860, data);
6531 }
6532
6533 static void rtl_hw_start_8168(struct net_device *dev)
6534 {
6535 struct rtl8169_private *tp = netdev_priv(dev);
6536 void __iomem *ioaddr = tp->mmio_addr;
6537
6538 RTL_W8(Cfg9346, Cfg9346_Unlock);
6539
6540 RTL_W8(MaxTxPacketSize, TxPacketMax);
6541
6542 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
6543
6544 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
6545
6546 RTL_W16(CPlusCmd, tp->cp_cmd);
6547
6548 RTL_W16(IntrMitigate, 0x5151);
6549
6550 /* Work around for RxFIFO overflow. */
6551 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
6552 tp->event_slow |= RxFIFOOver | PCSTimeout;
6553 tp->event_slow &= ~RxOverflow;
6554 }
6555
6556 rtl_set_rx_tx_desc_registers(tp, ioaddr);
6557
6558 rtl_set_rx_tx_config_registers(tp);
6559
6560 RTL_R8(IntrMask);
6561
6562 switch (tp->mac_version) {
6563 case RTL_GIGA_MAC_VER_11:
6564 rtl_hw_start_8168bb(tp);
6565 break;
6566
6567 case RTL_GIGA_MAC_VER_12:
6568 case RTL_GIGA_MAC_VER_17:
6569 rtl_hw_start_8168bef(tp);
6570 break;
6571
6572 case RTL_GIGA_MAC_VER_18:
6573 rtl_hw_start_8168cp_1(tp);
6574 break;
6575
6576 case RTL_GIGA_MAC_VER_19:
6577 rtl_hw_start_8168c_1(tp);
6578 break;
6579
6580 case RTL_GIGA_MAC_VER_20:
6581 rtl_hw_start_8168c_2(tp);
6582 break;
6583
6584 case RTL_GIGA_MAC_VER_21:
6585 rtl_hw_start_8168c_3(tp);
6586 break;
6587
6588 case RTL_GIGA_MAC_VER_22:
6589 rtl_hw_start_8168c_4(tp);
6590 break;
6591
6592 case RTL_GIGA_MAC_VER_23:
6593 rtl_hw_start_8168cp_2(tp);
6594 break;
6595
6596 case RTL_GIGA_MAC_VER_24:
6597 rtl_hw_start_8168cp_3(tp);
6598 break;
6599
6600 case RTL_GIGA_MAC_VER_25:
6601 case RTL_GIGA_MAC_VER_26:
6602 case RTL_GIGA_MAC_VER_27:
6603 rtl_hw_start_8168d(tp);
6604 break;
6605
6606 case RTL_GIGA_MAC_VER_28:
6607 rtl_hw_start_8168d_4(tp);
6608 break;
6609
6610 case RTL_GIGA_MAC_VER_31:
6611 rtl_hw_start_8168dp(tp);
6612 break;
6613
6614 case RTL_GIGA_MAC_VER_32:
6615 case RTL_GIGA_MAC_VER_33:
6616 rtl_hw_start_8168e_1(tp);
6617 break;
6618 case RTL_GIGA_MAC_VER_34:
6619 rtl_hw_start_8168e_2(tp);
6620 break;
6621
6622 case RTL_GIGA_MAC_VER_35:
6623 case RTL_GIGA_MAC_VER_36:
6624 rtl_hw_start_8168f_1(tp);
6625 break;
6626
6627 case RTL_GIGA_MAC_VER_38:
6628 rtl_hw_start_8411(tp);
6629 break;
6630
6631 case RTL_GIGA_MAC_VER_40:
6632 case RTL_GIGA_MAC_VER_41:
6633 rtl_hw_start_8168g_1(tp);
6634 break;
6635 case RTL_GIGA_MAC_VER_42:
6636 rtl_hw_start_8168g_2(tp);
6637 break;
6638
6639 case RTL_GIGA_MAC_VER_44:
6640 rtl_hw_start_8411_2(tp);
6641 break;
6642
6643 case RTL_GIGA_MAC_VER_45:
6644 case RTL_GIGA_MAC_VER_46:
6645 rtl_hw_start_8168h_1(tp);
6646 break;
6647
6648 case RTL_GIGA_MAC_VER_49:
6649 rtl_hw_start_8168ep_1(tp);
6650 break;
6651
6652 case RTL_GIGA_MAC_VER_50:
6653 rtl_hw_start_8168ep_2(tp);
6654 break;
6655
6656 case RTL_GIGA_MAC_VER_51:
6657 rtl_hw_start_8168ep_3(tp);
6658 break;
6659
6660 default:
6661 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
6662 dev->name, tp->mac_version);
6663 break;
6664 }
6665
6666 RTL_W8(Cfg9346, Cfg9346_Lock);
6667
6668 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
6669
6670 rtl_set_rx_mode(dev);
6671
6672 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6673 }
6674
6675 #define R810X_CPCMD_QUIRK_MASK (\
6676 EnableBist | \
6677 Mac_dbgo_oe | \
6678 Force_half_dup | \
6679 Force_rxflow_en | \
6680 Force_txflow_en | \
6681 Cxpl_dbg_sel | \
6682 ASF | \
6683 PktCntrDisable | \
6684 Mac_dbgo_sel)
6685
6686 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
6687 {
6688 void __iomem *ioaddr = tp->mmio_addr;
6689 struct pci_dev *pdev = tp->pci_dev;
6690 static const struct ephy_info e_info_8102e_1[] = {
6691 { 0x01, 0, 0x6e65 },
6692 { 0x02, 0, 0x091f },
6693 { 0x03, 0, 0xc2f9 },
6694 { 0x06, 0, 0xafb5 },
6695 { 0x07, 0, 0x0e00 },
6696 { 0x19, 0, 0xec80 },
6697 { 0x01, 0, 0x2e65 },
6698 { 0x01, 0, 0x6e65 }
6699 };
6700 u8 cfg1;
6701
6702 rtl_csi_access_enable_2(tp);
6703
6704 RTL_W8(DBG_REG, FIX_NAK_1);
6705
6706 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6707
6708 RTL_W8(Config1,
6709 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
6710 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
6711
6712 cfg1 = RTL_R8(Config1);
6713 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
6714 RTL_W8(Config1, cfg1 & ~LEDS0);
6715
6716 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
6717 }
6718
6719 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
6720 {
6721 void __iomem *ioaddr = tp->mmio_addr;
6722 struct pci_dev *pdev = tp->pci_dev;
6723
6724 rtl_csi_access_enable_2(tp);
6725
6726 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6727
6728 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
6729 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
6730 }
6731
6732 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
6733 {
6734 rtl_hw_start_8102e_2(tp);
6735
6736 rtl_ephy_write(tp, 0x03, 0xc2f9);
6737 }
6738
6739 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
6740 {
6741 void __iomem *ioaddr = tp->mmio_addr;
6742 static const struct ephy_info e_info_8105e_1[] = {
6743 { 0x07, 0, 0x4000 },
6744 { 0x19, 0, 0x0200 },
6745 { 0x19, 0, 0x0020 },
6746 { 0x1e, 0, 0x2000 },
6747 { 0x03, 0, 0x0001 },
6748 { 0x19, 0, 0x0100 },
6749 { 0x19, 0, 0x0004 },
6750 { 0x0a, 0, 0x0020 }
6751 };
6752
6753 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6754 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6755
6756 /* Disable Early Tally Counter */
6757 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
6758
6759 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
6760 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
6761
6762 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
6763
6764 rtl_pcie_state_l2l3_enable(tp, false);
6765 }
6766
6767 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
6768 {
6769 rtl_hw_start_8105e_1(tp);
6770 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
6771 }
6772
6773 static void rtl_hw_start_8402(struct rtl8169_private *tp)
6774 {
6775 void __iomem *ioaddr = tp->mmio_addr;
6776 static const struct ephy_info e_info_8402[] = {
6777 { 0x19, 0xffff, 0xff64 },
6778 { 0x1e, 0, 0x4000 }
6779 };
6780
6781 rtl_csi_access_enable_2(tp);
6782
6783 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6784 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6785
6786 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6787 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6788
6789 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
6790
6791 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
6792
6793 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
6794 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
6795 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6796 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6797 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6798 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6799 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
6800
6801 rtl_pcie_state_l2l3_enable(tp, false);
6802 }
6803
6804 static void rtl_hw_start_8106(struct rtl8169_private *tp)
6805 {
6806 void __iomem *ioaddr = tp->mmio_addr;
6807
6808 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6809 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6810
6811 RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
6812 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
6813 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6814
6815 rtl_pcie_state_l2l3_enable(tp, false);
6816 }
6817
6818 static void rtl_hw_start_8101(struct net_device *dev)
6819 {
6820 struct rtl8169_private *tp = netdev_priv(dev);
6821 void __iomem *ioaddr = tp->mmio_addr;
6822 struct pci_dev *pdev = tp->pci_dev;
6823
6824 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
6825 tp->event_slow &= ~RxFIFOOver;
6826
6827 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
6828 tp->mac_version == RTL_GIGA_MAC_VER_16)
6829 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
6830 PCI_EXP_DEVCTL_NOSNOOP_EN);
6831
6832 RTL_W8(Cfg9346, Cfg9346_Unlock);
6833
6834 RTL_W8(MaxTxPacketSize, TxPacketMax);
6835
6836 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
6837
6838 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
6839 RTL_W16(CPlusCmd, tp->cp_cmd);
6840
6841 rtl_set_rx_tx_desc_registers(tp, ioaddr);
6842
6843 rtl_set_rx_tx_config_registers(tp);
6844
6845 switch (tp->mac_version) {
6846 case RTL_GIGA_MAC_VER_07:
6847 rtl_hw_start_8102e_1(tp);
6848 break;
6849
6850 case RTL_GIGA_MAC_VER_08:
6851 rtl_hw_start_8102e_3(tp);
6852 break;
6853
6854 case RTL_GIGA_MAC_VER_09:
6855 rtl_hw_start_8102e_2(tp);
6856 break;
6857
6858 case RTL_GIGA_MAC_VER_29:
6859 rtl_hw_start_8105e_1(tp);
6860 break;
6861 case RTL_GIGA_MAC_VER_30:
6862 rtl_hw_start_8105e_2(tp);
6863 break;
6864
6865 case RTL_GIGA_MAC_VER_37:
6866 rtl_hw_start_8402(tp);
6867 break;
6868
6869 case RTL_GIGA_MAC_VER_39:
6870 rtl_hw_start_8106(tp);
6871 break;
6872 case RTL_GIGA_MAC_VER_43:
6873 rtl_hw_start_8168g_2(tp);
6874 break;
6875 case RTL_GIGA_MAC_VER_47:
6876 case RTL_GIGA_MAC_VER_48:
6877 rtl_hw_start_8168h_1(tp);
6878 break;
6879 }
6880
6881 RTL_W8(Cfg9346, Cfg9346_Lock);
6882
6883 RTL_W16(IntrMitigate, 0x0000);
6884
6885 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
6886
6887 rtl_set_rx_mode(dev);
6888
6889 RTL_R8(IntrMask);
6890
6891 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6892 }
6893
6894 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
6895 {
6896 struct rtl8169_private *tp = netdev_priv(dev);
6897
6898 if (new_mtu > ETH_DATA_LEN)
6899 rtl_hw_jumbo_enable(tp);
6900 else
6901 rtl_hw_jumbo_disable(tp);
6902
6903 dev->mtu = new_mtu;
6904 netdev_update_features(dev);
6905
6906 return 0;
6907 }
6908
6909 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
6910 {
6911 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
6912 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
6913 }
6914
6915 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
6916 void **data_buff, struct RxDesc *desc)
6917 {
6918 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
6919 DMA_FROM_DEVICE);
6920
6921 kfree(*data_buff);
6922 *data_buff = NULL;
6923 rtl8169_make_unusable_by_asic(desc);
6924 }
6925
6926 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
6927 {
6928 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
6929
6930 /* Force memory writes to complete before releasing descriptor */
6931 dma_wmb();
6932
6933 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
6934 }
6935
6936 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
6937 u32 rx_buf_sz)
6938 {
6939 desc->addr = cpu_to_le64(mapping);
6940 rtl8169_mark_to_asic(desc, rx_buf_sz);
6941 }
6942
6943 static inline void *rtl8169_align(void *data)
6944 {
6945 return (void *)ALIGN((long)data, 16);
6946 }
6947
6948 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
6949 struct RxDesc *desc)
6950 {
6951 void *data;
6952 dma_addr_t mapping;
6953 struct device *d = &tp->pci_dev->dev;
6954 struct net_device *dev = tp->dev;
6955 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
6956
6957 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
6958 if (!data)
6959 return NULL;
6960
6961 if (rtl8169_align(data) != data) {
6962 kfree(data);
6963 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
6964 if (!data)
6965 return NULL;
6966 }
6967
6968 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
6969 DMA_FROM_DEVICE);
6970 if (unlikely(dma_mapping_error(d, mapping))) {
6971 if (net_ratelimit())
6972 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
6973 goto err_out;
6974 }
6975
6976 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6977 return data;
6978
6979 err_out:
6980 kfree(data);
6981 return NULL;
6982 }
6983
6984 static void rtl8169_rx_clear(struct rtl8169_private *tp)
6985 {
6986 unsigned int i;
6987
6988 for (i = 0; i < NUM_RX_DESC; i++) {
6989 if (tp->Rx_databuff[i]) {
6990 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
6991 tp->RxDescArray + i);
6992 }
6993 }
6994 }
6995
6996 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
6997 {
6998 desc->opts1 |= cpu_to_le32(RingEnd);
6999 }
7000
7001 static int rtl8169_rx_fill(struct rtl8169_private *tp)
7002 {
7003 unsigned int i;
7004
7005 for (i = 0; i < NUM_RX_DESC; i++) {
7006 void *data;
7007
7008 if (tp->Rx_databuff[i])
7009 continue;
7010
7011 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
7012 if (!data) {
7013 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
7014 goto err_out;
7015 }
7016 tp->Rx_databuff[i] = data;
7017 }
7018
7019 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
7020 return 0;
7021
7022 err_out:
7023 rtl8169_rx_clear(tp);
7024 return -ENOMEM;
7025 }
7026
7027 static int rtl8169_init_ring(struct net_device *dev)
7028 {
7029 struct rtl8169_private *tp = netdev_priv(dev);
7030
7031 rtl8169_init_ring_indexes(tp);
7032
7033 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
7034 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
7035
7036 return rtl8169_rx_fill(tp);
7037 }
7038
7039 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
7040 struct TxDesc *desc)
7041 {
7042 unsigned int len = tx_skb->len;
7043
7044 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
7045
7046 desc->opts1 = 0x00;
7047 desc->opts2 = 0x00;
7048 desc->addr = 0x00;
7049 tx_skb->len = 0;
7050 }
7051
7052 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
7053 unsigned int n)
7054 {
7055 unsigned int i;
7056
7057 for (i = 0; i < n; i++) {
7058 unsigned int entry = (start + i) % NUM_TX_DESC;
7059 struct ring_info *tx_skb = tp->tx_skb + entry;
7060 unsigned int len = tx_skb->len;
7061
7062 if (len) {
7063 struct sk_buff *skb = tx_skb->skb;
7064
7065 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
7066 tp->TxDescArray + entry);
7067 if (skb) {
7068 dev_consume_skb_any(skb);
7069 tx_skb->skb = NULL;
7070 }
7071 }
7072 }
7073 }
7074
7075 static void rtl8169_tx_clear(struct rtl8169_private *tp)
7076 {
7077 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
7078 tp->cur_tx = tp->dirty_tx = 0;
7079 }
7080
7081 static void rtl_reset_work(struct rtl8169_private *tp)
7082 {
7083 struct net_device *dev = tp->dev;
7084 int i;
7085
7086 napi_disable(&tp->napi);
7087 netif_stop_queue(dev);
7088 synchronize_sched();
7089
7090 rtl8169_hw_reset(tp);
7091
7092 for (i = 0; i < NUM_RX_DESC; i++)
7093 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
7094
7095 rtl8169_tx_clear(tp);
7096 rtl8169_init_ring_indexes(tp);
7097
7098 napi_enable(&tp->napi);
7099 rtl_hw_start(dev);
7100 netif_wake_queue(dev);
7101 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
7102 }
7103
7104 static void rtl8169_tx_timeout(struct net_device *dev)
7105 {
7106 struct rtl8169_private *tp = netdev_priv(dev);
7107
7108 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7109 }
7110
7111 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
7112 u32 *opts)
7113 {
7114 struct skb_shared_info *info = skb_shinfo(skb);
7115 unsigned int cur_frag, entry;
7116 struct TxDesc *uninitialized_var(txd);
7117 struct device *d = &tp->pci_dev->dev;
7118
7119 entry = tp->cur_tx;
7120 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
7121 const skb_frag_t *frag = info->frags + cur_frag;
7122 dma_addr_t mapping;
7123 u32 status, len;
7124 void *addr;
7125
7126 entry = (entry + 1) % NUM_TX_DESC;
7127
7128 txd = tp->TxDescArray + entry;
7129 len = skb_frag_size(frag);
7130 addr = skb_frag_address(frag);
7131 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
7132 if (unlikely(dma_mapping_error(d, mapping))) {
7133 if (net_ratelimit())
7134 netif_err(tp, drv, tp->dev,
7135 "Failed to map TX fragments DMA!\n");
7136 goto err_out;
7137 }
7138
7139 /* Anti gcc 2.95.3 bugware (sic) */
7140 status = opts[0] | len |
7141 (RingEnd * !((entry + 1) % NUM_TX_DESC));
7142
7143 txd->opts1 = cpu_to_le32(status);
7144 txd->opts2 = cpu_to_le32(opts[1]);
7145 txd->addr = cpu_to_le64(mapping);
7146
7147 tp->tx_skb[entry].len = len;
7148 }
7149
7150 if (cur_frag) {
7151 tp->tx_skb[entry].skb = skb;
7152 txd->opts1 |= cpu_to_le32(LastFrag);
7153 }
7154
7155 return cur_frag;
7156
7157 err_out:
7158 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
7159 return -EIO;
7160 }
7161
7162 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
7163 {
7164 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
7165 }
7166
7167 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
7168 struct net_device *dev);
7169 /* r8169_csum_workaround()
7170 * The hw limites the value the transport offset. When the offset is out of the
7171 * range, calculate the checksum by sw.
7172 */
7173 static void r8169_csum_workaround(struct rtl8169_private *tp,
7174 struct sk_buff *skb)
7175 {
7176 if (skb_shinfo(skb)->gso_size) {
7177 netdev_features_t features = tp->dev->features;
7178 struct sk_buff *segs, *nskb;
7179
7180 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
7181 segs = skb_gso_segment(skb, features);
7182 if (IS_ERR(segs) || !segs)
7183 goto drop;
7184
7185 do {
7186 nskb = segs;
7187 segs = segs->next;
7188 nskb->next = NULL;
7189 rtl8169_start_xmit(nskb, tp->dev);
7190 } while (segs);
7191
7192 dev_consume_skb_any(skb);
7193 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
7194 if (skb_checksum_help(skb) < 0)
7195 goto drop;
7196
7197 rtl8169_start_xmit(skb, tp->dev);
7198 } else {
7199 struct net_device_stats *stats;
7200
7201 drop:
7202 stats = &tp->dev->stats;
7203 stats->tx_dropped++;
7204 dev_kfree_skb_any(skb);
7205 }
7206 }
7207
7208 /* msdn_giant_send_check()
7209 * According to the document of microsoft, the TCP Pseudo Header excludes the
7210 * packet length for IPv6 TCP large packets.
7211 */
7212 static int msdn_giant_send_check(struct sk_buff *skb)
7213 {
7214 const struct ipv6hdr *ipv6h;
7215 struct tcphdr *th;
7216 int ret;
7217
7218 ret = skb_cow_head(skb, 0);
7219 if (ret)
7220 return ret;
7221
7222 ipv6h = ipv6_hdr(skb);
7223 th = tcp_hdr(skb);
7224
7225 th->check = 0;
7226 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
7227
7228 return ret;
7229 }
7230
7231 static inline __be16 get_protocol(struct sk_buff *skb)
7232 {
7233 __be16 protocol;
7234
7235 if (skb->protocol == htons(ETH_P_8021Q))
7236 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
7237 else
7238 protocol = skb->protocol;
7239
7240 return protocol;
7241 }
7242
7243 static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
7244 struct sk_buff *skb, u32 *opts)
7245 {
7246 u32 mss = skb_shinfo(skb)->gso_size;
7247
7248 if (mss) {
7249 opts[0] |= TD_LSO;
7250 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
7251 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
7252 const struct iphdr *ip = ip_hdr(skb);
7253
7254 if (ip->protocol == IPPROTO_TCP)
7255 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
7256 else if (ip->protocol == IPPROTO_UDP)
7257 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
7258 else
7259 WARN_ON_ONCE(1);
7260 }
7261
7262 return true;
7263 }
7264
7265 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
7266 struct sk_buff *skb, u32 *opts)
7267 {
7268 u32 transport_offset = (u32)skb_transport_offset(skb);
7269 u32 mss = skb_shinfo(skb)->gso_size;
7270
7271 if (mss) {
7272 if (transport_offset > GTTCPHO_MAX) {
7273 netif_warn(tp, tx_err, tp->dev,
7274 "Invalid transport offset 0x%x for TSO\n",
7275 transport_offset);
7276 return false;
7277 }
7278
7279 switch (get_protocol(skb)) {
7280 case htons(ETH_P_IP):
7281 opts[0] |= TD1_GTSENV4;
7282 break;
7283
7284 case htons(ETH_P_IPV6):
7285 if (msdn_giant_send_check(skb))
7286 return false;
7287
7288 opts[0] |= TD1_GTSENV6;
7289 break;
7290
7291 default:
7292 WARN_ON_ONCE(1);
7293 break;
7294 }
7295
7296 opts[0] |= transport_offset << GTTCPHO_SHIFT;
7297 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
7298 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
7299 u8 ip_protocol;
7300
7301 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
7302 return !(skb_checksum_help(skb) || eth_skb_pad(skb));
7303
7304 if (transport_offset > TCPHO_MAX) {
7305 netif_warn(tp, tx_err, tp->dev,
7306 "Invalid transport offset 0x%x\n",
7307 transport_offset);
7308 return false;
7309 }
7310
7311 switch (get_protocol(skb)) {
7312 case htons(ETH_P_IP):
7313 opts[1] |= TD1_IPv4_CS;
7314 ip_protocol = ip_hdr(skb)->protocol;
7315 break;
7316
7317 case htons(ETH_P_IPV6):
7318 opts[1] |= TD1_IPv6_CS;
7319 ip_protocol = ipv6_hdr(skb)->nexthdr;
7320 break;
7321
7322 default:
7323 ip_protocol = IPPROTO_RAW;
7324 break;
7325 }
7326
7327 if (ip_protocol == IPPROTO_TCP)
7328 opts[1] |= TD1_TCP_CS;
7329 else if (ip_protocol == IPPROTO_UDP)
7330 opts[1] |= TD1_UDP_CS;
7331 else
7332 WARN_ON_ONCE(1);
7333
7334 opts[1] |= transport_offset << TCPHO_SHIFT;
7335 } else {
7336 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
7337 return !eth_skb_pad(skb);
7338 }
7339
7340 return true;
7341 }
7342
7343 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
7344 struct net_device *dev)
7345 {
7346 struct rtl8169_private *tp = netdev_priv(dev);
7347 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
7348 struct TxDesc *txd = tp->TxDescArray + entry;
7349 void __iomem *ioaddr = tp->mmio_addr;
7350 struct device *d = &tp->pci_dev->dev;
7351 dma_addr_t mapping;
7352 u32 status, len;
7353 u32 opts[2];
7354 int frags;
7355
7356 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
7357 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
7358 goto err_stop_0;
7359 }
7360
7361 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
7362 goto err_stop_0;
7363
7364 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
7365 opts[0] = DescOwn;
7366
7367 if (!tp->tso_csum(tp, skb, opts)) {
7368 r8169_csum_workaround(tp, skb);
7369 return NETDEV_TX_OK;
7370 }
7371
7372 len = skb_headlen(skb);
7373 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
7374 if (unlikely(dma_mapping_error(d, mapping))) {
7375 if (net_ratelimit())
7376 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
7377 goto err_dma_0;
7378 }
7379
7380 tp->tx_skb[entry].len = len;
7381 txd->addr = cpu_to_le64(mapping);
7382
7383 frags = rtl8169_xmit_frags(tp, skb, opts);
7384 if (frags < 0)
7385 goto err_dma_1;
7386 else if (frags)
7387 opts[0] |= FirstFrag;
7388 else {
7389 opts[0] |= FirstFrag | LastFrag;
7390 tp->tx_skb[entry].skb = skb;
7391 }
7392
7393 txd->opts2 = cpu_to_le32(opts[1]);
7394
7395 skb_tx_timestamp(skb);
7396
7397 /* Force memory writes to complete before releasing descriptor */
7398 dma_wmb();
7399
7400 /* Anti gcc 2.95.3 bugware (sic) */
7401 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
7402 txd->opts1 = cpu_to_le32(status);
7403
7404 /* Force all memory writes to complete before notifying device */
7405 wmb();
7406
7407 tp->cur_tx += frags + 1;
7408
7409 RTL_W8(TxPoll, NPQ);
7410
7411 mmiowb();
7412
7413 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
7414 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
7415 * not miss a ring update when it notices a stopped queue.
7416 */
7417 smp_wmb();
7418 netif_stop_queue(dev);
7419 /* Sync with rtl_tx:
7420 * - publish queue status and cur_tx ring index (write barrier)
7421 * - refresh dirty_tx ring index (read barrier).
7422 * May the current thread have a pessimistic view of the ring
7423 * status and forget to wake up queue, a racing rtl_tx thread
7424 * can't.
7425 */
7426 smp_mb();
7427 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
7428 netif_wake_queue(dev);
7429 }
7430
7431 return NETDEV_TX_OK;
7432
7433 err_dma_1:
7434 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
7435 err_dma_0:
7436 dev_kfree_skb_any(skb);
7437 dev->stats.tx_dropped++;
7438 return NETDEV_TX_OK;
7439
7440 err_stop_0:
7441 netif_stop_queue(dev);
7442 dev->stats.tx_dropped++;
7443 return NETDEV_TX_BUSY;
7444 }
7445
7446 static void rtl8169_pcierr_interrupt(struct net_device *dev)
7447 {
7448 struct rtl8169_private *tp = netdev_priv(dev);
7449 struct pci_dev *pdev = tp->pci_dev;
7450 u16 pci_status, pci_cmd;
7451
7452 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
7453 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
7454
7455 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
7456 pci_cmd, pci_status);
7457
7458 /*
7459 * The recovery sequence below admits a very elaborated explanation:
7460 * - it seems to work;
7461 * - I did not see what else could be done;
7462 * - it makes iop3xx happy.
7463 *
7464 * Feel free to adjust to your needs.
7465 */
7466 if (pdev->broken_parity_status)
7467 pci_cmd &= ~PCI_COMMAND_PARITY;
7468 else
7469 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
7470
7471 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
7472
7473 pci_write_config_word(pdev, PCI_STATUS,
7474 pci_status & (PCI_STATUS_DETECTED_PARITY |
7475 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
7476 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
7477
7478 /* The infamous DAC f*ckup only happens at boot time */
7479 if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
7480 void __iomem *ioaddr = tp->mmio_addr;
7481
7482 netif_info(tp, intr, dev, "disabling PCI DAC\n");
7483 tp->cp_cmd &= ~PCIDAC;
7484 RTL_W16(CPlusCmd, tp->cp_cmd);
7485 dev->features &= ~NETIF_F_HIGHDMA;
7486 }
7487
7488 rtl8169_hw_reset(tp);
7489
7490 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7491 }
7492
7493 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
7494 {
7495 unsigned int dirty_tx, tx_left;
7496
7497 dirty_tx = tp->dirty_tx;
7498 smp_rmb();
7499 tx_left = tp->cur_tx - dirty_tx;
7500
7501 while (tx_left > 0) {
7502 unsigned int entry = dirty_tx % NUM_TX_DESC;
7503 struct ring_info *tx_skb = tp->tx_skb + entry;
7504 u32 status;
7505
7506 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
7507 if (status & DescOwn)
7508 break;
7509
7510 /* This barrier is needed to keep us from reading
7511 * any other fields out of the Tx descriptor until
7512 * we know the status of DescOwn
7513 */
7514 dma_rmb();
7515
7516 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
7517 tp->TxDescArray + entry);
7518 if (status & LastFrag) {
7519 u64_stats_update_begin(&tp->tx_stats.syncp);
7520 tp->tx_stats.packets++;
7521 tp->tx_stats.bytes += tx_skb->skb->len;
7522 u64_stats_update_end(&tp->tx_stats.syncp);
7523 dev_consume_skb_any(tx_skb->skb);
7524 tx_skb->skb = NULL;
7525 }
7526 dirty_tx++;
7527 tx_left--;
7528 }
7529
7530 if (tp->dirty_tx != dirty_tx) {
7531 tp->dirty_tx = dirty_tx;
7532 /* Sync with rtl8169_start_xmit:
7533 * - publish dirty_tx ring index (write barrier)
7534 * - refresh cur_tx ring index and queue status (read barrier)
7535 * May the current thread miss the stopped queue condition,
7536 * a racing xmit thread can only have a right view of the
7537 * ring status.
7538 */
7539 smp_mb();
7540 if (netif_queue_stopped(dev) &&
7541 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
7542 netif_wake_queue(dev);
7543 }
7544 /*
7545 * 8168 hack: TxPoll requests are lost when the Tx packets are
7546 * too close. Let's kick an extra TxPoll request when a burst
7547 * of start_xmit activity is detected (if it is not detected,
7548 * it is slow enough). -- FR
7549 */
7550 if (tp->cur_tx != dirty_tx) {
7551 void __iomem *ioaddr = tp->mmio_addr;
7552
7553 RTL_W8(TxPoll, NPQ);
7554 }
7555 }
7556 }
7557
7558 static inline int rtl8169_fragmented_frame(u32 status)
7559 {
7560 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
7561 }
7562
7563 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
7564 {
7565 u32 status = opts1 & RxProtoMask;
7566
7567 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
7568 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
7569 skb->ip_summed = CHECKSUM_UNNECESSARY;
7570 else
7571 skb_checksum_none_assert(skb);
7572 }
7573
7574 static struct sk_buff *rtl8169_try_rx_copy(void *data,
7575 struct rtl8169_private *tp,
7576 int pkt_size,
7577 dma_addr_t addr)
7578 {
7579 struct sk_buff *skb;
7580 struct device *d = &tp->pci_dev->dev;
7581
7582 data = rtl8169_align(data);
7583 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
7584 prefetch(data);
7585 skb = napi_alloc_skb(&tp->napi, pkt_size);
7586 if (skb)
7587 memcpy(skb->data, data, pkt_size);
7588 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
7589
7590 return skb;
7591 }
7592
7593 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
7594 {
7595 unsigned int cur_rx, rx_left;
7596 unsigned int count;
7597
7598 cur_rx = tp->cur_rx;
7599
7600 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
7601 unsigned int entry = cur_rx % NUM_RX_DESC;
7602 struct RxDesc *desc = tp->RxDescArray + entry;
7603 u32 status;
7604
7605 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
7606 if (status & DescOwn)
7607 break;
7608
7609 /* This barrier is needed to keep us from reading
7610 * any other fields out of the Rx descriptor until
7611 * we know the status of DescOwn
7612 */
7613 dma_rmb();
7614
7615 if (unlikely(status & RxRES)) {
7616 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
7617 status);
7618 dev->stats.rx_errors++;
7619 if (status & (RxRWT | RxRUNT))
7620 dev->stats.rx_length_errors++;
7621 if (status & RxCRC)
7622 dev->stats.rx_crc_errors++;
7623 if (status & RxFOVF) {
7624 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7625 dev->stats.rx_fifo_errors++;
7626 }
7627 if ((status & (RxRUNT | RxCRC)) &&
7628 !(status & (RxRWT | RxFOVF)) &&
7629 (dev->features & NETIF_F_RXALL))
7630 goto process_pkt;
7631 } else {
7632 struct sk_buff *skb;
7633 dma_addr_t addr;
7634 int pkt_size;
7635
7636 process_pkt:
7637 addr = le64_to_cpu(desc->addr);
7638 if (likely(!(dev->features & NETIF_F_RXFCS)))
7639 pkt_size = (status & 0x00003fff) - 4;
7640 else
7641 pkt_size = status & 0x00003fff;
7642
7643 /*
7644 * The driver does not support incoming fragmented
7645 * frames. They are seen as a symptom of over-mtu
7646 * sized frames.
7647 */
7648 if (unlikely(rtl8169_fragmented_frame(status))) {
7649 dev->stats.rx_dropped++;
7650 dev->stats.rx_length_errors++;
7651 goto release_descriptor;
7652 }
7653
7654 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
7655 tp, pkt_size, addr);
7656 if (!skb) {
7657 dev->stats.rx_dropped++;
7658 goto release_descriptor;
7659 }
7660
7661 rtl8169_rx_csum(skb, status);
7662 skb_put(skb, pkt_size);
7663 skb->protocol = eth_type_trans(skb, dev);
7664
7665 rtl8169_rx_vlan_tag(desc, skb);
7666
7667 if (skb->pkt_type == PACKET_MULTICAST)
7668 dev->stats.multicast++;
7669
7670 napi_gro_receive(&tp->napi, skb);
7671
7672 u64_stats_update_begin(&tp->rx_stats.syncp);
7673 tp->rx_stats.packets++;
7674 tp->rx_stats.bytes += pkt_size;
7675 u64_stats_update_end(&tp->rx_stats.syncp);
7676 }
7677 release_descriptor:
7678 desc->opts2 = 0;
7679 rtl8169_mark_to_asic(desc, rx_buf_sz);
7680 }
7681
7682 count = cur_rx - tp->cur_rx;
7683 tp->cur_rx = cur_rx;
7684
7685 return count;
7686 }
7687
7688 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
7689 {
7690 struct net_device *dev = dev_instance;
7691 struct rtl8169_private *tp = netdev_priv(dev);
7692 int handled = 0;
7693 u16 status;
7694
7695 status = rtl_get_events(tp);
7696 if (status && status != 0xffff) {
7697 status &= RTL_EVENT_NAPI | tp->event_slow;
7698 if (status) {
7699 handled = 1;
7700
7701 rtl_irq_disable(tp);
7702 napi_schedule(&tp->napi);
7703 }
7704 }
7705 return IRQ_RETVAL(handled);
7706 }
7707
7708 /*
7709 * Workqueue context.
7710 */
7711 static void rtl_slow_event_work(struct rtl8169_private *tp)
7712 {
7713 struct net_device *dev = tp->dev;
7714 u16 status;
7715
7716 status = rtl_get_events(tp) & tp->event_slow;
7717 rtl_ack_events(tp, status);
7718
7719 if (unlikely(status & RxFIFOOver)) {
7720 switch (tp->mac_version) {
7721 /* Work around for rx fifo overflow */
7722 case RTL_GIGA_MAC_VER_11:
7723 netif_stop_queue(dev);
7724 /* XXX - Hack alert. See rtl_task(). */
7725 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
7726 default:
7727 break;
7728 }
7729 }
7730
7731 if (unlikely(status & SYSErr))
7732 rtl8169_pcierr_interrupt(dev);
7733
7734 if (status & LinkChg)
7735 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
7736
7737 rtl_irq_enable_all(tp);
7738 }
7739
7740 static void rtl_task(struct work_struct *work)
7741 {
7742 static const struct {
7743 int bitnr;
7744 void (*action)(struct rtl8169_private *);
7745 } rtl_work[] = {
7746 /* XXX - keep rtl_slow_event_work() as first element. */
7747 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
7748 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
7749 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
7750 };
7751 struct rtl8169_private *tp =
7752 container_of(work, struct rtl8169_private, wk.work);
7753 struct net_device *dev = tp->dev;
7754 int i;
7755
7756 rtl_lock_work(tp);
7757
7758 if (!netif_running(dev) ||
7759 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
7760 goto out_unlock;
7761
7762 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
7763 bool pending;
7764
7765 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
7766 if (pending)
7767 rtl_work[i].action(tp);
7768 }
7769
7770 out_unlock:
7771 rtl_unlock_work(tp);
7772 }
7773
7774 static int rtl8169_poll(struct napi_struct *napi, int budget)
7775 {
7776 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
7777 struct net_device *dev = tp->dev;
7778 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
7779 int work_done= 0;
7780 u16 status;
7781
7782 status = rtl_get_events(tp);
7783 rtl_ack_events(tp, status & ~tp->event_slow);
7784
7785 if (status & RTL_EVENT_NAPI_RX)
7786 work_done = rtl_rx(dev, tp, (u32) budget);
7787
7788 if (status & RTL_EVENT_NAPI_TX)
7789 rtl_tx(dev, tp);
7790
7791 if (status & tp->event_slow) {
7792 enable_mask &= ~tp->event_slow;
7793
7794 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
7795 }
7796
7797 if (work_done < budget) {
7798 napi_complete_done(napi, work_done);
7799
7800 rtl_irq_enable(tp, enable_mask);
7801 mmiowb();
7802 }
7803
7804 return work_done;
7805 }
7806
7807 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
7808 {
7809 struct rtl8169_private *tp = netdev_priv(dev);
7810
7811 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
7812 return;
7813
7814 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
7815 RTL_W32(RxMissed, 0);
7816 }
7817
7818 static void rtl8169_down(struct net_device *dev)
7819 {
7820 struct rtl8169_private *tp = netdev_priv(dev);
7821 void __iomem *ioaddr = tp->mmio_addr;
7822
7823 del_timer_sync(&tp->timer);
7824
7825 napi_disable(&tp->napi);
7826 netif_stop_queue(dev);
7827
7828 rtl8169_hw_reset(tp);
7829 /*
7830 * At this point device interrupts can not be enabled in any function,
7831 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
7832 * and napi is disabled (rtl8169_poll).
7833 */
7834 rtl8169_rx_missed(dev, ioaddr);
7835
7836 /* Give a racing hard_start_xmit a few cycles to complete. */
7837 synchronize_sched();
7838
7839 rtl8169_tx_clear(tp);
7840
7841 rtl8169_rx_clear(tp);
7842
7843 rtl_pll_power_down(tp);
7844 }
7845
7846 static int rtl8169_close(struct net_device *dev)
7847 {
7848 struct rtl8169_private *tp = netdev_priv(dev);
7849 struct pci_dev *pdev = tp->pci_dev;
7850
7851 pm_runtime_get_sync(&pdev->dev);
7852
7853 /* Update counters before going down */
7854 rtl8169_update_counters(dev);
7855
7856 rtl_lock_work(tp);
7857 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7858
7859 rtl8169_down(dev);
7860 rtl_unlock_work(tp);
7861
7862 cancel_work_sync(&tp->wk.work);
7863
7864 free_irq(pdev->irq, dev);
7865
7866 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7867 tp->RxPhyAddr);
7868 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7869 tp->TxPhyAddr);
7870 tp->TxDescArray = NULL;
7871 tp->RxDescArray = NULL;
7872
7873 pm_runtime_put_sync(&pdev->dev);
7874
7875 return 0;
7876 }
7877
7878 #ifdef CONFIG_NET_POLL_CONTROLLER
7879 static void rtl8169_netpoll(struct net_device *dev)
7880 {
7881 struct rtl8169_private *tp = netdev_priv(dev);
7882
7883 rtl8169_interrupt(tp->pci_dev->irq, dev);
7884 }
7885 #endif
7886
7887 static int rtl_open(struct net_device *dev)
7888 {
7889 struct rtl8169_private *tp = netdev_priv(dev);
7890 void __iomem *ioaddr = tp->mmio_addr;
7891 struct pci_dev *pdev = tp->pci_dev;
7892 int retval = -ENOMEM;
7893
7894 pm_runtime_get_sync(&pdev->dev);
7895
7896 /*
7897 * Rx and Tx descriptors needs 256 bytes alignment.
7898 * dma_alloc_coherent provides more.
7899 */
7900 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
7901 &tp->TxPhyAddr, GFP_KERNEL);
7902 if (!tp->TxDescArray)
7903 goto err_pm_runtime_put;
7904
7905 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
7906 &tp->RxPhyAddr, GFP_KERNEL);
7907 if (!tp->RxDescArray)
7908 goto err_free_tx_0;
7909
7910 retval = rtl8169_init_ring(dev);
7911 if (retval < 0)
7912 goto err_free_rx_1;
7913
7914 INIT_WORK(&tp->wk.work, rtl_task);
7915
7916 smp_mb();
7917
7918 rtl_request_firmware(tp);
7919
7920 retval = request_irq(pdev->irq, rtl8169_interrupt,
7921 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
7922 dev->name, dev);
7923 if (retval < 0)
7924 goto err_release_fw_2;
7925
7926 rtl_lock_work(tp);
7927
7928 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7929
7930 napi_enable(&tp->napi);
7931
7932 rtl8169_init_phy(dev, tp);
7933
7934 __rtl8169_set_features(dev, dev->features);
7935
7936 rtl_pll_power_up(tp);
7937
7938 rtl_hw_start(dev);
7939
7940 if (!rtl8169_init_counter_offsets(dev))
7941 netif_warn(tp, hw, dev, "counter reset/update failed\n");
7942
7943 netif_start_queue(dev);
7944
7945 rtl_unlock_work(tp);
7946
7947 tp->saved_wolopts = 0;
7948 pm_runtime_put_sync(&pdev->dev);
7949
7950 rtl8169_check_link_status(dev, tp, ioaddr);
7951 out:
7952 return retval;
7953
7954 err_release_fw_2:
7955 rtl_release_firmware(tp);
7956 rtl8169_rx_clear(tp);
7957 err_free_rx_1:
7958 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7959 tp->RxPhyAddr);
7960 tp->RxDescArray = NULL;
7961 err_free_tx_0:
7962 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7963 tp->TxPhyAddr);
7964 tp->TxDescArray = NULL;
7965 err_pm_runtime_put:
7966 pm_runtime_put_noidle(&pdev->dev);
7967 goto out;
7968 }
7969
7970 static void
7971 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
7972 {
7973 struct rtl8169_private *tp = netdev_priv(dev);
7974 void __iomem *ioaddr = tp->mmio_addr;
7975 struct pci_dev *pdev = tp->pci_dev;
7976 struct rtl8169_counters *counters = tp->counters;
7977 unsigned int start;
7978
7979 pm_runtime_get_noresume(&pdev->dev);
7980
7981 if (netif_running(dev) && pm_runtime_active(&pdev->dev))
7982 rtl8169_rx_missed(dev, ioaddr);
7983
7984 do {
7985 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
7986 stats->rx_packets = tp->rx_stats.packets;
7987 stats->rx_bytes = tp->rx_stats.bytes;
7988 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
7989
7990 do {
7991 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
7992 stats->tx_packets = tp->tx_stats.packets;
7993 stats->tx_bytes = tp->tx_stats.bytes;
7994 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
7995
7996 stats->rx_dropped = dev->stats.rx_dropped;
7997 stats->tx_dropped = dev->stats.tx_dropped;
7998 stats->rx_length_errors = dev->stats.rx_length_errors;
7999 stats->rx_errors = dev->stats.rx_errors;
8000 stats->rx_crc_errors = dev->stats.rx_crc_errors;
8001 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
8002 stats->rx_missed_errors = dev->stats.rx_missed_errors;
8003 stats->multicast = dev->stats.multicast;
8004
8005 /*
8006 * Fetch additonal counter values missing in stats collected by driver
8007 * from tally counters.
8008 */
8009 if (pm_runtime_active(&pdev->dev))
8010 rtl8169_update_counters(dev);
8011
8012 /*
8013 * Subtract values fetched during initalization.
8014 * See rtl8169_init_counter_offsets for a description why we do that.
8015 */
8016 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
8017 le64_to_cpu(tp->tc_offset.tx_errors);
8018 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
8019 le32_to_cpu(tp->tc_offset.tx_multi_collision);
8020 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
8021 le16_to_cpu(tp->tc_offset.tx_aborted);
8022
8023 pm_runtime_put_noidle(&pdev->dev);
8024 }
8025
8026 static void rtl8169_net_suspend(struct net_device *dev)
8027 {
8028 struct rtl8169_private *tp = netdev_priv(dev);
8029
8030 if (!netif_running(dev))
8031 return;
8032
8033 netif_device_detach(dev);
8034 netif_stop_queue(dev);
8035
8036 rtl_lock_work(tp);
8037 napi_disable(&tp->napi);
8038 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
8039 rtl_unlock_work(tp);
8040
8041 rtl_pll_power_down(tp);
8042 }
8043
8044 #ifdef CONFIG_PM
8045
8046 static int rtl8169_suspend(struct device *device)
8047 {
8048 struct pci_dev *pdev = to_pci_dev(device);
8049 struct net_device *dev = pci_get_drvdata(pdev);
8050
8051 rtl8169_net_suspend(dev);
8052
8053 return 0;
8054 }
8055
8056 static void __rtl8169_resume(struct net_device *dev)
8057 {
8058 struct rtl8169_private *tp = netdev_priv(dev);
8059
8060 netif_device_attach(dev);
8061
8062 rtl_pll_power_up(tp);
8063
8064 rtl_lock_work(tp);
8065 napi_enable(&tp->napi);
8066 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
8067 rtl_unlock_work(tp);
8068
8069 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
8070 }
8071
8072 static int rtl8169_resume(struct device *device)
8073 {
8074 struct pci_dev *pdev = to_pci_dev(device);
8075 struct net_device *dev = pci_get_drvdata(pdev);
8076 struct rtl8169_private *tp = netdev_priv(dev);
8077
8078 rtl8169_init_phy(dev, tp);
8079
8080 if (netif_running(dev))
8081 __rtl8169_resume(dev);
8082
8083 return 0;
8084 }
8085
8086 static int rtl8169_runtime_suspend(struct device *device)
8087 {
8088 struct pci_dev *pdev = to_pci_dev(device);
8089 struct net_device *dev = pci_get_drvdata(pdev);
8090 struct rtl8169_private *tp = netdev_priv(dev);
8091
8092 if (!tp->TxDescArray) {
8093 rtl_pll_power_down(tp);
8094 return 0;
8095 }
8096
8097 rtl_lock_work(tp);
8098 tp->saved_wolopts = __rtl8169_get_wol(tp);
8099 __rtl8169_set_wol(tp, WAKE_ANY);
8100 rtl_unlock_work(tp);
8101
8102 rtl8169_net_suspend(dev);
8103
8104 /* Update counters before going runtime suspend */
8105 rtl8169_rx_missed(dev, tp->mmio_addr);
8106 rtl8169_update_counters(dev);
8107
8108 return 0;
8109 }
8110
8111 static int rtl8169_runtime_resume(struct device *device)
8112 {
8113 struct pci_dev *pdev = to_pci_dev(device);
8114 struct net_device *dev = pci_get_drvdata(pdev);
8115 struct rtl8169_private *tp = netdev_priv(dev);
8116 rtl_rar_set(tp, dev->dev_addr);
8117
8118 if (!tp->TxDescArray)
8119 return 0;
8120
8121 rtl_lock_work(tp);
8122 __rtl8169_set_wol(tp, tp->saved_wolopts);
8123 tp->saved_wolopts = 0;
8124 rtl_unlock_work(tp);
8125
8126 rtl8169_init_phy(dev, tp);
8127
8128 __rtl8169_resume(dev);
8129
8130 return 0;
8131 }
8132
8133 static int rtl8169_runtime_idle(struct device *device)
8134 {
8135 struct pci_dev *pdev = to_pci_dev(device);
8136 struct net_device *dev = pci_get_drvdata(pdev);
8137
8138 if (!netif_running(dev) || !netif_carrier_ok(dev))
8139 pm_schedule_suspend(device, 10000);
8140
8141 return -EBUSY;
8142 }
8143
8144 static const struct dev_pm_ops rtl8169_pm_ops = {
8145 .suspend = rtl8169_suspend,
8146 .resume = rtl8169_resume,
8147 .freeze = rtl8169_suspend,
8148 .thaw = rtl8169_resume,
8149 .poweroff = rtl8169_suspend,
8150 .restore = rtl8169_resume,
8151 .runtime_suspend = rtl8169_runtime_suspend,
8152 .runtime_resume = rtl8169_runtime_resume,
8153 .runtime_idle = rtl8169_runtime_idle,
8154 };
8155
8156 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
8157
8158 #else /* !CONFIG_PM */
8159
8160 #define RTL8169_PM_OPS NULL
8161
8162 #endif /* !CONFIG_PM */
8163
8164 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
8165 {
8166 void __iomem *ioaddr = tp->mmio_addr;
8167
8168 /* WoL fails with 8168b when the receiver is disabled. */
8169 switch (tp->mac_version) {
8170 case RTL_GIGA_MAC_VER_11:
8171 case RTL_GIGA_MAC_VER_12:
8172 case RTL_GIGA_MAC_VER_17:
8173 pci_clear_master(tp->pci_dev);
8174
8175 RTL_W8(ChipCmd, CmdRxEnb);
8176 /* PCI commit */
8177 RTL_R8(ChipCmd);
8178 break;
8179 default:
8180 break;
8181 }
8182 }
8183
8184 static void rtl_shutdown(struct pci_dev *pdev)
8185 {
8186 struct net_device *dev = pci_get_drvdata(pdev);
8187 struct rtl8169_private *tp = netdev_priv(dev);
8188
8189 rtl8169_net_suspend(dev);
8190
8191 /* Restore original MAC address */
8192 rtl_rar_set(tp, dev->perm_addr);
8193
8194 rtl8169_hw_reset(tp);
8195
8196 if (system_state == SYSTEM_POWER_OFF) {
8197 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
8198 rtl_wol_suspend_quirk(tp);
8199 rtl_wol_shutdown_quirk(tp);
8200 }
8201
8202 pci_wake_from_d3(pdev, true);
8203 pci_set_power_state(pdev, PCI_D3hot);
8204 }
8205 }
8206
8207 static void rtl_remove_one(struct pci_dev *pdev)
8208 {
8209 struct net_device *dev = pci_get_drvdata(pdev);
8210 struct rtl8169_private *tp = netdev_priv(dev);
8211
8212 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
8213 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
8214 tp->mac_version == RTL_GIGA_MAC_VER_31 ||
8215 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8216 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8217 tp->mac_version == RTL_GIGA_MAC_VER_51) &&
8218 r8168_check_dash(tp)) {
8219 rtl8168_driver_stop(tp);
8220 }
8221
8222 netif_napi_del(&tp->napi);
8223
8224 unregister_netdev(dev);
8225
8226 rtl_release_firmware(tp);
8227
8228 if (pci_dev_run_wake(pdev))
8229 pm_runtime_get_noresume(&pdev->dev);
8230
8231 /* restore original MAC address */
8232 rtl_rar_set(tp, dev->perm_addr);
8233 }
8234
8235 static const struct net_device_ops rtl_netdev_ops = {
8236 .ndo_open = rtl_open,
8237 .ndo_stop = rtl8169_close,
8238 .ndo_get_stats64 = rtl8169_get_stats64,
8239 .ndo_start_xmit = rtl8169_start_xmit,
8240 .ndo_tx_timeout = rtl8169_tx_timeout,
8241 .ndo_validate_addr = eth_validate_addr,
8242 .ndo_change_mtu = rtl8169_change_mtu,
8243 .ndo_fix_features = rtl8169_fix_features,
8244 .ndo_set_features = rtl8169_set_features,
8245 .ndo_set_mac_address = rtl_set_mac_address,
8246 .ndo_do_ioctl = rtl8169_ioctl,
8247 .ndo_set_rx_mode = rtl_set_rx_mode,
8248 #ifdef CONFIG_NET_POLL_CONTROLLER
8249 .ndo_poll_controller = rtl8169_netpoll,
8250 #endif
8251
8252 };
8253
8254 static const struct rtl_cfg_info {
8255 void (*hw_start)(struct net_device *);
8256 unsigned int region;
8257 unsigned int align;
8258 u16 event_slow;
8259 unsigned features;
8260 const struct rtl_coalesce_info *coalesce_info;
8261 u8 default_ver;
8262 } rtl_cfg_infos [] = {
8263 [RTL_CFG_0] = {
8264 .hw_start = rtl_hw_start_8169,
8265 .region = 1,
8266 .align = 0,
8267 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
8268 .features = RTL_FEATURE_GMII,
8269 .coalesce_info = rtl_coalesce_info_8169,
8270 .default_ver = RTL_GIGA_MAC_VER_01,
8271 },
8272 [RTL_CFG_1] = {
8273 .hw_start = rtl_hw_start_8168,
8274 .region = 2,
8275 .align = 8,
8276 .event_slow = SYSErr | LinkChg | RxOverflow,
8277 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
8278 .coalesce_info = rtl_coalesce_info_8168_8136,
8279 .default_ver = RTL_GIGA_MAC_VER_11,
8280 },
8281 [RTL_CFG_2] = {
8282 .hw_start = rtl_hw_start_8101,
8283 .region = 2,
8284 .align = 8,
8285 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
8286 PCSTimeout,
8287 .features = RTL_FEATURE_MSI,
8288 .coalesce_info = rtl_coalesce_info_8168_8136,
8289 .default_ver = RTL_GIGA_MAC_VER_13,
8290 }
8291 };
8292
8293 /* Cfg9346_Unlock assumed. */
8294 static unsigned rtl_try_msi(struct rtl8169_private *tp,
8295 const struct rtl_cfg_info *cfg)
8296 {
8297 void __iomem *ioaddr = tp->mmio_addr;
8298 unsigned msi = 0;
8299 u8 cfg2;
8300
8301 cfg2 = RTL_R8(Config2) & ~MSIEnable;
8302 if (cfg->features & RTL_FEATURE_MSI) {
8303 if (pci_enable_msi(tp->pci_dev)) {
8304 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
8305 } else {
8306 cfg2 |= MSIEnable;
8307 msi = RTL_FEATURE_MSI;
8308 }
8309 }
8310 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
8311 RTL_W8(Config2, cfg2);
8312 return msi;
8313 }
8314
8315 DECLARE_RTL_COND(rtl_link_list_ready_cond)
8316 {
8317 void __iomem *ioaddr = tp->mmio_addr;
8318
8319 return RTL_R8(MCU) & LINK_LIST_RDY;
8320 }
8321
8322 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
8323 {
8324 void __iomem *ioaddr = tp->mmio_addr;
8325
8326 return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
8327 }
8328
8329 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
8330 {
8331 void __iomem *ioaddr = tp->mmio_addr;
8332 u32 data;
8333
8334 tp->ocp_base = OCP_STD_PHY_BASE;
8335
8336 RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
8337
8338 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
8339 return;
8340
8341 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
8342 return;
8343
8344 RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
8345 msleep(1);
8346 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
8347
8348 data = r8168_mac_ocp_read(tp, 0xe8de);
8349 data &= ~(1 << 14);
8350 r8168_mac_ocp_write(tp, 0xe8de, data);
8351
8352 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
8353 return;
8354
8355 data = r8168_mac_ocp_read(tp, 0xe8de);
8356 data |= (1 << 15);
8357 r8168_mac_ocp_write(tp, 0xe8de, data);
8358
8359 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
8360 return;
8361 }
8362
8363 static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
8364 {
8365 rtl8168ep_stop_cmac(tp);
8366 rtl_hw_init_8168g(tp);
8367 }
8368
8369 static void rtl_hw_initialize(struct rtl8169_private *tp)
8370 {
8371 switch (tp->mac_version) {
8372 case RTL_GIGA_MAC_VER_40:
8373 case RTL_GIGA_MAC_VER_41:
8374 case RTL_GIGA_MAC_VER_42:
8375 case RTL_GIGA_MAC_VER_43:
8376 case RTL_GIGA_MAC_VER_44:
8377 case RTL_GIGA_MAC_VER_45:
8378 case RTL_GIGA_MAC_VER_46:
8379 case RTL_GIGA_MAC_VER_47:
8380 case RTL_GIGA_MAC_VER_48:
8381 rtl_hw_init_8168g(tp);
8382 break;
8383 case RTL_GIGA_MAC_VER_49:
8384 case RTL_GIGA_MAC_VER_50:
8385 case RTL_GIGA_MAC_VER_51:
8386 rtl_hw_init_8168ep(tp);
8387 break;
8388 default:
8389 break;
8390 }
8391 }
8392
8393 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8394 {
8395 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
8396 const unsigned int region = cfg->region;
8397 struct rtl8169_private *tp;
8398 struct mii_if_info *mii;
8399 struct net_device *dev;
8400 void __iomem *ioaddr;
8401 int chipset, i;
8402 int rc;
8403
8404 if (netif_msg_drv(&debug)) {
8405 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
8406 MODULENAME, RTL8169_VERSION);
8407 }
8408
8409 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
8410 if (!dev)
8411 return -ENOMEM;
8412
8413 SET_NETDEV_DEV(dev, &pdev->dev);
8414 dev->netdev_ops = &rtl_netdev_ops;
8415 tp = netdev_priv(dev);
8416 tp->dev = dev;
8417 tp->pci_dev = pdev;
8418 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
8419
8420 mii = &tp->mii;
8421 mii->dev = dev;
8422 mii->mdio_read = rtl_mdio_read;
8423 mii->mdio_write = rtl_mdio_write;
8424 mii->phy_id_mask = 0x1f;
8425 mii->reg_num_mask = 0x1f;
8426 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
8427
8428 /* disable ASPM completely as that cause random device stop working
8429 * problems as well as full system hangs for some PCIe devices users */
8430 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
8431 PCIE_LINK_STATE_CLKPM);
8432
8433 /* enable device (incl. PCI PM wakeup and hotplug setup) */
8434 rc = pcim_enable_device(pdev);
8435 if (rc < 0) {
8436 netif_err(tp, probe, dev, "enable failure\n");
8437 return rc;
8438 }
8439
8440 if (pcim_set_mwi(pdev) < 0)
8441 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
8442
8443 /* make sure PCI base addr 1 is MMIO */
8444 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
8445 netif_err(tp, probe, dev,
8446 "region #%d not an MMIO resource, aborting\n",
8447 region);
8448 return -ENODEV;
8449 }
8450
8451 /* check for weird/broken PCI region reporting */
8452 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
8453 netif_err(tp, probe, dev,
8454 "Invalid PCI region size(s), aborting\n");
8455 return -ENODEV;
8456 }
8457
8458 rc = pci_request_regions(pdev, MODULENAME);
8459 if (rc < 0) {
8460 netif_err(tp, probe, dev, "could not request regions\n");
8461 return rc;
8462 }
8463
8464 /* ioremap MMIO region */
8465 ioaddr = devm_ioremap(&pdev->dev, pci_resource_start(pdev, region),
8466 R8169_REGS_SIZE);
8467 if (!ioaddr) {
8468 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
8469 return -EIO;
8470 }
8471 tp->mmio_addr = ioaddr;
8472
8473 if (!pci_is_pcie(pdev))
8474 netif_info(tp, probe, dev, "not PCI Express\n");
8475
8476 /* Identify chip attached to board */
8477 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
8478
8479 tp->cp_cmd = 0;
8480
8481 if ((sizeof(dma_addr_t) > 4) &&
8482 (use_dac == 1 || (use_dac == -1 && pci_is_pcie(pdev) &&
8483 tp->mac_version >= RTL_GIGA_MAC_VER_18)) &&
8484 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
8485 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
8486
8487 /* CPlusCmd Dual Access Cycle is only needed for non-PCIe */
8488 if (!pci_is_pcie(pdev))
8489 tp->cp_cmd |= PCIDAC;
8490 dev->features |= NETIF_F_HIGHDMA;
8491 } else {
8492 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
8493 if (rc < 0) {
8494 netif_err(tp, probe, dev, "DMA configuration failed\n");
8495 return rc;
8496 }
8497 }
8498
8499 rtl_init_rxcfg(tp);
8500
8501 rtl_irq_disable(tp);
8502
8503 rtl_hw_initialize(tp);
8504
8505 rtl_hw_reset(tp);
8506
8507 rtl_ack_events(tp, 0xffff);
8508
8509 pci_set_master(pdev);
8510
8511 rtl_init_mdio_ops(tp);
8512 rtl_init_pll_power_ops(tp);
8513 rtl_init_jumbo_ops(tp);
8514 rtl_init_csi_ops(tp);
8515
8516 rtl8169_print_mac_version(tp);
8517
8518 chipset = tp->mac_version;
8519 tp->txd_version = rtl_chip_infos[chipset].txd_version;
8520
8521 RTL_W8(Cfg9346, Cfg9346_Unlock);
8522 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
8523 RTL_W8(Config5, RTL_R8(Config5) & (BWF | MWF | UWF | LanWake | PMEStatus));
8524 switch (tp->mac_version) {
8525 case RTL_GIGA_MAC_VER_34:
8526 case RTL_GIGA_MAC_VER_35:
8527 case RTL_GIGA_MAC_VER_36:
8528 case RTL_GIGA_MAC_VER_37:
8529 case RTL_GIGA_MAC_VER_38:
8530 case RTL_GIGA_MAC_VER_40:
8531 case RTL_GIGA_MAC_VER_41:
8532 case RTL_GIGA_MAC_VER_42:
8533 case RTL_GIGA_MAC_VER_43:
8534 case RTL_GIGA_MAC_VER_44:
8535 case RTL_GIGA_MAC_VER_45:
8536 case RTL_GIGA_MAC_VER_46:
8537 case RTL_GIGA_MAC_VER_47:
8538 case RTL_GIGA_MAC_VER_48:
8539 case RTL_GIGA_MAC_VER_49:
8540 case RTL_GIGA_MAC_VER_50:
8541 case RTL_GIGA_MAC_VER_51:
8542 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
8543 tp->features |= RTL_FEATURE_WOL;
8544 if ((RTL_R8(Config3) & LinkUp) != 0)
8545 tp->features |= RTL_FEATURE_WOL;
8546 break;
8547 default:
8548 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
8549 tp->features |= RTL_FEATURE_WOL;
8550 break;
8551 }
8552 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
8553 tp->features |= RTL_FEATURE_WOL;
8554 tp->features |= rtl_try_msi(tp, cfg);
8555 RTL_W8(Cfg9346, Cfg9346_Lock);
8556
8557 if (rtl_tbi_enabled(tp)) {
8558 tp->set_speed = rtl8169_set_speed_tbi;
8559 tp->get_link_ksettings = rtl8169_get_link_ksettings_tbi;
8560 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
8561 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
8562 tp->link_ok = rtl8169_tbi_link_ok;
8563 tp->do_ioctl = rtl_tbi_ioctl;
8564 } else {
8565 tp->set_speed = rtl8169_set_speed_xmii;
8566 tp->get_link_ksettings = rtl8169_get_link_ksettings_xmii;
8567 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
8568 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
8569 tp->link_ok = rtl8169_xmii_link_ok;
8570 tp->do_ioctl = rtl_xmii_ioctl;
8571 }
8572
8573 mutex_init(&tp->wk.mutex);
8574 u64_stats_init(&tp->rx_stats.syncp);
8575 u64_stats_init(&tp->tx_stats.syncp);
8576
8577 /* Get MAC address */
8578 if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
8579 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
8580 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
8581 tp->mac_version == RTL_GIGA_MAC_VER_38 ||
8582 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
8583 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
8584 tp->mac_version == RTL_GIGA_MAC_VER_42 ||
8585 tp->mac_version == RTL_GIGA_MAC_VER_43 ||
8586 tp->mac_version == RTL_GIGA_MAC_VER_44 ||
8587 tp->mac_version == RTL_GIGA_MAC_VER_45 ||
8588 tp->mac_version == RTL_GIGA_MAC_VER_46 ||
8589 tp->mac_version == RTL_GIGA_MAC_VER_47 ||
8590 tp->mac_version == RTL_GIGA_MAC_VER_48 ||
8591 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8592 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8593 tp->mac_version == RTL_GIGA_MAC_VER_51) {
8594 u16 mac_addr[3];
8595
8596 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
8597 *(u16 *)&mac_addr[2] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
8598
8599 if (is_valid_ether_addr((u8 *)mac_addr))
8600 rtl_rar_set(tp, (u8 *)mac_addr);
8601 }
8602 for (i = 0; i < ETH_ALEN; i++)
8603 dev->dev_addr[i] = RTL_R8(MAC0 + i);
8604
8605 dev->ethtool_ops = &rtl8169_ethtool_ops;
8606 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
8607
8608 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
8609
8610 /* don't enable SG, IP_CSUM and TSO by default - it might not work
8611 * properly for all devices */
8612 dev->features |= NETIF_F_RXCSUM |
8613 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
8614
8615 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
8616 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
8617 NETIF_F_HW_VLAN_CTAG_RX;
8618 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
8619 NETIF_F_HIGHDMA;
8620
8621 tp->cp_cmd |= RxChkSum | RxVlan;
8622
8623 /*
8624 * Pretend we are using VLANs; This bypasses a nasty bug where
8625 * Interrupts stop flowing on high load on 8110SCd controllers.
8626 */
8627 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
8628 /* Disallow toggling */
8629 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
8630
8631 if (tp->txd_version == RTL_TD_0)
8632 tp->tso_csum = rtl8169_tso_csum_v1;
8633 else if (tp->txd_version == RTL_TD_1) {
8634 tp->tso_csum = rtl8169_tso_csum_v2;
8635 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
8636 } else
8637 WARN_ON_ONCE(1);
8638
8639 dev->hw_features |= NETIF_F_RXALL;
8640 dev->hw_features |= NETIF_F_RXFCS;
8641
8642 /* MTU range: 60 - hw-specific max */
8643 dev->min_mtu = ETH_ZLEN;
8644 dev->max_mtu = rtl_chip_infos[chipset].jumbo_max;
8645
8646 tp->hw_start = cfg->hw_start;
8647 tp->event_slow = cfg->event_slow;
8648 tp->coalesce_info = cfg->coalesce_info;
8649
8650 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
8651 ~(RxBOVF | RxFOVF) : ~0;
8652
8653 timer_setup(&tp->timer, rtl8169_phy_timer, 0);
8654
8655 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
8656
8657 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
8658 &tp->counters_phys_addr,
8659 GFP_KERNEL);
8660 if (!tp->counters)
8661 return -ENOMEM;
8662
8663 rc = register_netdev(dev);
8664 if (rc < 0)
8665 return rc;
8666
8667 pci_set_drvdata(pdev, dev);
8668
8669 netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
8670 rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
8671 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
8672 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
8673 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
8674 "tx checksumming: %s]\n",
8675 rtl_chip_infos[chipset].jumbo_max,
8676 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
8677 }
8678
8679 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
8680 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
8681 tp->mac_version == RTL_GIGA_MAC_VER_31 ||
8682 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8683 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8684 tp->mac_version == RTL_GIGA_MAC_VER_51) &&
8685 r8168_check_dash(tp)) {
8686 rtl8168_driver_start(tp);
8687 }
8688
8689 netif_carrier_off(dev);
8690
8691 if (pci_dev_run_wake(pdev))
8692 pm_runtime_put_sync(&pdev->dev);
8693
8694 return 0;
8695 }
8696
8697 static struct pci_driver rtl8169_pci_driver = {
8698 .name = MODULENAME,
8699 .id_table = rtl8169_pci_tbl,
8700 .probe = rtl_init_one,
8701 .remove = rtl_remove_one,
8702 .shutdown = rtl_shutdown,
8703 .driver.pm = RTL8169_PM_OPS,
8704 };
8705
8706 module_pci_driver(rtl8169_pci_driver);
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