1 # SPDX-License-Identifier: GPL-2.0
3 menu "DesignWare PCI Core Support"
11 depends on PCI_MSI_IRQ_DOMAIN
16 depends on PCI_ENDPOINT
22 config PCI_DRA7XX_HOST
23 bool "TI DRA7xx PCIe controller Host Mode"
24 depends on SOC_DRA7XX || COMPILE_TEST
25 depends on PCI && PCI_MSI_IRQ_DOMAIN
26 depends on OF && HAS_IOMEM && TI_PIPE3
31 Enables support for the PCIe controller in the DRA7xx SoC to work in
32 host mode. There are two instances of PCIe controller in DRA7xx.
33 This controller can work either as EP or RC. In order to enable
34 host-specific features PCI_DRA7XX_HOST must be selected and in order
35 to enable device-specific features PCI_DRA7XX_EP must be selected.
36 This uses the DesignWare core.
39 bool "TI DRA7xx PCIe controller Endpoint Mode"
40 depends on SOC_DRA7XX || COMPILE_TEST
41 depends on PCI_ENDPOINT
42 depends on OF && HAS_IOMEM && TI_PIPE3
46 Enables support for the PCIe controller in the DRA7xx SoC to work in
47 endpoint mode. There are two instances of PCIe controller in DRA7xx.
48 This controller can work either as EP or RC. In order to enable
49 host-specific features PCI_DRA7XX_HOST must be selected and in order
50 to enable device-specific features PCI_DRA7XX_EP must be selected.
51 This uses the DesignWare core.
54 bool "Platform bus based DesignWare PCIe Controller"
56 depends on PCI_MSI_IRQ_DOMAIN
59 This selects the DesignWare PCIe controller support. Select this if
60 you have a PCIe controller on Platform bus.
62 If you have a controller with this interface, say Y or M here.
67 bool "Samsung Exynos PCIe controller"
69 depends on SOC_EXYNOS5440
70 depends on PCI_MSI_IRQ_DOMAIN
75 bool "Freescale i.MX6 PCIe controller"
78 depends on PCI_MSI_IRQ_DOMAIN
83 bool "STMicroelectronics SPEAr PCIe controller"
85 depends on ARCH_SPEAR13XX
86 depends on PCI_MSI_IRQ_DOMAIN
90 Say Y here if you want PCIe support on SPEAr13XX SoCs.
93 bool "TI Keystone PCIe controller"
95 depends on ARCH_KEYSTONE
96 depends on PCI_MSI_IRQ_DOMAIN
100 Say Y here if you want to enable PCI controller support on Keystone
101 SoCs. The PCI controller on Keystone is based on DesignWare hardware
102 and therefore the driver re-uses the DesignWare core functions to
103 implement the driver.
105 config PCI_LAYERSCAPE
106 bool "Freescale Layerscape PCIe controller"
108 depends on OF && (ARM || ARCH_LAYERSCAPE)
109 depends on PCI_MSI_IRQ_DOMAIN
113 Say Y here if you want PCIe controller support on Layerscape SoCs.
116 depends on OF && ARM64
117 bool "HiSilicon Hip05 and Hip06 SoCs PCIe controllers"
119 depends on PCI_MSI_IRQ_DOMAIN
122 select PCI_HOST_COMMON
124 Say Y here if you want PCIe controller support on HiSilicon
128 bool "Qualcomm PCIe controller"
130 depends on ARCH_QCOM && OF
131 depends on PCI_MSI_IRQ_DOMAIN
135 Say Y here to enable PCIe controller support on Qualcomm SoCs. The
136 PCIe controller uses the DesignWare core plus Qualcomm-specific
139 config PCIE_ARMADA_8K
140 bool "Marvell Armada-8K PCIe controller"
142 depends on ARCH_MVEBU
143 depends on PCI_MSI_IRQ_DOMAIN
147 Say Y here if you want to enable PCIe controller support on
148 Armada-8K SoCs. The PCIe controller on Armada-8K is based on
149 DesignWare hardware and therefore the driver re-uses the
150 DesignWare core functions to implement the driver.
155 config PCIE_ARTPEC6_HOST
156 bool "Axis ARTPEC-6 PCIe controller Host Mode"
157 depends on MACH_ARTPEC6
158 depends on PCI && PCI_MSI_IRQ_DOMAIN
163 Enables support for the PCIe controller in the ARTPEC-6 SoC to work in
164 host mode. This uses the DesignWare core.
166 config PCIE_ARTPEC6_EP
167 bool "Axis ARTPEC-6 PCIe controller Endpoint Mode"
168 depends on MACH_ARTPEC6
169 depends on PCI_ENDPOINT
173 Enables support for the PCIe controller in the ARTPEC-6 SoC to work in
174 endpoint mode. This uses the DesignWare core.
177 depends on OF && ARM64
178 bool "HiSilicon Kirin series SoCs PCIe controllers"
183 Say Y here if you want PCIe controller support
184 on HiSilicon Kirin series SoCs.
187 bool "HiSilicon STB SoCs PCIe controllers"
190 depends on PCI_MSI_IRQ_DOMAIN
194 Say Y here if you want PCIe controller support on HiSilicon STB SoCs