drivers/pci/dwc/pci-dra7xx.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs
   4  *
   5  * Copyright (C) 2013-2014 Texas Instruments Incorporated - http://www.ti.com
   6  *
   7  * Authors: Kishon Vijay Abraham I <kishon@ti.com>
   8  */
   9
  10 #include <linux/delay.h>
  11 #include <linux/device.h>
  12 #include <linux/err.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/irq.h>
  15 #include <linux/irqdomain.h>
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/of_device.h>
  19 #include <linux/of_gpio.h>
  20 #include <linux/of_pci.h>
  21 #include <linux/pci.h>
  22 #include <linux/phy/phy.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/pm_runtime.h>
  25 #include <linux/resource.h>
  26 #include <linux/types.h>
  27 #include <linux/mfd/syscon.h>
  28 #include <linux/regmap.h>
  29
  30 #include "pcie-designware.h"
  31
  32 /* PCIe controller wrapper DRA7XX configuration registers */
  33
  34 #define PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN             0x0024
  35 #define PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN         0x0028
  36 #define ERR_SYS                                         BIT(0)
  37 #define ERR_FATAL                                       BIT(1)
  38 #define ERR_NONFATAL                                    BIT(2)
  39 #define ERR_COR                                         BIT(3)
  40 #define ERR_AXI                                         BIT(4)
  41 #define ERR_ECRC                                        BIT(5)
  42 #define PME_TURN_OFF                                    BIT(8)
  43 #define PME_TO_ACK                                      BIT(9)
  44 #define PM_PME                                          BIT(10)
  45 #define LINK_REQ_RST                                    BIT(11)
  46 #define LINK_UP_EVT                                     BIT(12)
  47 #define CFG_BME_EVT                                     BIT(13)
  48 #define CFG_MSE_EVT                                     BIT(14)
  49 #define INTERRUPTS (ERR_SYS | ERR_FATAL | ERR_NONFATAL | ERR_COR | ERR_AXI | \
  50                         ERR_ECRC | PME_TURN_OFF | PME_TO_ACK | PM_PME | \
  51                         LINK_REQ_RST | LINK_UP_EVT | CFG_BME_EVT | CFG_MSE_EVT)
  52
  53 #define PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI              0x0034
  54 #define PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI          0x0038
  55 #define INTA                                            BIT(0)
  56 #define INTB                                            BIT(1)
  57 #define INTC                                            BIT(2)
  58 #define INTD                                            BIT(3)
  59 #define MSI                                             BIT(4)
  60 #define LEG_EP_INTERRUPTS (INTA | INTB | INTC | INTD)
  61
  62 #define PCIECTRL_TI_CONF_DEVICE_TYPE                    0x0100
  63 #define DEVICE_TYPE_EP                                  0x0
  64 #define DEVICE_TYPE_LEG_EP                              0x1
  65 #define DEVICE_TYPE_RC                                  0x4
  66
  67 #define PCIECTRL_DRA7XX_CONF_DEVICE_CMD                 0x0104
  68 #define LTSSM_EN                                        0x1
  69
  70 #define PCIECTRL_DRA7XX_CONF_PHY_CS                     0x010C
  71 #define LINK_UP                                         BIT(16)
  72 #define DRA7XX_CPU_TO_BUS_ADDR                          0x0FFFFFFF
  73
  74 #define EXP_CAP_ID_OFFSET                               0x70
  75
  76 #define PCIECTRL_TI_CONF_INTX_ASSERT                    0x0124
  77 #define PCIECTRL_TI_CONF_INTX_DEASSERT                  0x0128
  78
  79 #define PCIECTRL_TI_CONF_MSI_XMT                        0x012c
  80 #define MSI_REQ_GRANT                                   BIT(0)
  81 #define MSI_VECTOR_SHIFT                                7
  82
  83 struct dra7xx_pcie {
  84         struct dw_pcie          *pci;
  85         void __iomem            *base;          /* DT ti_conf */
  86         int                     phy_count;      /* DT phy-names count */
  87         struct phy              **phy;
  88         int                     link_gen;
  89         struct irq_domain       *irq_domain;
  90         enum dw_pcie_device_mode mode;
  91 };
  92
  93 struct dra7xx_pcie_of_data {
  94         enum dw_pcie_device_mode mode;
  95 };
  96
  97 #define to_dra7xx_pcie(x)       dev_get_drvdata((x)->dev)
  98
  99 static inline u32 dra7xx_pcie_readl(struct dra7xx_pcie *pcie, u32 offset)
 100 {
 101         return readl(pcie->base + offset);
 102 }
 103
 104 static inline void dra7xx_pcie_writel(struct dra7xx_pcie *pcie, u32 offset,
 105                                       u32 value)
 106 {
 107         writel(value, pcie->base + offset);
 108 }
 109
 110 static u64 dra7xx_pcie_cpu_addr_fixup(struct dw_pcie *pci, u64 pci_addr)
 111 {
 112         return pci_addr & DRA7XX_CPU_TO_BUS_ADDR;
 113 }
 114
 115 static int dra7xx_pcie_link_up(struct dw_pcie *pci)
 116 {
 117         struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
 118         u32 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_PHY_CS);
 119
 120         return !!(reg & LINK_UP);
 121 }
 122
 123 static void dra7xx_pcie_stop_link(struct dw_pcie *pci)
 124 {
 125         struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
 126         u32 reg;
 127
 128         reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
 129         reg &= ~LTSSM_EN;
 130         dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
 131 }
 132
 133 static int dra7xx_pcie_establish_link(struct dw_pcie *pci)
 134 {
 135         struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
 136         struct device *dev = pci->dev;
 137         u32 reg;
 138         u32 exp_cap_off = EXP_CAP_ID_OFFSET;
 139
 140         if (dw_pcie_link_up(pci)) {
 141                 dev_err(dev, "link is already up\n");
 142                 return 0;
 143         }
 144
 145         if (dra7xx->link_gen == 1) {
 146                 dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCAP,
 147                              4, &reg);
 148                 if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
 149                         reg &= ~((u32)PCI_EXP_LNKCAP_SLS);
 150                         reg |= PCI_EXP_LNKCAP_SLS_2_5GB;
 151                         dw_pcie_write(pci->dbi_base + exp_cap_off +
 152                                       PCI_EXP_LNKCAP, 4, reg);
 153                 }
 154
 155                 dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2,
 156                              2, &reg);
 157                 if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
 158                         reg &= ~((u32)PCI_EXP_LNKCAP_SLS);
 159                         reg |= PCI_EXP_LNKCAP_SLS_2_5GB;
 160                         dw_pcie_write(pci->dbi_base + exp_cap_off +
 161                                       PCI_EXP_LNKCTL2, 2, reg);
 162                 }
 163         }
 164
 165         reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
 166         reg |= LTSSM_EN;
 167         dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
 168
 169         return 0;
 170 }
 171
 172 static void dra7xx_pcie_enable_msi_interrupts(struct dra7xx_pcie *dra7xx)
 173 {
 174         dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI,
 175                            LEG_EP_INTERRUPTS | MSI);
 176
 177         dra7xx_pcie_writel(dra7xx,
 178                            PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI,
 179                            MSI | LEG_EP_INTERRUPTS);
 180 }
 181
 182 static void dra7xx_pcie_enable_wrapper_interrupts(struct dra7xx_pcie *dra7xx)
 183 {
 184         dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN,
 185                            INTERRUPTS);
 186         dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN,
 187                            INTERRUPTS);
 188 }
 189
 190 static void dra7xx_pcie_enable_interrupts(struct dra7xx_pcie *dra7xx)
 191 {
 192         dra7xx_pcie_enable_wrapper_interrupts(dra7xx);
 193         dra7xx_pcie_enable_msi_interrupts(dra7xx);
 194 }
 195
 196 static int dra7xx_pcie_host_init(struct pcie_port *pp)
 197 {
 198         struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 199         struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
 200
 201         dw_pcie_setup_rc(pp);
 202
 203         dra7xx_pcie_establish_link(pci);
 204         dw_pcie_wait_for_link(pci);
 205         dw_pcie_msi_init(pp);
 206         dra7xx_pcie_enable_interrupts(dra7xx);
 207
 208         return 0;
 209 }
 210
 211 static const struct dw_pcie_host_ops dra7xx_pcie_host_ops = {
 212         .host_init = dra7xx_pcie_host_init,
 213 };
 214
 215 static int dra7xx_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
 216                                 irq_hw_number_t hwirq)
 217 {
 218         irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
 219         irq_set_chip_data(irq, domain->host_data);
 220
 221         return 0;
 222 }
 223
 224 static const struct irq_domain_ops intx_domain_ops = {
 225         .map = dra7xx_pcie_intx_map,
 226         .xlate = pci_irqd_intx_xlate,
 227 };
 228
 229 static int dra7xx_pcie_init_irq_domain(struct pcie_port *pp)
 230 {
 231         struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 232         struct device *dev = pci->dev;
 233         struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
 234         struct device_node *node = dev->of_node;
 235         struct device_node *pcie_intc_node =  of_get_next_child(node, NULL);
 236
 237         if (!pcie_intc_node) {
 238                 dev_err(dev, "No PCIe Intc node found\n");
 239                 return -ENODEV;
 240         }
 241
 242         dra7xx->irq_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
 243                                                    &intx_domain_ops, pp);
 244         if (!dra7xx->irq_domain) {
 245                 dev_err(dev, "Failed to get a INTx IRQ domain\n");
 246                 return -ENODEV;
 247         }
 248
 249         return 0;
 250 }
 251
 252 static irqreturn_t dra7xx_pcie_msi_irq_handler(int irq, void *arg)
 253 {
 254         struct dra7xx_pcie *dra7xx = arg;
 255         struct dw_pcie *pci = dra7xx->pci;
 256         struct pcie_port *pp = &pci->pp;
 257         unsigned long reg;
 258         u32 virq, bit;
 259
 260         reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI);
 261
 262         switch (reg) {
 263         case MSI:
 264                 dw_handle_msi_irq(pp);
 265                 break;
 266         case INTA:
 267         case INTB:
 268         case INTC:
 269         case INTD:
 270                 for_each_set_bit(bit, &reg, PCI_NUM_INTX) {
 271                         virq = irq_find_mapping(dra7xx->irq_domain, bit);
 272                         if (virq)
 273                                 generic_handle_irq(virq);
 274                 }
 275                 break;
 276         }
 277
 278         dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI, reg);
 279
 280         return IRQ_HANDLED;
 281 }
 282
 283 static irqreturn_t dra7xx_pcie_irq_handler(int irq, void *arg)
 284 {
 285         struct dra7xx_pcie *dra7xx = arg;
 286         struct dw_pcie *pci = dra7xx->pci;
 287         struct device *dev = pci->dev;
 288         struct dw_pcie_ep *ep = &pci->ep;
 289         u32 reg;
 290
 291         reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN);
 292
 293         if (reg & ERR_SYS)
 294                 dev_dbg(dev, "System Error\n");
 295
 296         if (reg & ERR_FATAL)
 297                 dev_dbg(dev, "Fatal Error\n");
 298
 299         if (reg & ERR_NONFATAL)
 300                 dev_dbg(dev, "Non Fatal Error\n");
 301
 302         if (reg & ERR_COR)
 303                 dev_dbg(dev, "Correctable Error\n");
 304
 305         if (reg & ERR_AXI)
 306                 dev_dbg(dev, "AXI tag lookup fatal Error\n");
 307
 308         if (reg & ERR_ECRC)
 309                 dev_dbg(dev, "ECRC Error\n");
 310
 311         if (reg & PME_TURN_OFF)
 312                 dev_dbg(dev,
 313                         "Power Management Event Turn-Off message received\n");
 314
 315         if (reg & PME_TO_ACK)
 316                 dev_dbg(dev,
 317                         "Power Management Turn-Off Ack message received\n");
 318
 319         if (reg & PM_PME)
 320                 dev_dbg(dev, "PM Power Management Event message received\n");
 321
 322         if (reg & LINK_REQ_RST)
 323                 dev_dbg(dev, "Link Request Reset\n");
 324
 325         if (reg & LINK_UP_EVT) {
 326                 if (dra7xx->mode == DW_PCIE_EP_TYPE)
 327                         dw_pcie_ep_linkup(ep);
 328                 dev_dbg(dev, "Link-up state change\n");
 329         }
 330
 331         if (reg & CFG_BME_EVT)
 332                 dev_dbg(dev, "CFG 'Bus Master Enable' change\n");
 333
 334         if (reg & CFG_MSE_EVT)
 335                 dev_dbg(dev, "CFG 'Memory Space Enable' change\n");
 336
 337         dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN, reg);
 338
 339         return IRQ_HANDLED;
 340 }
 341
 342 static void dra7xx_pcie_ep_init(struct dw_pcie_ep *ep)
 343 {
 344         struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
 345         struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
 346         enum pci_barno bar;
 347
 348         for (bar = BAR_0; bar <= BAR_5; bar++)
 349                 dw_pcie_ep_reset_bar(pci, bar);
 350
 351         dra7xx_pcie_enable_wrapper_interrupts(dra7xx);
 352 }
 353
 354 static void dra7xx_pcie_raise_legacy_irq(struct dra7xx_pcie *dra7xx)
 355 {
 356         dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_INTX_ASSERT, 0x1);
 357         mdelay(1);
 358         dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_INTX_DEASSERT, 0x1);
 359 }
 360
 361 static void dra7xx_pcie_raise_msi_irq(struct dra7xx_pcie *dra7xx,
 362                                       u8 interrupt_num)
 363 {
 364         u32 reg;
 365
 366         reg = (interrupt_num - 1) << MSI_VECTOR_SHIFT;
 367         reg |= MSI_REQ_GRANT;
 368         dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_MSI_XMT, reg);
 369 }
 370
 371 static int dra7xx_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
 372                                  enum pci_epc_irq_type type, u8 interrupt_num)
 373 {
 374         struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
 375         struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
 376
 377         switch (type) {
 378         case PCI_EPC_IRQ_LEGACY:
 379                 dra7xx_pcie_raise_legacy_irq(dra7xx);
 380                 break;
 381         case PCI_EPC_IRQ_MSI:
 382                 dra7xx_pcie_raise_msi_irq(dra7xx, interrupt_num);
 383                 break;
 384         default:
 385                 dev_err(pci->dev, "UNKNOWN IRQ type\n");
 386         }
 387
 388         return 0;
 389 }
 390
 391 static struct dw_pcie_ep_ops pcie_ep_ops = {
 392         .ep_init = dra7xx_pcie_ep_init,
 393         .raise_irq = dra7xx_pcie_raise_irq,
 394 };
 395
 396 static int __init dra7xx_add_pcie_ep(struct dra7xx_pcie *dra7xx,
 397                                      struct platform_device *pdev)
 398 {
 399         int ret;
 400         struct dw_pcie_ep *ep;
 401         struct resource *res;
 402         struct device *dev = &pdev->dev;
 403         struct dw_pcie *pci = dra7xx->pci;
 404
 405         ep = &pci->ep;
 406         ep->ops = &pcie_ep_ops;
 407
 408         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ep_dbics");
 409         pci->dbi_base = devm_ioremap(dev, res->start, resource_size(res));
 410         if (!pci->dbi_base)
 411                 return -ENOMEM;
 412
 413         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ep_dbics2");
 414         pci->dbi_base2 = devm_ioremap(dev, res->start, resource_size(res));
 415         if (!pci->dbi_base2)
 416                 return -ENOMEM;
 417
 418         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
 419         if (!res)
 420                 return -EINVAL;
 421
 422         ep->phys_base = res->start;
 423         ep->addr_size = resource_size(res);
 424
 425         ret = dw_pcie_ep_init(ep);
 426         if (ret) {
 427                 dev_err(dev, "failed to initialize endpoint\n");
 428                 return ret;
 429         }
 430
 431         return 0;
 432 }
 433
 434 static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
 435                                        struct platform_device *pdev)
 436 {
 437         int ret;
 438         struct dw_pcie *pci = dra7xx->pci;
 439         struct pcie_port *pp = &pci->pp;
 440         struct device *dev = pci->dev;
 441         struct resource *res;
 442
 443         pp->irq = platform_get_irq(pdev, 1);
 444         if (pp->irq < 0) {
 445                 dev_err(dev, "missing IRQ resource\n");
 446                 return pp->irq;
 447         }
 448
 449         ret = devm_request_irq(dev, pp->irq, dra7xx_pcie_msi_irq_handler,
 450                                IRQF_SHARED | IRQF_NO_THREAD,
 451                                "dra7-pcie-msi", dra7xx);
 452         if (ret) {
 453                 dev_err(dev, "failed to request irq\n");
 454                 return ret;
 455         }
 456
 457         ret = dra7xx_pcie_init_irq_domain(pp);
 458         if (ret < 0)
 459                 return ret;
 460
 461         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc_dbics");
 462         pci->dbi_base = devm_ioremap(dev, res->start, resource_size(res));
 463         if (!pci->dbi_base)
 464                 return -ENOMEM;
 465
 466         pp->ops = &dra7xx_pcie_host_ops;
 467
 468         ret = dw_pcie_host_init(pp);
 469         if (ret) {
 470                 dev_err(dev, "failed to initialize host\n");
 471                 return ret;
 472         }
 473
 474         return 0;
 475 }
 476
 477 static const struct dw_pcie_ops dw_pcie_ops = {
 478         .cpu_addr_fixup = dra7xx_pcie_cpu_addr_fixup,
 479         .start_link = dra7xx_pcie_establish_link,
 480         .stop_link = dra7xx_pcie_stop_link,
 481         .link_up = dra7xx_pcie_link_up,
 482 };
 483
 484 static void dra7xx_pcie_disable_phy(struct dra7xx_pcie *dra7xx)
 485 {
 486         int phy_count = dra7xx->phy_count;
 487
 488         while (phy_count--) {
 489                 phy_power_off(dra7xx->phy[phy_count]);
 490                 phy_exit(dra7xx->phy[phy_count]);
 491         }
 492 }
 493
 494 static int dra7xx_pcie_enable_phy(struct dra7xx_pcie *dra7xx)
 495 {
 496         int phy_count = dra7xx->phy_count;
 497         int ret;
 498         int i;
 499
 500         for (i = 0; i < phy_count; i++) {
 501                 ret = phy_init(dra7xx->phy[i]);
 502                 if (ret < 0)
 503                         goto err_phy;
 504
 505                 ret = phy_power_on(dra7xx->phy[i]);
 506                 if (ret < 0) {
 507                         phy_exit(dra7xx->phy[i]);
 508                         goto err_phy;
 509                 }
 510         }
 511
 512         return 0;
 513
 514 err_phy:
 515         while (--i >= 0) {
 516                 phy_power_off(dra7xx->phy[i]);
 517                 phy_exit(dra7xx->phy[i]);
 518         }
 519
 520         return ret;
 521 }
 522
 523 static const struct dra7xx_pcie_of_data dra7xx_pcie_rc_of_data = {
 524         .mode = DW_PCIE_RC_TYPE,
 525 };
 526
 527 static const struct dra7xx_pcie_of_data dra7xx_pcie_ep_of_data = {
 528         .mode = DW_PCIE_EP_TYPE,
 529 };
 530
 531 static const struct of_device_id of_dra7xx_pcie_match[] = {
 532         {
 533                 .compatible = "ti,dra7-pcie",
 534                 .data = &dra7xx_pcie_rc_of_data,
 535         },
 536         {
 537                 .compatible = "ti,dra7-pcie-ep",
 538                 .data = &dra7xx_pcie_ep_of_data,
 539         },
 540         {},
 541 };
 542
 543 /*
 544  * dra7xx_pcie_ep_unaligned_memaccess: workaround for AM572x/AM571x Errata i870
 545  * @dra7xx: the dra7xx device where the workaround should be applied
 546  *
 547  * Access to the PCIe slave port that are not 32-bit aligned will result
 548  * in incorrect mapping to TLP Address and Byte enable fields. Therefore,
 549  * byte and half-word accesses are not possible to byte offset 0x1, 0x2, or
 550  * 0x3.
 551  *
 552  * To avoid this issue set PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE to 1.
 553  */
 554 static int dra7xx_pcie_ep_unaligned_memaccess(struct device *dev)
 555 {
 556         int ret;
 557         struct device_node *np = dev->of_node;
 558         struct of_phandle_args args;
 559         struct regmap *regmap;
 560
 561         regmap = syscon_regmap_lookup_by_phandle(np,
 562                                                  "ti,syscon-unaligned-access");
 563         if (IS_ERR(regmap)) {
 564                 dev_dbg(dev, "can't get ti,syscon-unaligned-access\n");
 565                 return -EINVAL;
 566         }
 567
 568         ret = of_parse_phandle_with_fixed_args(np, "ti,syscon-unaligned-access",
 569                                                2, 0, &args);
 570         if (ret) {
 571                 dev_err(dev, "failed to parse ti,syscon-unaligned-access\n");
 572                 return ret;
 573         }
 574
 575         ret = regmap_update_bits(regmap, args.args[0], args.args[1],
 576                                  args.args[1]);
 577         if (ret)
 578                 dev_err(dev, "failed to enable unaligned access\n");
 579
 580         of_node_put(args.np);
 581
 582         return ret;
 583 }
 584
 585 static int __init dra7xx_pcie_probe(struct platform_device *pdev)
 586 {
 587         u32 reg;
 588         int ret;
 589         int irq;
 590         int i;
 591         int phy_count;
 592         struct phy **phy;
 593         struct device_link **link;
 594         void __iomem *base;
 595         struct resource *res;
 596         struct dw_pcie *pci;
 597         struct dra7xx_pcie *dra7xx;
 598         struct device *dev = &pdev->dev;
 599         struct device_node *np = dev->of_node;
 600         char name[10];
 601         struct gpio_desc *reset;
 602         const struct of_device_id *match;
 603         const struct dra7xx_pcie_of_data *data;
 604         enum dw_pcie_device_mode mode;
 605
 606         match = of_match_device(of_match_ptr(of_dra7xx_pcie_match), dev);
 607         if (!match)
 608                 return -EINVAL;
 609
 610         data = (struct dra7xx_pcie_of_data *)match->data;
 611         mode = (enum dw_pcie_device_mode)data->mode;
 612
 613         dra7xx = devm_kzalloc(dev, sizeof(*dra7xx), GFP_KERNEL);
 614         if (!dra7xx)
 615                 return -ENOMEM;
 616
 617         pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
 618         if (!pci)
 619                 return -ENOMEM;
 620
 621         pci->dev = dev;
 622         pci->ops = &dw_pcie_ops;
 623
 624         irq = platform_get_irq(pdev, 0);
 625         if (irq < 0) {
 626                 dev_err(dev, "missing IRQ resource: %d\n", irq);
 627                 return irq;
 628         }
 629
 630         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ti_conf");
 631         base = devm_ioremap_nocache(dev, res->start, resource_size(res));
 632         if (!base)
 633                 return -ENOMEM;
 634
 635         phy_count = of_property_count_strings(np, "phy-names");
 636         if (phy_count < 0) {
 637                 dev_err(dev, "unable to find the strings\n");
 638                 return phy_count;
 639         }
 640
 641         phy = devm_kzalloc(dev, sizeof(*phy) * phy_count, GFP_KERNEL);
 642         if (!phy)
 643                 return -ENOMEM;
 644
 645         link = devm_kzalloc(dev, sizeof(*link) * phy_count, GFP_KERNEL);
 646         if (!link)
 647                 return -ENOMEM;
 648
 649         for (i = 0; i < phy_count; i++) {
 650                 snprintf(name, sizeof(name), "pcie-phy%d", i);
 651                 phy[i] = devm_phy_get(dev, name);
 652                 if (IS_ERR(phy[i]))
 653                         return PTR_ERR(phy[i]);
 654
 655                 link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS);
 656                 if (!link[i]) {
 657                         ret = -EINVAL;
 658                         goto err_link;
 659                 }
 660         }
 661
 662         dra7xx->base = base;
 663         dra7xx->phy = phy;
 664         dra7xx->pci = pci;
 665         dra7xx->phy_count = phy_count;
 666
 667         ret = dra7xx_pcie_enable_phy(dra7xx);
 668         if (ret) {
 669                 dev_err(dev, "failed to enable phy\n");
 670                 return ret;
 671         }
 672
 673         platform_set_drvdata(pdev, dra7xx);
 674
 675         pm_runtime_enable(dev);
 676         ret = pm_runtime_get_sync(dev);
 677         if (ret < 0) {
 678                 dev_err(dev, "pm_runtime_get_sync failed\n");
 679                 goto err_get_sync;
 680         }
 681
 682         reset = devm_gpiod_get_optional(dev, NULL, GPIOD_OUT_HIGH);
 683         if (IS_ERR(reset)) {
 684                 ret = PTR_ERR(reset);
 685                 dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
 686                 goto err_gpio;
 687         }
 688
 689         reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
 690         reg &= ~LTSSM_EN;
 691         dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
 692
 693         dra7xx->link_gen = of_pci_get_max_link_speed(np);
 694         if (dra7xx->link_gen < 0 || dra7xx->link_gen > 2)
 695                 dra7xx->link_gen = 2;
 696
 697         switch (mode) {
 698         case DW_PCIE_RC_TYPE:
 699                 if (!IS_ENABLED(CONFIG_PCI_DRA7XX_HOST)) {
 700                         ret = -ENODEV;
 701                         goto err_gpio;
 702                 }
 703
 704                 dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE,
 705                                    DEVICE_TYPE_RC);
 706                 ret = dra7xx_add_pcie_port(dra7xx, pdev);
 707                 if (ret < 0)
 708                         goto err_gpio;
 709                 break;
 710         case DW_PCIE_EP_TYPE:
 711                 if (!IS_ENABLED(CONFIG_PCI_DRA7XX_EP)) {
 712                         ret = -ENODEV;
 713                         goto err_gpio;
 714                 }
 715
 716                 dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE,
 717                                    DEVICE_TYPE_EP);
 718
 719                 ret = dra7xx_pcie_ep_unaligned_memaccess(dev);
 720                 if (ret)
 721                         goto err_gpio;
 722
 723                 ret = dra7xx_add_pcie_ep(dra7xx, pdev);
 724                 if (ret < 0)
 725                         goto err_gpio;
 726                 break;
 727         default:
 728                 dev_err(dev, "INVALID device type %d\n", mode);
 729         }
 730         dra7xx->mode = mode;
 731
 732         ret = devm_request_irq(dev, irq, dra7xx_pcie_irq_handler,
 733                                IRQF_SHARED, "dra7xx-pcie-main", dra7xx);
 734         if (ret) {
 735                 dev_err(dev, "failed to request irq\n");
 736                 goto err_gpio;
 737         }
 738
 739         return 0;
 740
 741 err_gpio:
 742         pm_runtime_put(dev);
 743
 744 err_get_sync:
 745         pm_runtime_disable(dev);
 746         dra7xx_pcie_disable_phy(dra7xx);
 747
 748 err_link:
 749         while (--i >= 0)
 750                 device_link_del(link[i]);
 751
 752         return ret;
 753 }
 754
 755 #ifdef CONFIG_PM_SLEEP
 756 static int dra7xx_pcie_suspend(struct device *dev)
 757 {
 758         struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
 759         struct dw_pcie *pci = dra7xx->pci;
 760         u32 val;
 761
 762         if (dra7xx->mode != DW_PCIE_RC_TYPE)
 763                 return 0;
 764
 765         /* clear MSE */
 766         val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
 767         val &= ~PCI_COMMAND_MEMORY;
 768         dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
 769
 770         return 0;
 771 }
 772
 773 static int dra7xx_pcie_resume(struct device *dev)
 774 {
 775         struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
 776         struct dw_pcie *pci = dra7xx->pci;
 777         u32 val;
 778
 779         if (dra7xx->mode != DW_PCIE_RC_TYPE)
 780                 return 0;
 781
 782         /* set MSE */
 783         val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
 784         val |= PCI_COMMAND_MEMORY;
 785         dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
 786
 787         return 0;
 788 }
 789
 790 static int dra7xx_pcie_suspend_noirq(struct device *dev)
 791 {
 792         struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
 793
 794         dra7xx_pcie_disable_phy(dra7xx);
 795
 796         return 0;
 797 }
 798
 799 static int dra7xx_pcie_resume_noirq(struct device *dev)
 800 {
 801         struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
 802         int ret;
 803
 804         ret = dra7xx_pcie_enable_phy(dra7xx);
 805         if (ret) {
 806                 dev_err(dev, "failed to enable phy\n");
 807                 return ret;
 808         }
 809
 810         return 0;
 811 }
 812 #endif
 813
 814 static void dra7xx_pcie_shutdown(struct platform_device *pdev)
 815 {
 816         struct device *dev = &pdev->dev;
 817         struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
 818         int ret;
 819
 820         dra7xx_pcie_stop_link(dra7xx->pci);
 821
 822         ret = pm_runtime_put_sync(dev);
 823         if (ret < 0)
 824                 dev_dbg(dev, "pm_runtime_put_sync failed\n");
 825
 826         pm_runtime_disable(dev);
 827         dra7xx_pcie_disable_phy(dra7xx);
 828 }
 829
 830 static const struct dev_pm_ops dra7xx_pcie_pm_ops = {
 831         SET_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend, dra7xx_pcie_resume)
 832         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend_noirq,
 833                                       dra7xx_pcie_resume_noirq)
 834 };
 835
 836 static struct platform_driver dra7xx_pcie_driver = {
 837         .driver = {
 838                 .name   = "dra7-pcie",
 839                 .of_match_table = of_dra7xx_pcie_match,
 840                 .suppress_bind_attrs = true,
 841                 .pm     = &dra7xx_pcie_pm_ops,
 842         },
 843         .shutdown = dra7xx_pcie_shutdown,
 844 };
 845 builtin_platform_driver_probe(dra7xx_pcie_driver, dra7xx_pcie_probe);