drivers/pinctrl/intel/pinctrl-intel.c

   1 /*
   2  * Intel pinctrl/GPIO core driver.
   3  *
   4  * Copyright (C) 2015, Intel Corporation
   5  * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
   6  *          Mika Westerberg <mika.westerberg@linux.intel.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/gpio/driver.h>
  16 #include <linux/log2.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pinctrl/pinctrl.h>
  19 #include <linux/pinctrl/pinmux.h>
  20 #include <linux/pinctrl/pinconf.h>
  21 #include <linux/pinctrl/pinconf-generic.h>
  22
  23 #include "../core.h"
  24 #include "pinctrl-intel.h"
  25
  26 /* Offset from regs */
  27 #define REVID                           0x000
  28 #define REVID_SHIFT                     16
  29 #define REVID_MASK                      GENMASK(31, 16)
  30
  31 #define PADBAR                          0x00c
  32 #define GPI_IS                          0x100
  33
  34 #define PADOWN_BITS                     4
  35 #define PADOWN_SHIFT(p)                 ((p) % 8 * PADOWN_BITS)
  36 #define PADOWN_MASK(p)                  (0xf << PADOWN_SHIFT(p))
  37 #define PADOWN_GPP(p)                   ((p) / 8)
  38
  39 /* Offset from pad_regs */
  40 #define PADCFG0                         0x000
  41 #define PADCFG0_RXEVCFG_SHIFT           25
  42 #define PADCFG0_RXEVCFG_MASK            (3 << PADCFG0_RXEVCFG_SHIFT)
  43 #define PADCFG0_RXEVCFG_LEVEL           0
  44 #define PADCFG0_RXEVCFG_EDGE            1
  45 #define PADCFG0_RXEVCFG_DISABLED        2
  46 #define PADCFG0_RXEVCFG_EDGE_BOTH       3
  47 #define PADCFG0_PREGFRXSEL              BIT(24)
  48 #define PADCFG0_RXINV                   BIT(23)
  49 #define PADCFG0_GPIROUTIOXAPIC          BIT(20)
  50 #define PADCFG0_GPIROUTSCI              BIT(19)
  51 #define PADCFG0_GPIROUTSMI              BIT(18)
  52 #define PADCFG0_GPIROUTNMI              BIT(17)
  53 #define PADCFG0_PMODE_SHIFT             10
  54 #define PADCFG0_PMODE_MASK              (0xf << PADCFG0_PMODE_SHIFT)
  55 #define PADCFG0_GPIORXDIS               BIT(9)
  56 #define PADCFG0_GPIOTXDIS               BIT(8)
  57 #define PADCFG0_GPIORXSTATE             BIT(1)
  58 #define PADCFG0_GPIOTXSTATE             BIT(0)
  59
  60 #define PADCFG1                         0x004
  61 #define PADCFG1_TERM_UP                 BIT(13)
  62 #define PADCFG1_TERM_SHIFT              10
  63 #define PADCFG1_TERM_MASK               (7 << PADCFG1_TERM_SHIFT)
  64 #define PADCFG1_TERM_20K                4
  65 #define PADCFG1_TERM_2K                 3
  66 #define PADCFG1_TERM_5K                 2
  67 #define PADCFG1_TERM_1K                 1
  68
  69 #define PADCFG2                         0x008
  70 #define PADCFG2_DEBEN                   BIT(0)
  71 #define PADCFG2_DEBOUNCE_SHIFT          1
  72 #define PADCFG2_DEBOUNCE_MASK           GENMASK(4, 1)
  73
  74 #define DEBOUNCE_PERIOD                 31250 /* ns */
  75
  76 struct intel_pad_context {
  77         u32 padcfg0;
  78         u32 padcfg1;
  79         u32 padcfg2;
  80 };
  81
  82 struct intel_community_context {
  83         u32 *intmask;
  84 };
  85
  86 struct intel_pinctrl_context {
  87         struct intel_pad_context *pads;
  88         struct intel_community_context *communities;
  89 };
  90
  91 /**
  92  * struct intel_pinctrl - Intel pinctrl private structure
  93  * @dev: Pointer to the device structure
  94  * @lock: Lock to serialize register access
  95  * @pctldesc: Pin controller description
  96  * @pctldev: Pointer to the pin controller device
  97  * @chip: GPIO chip in this pin controller
  98  * @soc: SoC/PCH specific pin configuration data
  99  * @communities: All communities in this pin controller
 100  * @ncommunities: Number of communities in this pin controller
 101  * @context: Configuration saved over system sleep
 102  * @irq: pinctrl/GPIO chip irq number
 103  */
 104 struct intel_pinctrl {
 105         struct device *dev;
 106         raw_spinlock_t lock;
 107         struct pinctrl_desc pctldesc;
 108         struct pinctrl_dev *pctldev;
 109         struct gpio_chip chip;
 110         const struct intel_pinctrl_soc_data *soc;
 111         struct intel_community *communities;
 112         size_t ncommunities;
 113         struct intel_pinctrl_context context;
 114         int irq;
 115 };
 116
 117 #define pin_to_padno(c, p)      ((p) - (c)->pin_base)
 118 #define padgroup_offset(g, p)   ((p) - (g)->base)
 119
 120 static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl,
 121                                                    unsigned pin)
 122 {
 123         struct intel_community *community;
 124         int i;
 125
 126         for (i = 0; i < pctrl->ncommunities; i++) {
 127                 community = &pctrl->communities[i];
 128                 if (pin >= community->pin_base &&
 129                     pin < community->pin_base + community->npins)
 130                         return community;
 131         }
 132
 133         dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin);
 134         return NULL;
 135 }
 136
 137 static const struct intel_padgroup *
 138 intel_community_get_padgroup(const struct intel_community *community,
 139                              unsigned pin)
 140 {
 141         int i;
 142
 143         for (i = 0; i < community->ngpps; i++) {
 144                 const struct intel_padgroup *padgrp = &community->gpps[i];
 145
 146                 if (pin >= padgrp->base && pin < padgrp->base + padgrp->size)
 147                         return padgrp;
 148         }
 149
 150         return NULL;
 151 }
 152
 153 static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, unsigned pin,
 154                                       unsigned reg)
 155 {
 156         const struct intel_community *community;
 157         unsigned padno;
 158         size_t nregs;
 159
 160         community = intel_get_community(pctrl, pin);
 161         if (!community)
 162                 return NULL;
 163
 164         padno = pin_to_padno(community, pin);
 165         nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2;
 166
 167         if (reg == PADCFG2 && !(community->features & PINCTRL_FEATURE_DEBOUNCE))
 168                 return NULL;
 169
 170         return community->pad_regs + reg + padno * nregs * 4;
 171 }
 172
 173 static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin)
 174 {
 175         const struct intel_community *community;
 176         const struct intel_padgroup *padgrp;
 177         unsigned gpp, offset, gpp_offset;
 178         void __iomem *padown;
 179
 180         community = intel_get_community(pctrl, pin);
 181         if (!community)
 182                 return false;
 183         if (!community->padown_offset)
 184                 return true;
 185
 186         padgrp = intel_community_get_padgroup(community, pin);
 187         if (!padgrp)
 188                 return false;
 189
 190         gpp_offset = padgroup_offset(padgrp, pin);
 191         gpp = PADOWN_GPP(gpp_offset);
 192         offset = community->padown_offset + padgrp->padown_num * 4 + gpp * 4;
 193         padown = community->regs + offset;
 194
 195         return !(readl(padown) & PADOWN_MASK(gpp_offset));
 196 }
 197
 198 static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned pin)
 199 {
 200         const struct intel_community *community;
 201         const struct intel_padgroup *padgrp;
 202         unsigned offset, gpp_offset;
 203         void __iomem *hostown;
 204
 205         community = intel_get_community(pctrl, pin);
 206         if (!community)
 207                 return true;
 208         if (!community->hostown_offset)
 209                 return false;
 210
 211         padgrp = intel_community_get_padgroup(community, pin);
 212         if (!padgrp)
 213                 return true;
 214
 215         gpp_offset = padgroup_offset(padgrp, pin);
 216         offset = community->hostown_offset + padgrp->reg_num * 4;
 217         hostown = community->regs + offset;
 218
 219         return !(readl(hostown) & BIT(gpp_offset));
 220 }
 221
 222 static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin)
 223 {
 224         struct intel_community *community;
 225         const struct intel_padgroup *padgrp;
 226         unsigned offset, gpp_offset;
 227         u32 value;
 228
 229         community = intel_get_community(pctrl, pin);
 230         if (!community)
 231                 return true;
 232         if (!community->padcfglock_offset)
 233                 return false;
 234
 235         padgrp = intel_community_get_padgroup(community, pin);
 236         if (!padgrp)
 237                 return true;
 238
 239         gpp_offset = padgroup_offset(padgrp, pin);
 240
 241         /*
 242          * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad,
 243          * the pad is considered unlocked. Any other case means that it is
 244          * either fully or partially locked and we don't touch it.
 245          */
 246         offset = community->padcfglock_offset + padgrp->reg_num * 8;
 247         value = readl(community->regs + offset);
 248         if (value & BIT(gpp_offset))
 249                 return true;
 250
 251         offset = community->padcfglock_offset + 4 + padgrp->reg_num * 8;
 252         value = readl(community->regs + offset);
 253         if (value & BIT(gpp_offset))
 254                 return true;
 255
 256         return false;
 257 }
 258
 259 static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned pin)
 260 {
 261         return intel_pad_owned_by_host(pctrl, pin) &&
 262                 !intel_pad_locked(pctrl, pin);
 263 }
 264
 265 static int intel_get_groups_count(struct pinctrl_dev *pctldev)
 266 {
 267         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 268
 269         return pctrl->soc->ngroups;
 270 }
 271
 272 static const char *intel_get_group_name(struct pinctrl_dev *pctldev,
 273                                       unsigned group)
 274 {
 275         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 276
 277         return pctrl->soc->groups[group].name;
 278 }
 279
 280 static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
 281                               const unsigned **pins, unsigned *npins)
 282 {
 283         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 284
 285         *pins = pctrl->soc->groups[group].pins;
 286         *npins = pctrl->soc->groups[group].npins;
 287         return 0;
 288 }
 289
 290 static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
 291                                unsigned pin)
 292 {
 293         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 294         void __iomem *padcfg;
 295         u32 cfg0, cfg1, mode;
 296         bool locked, acpi;
 297
 298         if (!intel_pad_owned_by_host(pctrl, pin)) {
 299                 seq_puts(s, "not available");
 300                 return;
 301         }
 302
 303         cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0));
 304         cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
 305
 306         mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
 307         if (!mode)
 308                 seq_puts(s, "GPIO ");
 309         else
 310                 seq_printf(s, "mode %d ", mode);
 311
 312         seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1);
 313
 314         /* Dump the additional PADCFG registers if available */
 315         padcfg = intel_get_padcfg(pctrl, pin, PADCFG2);
 316         if (padcfg)
 317                 seq_printf(s, " 0x%08x", readl(padcfg));
 318
 319         locked = intel_pad_locked(pctrl, pin);
 320         acpi = intel_pad_acpi_mode(pctrl, pin);
 321
 322         if (locked || acpi) {
 323                 seq_puts(s, " [");
 324                 if (locked) {
 325                         seq_puts(s, "LOCKED");
 326                         if (acpi)
 327                                 seq_puts(s, ", ");
 328                 }
 329                 if (acpi)
 330                         seq_puts(s, "ACPI");
 331                 seq_puts(s, "]");
 332         }
 333 }
 334
 335 static const struct pinctrl_ops intel_pinctrl_ops = {
 336         .get_groups_count = intel_get_groups_count,
 337         .get_group_name = intel_get_group_name,
 338         .get_group_pins = intel_get_group_pins,
 339         .pin_dbg_show = intel_pin_dbg_show,
 340 };
 341
 342 static int intel_get_functions_count(struct pinctrl_dev *pctldev)
 343 {
 344         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 345
 346         return pctrl->soc->nfunctions;
 347 }
 348
 349 static const char *intel_get_function_name(struct pinctrl_dev *pctldev,
 350                                            unsigned function)
 351 {
 352         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 353
 354         return pctrl->soc->functions[function].name;
 355 }
 356
 357 static int intel_get_function_groups(struct pinctrl_dev *pctldev,
 358                                      unsigned function,
 359                                      const char * const **groups,
 360                                      unsigned * const ngroups)
 361 {
 362         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 363
 364         *groups = pctrl->soc->functions[function].groups;
 365         *ngroups = pctrl->soc->functions[function].ngroups;
 366         return 0;
 367 }
 368
 369 static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function,
 370                                 unsigned group)
 371 {
 372         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 373         const struct intel_pingroup *grp = &pctrl->soc->groups[group];
 374         unsigned long flags;
 375         int i;
 376
 377         raw_spin_lock_irqsave(&pctrl->lock, flags);
 378
 379         /*
 380          * All pins in the groups needs to be accessible and writable
 381          * before we can enable the mux for this group.
 382          */
 383         for (i = 0; i < grp->npins; i++) {
 384                 if (!intel_pad_usable(pctrl, grp->pins[i])) {
 385                         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 386                         return -EBUSY;
 387                 }
 388         }
 389
 390         /* Now enable the mux setting for each pin in the group */
 391         for (i = 0; i < grp->npins; i++) {
 392                 void __iomem *padcfg0;
 393                 u32 value;
 394
 395                 padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0);
 396                 value = readl(padcfg0);
 397
 398                 value &= ~PADCFG0_PMODE_MASK;
 399
 400                 if (grp->modes)
 401                         value |= grp->modes[i] << PADCFG0_PMODE_SHIFT;
 402                 else
 403                         value |= grp->mode << PADCFG0_PMODE_SHIFT;
 404
 405                 writel(value, padcfg0);
 406         }
 407
 408         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 409
 410         return 0;
 411 }
 412
 413 static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input)
 414 {
 415         u32 value;
 416
 417         value = readl(padcfg0);
 418         if (input) {
 419                 value &= ~PADCFG0_GPIORXDIS;
 420                 value |= PADCFG0_GPIOTXDIS;
 421         } else {
 422                 value &= ~PADCFG0_GPIOTXDIS;
 423                 value |= PADCFG0_GPIORXDIS;
 424         }
 425         writel(value, padcfg0);
 426 }
 427
 428 static void intel_gpio_set_gpio_mode(void __iomem *padcfg0)
 429 {
 430         u32 value;
 431
 432         /* Put the pad into GPIO mode */
 433         value = readl(padcfg0) & ~PADCFG0_PMODE_MASK;
 434         /* Disable SCI/SMI/NMI generation */
 435         value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
 436         value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI);
 437         writel(value, padcfg0);
 438 }
 439
 440 static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
 441                                      struct pinctrl_gpio_range *range,
 442                                      unsigned pin)
 443 {
 444         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 445         void __iomem *padcfg0;
 446         unsigned long flags;
 447
 448         raw_spin_lock_irqsave(&pctrl->lock, flags);
 449
 450         if (!intel_pad_usable(pctrl, pin)) {
 451                 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 452                 return -EBUSY;
 453         }
 454
 455         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
 456         intel_gpio_set_gpio_mode(padcfg0);
 457         /* Disable TX buffer and enable RX (this will be input) */
 458         __intel_gpio_set_direction(padcfg0, true);
 459
 460         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 461
 462         return 0;
 463 }
 464
 465 static int intel_gpio_set_direction(struct pinctrl_dev *pctldev,
 466                                     struct pinctrl_gpio_range *range,
 467                                     unsigned pin, bool input)
 468 {
 469         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 470         void __iomem *padcfg0;
 471         unsigned long flags;
 472
 473         raw_spin_lock_irqsave(&pctrl->lock, flags);
 474
 475         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
 476         __intel_gpio_set_direction(padcfg0, input);
 477
 478         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 479
 480         return 0;
 481 }
 482
 483 static const struct pinmux_ops intel_pinmux_ops = {
 484         .get_functions_count = intel_get_functions_count,
 485         .get_function_name = intel_get_function_name,
 486         .get_function_groups = intel_get_function_groups,
 487         .set_mux = intel_pinmux_set_mux,
 488         .gpio_request_enable = intel_gpio_request_enable,
 489         .gpio_set_direction = intel_gpio_set_direction,
 490 };
 491
 492 static int intel_config_get(struct pinctrl_dev *pctldev, unsigned pin,
 493                             unsigned long *config)
 494 {
 495         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 496         enum pin_config_param param = pinconf_to_config_param(*config);
 497         const struct intel_community *community;
 498         u32 value, term;
 499         u32 arg = 0;
 500
 501         if (!intel_pad_owned_by_host(pctrl, pin))
 502                 return -ENOTSUPP;
 503
 504         community = intel_get_community(pctrl, pin);
 505         value = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
 506         term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT;
 507
 508         switch (param) {
 509         case PIN_CONFIG_BIAS_DISABLE:
 510                 if (term)
 511                         return -EINVAL;
 512                 break;
 513
 514         case PIN_CONFIG_BIAS_PULL_UP:
 515                 if (!term || !(value & PADCFG1_TERM_UP))
 516                         return -EINVAL;
 517
 518                 switch (term) {
 519                 case PADCFG1_TERM_1K:
 520                         arg = 1000;
 521                         break;
 522                 case PADCFG1_TERM_2K:
 523                         arg = 2000;
 524                         break;
 525                 case PADCFG1_TERM_5K:
 526                         arg = 5000;
 527                         break;
 528                 case PADCFG1_TERM_20K:
 529                         arg = 20000;
 530                         break;
 531                 }
 532
 533                 break;
 534
 535         case PIN_CONFIG_BIAS_PULL_DOWN:
 536                 if (!term || value & PADCFG1_TERM_UP)
 537                         return -EINVAL;
 538
 539                 switch (term) {
 540                 case PADCFG1_TERM_1K:
 541                         if (!(community->features & PINCTRL_FEATURE_1K_PD))
 542                                 return -EINVAL;
 543                         arg = 1000;
 544                         break;
 545                 case PADCFG1_TERM_5K:
 546                         arg = 5000;
 547                         break;
 548                 case PADCFG1_TERM_20K:
 549                         arg = 20000;
 550                         break;
 551                 }
 552
 553                 break;
 554
 555         case PIN_CONFIG_INPUT_DEBOUNCE: {
 556                 void __iomem *padcfg2;
 557                 u32 v;
 558
 559                 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
 560                 if (!padcfg2)
 561                         return -ENOTSUPP;
 562
 563                 v = readl(padcfg2);
 564                 if (!(v & PADCFG2_DEBEN))
 565                         return -EINVAL;
 566
 567                 v = (v & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT;
 568                 arg = BIT(v) * DEBOUNCE_PERIOD / 1000;
 569
 570                 break;
 571         }
 572
 573         default:
 574                 return -ENOTSUPP;
 575         }
 576
 577         *config = pinconf_to_config_packed(param, arg);
 578         return 0;
 579 }
 580
 581 static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned pin,
 582                                  unsigned long config)
 583 {
 584         unsigned param = pinconf_to_config_param(config);
 585         unsigned arg = pinconf_to_config_argument(config);
 586         const struct intel_community *community;
 587         void __iomem *padcfg1;
 588         unsigned long flags;
 589         int ret = 0;
 590         u32 value;
 591
 592         raw_spin_lock_irqsave(&pctrl->lock, flags);
 593
 594         community = intel_get_community(pctrl, pin);
 595         padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
 596         value = readl(padcfg1);
 597
 598         switch (param) {
 599         case PIN_CONFIG_BIAS_DISABLE:
 600                 value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP);
 601                 break;
 602
 603         case PIN_CONFIG_BIAS_PULL_UP:
 604                 value &= ~PADCFG1_TERM_MASK;
 605
 606                 value |= PADCFG1_TERM_UP;
 607
 608                 switch (arg) {
 609                 case 20000:
 610                         value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
 611                         break;
 612                 case 5000:
 613                         value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
 614                         break;
 615                 case 2000:
 616                         value |= PADCFG1_TERM_2K << PADCFG1_TERM_SHIFT;
 617                         break;
 618                 case 1000:
 619                         value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
 620                         break;
 621                 default:
 622                         ret = -EINVAL;
 623                 }
 624
 625                 break;
 626
 627         case PIN_CONFIG_BIAS_PULL_DOWN:
 628                 value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK);
 629
 630                 switch (arg) {
 631                 case 20000:
 632                         value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
 633                         break;
 634                 case 5000:
 635                         value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
 636                         break;
 637                 case 1000:
 638                         if (!(community->features & PINCTRL_FEATURE_1K_PD)) {
 639                                 ret = -EINVAL;
 640                                 break;
 641                         }
 642                         value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
 643                         break;
 644                 default:
 645                         ret = -EINVAL;
 646                 }
 647
 648                 break;
 649         }
 650
 651         if (!ret)
 652                 writel(value, padcfg1);
 653
 654         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 655
 656         return ret;
 657 }
 658
 659 static int intel_config_set_debounce(struct intel_pinctrl *pctrl, unsigned pin,
 660                                      unsigned debounce)
 661 {
 662         void __iomem *padcfg0, *padcfg2;
 663         unsigned long flags;
 664         u32 value0, value2;
 665         int ret = 0;
 666
 667         padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
 668         if (!padcfg2)
 669                 return -ENOTSUPP;
 670
 671         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
 672
 673         raw_spin_lock_irqsave(&pctrl->lock, flags);
 674
 675         value0 = readl(padcfg0);
 676         value2 = readl(padcfg2);
 677
 678         /* Disable glitch filter and debouncer */
 679         value0 &= ~PADCFG0_PREGFRXSEL;
 680         value2 &= ~(PADCFG2_DEBEN | PADCFG2_DEBOUNCE_MASK);
 681
 682         if (debounce) {
 683                 unsigned long v;
 684
 685                 v = order_base_2(debounce * 1000 / DEBOUNCE_PERIOD);
 686                 if (v < 3 || v > 15) {
 687                         ret = -EINVAL;
 688                         goto exit_unlock;
 689                 } else {
 690                         /* Enable glitch filter and debouncer */
 691                         value0 |= PADCFG0_PREGFRXSEL;
 692                         value2 |= v << PADCFG2_DEBOUNCE_SHIFT;
 693                         value2 |= PADCFG2_DEBEN;
 694                 }
 695         }
 696
 697         writel(value0, padcfg0);
 698         writel(value2, padcfg2);
 699
 700 exit_unlock:
 701         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 702
 703         return ret;
 704 }
 705
 706 static int intel_config_set(struct pinctrl_dev *pctldev, unsigned pin,
 707                           unsigned long *configs, unsigned nconfigs)
 708 {
 709         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 710         int i, ret;
 711
 712         if (!intel_pad_usable(pctrl, pin))
 713                 return -ENOTSUPP;
 714
 715         for (i = 0; i < nconfigs; i++) {
 716                 switch (pinconf_to_config_param(configs[i])) {
 717                 case PIN_CONFIG_BIAS_DISABLE:
 718                 case PIN_CONFIG_BIAS_PULL_UP:
 719                 case PIN_CONFIG_BIAS_PULL_DOWN:
 720                         ret = intel_config_set_pull(pctrl, pin, configs[i]);
 721                         if (ret)
 722                                 return ret;
 723                         break;
 724
 725                 case PIN_CONFIG_INPUT_DEBOUNCE:
 726                         ret = intel_config_set_debounce(pctrl, pin,
 727                                 pinconf_to_config_argument(configs[i]));
 728                         if (ret)
 729                                 return ret;
 730                         break;
 731
 732                 default:
 733                         return -ENOTSUPP;
 734                 }
 735         }
 736
 737         return 0;
 738 }
 739
 740 static const struct pinconf_ops intel_pinconf_ops = {
 741         .is_generic = true,
 742         .pin_config_get = intel_config_get,
 743         .pin_config_set = intel_config_set,
 744 };
 745
 746 static const struct pinctrl_desc intel_pinctrl_desc = {
 747         .pctlops = &intel_pinctrl_ops,
 748         .pmxops = &intel_pinmux_ops,
 749         .confops = &intel_pinconf_ops,
 750         .owner = THIS_MODULE,
 751 };
 752
 753 static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
 754 {
 755         struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
 756         void __iomem *reg;
 757         u32 padcfg0;
 758
 759         reg = intel_get_padcfg(pctrl, offset, PADCFG0);
 760         if (!reg)
 761                 return -EINVAL;
 762
 763         padcfg0 = readl(reg);
 764         if (!(padcfg0 & PADCFG0_GPIOTXDIS))
 765                 return !!(padcfg0 & PADCFG0_GPIOTXSTATE);
 766
 767         return !!(padcfg0 & PADCFG0_GPIORXSTATE);
 768 }
 769
 770 static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 771 {
 772         struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
 773         unsigned long flags;
 774         void __iomem *reg;
 775         u32 padcfg0;
 776
 777         reg = intel_get_padcfg(pctrl, offset, PADCFG0);
 778         if (!reg)
 779                 return;
 780
 781         raw_spin_lock_irqsave(&pctrl->lock, flags);
 782         padcfg0 = readl(reg);
 783         if (value)
 784                 padcfg0 |= PADCFG0_GPIOTXSTATE;
 785         else
 786                 padcfg0 &= ~PADCFG0_GPIOTXSTATE;
 787         writel(padcfg0, reg);
 788         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 789 }
 790
 791 static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 792 {
 793         return pinctrl_gpio_direction_input(chip->base + offset);
 794 }
 795
 796 static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
 797                                        int value)
 798 {
 799         intel_gpio_set(chip, offset, value);
 800         return pinctrl_gpio_direction_output(chip->base + offset);
 801 }
 802
 803 static const struct gpio_chip intel_gpio_chip = {
 804         .owner = THIS_MODULE,
 805         .request = gpiochip_generic_request,
 806         .free = gpiochip_generic_free,
 807         .direction_input = intel_gpio_direction_input,
 808         .direction_output = intel_gpio_direction_output,
 809         .get = intel_gpio_get,
 810         .set = intel_gpio_set,
 811         .set_config = gpiochip_generic_config,
 812 };
 813
 814 /**
 815  * intel_gpio_to_pin() - Translate from GPIO offset to pin number
 816  * @pctrl: Pinctrl structure
 817  * @offset: GPIO offset from gpiolib
 818  * @commmunity: Community is filled here if not %NULL
 819  * @padgrp: Pad group is filled here if not %NULL
 820  *
 821  * When coming through gpiolib irqchip, the GPIO offset is not
 822  * automatically translated to pinctrl pin number. This function can be
 823  * used to find out the corresponding pinctrl pin.
 824  */
 825 static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned offset,
 826                              const struct intel_community **community,
 827                              const struct intel_padgroup **padgrp)
 828 {
 829         int i;
 830
 831         for (i = 0; i < pctrl->ncommunities; i++) {
 832                 const struct intel_community *comm = &pctrl->communities[i];
 833                 int j;
 834
 835                 for (j = 0; j < comm->ngpps; j++) {
 836                         const struct intel_padgroup *pgrp = &comm->gpps[j];
 837
 838                         if (pgrp->gpio_base < 0)
 839                                 continue;
 840
 841                         if (offset >= pgrp->gpio_base &&
 842                             offset < pgrp->gpio_base + pgrp->size) {
 843                                 int pin;
 844
 845                                 pin = pgrp->base + offset - pgrp->gpio_base;
 846                                 if (community)
 847                                         *community = comm;
 848                                 if (padgrp)
 849                                         *padgrp = pgrp;
 850
 851                                 return pin;
 852                         }
 853                 }
 854         }
 855
 856         return -EINVAL;
 857 }
 858
 859 static void intel_gpio_irq_ack(struct irq_data *d)
 860 {
 861         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 862         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
 863         const struct intel_community *community;
 864         const struct intel_padgroup *padgrp;
 865         int pin;
 866
 867         pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
 868         if (pin >= 0) {
 869                 unsigned gpp, gpp_offset, is_offset;
 870
 871                 gpp = padgrp->reg_num;
 872                 gpp_offset = padgroup_offset(padgrp, pin);
 873                 is_offset = community->is_offset + gpp * 4;
 874
 875                 raw_spin_lock(&pctrl->lock);
 876                 writel(BIT(gpp_offset), community->regs + is_offset);
 877                 raw_spin_unlock(&pctrl->lock);
 878         }
 879 }
 880
 881 static void intel_gpio_irq_enable(struct irq_data *d)
 882 {
 883         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 884         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
 885         const struct intel_community *community;
 886         const struct intel_padgroup *padgrp;
 887         int pin;
 888
 889         pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
 890         if (pin >= 0) {
 891                 unsigned gpp, gpp_offset, is_offset;
 892                 unsigned long flags;
 893                 u32 value;
 894
 895                 gpp = padgrp->reg_num;
 896                 gpp_offset = padgroup_offset(padgrp, pin);
 897                 is_offset = community->is_offset + gpp * 4;
 898
 899                 raw_spin_lock_irqsave(&pctrl->lock, flags);
 900                 /* Clear interrupt status first to avoid unexpected interrupt */
 901                 writel(BIT(gpp_offset), community->regs + is_offset);
 902
 903                 value = readl(community->regs + community->ie_offset + gpp * 4);
 904                 value |= BIT(gpp_offset);
 905                 writel(value, community->regs + community->ie_offset + gpp * 4);
 906                 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 907         }
 908 }
 909
 910 static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
 911 {
 912         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 913         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
 914         const struct intel_community *community;
 915         const struct intel_padgroup *padgrp;
 916         int pin;
 917
 918         pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
 919         if (pin >= 0) {
 920                 unsigned gpp, gpp_offset;
 921                 unsigned long flags;
 922                 void __iomem *reg;
 923                 u32 value;
 924
 925                 gpp = padgrp->reg_num;
 926                 gpp_offset = padgroup_offset(padgrp, pin);
 927
 928                 reg = community->regs + community->ie_offset + gpp * 4;
 929
 930                 raw_spin_lock_irqsave(&pctrl->lock, flags);
 931                 value = readl(reg);
 932                 if (mask)
 933                         value &= ~BIT(gpp_offset);
 934                 else
 935                         value |= BIT(gpp_offset);
 936                 writel(value, reg);
 937                 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 938         }
 939 }
 940
 941 static void intel_gpio_irq_mask(struct irq_data *d)
 942 {
 943         intel_gpio_irq_mask_unmask(d, true);
 944 }
 945
 946 static void intel_gpio_irq_unmask(struct irq_data *d)
 947 {
 948         intel_gpio_irq_mask_unmask(d, false);
 949 }
 950
 951 static int intel_gpio_irq_type(struct irq_data *d, unsigned type)
 952 {
 953         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 954         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
 955         unsigned pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
 956         unsigned long flags;
 957         void __iomem *reg;
 958         u32 value;
 959
 960         reg = intel_get_padcfg(pctrl, pin, PADCFG0);
 961         if (!reg)
 962                 return -EINVAL;
 963
 964         /*
 965          * If the pin is in ACPI mode it is still usable as a GPIO but it
 966          * cannot be used as IRQ because GPI_IS status bit will not be
 967          * updated by the host controller hardware.
 968          */
 969         if (intel_pad_acpi_mode(pctrl, pin)) {
 970                 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin);
 971                 return -EPERM;
 972         }
 973
 974         raw_spin_lock_irqsave(&pctrl->lock, flags);
 975
 976         intel_gpio_set_gpio_mode(reg);
 977
 978         value = readl(reg);
 979
 980         value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV);
 981
 982         if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
 983                 value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT;
 984         } else if (type & IRQ_TYPE_EDGE_FALLING) {
 985                 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
 986                 value |= PADCFG0_RXINV;
 987         } else if (type & IRQ_TYPE_EDGE_RISING) {
 988                 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
 989         } else if (type & IRQ_TYPE_LEVEL_MASK) {
 990                 if (type & IRQ_TYPE_LEVEL_LOW)
 991                         value |= PADCFG0_RXINV;
 992         } else {
 993                 value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT;
 994         }
 995
 996         writel(value, reg);
 997
 998         if (type & IRQ_TYPE_EDGE_BOTH)
 999                 irq_set_handler_locked(d, handle_edge_irq);
1000         else if (type & IRQ_TYPE_LEVEL_MASK)
1001                 irq_set_handler_locked(d, handle_level_irq);
1002
1003         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1004
1005         return 0;
1006 }
1007
1008 static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on)
1009 {
1010         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1011         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1012         unsigned pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
1013
1014         if (on)
1015                 enable_irq_wake(pctrl->irq);
1016         else
1017                 disable_irq_wake(pctrl->irq);
1018
1019         dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin);
1020         return 0;
1021 }
1022
1023 static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
1024         const struct intel_community *community)
1025 {
1026         struct gpio_chip *gc = &pctrl->chip;
1027         irqreturn_t ret = IRQ_NONE;
1028         int gpp;
1029
1030         for (gpp = 0; gpp < community->ngpps; gpp++) {
1031                 const struct intel_padgroup *padgrp = &community->gpps[gpp];
1032                 unsigned long pending, enabled, gpp_offset;
1033
1034                 pending = readl(community->regs + community->is_offset +
1035                                 padgrp->reg_num * 4);
1036                 enabled = readl(community->regs + community->ie_offset +
1037                                 padgrp->reg_num * 4);
1038
1039                 /* Only interrupts that are enabled */
1040                 pending &= enabled;
1041
1042                 for_each_set_bit(gpp_offset, &pending, padgrp->size) {
1043                         unsigned irq;
1044
1045                         irq = irq_find_mapping(gc->irq.domain,
1046                                                padgrp->gpio_base + gpp_offset);
1047                         generic_handle_irq(irq);
1048
1049                         ret |= IRQ_HANDLED;
1050                 }
1051         }
1052
1053         return ret;
1054 }
1055
1056 static irqreturn_t intel_gpio_irq(int irq, void *data)
1057 {
1058         const struct intel_community *community;
1059         struct intel_pinctrl *pctrl = data;
1060         irqreturn_t ret = IRQ_NONE;
1061         int i;
1062
1063         /* Need to check all communities for pending interrupts */
1064         for (i = 0; i < pctrl->ncommunities; i++) {
1065                 community = &pctrl->communities[i];
1066                 ret |= intel_gpio_community_irq_handler(pctrl, community);
1067         }
1068
1069         return ret;
1070 }
1071
1072 static struct irq_chip intel_gpio_irqchip = {
1073         .name = "intel-gpio",
1074         .irq_enable = intel_gpio_irq_enable,
1075         .irq_ack = intel_gpio_irq_ack,
1076         .irq_mask = intel_gpio_irq_mask,
1077         .irq_unmask = intel_gpio_irq_unmask,
1078         .irq_set_type = intel_gpio_irq_type,
1079         .irq_set_wake = intel_gpio_irq_wake,
1080         .flags = IRQCHIP_MASK_ON_SUSPEND,
1081 };
1082
1083 static int intel_gpio_add_pin_ranges(struct intel_pinctrl *pctrl,
1084                                      const struct intel_community *community)
1085 {
1086         int ret = 0, i;
1087
1088         for (i = 0; i < community->ngpps; i++) {
1089                 const struct intel_padgroup *gpp = &community->gpps[i];
1090
1091                 if (gpp->gpio_base < 0)
1092                         continue;
1093
1094                 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
1095                                              gpp->gpio_base, gpp->base,
1096                                              gpp->size);
1097                 if (ret)
1098                         return ret;
1099         }
1100
1101         return ret;
1102 }
1103
1104 static unsigned intel_gpio_ngpio(const struct intel_pinctrl *pctrl)
1105 {
1106         const struct intel_community *community;
1107         unsigned ngpio = 0;
1108         int i, j;
1109
1110         for (i = 0; i < pctrl->ncommunities; i++) {
1111                 community = &pctrl->communities[i];
1112                 for (j = 0; j < community->ngpps; j++) {
1113                         const struct intel_padgroup *gpp = &community->gpps[j];
1114
1115                         if (gpp->gpio_base < 0)
1116                                 continue;
1117
1118                         if (gpp->gpio_base + gpp->size > ngpio)
1119                                 ngpio = gpp->gpio_base + gpp->size;
1120                 }
1121         }
1122
1123         return ngpio;
1124 }
1125
1126 static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
1127 {
1128         int ret, i;
1129
1130         pctrl->chip = intel_gpio_chip;
1131
1132         pctrl->chip.ngpio = intel_gpio_ngpio(pctrl);
1133         pctrl->chip.label = dev_name(pctrl->dev);
1134         pctrl->chip.parent = pctrl->dev;
1135         pctrl->chip.base = -1;
1136         pctrl->irq = irq;
1137
1138         ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl);
1139         if (ret) {
1140                 dev_err(pctrl->dev, "failed to register gpiochip\n");
1141                 return ret;
1142         }
1143
1144         for (i = 0; i < pctrl->ncommunities; i++) {
1145                 struct intel_community *community = &pctrl->communities[i];
1146
1147                 ret = intel_gpio_add_pin_ranges(pctrl, community);
1148                 if (ret) {
1149                         dev_err(pctrl->dev, "failed to add GPIO pin range\n");
1150                         return ret;
1151                 }
1152         }
1153
1154         /*
1155          * We need to request the interrupt here (instead of providing chip
1156          * to the irq directly) because on some platforms several GPIO
1157          * controllers share the same interrupt line.
1158          */
1159         ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq,
1160                                IRQF_SHARED | IRQF_NO_THREAD,
1161                                dev_name(pctrl->dev), pctrl);
1162         if (ret) {
1163                 dev_err(pctrl->dev, "failed to request interrupt\n");
1164                 return ret;
1165         }
1166
1167         ret = gpiochip_irqchip_add(&pctrl->chip, &intel_gpio_irqchip, 0,
1168                                    handle_bad_irq, IRQ_TYPE_NONE);
1169         if (ret) {
1170                 dev_err(pctrl->dev, "failed to add irqchip\n");
1171                 return ret;
1172         }
1173
1174         gpiochip_set_chained_irqchip(&pctrl->chip, &intel_gpio_irqchip, irq,
1175                                      NULL);
1176         return 0;
1177 }
1178
1179 static int intel_pinctrl_add_padgroups(struct intel_pinctrl *pctrl,
1180                                        struct intel_community *community)
1181 {
1182         struct intel_padgroup *gpps;
1183         unsigned npins = community->npins;
1184         unsigned padown_num = 0;
1185         size_t ngpps, i;
1186
1187         if (community->gpps)
1188                 ngpps = community->ngpps;
1189         else
1190                 ngpps = DIV_ROUND_UP(community->npins, community->gpp_size);
1191
1192         gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL);
1193         if (!gpps)
1194                 return -ENOMEM;
1195
1196         for (i = 0; i < ngpps; i++) {
1197                 if (community->gpps) {
1198                         gpps[i] = community->gpps[i];
1199                 } else {
1200                         unsigned gpp_size = community->gpp_size;
1201
1202                         gpps[i].reg_num = i;
1203                         gpps[i].base = community->pin_base + i * gpp_size;
1204                         gpps[i].size = min(gpp_size, npins);
1205                         npins -= gpps[i].size;
1206                 }
1207
1208                 if (gpps[i].size > 32)
1209                         return -EINVAL;
1210
1211                 if (!gpps[i].gpio_base)
1212                         gpps[i].gpio_base = gpps[i].base;
1213
1214                 gpps[i].padown_num = padown_num;
1215
1216                 /*
1217                  * In older hardware the number of padown registers per
1218                  * group is fixed regardless of the group size.
1219                  */
1220                 if (community->gpp_num_padown_regs)
1221                         padown_num += community->gpp_num_padown_regs;
1222                 else
1223                         padown_num += DIV_ROUND_UP(gpps[i].size * 4, 32);
1224         }
1225
1226         community->ngpps = ngpps;
1227         community->gpps = gpps;
1228
1229         return 0;
1230 }
1231
1232 static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
1233 {
1234 #ifdef CONFIG_PM_SLEEP
1235         const struct intel_pinctrl_soc_data *soc = pctrl->soc;
1236         struct intel_community_context *communities;
1237         struct intel_pad_context *pads;
1238         int i;
1239
1240         pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL);
1241         if (!pads)
1242                 return -ENOMEM;
1243
1244         communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities,
1245                                    sizeof(*communities), GFP_KERNEL);
1246         if (!communities)
1247                 return -ENOMEM;
1248
1249
1250         for (i = 0; i < pctrl->ncommunities; i++) {
1251                 struct intel_community *community = &pctrl->communities[i];
1252                 u32 *intmask;
1253
1254                 intmask = devm_kcalloc(pctrl->dev, community->ngpps,
1255                                        sizeof(*intmask), GFP_KERNEL);
1256                 if (!intmask)
1257                         return -ENOMEM;
1258
1259                 communities[i].intmask = intmask;
1260         }
1261
1262         pctrl->context.pads = pads;
1263         pctrl->context.communities = communities;
1264 #endif
1265
1266         return 0;
1267 }
1268
1269 int intel_pinctrl_probe(struct platform_device *pdev,
1270                         const struct intel_pinctrl_soc_data *soc_data)
1271 {
1272         struct intel_pinctrl *pctrl;
1273         int i, ret, irq;
1274
1275         if (!soc_data)
1276                 return -EINVAL;
1277
1278         pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1279         if (!pctrl)
1280                 return -ENOMEM;
1281
1282         pctrl->dev = &pdev->dev;
1283         pctrl->soc = soc_data;
1284         raw_spin_lock_init(&pctrl->lock);
1285
1286         /*
1287          * Make a copy of the communities which we can use to hold pointers
1288          * to the registers.
1289          */
1290         pctrl->ncommunities = pctrl->soc->ncommunities;
1291         pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities,
1292                                   sizeof(*pctrl->communities), GFP_KERNEL);
1293         if (!pctrl->communities)
1294                 return -ENOMEM;
1295
1296         for (i = 0; i < pctrl->ncommunities; i++) {
1297                 struct intel_community *community = &pctrl->communities[i];
1298                 struct resource *res;
1299                 void __iomem *regs;
1300                 u32 padbar;
1301
1302                 *community = pctrl->soc->communities[i];
1303
1304                 res = platform_get_resource(pdev, IORESOURCE_MEM,
1305                                             community->barno);
1306                 regs = devm_ioremap_resource(&pdev->dev, res);
1307                 if (IS_ERR(regs))
1308                         return PTR_ERR(regs);
1309
1310                 /*
1311                  * Determine community features based on the revision if
1312                  * not specified already.
1313                  */
1314                 if (!community->features) {
1315                         u32 rev;
1316
1317                         rev = (readl(regs + REVID) & REVID_MASK) >> REVID_SHIFT;
1318                         if (rev >= 0x94) {
1319                                 community->features |= PINCTRL_FEATURE_DEBOUNCE;
1320                                 community->features |= PINCTRL_FEATURE_1K_PD;
1321                         }
1322                 }
1323
1324                 /* Read offset of the pad configuration registers */
1325                 padbar = readl(regs + PADBAR);
1326
1327                 community->regs = regs;
1328                 community->pad_regs = regs + padbar;
1329
1330                 if (!community->is_offset)
1331                         community->is_offset = GPI_IS;
1332
1333                 ret = intel_pinctrl_add_padgroups(pctrl, community);
1334                 if (ret)
1335                         return ret;
1336         }
1337
1338         irq = platform_get_irq(pdev, 0);
1339         if (irq < 0) {
1340                 dev_err(&pdev->dev, "failed to get interrupt number\n");
1341                 return irq;
1342         }
1343
1344         ret = intel_pinctrl_pm_init(pctrl);
1345         if (ret)
1346                 return ret;
1347
1348         pctrl->pctldesc = intel_pinctrl_desc;
1349         pctrl->pctldesc.name = dev_name(&pdev->dev);
1350         pctrl->pctldesc.pins = pctrl->soc->pins;
1351         pctrl->pctldesc.npins = pctrl->soc->npins;
1352
1353         pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc,
1354                                                pctrl);
1355         if (IS_ERR(pctrl->pctldev)) {
1356                 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1357                 return PTR_ERR(pctrl->pctldev);
1358         }
1359
1360         ret = intel_gpio_probe(pctrl, irq);
1361         if (ret)
1362                 return ret;
1363
1364         platform_set_drvdata(pdev, pctrl);
1365
1366         return 0;
1367 }
1368 EXPORT_SYMBOL_GPL(intel_pinctrl_probe);
1369
1370 #ifdef CONFIG_PM_SLEEP
1371 static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned pin)
1372 {
1373         const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin);
1374
1375         if (!pd || !intel_pad_usable(pctrl, pin))
1376                 return false;
1377
1378         /*
1379          * Only restore the pin if it is actually in use by the kernel (or
1380          * by userspace). It is possible that some pins are used by the
1381          * BIOS during resume and those are not always locked down so leave
1382          * them alone.
1383          */
1384         if (pd->mux_owner || pd->gpio_owner ||
1385             gpiochip_line_is_irq(&pctrl->chip, pin))
1386                 return true;
1387
1388         return false;
1389 }
1390
1391 int intel_pinctrl_suspend(struct device *dev)
1392 {
1393         struct platform_device *pdev = to_platform_device(dev);
1394         struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1395         struct intel_community_context *communities;
1396         struct intel_pad_context *pads;
1397         int i;
1398
1399         pads = pctrl->context.pads;
1400         for (i = 0; i < pctrl->soc->npins; i++) {
1401                 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1402                 void __iomem *padcfg;
1403                 u32 val;
1404
1405                 if (!intel_pinctrl_should_save(pctrl, desc->number))
1406                         continue;
1407
1408                 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0));
1409                 pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE;
1410                 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1));
1411                 pads[i].padcfg1 = val;
1412
1413                 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2);
1414                 if (padcfg)
1415                         pads[i].padcfg2 = readl(padcfg);
1416         }
1417
1418         communities = pctrl->context.communities;
1419         for (i = 0; i < pctrl->ncommunities; i++) {
1420                 struct intel_community *community = &pctrl->communities[i];
1421                 void __iomem *base;
1422                 unsigned gpp;
1423
1424                 base = community->regs + community->ie_offset;
1425                 for (gpp = 0; gpp < community->ngpps; gpp++)
1426                         communities[i].intmask[gpp] = readl(base + gpp * 4);
1427         }
1428
1429         return 0;
1430 }
1431 EXPORT_SYMBOL_GPL(intel_pinctrl_suspend);
1432
1433 static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
1434 {
1435         size_t i;
1436
1437         for (i = 0; i < pctrl->ncommunities; i++) {
1438                 const struct intel_community *community;
1439                 void __iomem *base;
1440                 unsigned gpp;
1441
1442                 community = &pctrl->communities[i];
1443                 base = community->regs;
1444
1445                 for (gpp = 0; gpp < community->ngpps; gpp++) {
1446                         /* Mask and clear all interrupts */
1447                         writel(0, base + community->ie_offset + gpp * 4);
1448                         writel(0xffff, base + community->is_offset + gpp * 4);
1449                 }
1450         }
1451 }
1452
1453 int intel_pinctrl_resume(struct device *dev)
1454 {
1455         struct platform_device *pdev = to_platform_device(dev);
1456         struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1457         const struct intel_community_context *communities;
1458         const struct intel_pad_context *pads;
1459         int i;
1460
1461         /* Mask all interrupts */
1462         intel_gpio_irq_init(pctrl);
1463
1464         pads = pctrl->context.pads;
1465         for (i = 0; i < pctrl->soc->npins; i++) {
1466                 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1467                 void __iomem *padcfg;
1468                 u32 val;
1469
1470                 if (!intel_pinctrl_should_save(pctrl, desc->number))
1471                         continue;
1472
1473                 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG0);
1474                 val = readl(padcfg) & ~PADCFG0_GPIORXSTATE;
1475                 if (val != pads[i].padcfg0) {
1476                         writel(pads[i].padcfg0, padcfg);
1477                         dev_dbg(dev, "restored pin %u padcfg0 %#08x\n",
1478                                 desc->number, readl(padcfg));
1479                 }
1480
1481                 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG1);
1482                 val = readl(padcfg);
1483                 if (val != pads[i].padcfg1) {
1484                         writel(pads[i].padcfg1, padcfg);
1485                         dev_dbg(dev, "restored pin %u padcfg1 %#08x\n",
1486                                 desc->number, readl(padcfg));
1487                 }
1488
1489                 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2);
1490                 if (padcfg) {
1491                         val = readl(padcfg);
1492                         if (val != pads[i].padcfg2) {
1493                                 writel(pads[i].padcfg2, padcfg);
1494                                 dev_dbg(dev, "restored pin %u padcfg2 %#08x\n",
1495                                         desc->number, readl(padcfg));
1496                         }
1497                 }
1498         }
1499
1500         communities = pctrl->context.communities;
1501         for (i = 0; i < pctrl->ncommunities; i++) {
1502                 struct intel_community *community = &pctrl->communities[i];
1503                 void __iomem *base;
1504                 unsigned gpp;
1505
1506                 base = community->regs + community->ie_offset;
1507                 for (gpp = 0; gpp < community->ngpps; gpp++) {
1508                         writel(communities[i].intmask[gpp], base + gpp * 4);
1509                         dev_dbg(dev, "restored mask %d/%u %#08x\n", i, gpp,
1510                                 readl(base + gpp * 4));
1511                 }
1512         }
1513
1514         return 0;
1515 }
1516 EXPORT_SYMBOL_GPL(intel_pinctrl_resume);
1517 #endif
1518
1519 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>");
1520 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1521 MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver");
1522 MODULE_LICENSE("GPL v2");