?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
x86/topology: Fix function name in documentation
[cris-mirror.git] / drivers / pinctrl / qcom / pinctrl-spmi-gpio.c
blob3e66e0d1001070c5925512228766c659fd07d2de
1 /*
2 * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14 #include <linux/gpio.h>
15 #include <linux/module.h>
16 #include <linux/of.h>
17 #include <linux/of_irq.h>
18 #include <linux/pinctrl/pinconf-generic.h>
19 #include <linux/pinctrl/pinconf.h>
20 #include <linux/pinctrl/pinmux.h>
21 #include <linux/platform_device.h>
22 #include <linux/regmap.h>
23 #include <linux/slab.h>
24 #include <linux/types.h>
25
26 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
27
28 #include "../core.h"
29 #include "../pinctrl-utils.h"
30
31 #define PMIC_GPIO_ADDRESS_RANGE 0x100
32
33 /* type and subtype registers base address offsets */
34 #define PMIC_GPIO_REG_TYPE 0x4
35 #define PMIC_GPIO_REG_SUBTYPE 0x5
36
37 /* GPIO peripheral type and subtype out_values */
38 #define PMIC_GPIO_TYPE 0x10
39 #define PMIC_GPIO_SUBTYPE_GPIO_4CH 0x1
40 #define PMIC_GPIO_SUBTYPE_GPIOC_4CH 0x5
41 #define PMIC_GPIO_SUBTYPE_GPIO_8CH 0x9
42 #define PMIC_GPIO_SUBTYPE_GPIOC_8CH 0xd
43 #define PMIC_GPIO_SUBTYPE_GPIO_LV 0x10
44 #define PMIC_GPIO_SUBTYPE_GPIO_MV 0x11
45
46 #define PMIC_MPP_REG_RT_STS 0x10
47 #define PMIC_MPP_REG_RT_STS_VAL_MASK 0x1
48
49 /* control register base address offsets */
50 #define PMIC_GPIO_REG_MODE_CTL 0x40
51 #define PMIC_GPIO_REG_DIG_VIN_CTL 0x41
52 #define PMIC_GPIO_REG_DIG_PULL_CTL 0x42
53 #define PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL 0x44
54 #define PMIC_GPIO_REG_DIG_IN_CTL 0x43
55 #define PMIC_GPIO_REG_DIG_OUT_CTL 0x45
56 #define PMIC_GPIO_REG_EN_CTL 0x46
57 #define PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL 0x4A
58
59 /* PMIC_GPIO_REG_MODE_CTL */
60 #define PMIC_GPIO_REG_MODE_VALUE_SHIFT 0x1
61 #define PMIC_GPIO_REG_MODE_FUNCTION_SHIFT 1
62 #define PMIC_GPIO_REG_MODE_FUNCTION_MASK 0x7
63 #define PMIC_GPIO_REG_MODE_DIR_SHIFT 4
64 #define PMIC_GPIO_REG_MODE_DIR_MASK 0x7
65
66 #define PMIC_GPIO_MODE_DIGITAL_INPUT 0
67 #define PMIC_GPIO_MODE_DIGITAL_OUTPUT 1
68 #define PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT 2
69 #define PMIC_GPIO_MODE_ANALOG_PASS_THRU 3
70 #define PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK 0x3
71
72 /* PMIC_GPIO_REG_DIG_VIN_CTL */
73 #define PMIC_GPIO_REG_VIN_SHIFT 0
74 #define PMIC_GPIO_REG_VIN_MASK 0x7
75
76 /* PMIC_GPIO_REG_DIG_PULL_CTL */
77 #define PMIC_GPIO_REG_PULL_SHIFT 0
78 #define PMIC_GPIO_REG_PULL_MASK 0x7
79
80 #define PMIC_GPIO_PULL_DOWN 4
81 #define PMIC_GPIO_PULL_DISABLE 5
82
83 /* PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL for LV/MV */
84 #define PMIC_GPIO_LV_MV_OUTPUT_INVERT 0x80
85 #define PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT 7
86 #define PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK 0xF
87
88 /* PMIC_GPIO_REG_DIG_IN_CTL */
89 #define PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN 0x80
90 #define PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK 0x7
91 #define PMIC_GPIO_DIG_IN_DTEST_SEL_MASK 0xf
92
93 /* PMIC_GPIO_REG_DIG_OUT_CTL */
94 #define PMIC_GPIO_REG_OUT_STRENGTH_SHIFT 0
95 #define PMIC_GPIO_REG_OUT_STRENGTH_MASK 0x3
96 #define PMIC_GPIO_REG_OUT_TYPE_SHIFT 4
97 #define PMIC_GPIO_REG_OUT_TYPE_MASK 0x3
98
99 /*
100 * Output type - indicates pin should be configured as push-pull,
101 * open drain or open source.
102 */
103 #define PMIC_GPIO_OUT_BUF_CMOS 0
104 #define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS 1
105 #define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS 2
106
107 /* PMIC_GPIO_REG_EN_CTL */
108 #define PMIC_GPIO_REG_MASTER_EN_SHIFT 7
109
110 #define PMIC_GPIO_PHYSICAL_OFFSET 1
111
112 /* PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL */
113 #define PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK 0x3
114
115 /* Qualcomm specific pin configurations */
116 #define PMIC_GPIO_CONF_PULL_UP (PIN_CONFIG_END + 1)
117 #define PMIC_GPIO_CONF_STRENGTH (PIN_CONFIG_END + 2)
118 #define PMIC_GPIO_CONF_ATEST (PIN_CONFIG_END + 3)
119 #define PMIC_GPIO_CONF_ANALOG_PASS (PIN_CONFIG_END + 4)
120 #define PMIC_GPIO_CONF_DTEST_BUFFER (PIN_CONFIG_END + 5)
121
122 /* The index of each function in pmic_gpio_functions[] array */
123 enum pmic_gpio_func_index {
124 PMIC_GPIO_FUNC_INDEX_NORMAL,
125 PMIC_GPIO_FUNC_INDEX_PAIRED,
126 PMIC_GPIO_FUNC_INDEX_FUNC1,
127 PMIC_GPIO_FUNC_INDEX_FUNC2,
128 PMIC_GPIO_FUNC_INDEX_FUNC3,
129 PMIC_GPIO_FUNC_INDEX_FUNC4,
130 PMIC_GPIO_FUNC_INDEX_DTEST1,
131 PMIC_GPIO_FUNC_INDEX_DTEST2,
132 PMIC_GPIO_FUNC_INDEX_DTEST3,
133 PMIC_GPIO_FUNC_INDEX_DTEST4,
134 };
135
136 /**
137 * struct pmic_gpio_pad - keep current GPIO settings
138 * @base: Address base in SPMI device.
139 * @irq: IRQ number which this GPIO generate.
140 * @is_enabled: Set to false when GPIO should be put in high Z state.
141 * @out_value: Cached pin output value
142 * @have_buffer: Set to true if GPIO output could be configured in push-pull,
143 * open-drain or open-source mode.
144 * @output_enabled: Set to true if GPIO output logic is enabled.
145 * @input_enabled: Set to true if GPIO input buffer logic is enabled.
146 * @analog_pass: Set to true if GPIO is in analog-pass-through mode.
147 * @lv_mv_type: Set to true if GPIO subtype is GPIO_LV(0x10) or GPIO_MV(0x11).
148 * @num_sources: Number of power-sources supported by this GPIO.
149 * @power_source: Current power-source used.
150 * @buffer_type: Push-pull, open-drain or open-source.
151 * @pullup: Constant current which flow trough GPIO output buffer.
152 * @strength: No, Low, Medium, High
153 * @function: See pmic_gpio_functions[]
154 * @atest: the ATEST selection for GPIO analog-pass-through mode
155 * @dtest_buffer: the DTEST buffer selection for digital input mode.
156 */
157 struct pmic_gpio_pad {
158 u16 base;
159 int irq;
160 bool is_enabled;
161 bool out_value;
162 bool have_buffer;
163 bool output_enabled;
164 bool input_enabled;
165 bool analog_pass;
166 bool lv_mv_type;
167 unsigned int num_sources;
168 unsigned int power_source;
169 unsigned int buffer_type;
170 unsigned int pullup;
171 unsigned int strength;
172 unsigned int function;
173 unsigned int atest;
174 unsigned int dtest_buffer;
175 };
176
177 struct pmic_gpio_state {
178 struct device *dev;
179 struct regmap *map;
180 struct pinctrl_dev *ctrl;
181 struct gpio_chip chip;
182 };
183
184 static const struct pinconf_generic_params pmic_gpio_bindings[] = {
185 {"qcom,pull-up-strength", PMIC_GPIO_CONF_PULL_UP, 0},
186 {"qcom,drive-strength", PMIC_GPIO_CONF_STRENGTH, 0},
187 {"qcom,atest", PMIC_GPIO_CONF_ATEST, 0},
188 {"qcom,analog-pass", PMIC_GPIO_CONF_ANALOG_PASS, 0},
189 {"qcom,dtest-buffer", PMIC_GPIO_CONF_DTEST_BUFFER, 0},
190 };
191
192 #ifdef CONFIG_DEBUG_FS
193 static const struct pin_config_item pmic_conf_items[ARRAY_SIZE(pmic_gpio_bindings)] = {
194 PCONFDUMP(PMIC_GPIO_CONF_PULL_UP, "pull up strength", NULL, true),
195 PCONFDUMP(PMIC_GPIO_CONF_STRENGTH, "drive-strength", NULL, true),
196 PCONFDUMP(PMIC_GPIO_CONF_ATEST, "atest", NULL, true),
197 PCONFDUMP(PMIC_GPIO_CONF_ANALOG_PASS, "analog-pass", NULL, true),
198 PCONFDUMP(PMIC_GPIO_CONF_DTEST_BUFFER, "dtest-buffer", NULL, true),
199 };
200 #endif
201
202 static const char *const pmic_gpio_groups[] = {
203 "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8",
204 "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15",
205 "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22",
206 "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
207 "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36",
208 };
209
210 static const char *const pmic_gpio_functions[] = {
211 [PMIC_GPIO_FUNC_INDEX_NORMAL] = PMIC_GPIO_FUNC_NORMAL,
212 [PMIC_GPIO_FUNC_INDEX_PAIRED] = PMIC_GPIO_FUNC_PAIRED,
213 [PMIC_GPIO_FUNC_INDEX_FUNC1] = PMIC_GPIO_FUNC_FUNC1,
214 [PMIC_GPIO_FUNC_INDEX_FUNC2] = PMIC_GPIO_FUNC_FUNC2,
215 [PMIC_GPIO_FUNC_INDEX_FUNC3] = PMIC_GPIO_FUNC_FUNC3,
216 [PMIC_GPIO_FUNC_INDEX_FUNC4] = PMIC_GPIO_FUNC_FUNC4,
217 [PMIC_GPIO_FUNC_INDEX_DTEST1] = PMIC_GPIO_FUNC_DTEST1,
218 [PMIC_GPIO_FUNC_INDEX_DTEST2] = PMIC_GPIO_FUNC_DTEST2,
219 [PMIC_GPIO_FUNC_INDEX_DTEST3] = PMIC_GPIO_FUNC_DTEST3,
220 [PMIC_GPIO_FUNC_INDEX_DTEST4] = PMIC_GPIO_FUNC_DTEST4,
221 };
222
223 static int pmic_gpio_read(struct pmic_gpio_state *state,
224 struct pmic_gpio_pad *pad, unsigned int addr)
225 {
226 unsigned int val;
227 int ret;
228
229 ret = regmap_read(state->map, pad->base + addr, &val);
230 if (ret < 0)
231 dev_err(state->dev, "read 0x%x failed\n", addr);
232 else
233 ret = val;
234
235 return ret;
236 }
237
238 static int pmic_gpio_write(struct pmic_gpio_state *state,
239 struct pmic_gpio_pad *pad, unsigned int addr,
240 unsigned int val)
241 {
242 int ret;
243
244 ret = regmap_write(state->map, pad->base + addr, val);
245 if (ret < 0)
246 dev_err(state->dev, "write 0x%x failed\n", addr);
247
248 return ret;
249 }
250
251 static int pmic_gpio_get_groups_count(struct pinctrl_dev *pctldev)
252 {
253 /* Every PIN is a group */
254 return pctldev->desc->npins;
255 }
256
257 static const char *pmic_gpio_get_group_name(struct pinctrl_dev *pctldev,
258 unsigned pin)
259 {
260 return pctldev->desc->pins[pin].name;
261 }
262
263 static int pmic_gpio_get_group_pins(struct pinctrl_dev *pctldev, unsigned pin,
264 const unsigned **pins, unsigned *num_pins)
265 {
266 *pins = &pctldev->desc->pins[pin].number;
267 *num_pins = 1;
268 return 0;
269 }
270
271 static const struct pinctrl_ops pmic_gpio_pinctrl_ops = {
272 .get_groups_count = pmic_gpio_get_groups_count,
273 .get_group_name = pmic_gpio_get_group_name,
274 .get_group_pins = pmic_gpio_get_group_pins,
275 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
276 .dt_free_map = pinctrl_utils_free_map,
277 };
278
279 static int pmic_gpio_get_functions_count(struct pinctrl_dev *pctldev)
280 {
281 return ARRAY_SIZE(pmic_gpio_functions);
282 }
283
284 static const char *pmic_gpio_get_function_name(struct pinctrl_dev *pctldev,
285 unsigned function)
286 {
287 return pmic_gpio_functions[function];
288 }
289
290 static int pmic_gpio_get_function_groups(struct pinctrl_dev *pctldev,
291 unsigned function,
292 const char *const **groups,
293 unsigned *const num_qgroups)
294 {
295 *groups = pmic_gpio_groups;
296 *num_qgroups = pctldev->desc->npins;
297 return 0;
298 }
299
300 static int pmic_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned function,
301 unsigned pin)
302 {
303 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
304 struct pmic_gpio_pad *pad;
305 unsigned int val;
306 int ret;
307
308 if (function > PMIC_GPIO_FUNC_INDEX_DTEST4) {
309 pr_err("function: %d is not defined\n", function);
310 return -EINVAL;
311 }
312
313 pad = pctldev->desc->pins[pin].drv_data;
314 /*
315 * Non-LV/MV subtypes only support 2 special functions,
316 * offsetting the dtestx function values by 2
317 */
318 if (!pad->lv_mv_type) {
319 if (function == PMIC_GPIO_FUNC_INDEX_FUNC3 ||
320 function == PMIC_GPIO_FUNC_INDEX_FUNC4) {
321 pr_err("LV/MV subtype doesn't have func3/func4\n");
322 return -EINVAL;
323 }
324 if (function >= PMIC_GPIO_FUNC_INDEX_DTEST1)
325 function -= (PMIC_GPIO_FUNC_INDEX_DTEST1 -
326 PMIC_GPIO_FUNC_INDEX_FUNC3);
327 }
328
329 pad->function = function;
330
331 if (pad->analog_pass)
332 val = PMIC_GPIO_MODE_ANALOG_PASS_THRU;
333 else if (pad->output_enabled && pad->input_enabled)
334 val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT;
335 else if (pad->output_enabled)
336 val = PMIC_GPIO_MODE_DIGITAL_OUTPUT;
337 else
338 val = PMIC_GPIO_MODE_DIGITAL_INPUT;
339
340 if (pad->lv_mv_type) {
341 ret = pmic_gpio_write(state, pad,
342 PMIC_GPIO_REG_MODE_CTL, val);
343 if (ret < 0)
344 return ret;
345
346 val = pad->atest - 1;
347 ret = pmic_gpio_write(state, pad,
348 PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, val);
349 if (ret < 0)
350 return ret;
351
352 val = pad->out_value
353 << PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT;
354 val |= pad->function
355 & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
356 ret = pmic_gpio_write(state, pad,
357 PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, val);
358 if (ret < 0)
359 return ret;
360 } else {
361 val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT;
362 val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
363 val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
364
365 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val);
366 if (ret < 0)
367 return ret;
368 }
369
370 val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT;
371
372 return pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val);
373 }
374
375 static const struct pinmux_ops pmic_gpio_pinmux_ops = {
376 .get_functions_count = pmic_gpio_get_functions_count,
377 .get_function_name = pmic_gpio_get_function_name,
378 .get_function_groups = pmic_gpio_get_function_groups,
379 .set_mux = pmic_gpio_set_mux,
380 };
381
382 static int pmic_gpio_config_get(struct pinctrl_dev *pctldev,
383 unsigned int pin, unsigned long *config)
384 {
385 unsigned param = pinconf_to_config_param(*config);
386 struct pmic_gpio_pad *pad;
387 unsigned arg;
388
389 pad = pctldev->desc->pins[pin].drv_data;
390
391 switch (param) {
392 case PIN_CONFIG_DRIVE_PUSH_PULL:
393 arg = pad->buffer_type == PMIC_GPIO_OUT_BUF_CMOS;
394 break;
395 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
396 arg = pad->buffer_type == PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS;
397 break;
398 case PIN_CONFIG_DRIVE_OPEN_SOURCE:
399 arg = pad->buffer_type == PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS;
400 break;
401 case PIN_CONFIG_BIAS_PULL_DOWN:
402 arg = pad->pullup == PMIC_GPIO_PULL_DOWN;
403 break;
404 case PIN_CONFIG_BIAS_DISABLE:
405 arg = pad->pullup = PMIC_GPIO_PULL_DISABLE;
406 break;
407 case PIN_CONFIG_BIAS_PULL_UP:
408 arg = pad->pullup == PMIC_GPIO_PULL_UP_30;
409 break;
410 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
411 arg = !pad->is_enabled;
412 break;
413 case PIN_CONFIG_POWER_SOURCE:
414 arg = pad->power_source;
415 break;
416 case PIN_CONFIG_INPUT_ENABLE:
417 arg = pad->input_enabled;
418 break;
419 case PIN_CONFIG_OUTPUT:
420 arg = pad->out_value;
421 break;
422 case PMIC_GPIO_CONF_PULL_UP:
423 arg = pad->pullup;
424 break;
425 case PMIC_GPIO_CONF_STRENGTH:
426 arg = pad->strength;
427 break;
428 case PMIC_GPIO_CONF_ATEST:
429 arg = pad->atest;
430 break;
431 case PMIC_GPIO_CONF_ANALOG_PASS:
432 arg = pad->analog_pass;
433 break;
434 case PMIC_GPIO_CONF_DTEST_BUFFER:
435 arg = pad->dtest_buffer;
436 break;
437 default:
438 return -EINVAL;
439 }
440
441 *config = pinconf_to_config_packed(param, arg);
442 return 0;
443 }
444
445 static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
446 unsigned long *configs, unsigned nconfs)
447 {
448 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
449 struct pmic_gpio_pad *pad;
450 unsigned param, arg;
451 unsigned int val;
452 int i, ret;
453
454 pad = pctldev->desc->pins[pin].drv_data;
455
456 pad->is_enabled = true;
457 for (i = 0; i < nconfs; i++) {
458 param = pinconf_to_config_param(configs[i]);
459 arg = pinconf_to_config_argument(configs[i]);
460
461 switch (param) {
462 case PIN_CONFIG_DRIVE_PUSH_PULL:
463 pad->buffer_type = PMIC_GPIO_OUT_BUF_CMOS;
464 break;
465 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
466 if (!pad->have_buffer)
467 return -EINVAL;
468 pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS;
469 break;
470 case PIN_CONFIG_DRIVE_OPEN_SOURCE:
471 if (!pad->have_buffer)
472 return -EINVAL;
473 pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS;
474 break;
475 case PIN_CONFIG_BIAS_DISABLE:
476 pad->pullup = PMIC_GPIO_PULL_DISABLE;
477 break;
478 case PIN_CONFIG_BIAS_PULL_UP:
479 pad->pullup = PMIC_GPIO_PULL_UP_30;
480 break;
481 case PIN_CONFIG_BIAS_PULL_DOWN:
482 if (arg)
483 pad->pullup = PMIC_GPIO_PULL_DOWN;
484 else
485 pad->pullup = PMIC_GPIO_PULL_DISABLE;
486 break;
487 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
488 pad->is_enabled = false;
489 break;
490 case PIN_CONFIG_POWER_SOURCE:
491 if (arg >= pad->num_sources)
492 return -EINVAL;
493 pad->power_source = arg;
494 break;
495 case PIN_CONFIG_INPUT_ENABLE:
496 pad->input_enabled = arg ? true : false;
497 break;
498 case PIN_CONFIG_OUTPUT:
499 pad->output_enabled = true;
500 pad->out_value = arg;
501 break;
502 case PMIC_GPIO_CONF_PULL_UP:
503 if (arg > PMIC_GPIO_PULL_UP_1P5_30)
504 return -EINVAL;
505 pad->pullup = arg;
506 break;
507 case PMIC_GPIO_CONF_STRENGTH:
508 if (arg > PMIC_GPIO_STRENGTH_LOW)
509 return -EINVAL;
510 pad->strength = arg;
511 break;
512 case PMIC_GPIO_CONF_ATEST:
513 if (!pad->lv_mv_type || arg > 4)
514 return -EINVAL;
515 pad->atest = arg;
516 break;
517 case PMIC_GPIO_CONF_ANALOG_PASS:
518 if (!pad->lv_mv_type)
519 return -EINVAL;
520 pad->analog_pass = true;
521 break;
522 case PMIC_GPIO_CONF_DTEST_BUFFER:
523 if (arg > 4)
524 return -EINVAL;
525 pad->dtest_buffer = arg;
526 break;
527 default:
528 return -EINVAL;
529 }
530 }
531
532 val = pad->power_source << PMIC_GPIO_REG_VIN_SHIFT;
533
534 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL, val);
535 if (ret < 0)
536 return ret;
537
538 val = pad->pullup << PMIC_GPIO_REG_PULL_SHIFT;
539
540 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL, val);
541 if (ret < 0)
542 return ret;
543
544 val = pad->buffer_type << PMIC_GPIO_REG_OUT_TYPE_SHIFT;
545 val |= pad->strength << PMIC_GPIO_REG_OUT_STRENGTH_SHIFT;
546
547 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL, val);
548 if (ret < 0)
549 return ret;
550
551 if (pad->dtest_buffer == 0) {
552 val = 0;
553 } else {
554 if (pad->lv_mv_type) {
555 val = pad->dtest_buffer - 1;
556 val |= PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN;
557 } else {
558 val = BIT(pad->dtest_buffer - 1);
559 }
560 }
561 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_IN_CTL, val);
562 if (ret < 0)
563 return ret;
564
565 if (pad->analog_pass)
566 val = PMIC_GPIO_MODE_ANALOG_PASS_THRU;
567 else if (pad->output_enabled && pad->input_enabled)
568 val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT;
569 else if (pad->output_enabled)
570 val = PMIC_GPIO_MODE_DIGITAL_OUTPUT;
571 else
572 val = PMIC_GPIO_MODE_DIGITAL_INPUT;
573
574 if (pad->lv_mv_type) {
575 ret = pmic_gpio_write(state, pad,
576 PMIC_GPIO_REG_MODE_CTL, val);
577 if (ret < 0)
578 return ret;
579
580 val = pad->atest - 1;
581 ret = pmic_gpio_write(state, pad,
582 PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, val);
583 if (ret < 0)
584 return ret;
585
586 val = pad->out_value
587 << PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT;
588 val |= pad->function
589 & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
590 ret = pmic_gpio_write(state, pad,
591 PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, val);
592 if (ret < 0)
593 return ret;
594 } else {
595 val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT;
596 val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
597 val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
598
599 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val);
600 if (ret < 0)
601 return ret;
602 }
603
604 val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT;
605
606 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val);
607
608 return ret;
609 }
610
611 static void pmic_gpio_config_dbg_show(struct pinctrl_dev *pctldev,
612 struct seq_file *s, unsigned pin)
613 {
614 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
615 struct pmic_gpio_pad *pad;
616 int ret, val, function;
617
618 static const char *const biases[] = {
619 "pull-up 30uA", "pull-up 1.5uA", "pull-up 31.5uA",
620 "pull-up 1.5uA + 30uA boost", "pull-down 10uA", "no pull"
621 };
622 static const char *const buffer_types[] = {
623 "push-pull", "open-drain", "open-source"
624 };
625 static const char *const strengths[] = {
626 "no", "high", "medium", "low"
627 };
628
629 pad = pctldev->desc->pins[pin].drv_data;
630
631 seq_printf(s, " gpio%-2d:", pin + PMIC_GPIO_PHYSICAL_OFFSET);
632
633 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_EN_CTL);
634
635 if (val < 0 || !(val >> PMIC_GPIO_REG_MASTER_EN_SHIFT)) {
636 seq_puts(s, " ---");
637 } else {
638 if (pad->input_enabled) {
639 ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS);
640 if (ret < 0)
641 return;
642
643 ret &= PMIC_MPP_REG_RT_STS_VAL_MASK;
644 pad->out_value = ret;
645 }
646 /*
647 * For the non-LV/MV subtypes only 2 special functions are
648 * available, offsetting the dtest function values by 2.
649 */
650 function = pad->function;
651 if (!pad->lv_mv_type &&
652 pad->function >= PMIC_GPIO_FUNC_INDEX_FUNC3)
653 function += PMIC_GPIO_FUNC_INDEX_DTEST1 -
654 PMIC_GPIO_FUNC_INDEX_FUNC3;
655
656 if (pad->analog_pass)
657 seq_puts(s, " analog-pass");
658 else
659 seq_printf(s, " %-4s",
660 pad->output_enabled ? "out" : "in");
661 seq_printf(s, " %-7s", pmic_gpio_functions[function]);
662 seq_printf(s, " vin-%d", pad->power_source);
663 seq_printf(s, " %-27s", biases[pad->pullup]);
664 seq_printf(s, " %-10s", buffer_types[pad->buffer_type]);
665 seq_printf(s, " %-4s", pad->out_value ? "high" : "low");
666 seq_printf(s, " %-7s", strengths[pad->strength]);
667 seq_printf(s, " atest-%d", pad->atest);
668 seq_printf(s, " dtest-%d", pad->dtest_buffer);
669 }
670 }
671
672 static const struct pinconf_ops pmic_gpio_pinconf_ops = {
673 .is_generic = true,
674 .pin_config_group_get = pmic_gpio_config_get,
675 .pin_config_group_set = pmic_gpio_config_set,
676 .pin_config_group_dbg_show = pmic_gpio_config_dbg_show,
677 };
678
679 static int pmic_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
680 {
681 struct pmic_gpio_state *state = gpiochip_get_data(chip);
682 unsigned long config;
683
684 config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1);
685
686 return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
687 }
688
689 static int pmic_gpio_direction_output(struct gpio_chip *chip,
690 unsigned pin, int val)
691 {
692 struct pmic_gpio_state *state = gpiochip_get_data(chip);
693 unsigned long config;
694
695 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val);
696
697 return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
698 }
699
700 static int pmic_gpio_get(struct gpio_chip *chip, unsigned pin)
701 {
702 struct pmic_gpio_state *state = gpiochip_get_data(chip);
703 struct pmic_gpio_pad *pad;
704 int ret;
705
706 pad = state->ctrl->desc->pins[pin].drv_data;
707
708 if (!pad->is_enabled)
709 return -EINVAL;
710
711 if (pad->input_enabled) {
712 ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS);
713 if (ret < 0)
714 return ret;
715
716 pad->out_value = ret & PMIC_MPP_REG_RT_STS_VAL_MASK;
717 }
718
719 return !!pad->out_value;
720 }
721
722 static void pmic_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
723 {
724 struct pmic_gpio_state *state = gpiochip_get_data(chip);
725 unsigned long config;
726
727 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value);
728
729 pmic_gpio_config_set(state->ctrl, pin, &config, 1);
730 }
731
732 static int pmic_gpio_of_xlate(struct gpio_chip *chip,
733 const struct of_phandle_args *gpio_desc,
734 u32 *flags)
735 {
736 if (chip->of_gpio_n_cells < 2)
737 return -EINVAL;
738
739 if (flags)
740 *flags = gpio_desc->args[1];
741
742 return gpio_desc->args[0] - PMIC_GPIO_PHYSICAL_OFFSET;
743 }
744
745 static int pmic_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
746 {
747 struct pmic_gpio_state *state = gpiochip_get_data(chip);
748 struct pmic_gpio_pad *pad;
749
750 pad = state->ctrl->desc->pins[pin].drv_data;
751
752 return pad->irq;
753 }
754
755 static void pmic_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
756 {
757 struct pmic_gpio_state *state = gpiochip_get_data(chip);
758 unsigned i;
759
760 for (i = 0; i < chip->ngpio; i++) {
761 pmic_gpio_config_dbg_show(state->ctrl, s, i);
762 seq_puts(s, "\n");
763 }
764 }
765
766 static const struct gpio_chip pmic_gpio_gpio_template = {
767 .direction_input = pmic_gpio_direction_input,
768 .direction_output = pmic_gpio_direction_output,
769 .get = pmic_gpio_get,
770 .set = pmic_gpio_set,
771 .request = gpiochip_generic_request,
772 .free = gpiochip_generic_free,
773 .of_xlate = pmic_gpio_of_xlate,
774 .to_irq = pmic_gpio_to_irq,
775 .dbg_show = pmic_gpio_dbg_show,
776 };
777
778 static int pmic_gpio_populate(struct pmic_gpio_state *state,
779 struct pmic_gpio_pad *pad)
780 {
781 int type, subtype, val, dir;
782
783 type = pmic_gpio_read(state, pad, PMIC_GPIO_REG_TYPE);
784 if (type < 0)
785 return type;
786
787 if (type != PMIC_GPIO_TYPE) {
788 dev_err(state->dev, "incorrect block type 0x%x at 0x%x\n",
789 type, pad->base);
790 return -ENODEV;
791 }
792
793 subtype = pmic_gpio_read(state, pad, PMIC_GPIO_REG_SUBTYPE);
794 if (subtype < 0)
795 return subtype;
796
797 switch (subtype) {
798 case PMIC_GPIO_SUBTYPE_GPIO_4CH:
799 pad->have_buffer = true;
800 case PMIC_GPIO_SUBTYPE_GPIOC_4CH:
801 pad->num_sources = 4;
802 break;
803 case PMIC_GPIO_SUBTYPE_GPIO_8CH:
804 pad->have_buffer = true;
805 case PMIC_GPIO_SUBTYPE_GPIOC_8CH:
806 pad->num_sources = 8;
807 break;
808 case PMIC_GPIO_SUBTYPE_GPIO_LV:
809 pad->num_sources = 1;
810 pad->have_buffer = true;
811 pad->lv_mv_type = true;
812 break;
813 case PMIC_GPIO_SUBTYPE_GPIO_MV:
814 pad->num_sources = 2;
815 pad->have_buffer = true;
816 pad->lv_mv_type = true;
817 break;
818 default:
819 dev_err(state->dev, "unknown GPIO type 0x%x\n", subtype);
820 return -ENODEV;
821 }
822
823 if (pad->lv_mv_type) {
824 val = pmic_gpio_read(state, pad,
825 PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL);
826 if (val < 0)
827 return val;
828
829 pad->out_value = !!(val & PMIC_GPIO_LV_MV_OUTPUT_INVERT);
830 pad->function = val & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
831
832 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL);
833 if (val < 0)
834 return val;
835
836 dir = val & PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK;
837 } else {
838 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL);
839 if (val < 0)
840 return val;
841
842 pad->out_value = val & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
843
844 dir = val >> PMIC_GPIO_REG_MODE_DIR_SHIFT;
845 dir &= PMIC_GPIO_REG_MODE_DIR_MASK;
846 pad->function = val >> PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
847 pad->function &= PMIC_GPIO_REG_MODE_FUNCTION_MASK;
848 }
849
850 switch (dir) {
851 case PMIC_GPIO_MODE_DIGITAL_INPUT:
852 pad->input_enabled = true;
853 pad->output_enabled = false;
854 break;
855 case PMIC_GPIO_MODE_DIGITAL_OUTPUT:
856 pad->input_enabled = false;
857 pad->output_enabled = true;
858 break;
859 case PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT:
860 pad->input_enabled = true;
861 pad->output_enabled = true;
862 break;
863 case PMIC_GPIO_MODE_ANALOG_PASS_THRU:
864 if (!pad->lv_mv_type)
865 return -ENODEV;
866 pad->analog_pass = true;
867 break;
868 default:
869 dev_err(state->dev, "unknown GPIO direction\n");
870 return -ENODEV;
871 }
872
873 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL);
874 if (val < 0)
875 return val;
876
877 pad->power_source = val >> PMIC_GPIO_REG_VIN_SHIFT;
878 pad->power_source &= PMIC_GPIO_REG_VIN_MASK;
879
880 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL);
881 if (val < 0)
882 return val;
883
884 pad->pullup = val >> PMIC_GPIO_REG_PULL_SHIFT;
885 pad->pullup &= PMIC_GPIO_REG_PULL_MASK;
886
887 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_IN_CTL);
888 if (val < 0)
889 return val;
890
891 if (pad->lv_mv_type && (val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN))
892 pad->dtest_buffer =
893 (val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK) + 1;
894 else if (!pad->lv_mv_type)
895 pad->dtest_buffer = ffs(val);
896 else
897 pad->dtest_buffer = 0;
898
899 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL);
900 if (val < 0)
901 return val;
902
903 pad->strength = val >> PMIC_GPIO_REG_OUT_STRENGTH_SHIFT;
904 pad->strength &= PMIC_GPIO_REG_OUT_STRENGTH_MASK;
905
906 pad->buffer_type = val >> PMIC_GPIO_REG_OUT_TYPE_SHIFT;
907 pad->buffer_type &= PMIC_GPIO_REG_OUT_TYPE_MASK;
908
909 if (pad->lv_mv_type) {
910 val = pmic_gpio_read(state, pad,
911 PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL);
912 if (val < 0)
913 return val;
914 pad->atest = (val & PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK) + 1;
915 }
916
917 /* Pin could be disabled with PIN_CONFIG_BIAS_HIGH_IMPEDANCE */
918 pad->is_enabled = true;
919 return 0;
920 }
921
922 static int pmic_gpio_probe(struct platform_device *pdev)
923 {
924 struct device *dev = &pdev->dev;
925 struct pinctrl_pin_desc *pindesc;
926 struct pinctrl_desc *pctrldesc;
927 struct pmic_gpio_pad *pad, *pads;
928 struct pmic_gpio_state *state;
929 int ret, npins, i;
930 u32 reg;
931
932 ret = of_property_read_u32(dev->of_node, "reg", &reg);
933 if (ret < 0) {
934 dev_err(dev, "missing base address");
935 return ret;
936 }
937
938 npins = platform_irq_count(pdev);
939 if (!npins)
940 return -EINVAL;
941 if (npins < 0)
942 return npins;
943
944 BUG_ON(npins > ARRAY_SIZE(pmic_gpio_groups));
945
946 state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
947 if (!state)
948 return -ENOMEM;
949
950 platform_set_drvdata(pdev, state);
951
952 state->dev = &pdev->dev;
953 state->map = dev_get_regmap(dev->parent, NULL);
954
955 pindesc = devm_kcalloc(dev, npins, sizeof(*pindesc), GFP_KERNEL);
956 if (!pindesc)
957 return -ENOMEM;
958
959 pads = devm_kcalloc(dev, npins, sizeof(*pads), GFP_KERNEL);
960 if (!pads)
961 return -ENOMEM;
962
963 pctrldesc = devm_kzalloc(dev, sizeof(*pctrldesc), GFP_KERNEL);
964 if (!pctrldesc)
965 return -ENOMEM;
966
967 pctrldesc->pctlops = &pmic_gpio_pinctrl_ops;
968 pctrldesc->pmxops = &pmic_gpio_pinmux_ops;
969 pctrldesc->confops = &pmic_gpio_pinconf_ops;
970 pctrldesc->owner = THIS_MODULE;
971 pctrldesc->name = dev_name(dev);
972 pctrldesc->pins = pindesc;
973 pctrldesc->npins = npins;
974 pctrldesc->num_custom_params = ARRAY_SIZE(pmic_gpio_bindings);
975 pctrldesc->custom_params = pmic_gpio_bindings;
976 #ifdef CONFIG_DEBUG_FS
977 pctrldesc->custom_conf_items = pmic_conf_items;
978 #endif
979
980 for (i = 0; i < npins; i++, pindesc++) {
981 pad = &pads[i];
982 pindesc->drv_data = pad;
983 pindesc->number = i;
984 pindesc->name = pmic_gpio_groups[i];
985
986 pad->irq = platform_get_irq(pdev, i);
987 if (pad->irq < 0)
988 return pad->irq;
989
990 pad->base = reg + i * PMIC_GPIO_ADDRESS_RANGE;
991
992 ret = pmic_gpio_populate(state, pad);
993 if (ret < 0)
994 return ret;
995 }
996
997 state->chip = pmic_gpio_gpio_template;
998 state->chip.parent = dev;
999 state->chip.base = -1;
1000 state->chip.ngpio = npins;
1001 state->chip.label = dev_name(dev);
1002 state->chip.of_gpio_n_cells = 2;
1003 state->chip.can_sleep = false;
1004
1005 state->ctrl = devm_pinctrl_register(dev, pctrldesc, state);
1006 if (IS_ERR(state->ctrl))
1007 return PTR_ERR(state->ctrl);
1008
1009 ret = gpiochip_add_data(&state->chip, state);
1010 if (ret) {
1011 dev_err(state->dev, "can't add gpio chip\n");
1012 return ret;
1013 }
1014
1015 ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0, npins);
1016 if (ret) {
1017 dev_err(dev, "failed to add pin range\n");
1018 goto err_range;
1019 }
1020
1021 return 0;
1022
1023 err_range:
1024 gpiochip_remove(&state->chip);
1025 return ret;
1026 }
1027
1028 static int pmic_gpio_remove(struct platform_device *pdev)
1029 {
1030 struct pmic_gpio_state *state = platform_get_drvdata(pdev);
1031
1032 gpiochip_remove(&state->chip);
1033 return 0;
1034 }
1035
1036 static const struct of_device_id pmic_gpio_of_match[] = {
1037 { .compatible = "qcom,pm8916-gpio" }, /* 4 GPIO's */
1038 { .compatible = "qcom,pm8941-gpio" }, /* 36 GPIO's */
1039 { .compatible = "qcom,pm8994-gpio" }, /* 22 GPIO's */
1040 { .compatible = "qcom,pmi8994-gpio" }, /* 10 GPIO's */
1041 { .compatible = "qcom,pma8084-gpio" }, /* 22 GPIO's */
1042 { .compatible = "qcom,spmi-gpio" }, /* Generic */
1043 { },
1044 };
1045
1046 MODULE_DEVICE_TABLE(of, pmic_gpio_of_match);
1047
1048 static struct platform_driver pmic_gpio_driver = {
1049 .driver = {
1050 .name = "qcom-spmi-gpio",
1051 .of_match_table = pmic_gpio_of_match,
1052 },
1053 .probe = pmic_gpio_probe,
1054 .remove = pmic_gpio_remove,
1055 };
1056
1057 module_platform_driver(pmic_gpio_driver);
1058
1059 MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>");
1060 MODULE_DESCRIPTION("Qualcomm SPMI PMIC GPIO pin control driver");
1061 MODULE_ALIAS("platform:qcom-spmi-gpio");
1062 MODULE_LICENSE("GPL v2");
CRIS linux kernel tree