drivers/pinctrl/samsung/pinctrl-exynos-arm.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 //
   3 // Exynos specific support for Samsung pinctrl/gpiolib driver with eint support.
   4 //
   5 // Copyright (c) 2012 Samsung Electronics Co., Ltd.
   6 //              http://www.samsung.com
   7 // Copyright (c) 2012 Linaro Ltd
   8 //              http://www.linaro.org
   9 //
  10 // Author: Thomas Abraham <thomas.ab@samsung.com>
  11 //
  12 // This file contains the Samsung Exynos specific information required by the
  13 // the Samsung pinctrl/gpiolib driver. It also includes the implementation of
  14 // external gpio and wakeup interrupt support.
  15
  16 #include <linux/device.h>
  17 #include <linux/of_address.h>
  18 #include <linux/slab.h>
  19 #include <linux/err.h>
  20 #include <linux/soc/samsung/exynos-regs-pmu.h>
  21
  22 #include "pinctrl-samsung.h"
  23 #include "pinctrl-exynos.h"
  24
  25 static const struct samsung_pin_bank_type bank_type_off = {
  26         .fld_width = { 4, 1, 2, 2, 2, 2, },
  27         .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
  28 };
  29
  30 static const struct samsung_pin_bank_type bank_type_alive = {
  31         .fld_width = { 4, 1, 2, 2, },
  32         .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
  33 };
  34
  35 /* Retention control for S5PV210 are located at the end of clock controller */
  36 #define S5P_OTHERS 0xE000
  37
  38 #define S5P_OTHERS_RET_IO               (1 << 31)
  39 #define S5P_OTHERS_RET_CF               (1 << 30)
  40 #define S5P_OTHERS_RET_MMC              (1 << 29)
  41 #define S5P_OTHERS_RET_UART             (1 << 28)
  42
  43 static void s5pv210_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
  44 {
  45         void __iomem *clk_base = (void __iomem *)drvdata->retention_ctrl->priv;
  46         u32 tmp;
  47
  48         tmp = __raw_readl(clk_base + S5P_OTHERS);
  49         tmp |= (S5P_OTHERS_RET_IO | S5P_OTHERS_RET_CF | S5P_OTHERS_RET_MMC |
  50                 S5P_OTHERS_RET_UART);
  51         __raw_writel(tmp, clk_base + S5P_OTHERS);
  52 }
  53
  54 static struct samsung_retention_ctrl *
  55 s5pv210_retention_init(struct samsung_pinctrl_drv_data *drvdata,
  56                        const struct samsung_retention_data *data)
  57 {
  58         struct samsung_retention_ctrl *ctrl;
  59         struct device_node *np;
  60         void __iomem *clk_base;
  61
  62         ctrl = devm_kzalloc(drvdata->dev, sizeof(*ctrl), GFP_KERNEL);
  63         if (!ctrl)
  64                 return ERR_PTR(-ENOMEM);
  65
  66         np = of_find_compatible_node(NULL, NULL, "samsung,s5pv210-clock");
  67         if (!np) {
  68                 pr_err("%s: failed to find clock controller DT node\n",
  69                         __func__);
  70                 return ERR_PTR(-ENODEV);
  71         }
  72
  73         clk_base = of_iomap(np, 0);
  74         if (!clk_base) {
  75                 pr_err("%s: failed to map clock registers\n", __func__);
  76                 return ERR_PTR(-EINVAL);
  77         }
  78
  79         ctrl->priv = (void __force *)clk_base;
  80         ctrl->disable = s5pv210_retention_disable;
  81
  82         return ctrl;
  83 }
  84
  85 static const struct samsung_retention_data s5pv210_retention_data __initconst = {
  86         .init    = s5pv210_retention_init,
  87 };
  88
  89 /* pin banks of s5pv210 pin-controller */
  90 static const struct samsung_pin_bank_data s5pv210_pin_bank[] __initconst = {
  91         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
  92         EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04),
  93         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
  94         EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
  95         EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
  96         EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
  97         EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18),
  98         EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpe0", 0x1c),
  99         EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpe1", 0x20),
 100         EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpf0", 0x24),
 101         EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpf1", 0x28),
 102         EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpf2", 0x2c),
 103         EXYNOS_PIN_BANK_EINTG(6, 0x180, "gpf3", 0x30),
 104         EXYNOS_PIN_BANK_EINTG(7, 0x1a0, "gpg0", 0x34),
 105         EXYNOS_PIN_BANK_EINTG(7, 0x1c0, "gpg1", 0x38),
 106         EXYNOS_PIN_BANK_EINTG(7, 0x1e0, "gpg2", 0x3c),
 107         EXYNOS_PIN_BANK_EINTG(7, 0x200, "gpg3", 0x40),
 108         EXYNOS_PIN_BANK_EINTN(7, 0x220, "gpi"),
 109         EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x44),
 110         EXYNOS_PIN_BANK_EINTG(6, 0x260, "gpj1", 0x48),
 111         EXYNOS_PIN_BANK_EINTG(8, 0x280, "gpj2", 0x4c),
 112         EXYNOS_PIN_BANK_EINTG(8, 0x2a0, "gpj3", 0x50),
 113         EXYNOS_PIN_BANK_EINTG(5, 0x2c0, "gpj4", 0x54),
 114         EXYNOS_PIN_BANK_EINTN(8, 0x2e0, "mp01"),
 115         EXYNOS_PIN_BANK_EINTN(4, 0x300, "mp02"),
 116         EXYNOS_PIN_BANK_EINTN(8, 0x320, "mp03"),
 117         EXYNOS_PIN_BANK_EINTN(8, 0x340, "mp04"),
 118         EXYNOS_PIN_BANK_EINTN(8, 0x360, "mp05"),
 119         EXYNOS_PIN_BANK_EINTN(8, 0x380, "mp06"),
 120         EXYNOS_PIN_BANK_EINTN(8, 0x3a0, "mp07"),
 121         EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gph0", 0x00),
 122         EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gph1", 0x04),
 123         EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gph2", 0x08),
 124         EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gph3", 0x0c),
 125 };
 126
 127 const struct samsung_pin_ctrl s5pv210_pin_ctrl[] __initconst = {
 128         {
 129                 /* pin-controller instance 0 data */
 130                 .pin_banks      = s5pv210_pin_bank,
 131                 .nr_banks       = ARRAY_SIZE(s5pv210_pin_bank),
 132                 .eint_gpio_init = exynos_eint_gpio_init,
 133                 .eint_wkup_init = exynos_eint_wkup_init,
 134                 .suspend        = exynos_pinctrl_suspend,
 135                 .resume         = exynos_pinctrl_resume,
 136                 .retention_data = &s5pv210_retention_data,
 137         },
 138 };
 139
 140 /* Pad retention control code for accessing PMU regmap */
 141 static atomic_t exynos_shared_retention_refcnt;
 142
 143 /* pin banks of exynos3250 pin-controller 0 */
 144 static const struct samsung_pin_bank_data exynos3250_pin_banks0[] __initconst = {
 145         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
 146         EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
 147         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb",  0x08),
 148         EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
 149         EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
 150         EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
 151         EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpd1", 0x18),
 152 };
 153
 154 /* pin banks of exynos3250 pin-controller 1 */
 155 static const struct samsung_pin_bank_data exynos3250_pin_banks1[] __initconst = {
 156         EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpe0"),
 157         EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpe1"),
 158         EXYNOS_PIN_BANK_EINTN(3, 0x180, "gpe2"),
 159         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpk0", 0x08),
 160         EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
 161         EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
 162         EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpl0", 0x18),
 163         EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24),
 164         EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28),
 165         EXYNOS_PIN_BANK_EINTG(5, 0x2a0, "gpm2", 0x2c),
 166         EXYNOS_PIN_BANK_EINTG(8, 0x2c0, "gpm3", 0x30),
 167         EXYNOS_PIN_BANK_EINTG(8, 0x2e0, "gpm4", 0x34),
 168         EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00),
 169         EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04),
 170         EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08),
 171         EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c),
 172 };
 173
 174 /*
 175  * PMU pad retention groups for Exynos3250 doesn't match pin banks, so handle
 176  * them all together
 177  */
 178 static const u32 exynos3250_retention_regs[] = {
 179         S5P_PAD_RET_MAUDIO_OPTION,
 180         S5P_PAD_RET_GPIO_OPTION,
 181         S5P_PAD_RET_UART_OPTION,
 182         S5P_PAD_RET_MMCA_OPTION,
 183         S5P_PAD_RET_MMCB_OPTION,
 184         S5P_PAD_RET_EBIA_OPTION,
 185         S5P_PAD_RET_EBIB_OPTION,
 186         S5P_PAD_RET_MMC2_OPTION,
 187         S5P_PAD_RET_SPI_OPTION,
 188 };
 189
 190 static const struct samsung_retention_data exynos3250_retention_data __initconst = {
 191         .regs    = exynos3250_retention_regs,
 192         .nr_regs = ARRAY_SIZE(exynos3250_retention_regs),
 193         .value   = EXYNOS_WAKEUP_FROM_LOWPWR,
 194         .refcnt  = &exynos_shared_retention_refcnt,
 195         .init    = exynos_retention_init,
 196 };
 197
 198 /*
 199  * Samsung pinctrl driver data for Exynos3250 SoC. Exynos3250 SoC includes
 200  * two gpio/pin-mux/pinconfig controllers.
 201  */
 202 const struct samsung_pin_ctrl exynos3250_pin_ctrl[] __initconst = {
 203         {
 204                 /* pin-controller instance 0 data */
 205                 .pin_banks      = exynos3250_pin_banks0,
 206                 .nr_banks       = ARRAY_SIZE(exynos3250_pin_banks0),
 207                 .eint_gpio_init = exynos_eint_gpio_init,
 208                 .suspend        = exynos_pinctrl_suspend,
 209                 .resume         = exynos_pinctrl_resume,
 210                 .retention_data = &exynos3250_retention_data,
 211         }, {
 212                 /* pin-controller instance 1 data */
 213                 .pin_banks      = exynos3250_pin_banks1,
 214                 .nr_banks       = ARRAY_SIZE(exynos3250_pin_banks1),
 215                 .eint_gpio_init = exynos_eint_gpio_init,
 216                 .eint_wkup_init = exynos_eint_wkup_init,
 217                 .suspend        = exynos_pinctrl_suspend,
 218                 .resume         = exynos_pinctrl_resume,
 219                 .retention_data = &exynos3250_retention_data,
 220         },
 221 };
 222
 223 /* pin banks of exynos4210 pin-controller 0 */
 224 static const struct samsung_pin_bank_data exynos4210_pin_banks0[] __initconst = {
 225         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
 226         EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
 227         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
 228         EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
 229         EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
 230         EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),
 231         EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18),
 232         EXYNOS_PIN_BANK_EINTG(5, 0x0E0, "gpe0", 0x1c),
 233         EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpe1", 0x20),
 234         EXYNOS_PIN_BANK_EINTG(6, 0x120, "gpe2", 0x24),
 235         EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpe3", 0x28),
 236         EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpe4", 0x2c),
 237         EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30),
 238         EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34),
 239         EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38),
 240         EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c),
 241 };
 242
 243 /* pin banks of exynos4210 pin-controller 1 */
 244 static const struct samsung_pin_bank_data exynos4210_pin_banks1[] __initconst = {
 245         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpj0", 0x00),
 246         EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpj1", 0x04),
 247         EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08),
 248         EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
 249         EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
 250         EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14),
 251         EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpl0", 0x18),
 252         EXYNOS_PIN_BANK_EINTG(3, 0x0E0, "gpl1", 0x1c),
 253         EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20),
 254         EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"),
 255         EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"),
 256         EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"),
 257         EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"),
 258         EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"),
 259         EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"),
 260         EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"),
 261         EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
 262         EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
 263         EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
 264         EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
 265 };
 266
 267 /* pin banks of exynos4210 pin-controller 2 */
 268 static const struct samsung_pin_bank_data exynos4210_pin_banks2[] __initconst = {
 269         EXYNOS_PIN_BANK_EINTN(7, 0x000, "gpz"),
 270 };
 271
 272 /* PMU pad retention groups registers for Exynos4 (without audio) */
 273 static const u32 exynos4_retention_regs[] = {
 274         S5P_PAD_RET_GPIO_OPTION,
 275         S5P_PAD_RET_UART_OPTION,
 276         S5P_PAD_RET_MMCA_OPTION,
 277         S5P_PAD_RET_MMCB_OPTION,
 278         S5P_PAD_RET_EBIA_OPTION,
 279         S5P_PAD_RET_EBIB_OPTION,
 280 };
 281
 282 static const struct samsung_retention_data exynos4_retention_data __initconst = {
 283         .regs    = exynos4_retention_regs,
 284         .nr_regs = ARRAY_SIZE(exynos4_retention_regs),
 285         .value   = EXYNOS_WAKEUP_FROM_LOWPWR,
 286         .refcnt  = &exynos_shared_retention_refcnt,
 287         .init    = exynos_retention_init,
 288 };
 289
 290 /* PMU retention control for audio pins can be tied to audio pin bank */
 291 static const u32 exynos4_audio_retention_regs[] = {
 292         S5P_PAD_RET_MAUDIO_OPTION,
 293 };
 294
 295 static const struct samsung_retention_data exynos4_audio_retention_data __initconst = {
 296         .regs    = exynos4_audio_retention_regs,
 297         .nr_regs = ARRAY_SIZE(exynos4_audio_retention_regs),
 298         .value   = EXYNOS_WAKEUP_FROM_LOWPWR,
 299         .init    = exynos_retention_init,
 300 };
 301
 302 /*
 303  * Samsung pinctrl driver data for Exynos4210 SoC. Exynos4210 SoC includes
 304  * three gpio/pin-mux/pinconfig controllers.
 305  */
 306 const struct samsung_pin_ctrl exynos4210_pin_ctrl[] __initconst = {
 307         {
 308                 /* pin-controller instance 0 data */
 309                 .pin_banks      = exynos4210_pin_banks0,
 310                 .nr_banks       = ARRAY_SIZE(exynos4210_pin_banks0),
 311                 .eint_gpio_init = exynos_eint_gpio_init,
 312                 .suspend        = exynos_pinctrl_suspend,
 313                 .resume         = exynos_pinctrl_resume,
 314                 .retention_data = &exynos4_retention_data,
 315         }, {
 316                 /* pin-controller instance 1 data */
 317                 .pin_banks      = exynos4210_pin_banks1,
 318                 .nr_banks       = ARRAY_SIZE(exynos4210_pin_banks1),
 319                 .eint_gpio_init = exynos_eint_gpio_init,
 320                 .eint_wkup_init = exynos_eint_wkup_init,
 321                 .suspend        = exynos_pinctrl_suspend,
 322                 .resume         = exynos_pinctrl_resume,
 323                 .retention_data = &exynos4_retention_data,
 324         }, {
 325                 /* pin-controller instance 2 data */
 326                 .pin_banks      = exynos4210_pin_banks2,
 327                 .nr_banks       = ARRAY_SIZE(exynos4210_pin_banks2),
 328                 .retention_data = &exynos4_audio_retention_data,
 329         },
 330 };
 331
 332 /* pin banks of exynos4x12 pin-controller 0 */
 333 static const struct samsung_pin_bank_data exynos4x12_pin_banks0[] __initconst = {
 334         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
 335         EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
 336         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
 337         EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
 338         EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
 339         EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),
 340         EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18),
 341         EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30),
 342         EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34),
 343         EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38),
 344         EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c),
 345         EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x40),
 346         EXYNOS_PIN_BANK_EINTG(5, 0x260, "gpj1", 0x44),
 347 };
 348
 349 /* pin banks of exynos4x12 pin-controller 1 */
 350 static const struct samsung_pin_bank_data exynos4x12_pin_banks1[] __initconst = {
 351         EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08),
 352         EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
 353         EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
 354         EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14),
 355         EXYNOS_PIN_BANK_EINTG(7, 0x0C0, "gpl0", 0x18),
 356         EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpl1", 0x1c),
 357         EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20),
 358         EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24),
 359         EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28),
 360         EXYNOS_PIN_BANK_EINTG(5, 0x2A0, "gpm2", 0x2c),
 361         EXYNOS_PIN_BANK_EINTG(8, 0x2C0, "gpm3", 0x30),
 362         EXYNOS_PIN_BANK_EINTG(8, 0x2E0, "gpm4", 0x34),
 363         EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"),
 364         EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"),
 365         EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"),
 366         EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"),
 367         EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"),
 368         EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"),
 369         EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"),
 370         EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
 371         EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
 372         EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
 373         EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
 374 };
 375
 376 /* pin banks of exynos4x12 pin-controller 2 */
 377 static const struct samsung_pin_bank_data exynos4x12_pin_banks2[] __initconst = {
 378         EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
 379 };
 380
 381 /* pin banks of exynos4x12 pin-controller 3 */
 382 static const struct samsung_pin_bank_data exynos4x12_pin_banks3[] __initconst = {
 383         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
 384         EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
 385         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpv2", 0x08),
 386         EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv3", 0x0c),
 387         EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpv4", 0x10),
 388 };
 389
 390 /*
 391  * Samsung pinctrl driver data for Exynos4x12 SoC. Exynos4x12 SoC includes
 392  * four gpio/pin-mux/pinconfig controllers.
 393  */
 394 const struct samsung_pin_ctrl exynos4x12_pin_ctrl[] __initconst = {
 395         {
 396                 /* pin-controller instance 0 data */
 397                 .pin_banks      = exynos4x12_pin_banks0,
 398                 .nr_banks       = ARRAY_SIZE(exynos4x12_pin_banks0),
 399                 .eint_gpio_init = exynos_eint_gpio_init,
 400                 .suspend        = exynos_pinctrl_suspend,
 401                 .resume         = exynos_pinctrl_resume,
 402                 .retention_data = &exynos4_retention_data,
 403         }, {
 404                 /* pin-controller instance 1 data */
 405                 .pin_banks      = exynos4x12_pin_banks1,
 406                 .nr_banks       = ARRAY_SIZE(exynos4x12_pin_banks1),
 407                 .eint_gpio_init = exynos_eint_gpio_init,
 408                 .eint_wkup_init = exynos_eint_wkup_init,
 409                 .suspend        = exynos_pinctrl_suspend,
 410                 .resume         = exynos_pinctrl_resume,
 411                 .retention_data = &exynos4_retention_data,
 412         }, {
 413                 /* pin-controller instance 2 data */
 414                 .pin_banks      = exynos4x12_pin_banks2,
 415                 .nr_banks       = ARRAY_SIZE(exynos4x12_pin_banks2),
 416                 .eint_gpio_init = exynos_eint_gpio_init,
 417                 .suspend        = exynos_pinctrl_suspend,
 418                 .resume         = exynos_pinctrl_resume,
 419                 .retention_data = &exynos4_audio_retention_data,
 420         }, {
 421                 /* pin-controller instance 3 data */
 422                 .pin_banks      = exynos4x12_pin_banks3,
 423                 .nr_banks       = ARRAY_SIZE(exynos4x12_pin_banks3),
 424                 .eint_gpio_init = exynos_eint_gpio_init,
 425                 .suspend        = exynos_pinctrl_suspend,
 426                 .resume         = exynos_pinctrl_resume,
 427         },
 428 };
 429
 430 /* pin banks of exynos5250 pin-controller 0 */
 431 static const struct samsung_pin_bank_data exynos5250_pin_banks0[] __initconst = {
 432         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
 433         EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
 434         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
 435         EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
 436         EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
 437         EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
 438         EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18),
 439         EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c),
 440         EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc1", 0x20),
 441         EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc2", 0x24),
 442         EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc3", 0x28),
 443         EXYNOS_PIN_BANK_EINTG(4, 0x160, "gpd0", 0x2c),
 444         EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x30),
 445         EXYNOS_PIN_BANK_EINTG(7, 0x2E0, "gpc4", 0x34),
 446         EXYNOS_PIN_BANK_EINTN(6, 0x1A0, "gpy0"),
 447         EXYNOS_PIN_BANK_EINTN(4, 0x1C0, "gpy1"),
 448         EXYNOS_PIN_BANK_EINTN(6, 0x1E0, "gpy2"),
 449         EXYNOS_PIN_BANK_EINTN(8, 0x200, "gpy3"),
 450         EXYNOS_PIN_BANK_EINTN(8, 0x220, "gpy4"),
 451         EXYNOS_PIN_BANK_EINTN(8, 0x240, "gpy5"),
 452         EXYNOS_PIN_BANK_EINTN(8, 0x260, "gpy6"),
 453         EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
 454         EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
 455         EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
 456         EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
 457 };
 458
 459 /* pin banks of exynos5250 pin-controller 1 */
 460 static const struct samsung_pin_bank_data exynos5250_pin_banks1[] __initconst = {
 461         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00),
 462         EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04),
 463         EXYNOS_PIN_BANK_EINTG(4, 0x040, "gpf0", 0x08),
 464         EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf1", 0x0c),
 465         EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10),
 466         EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14),
 467         EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18),
 468         EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gph0", 0x1c),
 469         EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph1", 0x20),
 470 };
 471
 472 /* pin banks of exynos5250 pin-controller 2 */
 473 static const struct samsung_pin_bank_data exynos5250_pin_banks2[] __initconst = {
 474         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
 475         EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
 476         EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08),
 477         EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c),
 478         EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10),
 479 };
 480
 481 /* pin banks of exynos5250 pin-controller 3 */
 482 static const struct samsung_pin_bank_data exynos5250_pin_banks3[] __initconst = {
 483         EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
 484 };
 485
 486 /*
 487  * Samsung pinctrl driver data for Exynos5250 SoC. Exynos5250 SoC includes
 488  * four gpio/pin-mux/pinconfig controllers.
 489  */
 490 const struct samsung_pin_ctrl exynos5250_pin_ctrl[] __initconst = {
 491         {
 492                 /* pin-controller instance 0 data */
 493                 .pin_banks      = exynos5250_pin_banks0,
 494                 .nr_banks       = ARRAY_SIZE(exynos5250_pin_banks0),
 495                 .eint_gpio_init = exynos_eint_gpio_init,
 496                 .eint_wkup_init = exynos_eint_wkup_init,
 497                 .suspend        = exynos_pinctrl_suspend,
 498                 .resume         = exynos_pinctrl_resume,
 499                 .retention_data = &exynos4_retention_data,
 500         }, {
 501                 /* pin-controller instance 1 data */
 502                 .pin_banks      = exynos5250_pin_banks1,
 503                 .nr_banks       = ARRAY_SIZE(exynos5250_pin_banks1),
 504                 .eint_gpio_init = exynos_eint_gpio_init,
 505                 .suspend        = exynos_pinctrl_suspend,
 506                 .resume         = exynos_pinctrl_resume,
 507                 .retention_data = &exynos4_retention_data,
 508         }, {
 509                 /* pin-controller instance 2 data */
 510                 .pin_banks      = exynos5250_pin_banks2,
 511                 .nr_banks       = ARRAY_SIZE(exynos5250_pin_banks2),
 512                 .eint_gpio_init = exynos_eint_gpio_init,
 513                 .suspend        = exynos_pinctrl_suspend,
 514                 .resume         = exynos_pinctrl_resume,
 515         }, {
 516                 /* pin-controller instance 3 data */
 517                 .pin_banks      = exynos5250_pin_banks3,
 518                 .nr_banks       = ARRAY_SIZE(exynos5250_pin_banks3),
 519                 .eint_gpio_init = exynos_eint_gpio_init,
 520                 .suspend        = exynos_pinctrl_suspend,
 521                 .resume         = exynos_pinctrl_resume,
 522                 .retention_data = &exynos4_audio_retention_data,
 523         },
 524 };
 525
 526 /* pin banks of exynos5260 pin-controller 0 */
 527 static const struct samsung_pin_bank_data exynos5260_pin_banks0[] __initconst = {
 528         EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpa0", 0x00),
 529         EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpa1", 0x04),
 530         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
 531         EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
 532         EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpb1", 0x10),
 533         EXYNOS_PIN_BANK_EINTG(5, 0x0a0, "gpb2", 0x14),
 534         EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpb3", 0x18),
 535         EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpb4", 0x1c),
 536         EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpb5", 0x20),
 537         EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd0", 0x24),
 538         EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpd1", 0x28),
 539         EXYNOS_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c),
 540         EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpe0", 0x30),
 541         EXYNOS_PIN_BANK_EINTG(5, 0x1a0, "gpe1", 0x34),
 542         EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpf0", 0x38),
 543         EXYNOS_PIN_BANK_EINTG(8, 0x1e0, "gpf1", 0x3c),
 544         EXYNOS_PIN_BANK_EINTG(2, 0x200, "gpk0", 0x40),
 545         EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00),
 546         EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04),
 547         EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08),
 548         EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c),
 549 };
 550
 551 /* pin banks of exynos5260 pin-controller 1 */
 552 static const struct samsung_pin_bank_data exynos5260_pin_banks1[] __initconst = {
 553         EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpc0", 0x00),
 554         EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpc1", 0x04),
 555         EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08),
 556         EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c),
 557         EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpc4", 0x10),
 558 };
 559
 560 /* pin banks of exynos5260 pin-controller 2 */
 561 static const struct samsung_pin_bank_data exynos5260_pin_banks2[] __initconst = {
 562         EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
 563         EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
 564 };
 565
 566 /*
 567  * Samsung pinctrl driver data for Exynos5260 SoC. Exynos5260 SoC includes
 568  * three gpio/pin-mux/pinconfig controllers.
 569  */
 570 const struct samsung_pin_ctrl exynos5260_pin_ctrl[] __initconst = {
 571         {
 572                 /* pin-controller instance 0 data */
 573                 .pin_banks      = exynos5260_pin_banks0,
 574                 .nr_banks       = ARRAY_SIZE(exynos5260_pin_banks0),
 575                 .eint_gpio_init = exynos_eint_gpio_init,
 576                 .eint_wkup_init = exynos_eint_wkup_init,
 577         }, {
 578                 /* pin-controller instance 1 data */
 579                 .pin_banks      = exynos5260_pin_banks1,
 580                 .nr_banks       = ARRAY_SIZE(exynos5260_pin_banks1),
 581                 .eint_gpio_init = exynos_eint_gpio_init,
 582         }, {
 583                 /* pin-controller instance 2 data */
 584                 .pin_banks      = exynos5260_pin_banks2,
 585                 .nr_banks       = ARRAY_SIZE(exynos5260_pin_banks2),
 586                 .eint_gpio_init = exynos_eint_gpio_init,
 587         },
 588 };
 589
 590 /* pin banks of exynos5410 pin-controller 0 */
 591 static const struct samsung_pin_bank_data exynos5410_pin_banks0[] __initconst = {
 592         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
 593         EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
 594         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
 595         EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
 596         EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
 597         EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
 598         EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18),
 599         EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c),
 600         EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc3", 0x20),
 601         EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc1", 0x24),
 602         EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc2", 0x28),
 603         EXYNOS_PIN_BANK_EINTN(2, 0x160, "gpm5"),
 604         EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x2c),
 605         EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpe0", 0x30),
 606         EXYNOS_PIN_BANK_EINTG(2, 0x1C0, "gpe1", 0x34),
 607         EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf0", 0x38),
 608         EXYNOS_PIN_BANK_EINTG(8, 0x200, "gpf1", 0x3c),
 609         EXYNOS_PIN_BANK_EINTG(8, 0x220, "gpg0", 0x40),
 610         EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpg1", 0x44),
 611         EXYNOS_PIN_BANK_EINTG(2, 0x260, "gpg2", 0x48),
 612         EXYNOS_PIN_BANK_EINTG(4, 0x280, "gph0", 0x4c),
 613         EXYNOS_PIN_BANK_EINTG(8, 0x2A0, "gph1", 0x50),
 614         EXYNOS_PIN_BANK_EINTN(8, 0x2C0, "gpm7"),
 615         EXYNOS_PIN_BANK_EINTN(6, 0x2E0, "gpy0"),
 616         EXYNOS_PIN_BANK_EINTN(4, 0x300, "gpy1"),
 617         EXYNOS_PIN_BANK_EINTN(6, 0x320, "gpy2"),
 618         EXYNOS_PIN_BANK_EINTN(8, 0x340, "gpy3"),
 619         EXYNOS_PIN_BANK_EINTN(8, 0x360, "gpy4"),
 620         EXYNOS_PIN_BANK_EINTN(8, 0x380, "gpy5"),
 621         EXYNOS_PIN_BANK_EINTN(8, 0x3A0, "gpy6"),
 622         EXYNOS_PIN_BANK_EINTN(8, 0x3C0, "gpy7"),
 623         EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
 624         EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
 625         EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
 626         EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
 627 };
 628
 629 /* pin banks of exynos5410 pin-controller 1 */
 630 static const struct samsung_pin_bank_data exynos5410_pin_banks1[] __initconst = {
 631         EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpj0", 0x00),
 632         EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpj1", 0x04),
 633         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpj2", 0x08),
 634         EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpj3", 0x0c),
 635         EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpj4", 0x10),
 636         EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpk0", 0x14),
 637         EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpk1", 0x18),
 638         EXYNOS_PIN_BANK_EINTG(8, 0x0E0, "gpk2", 0x1c),
 639         EXYNOS_PIN_BANK_EINTG(7, 0x100, "gpk3", 0x20),
 640 };
 641
 642 /* pin banks of exynos5410 pin-controller 2 */
 643 static const struct samsung_pin_bank_data exynos5410_pin_banks2[] __initconst = {
 644         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
 645         EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
 646         EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08),
 647         EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c),
 648         EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10),
 649 };
 650
 651 /* pin banks of exynos5410 pin-controller 3 */
 652 static const struct samsung_pin_bank_data exynos5410_pin_banks3[] __initconst = {
 653         EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
 654 };
 655
 656 /*
 657  * Samsung pinctrl driver data for Exynos5410 SoC. Exynos5410 SoC includes
 658  * four gpio/pin-mux/pinconfig controllers.
 659  */
 660 const struct samsung_pin_ctrl exynos5410_pin_ctrl[] __initconst = {
 661         {
 662                 /* pin-controller instance 0 data */
 663                 .pin_banks      = exynos5410_pin_banks0,
 664                 .nr_banks       = ARRAY_SIZE(exynos5410_pin_banks0),
 665                 .eint_gpio_init = exynos_eint_gpio_init,
 666                 .eint_wkup_init = exynos_eint_wkup_init,
 667                 .suspend        = exynos_pinctrl_suspend,
 668                 .resume         = exynos_pinctrl_resume,
 669         }, {
 670                 /* pin-controller instance 1 data */
 671                 .pin_banks      = exynos5410_pin_banks1,
 672                 .nr_banks       = ARRAY_SIZE(exynos5410_pin_banks1),
 673                 .eint_gpio_init = exynos_eint_gpio_init,
 674                 .suspend        = exynos_pinctrl_suspend,
 675                 .resume         = exynos_pinctrl_resume,
 676         }, {
 677                 /* pin-controller instance 2 data */
 678                 .pin_banks      = exynos5410_pin_banks2,
 679                 .nr_banks       = ARRAY_SIZE(exynos5410_pin_banks2),
 680                 .eint_gpio_init = exynos_eint_gpio_init,
 681                 .suspend        = exynos_pinctrl_suspend,
 682                 .resume         = exynos_pinctrl_resume,
 683         }, {
 684                 /* pin-controller instance 3 data */
 685                 .pin_banks      = exynos5410_pin_banks3,
 686                 .nr_banks       = ARRAY_SIZE(exynos5410_pin_banks3),
 687                 .eint_gpio_init = exynos_eint_gpio_init,
 688                 .suspend        = exynos_pinctrl_suspend,
 689                 .resume         = exynos_pinctrl_resume,
 690         },
 691 };
 692
 693 /* pin banks of exynos5420 pin-controller 0 */
 694 static const struct samsung_pin_bank_data exynos5420_pin_banks0[] __initconst = {
 695         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00),
 696         EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
 697         EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
 698         EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
 699         EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
 700 };
 701
 702 /* pin banks of exynos5420 pin-controller 1 */
 703 static const struct samsung_pin_bank_data exynos5420_pin_banks1[] __initconst = {
 704         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpc0", 0x00),
 705         EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc1", 0x04),
 706         EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08),
 707         EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c),
 708         EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpc4", 0x10),
 709         EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpd1", 0x14),
 710         EXYNOS_PIN_BANK_EINTN(6, 0x0C0, "gpy0"),
 711         EXYNOS_PIN_BANK_EINTN(4, 0x0E0, "gpy1"),
 712         EXYNOS_PIN_BANK_EINTN(6, 0x100, "gpy2"),
 713         EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpy3"),
 714         EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpy4"),
 715         EXYNOS_PIN_BANK_EINTN(8, 0x160, "gpy5"),
 716         EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy6"),
 717 };
 718
 719 /* pin banks of exynos5420 pin-controller 2 */
 720 static const struct samsung_pin_bank_data exynos5420_pin_banks2[] __initconst = {
 721         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00),
 722         EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04),
 723         EXYNOS_PIN_BANK_EINTG(6, 0x040, "gpf0", 0x08),
 724         EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpf1", 0x0c),
 725         EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10),
 726         EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14),
 727         EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18),
 728         EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gpj4", 0x1c),
 729 };
 730
 731 /* pin banks of exynos5420 pin-controller 3 */
 732 static const struct samsung_pin_bank_data exynos5420_pin_banks3[] __initconst = {
 733         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
 734         EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
 735         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
 736         EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
 737         EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
 738         EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
 739         EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpb3", 0x18),
 740         EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpb4", 0x1c),
 741         EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph0", 0x20),
 742 };
 743
 744 /* pin banks of exynos5420 pin-controller 4 */
 745 static const struct samsung_pin_bank_data exynos5420_pin_banks4[] __initconst = {
 746         EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
 747 };
 748
 749 /* PMU pad retention groups registers for Exynos5420 (without audio) */
 750 static const u32 exynos5420_retention_regs[] = {
 751         EXYNOS_PAD_RET_DRAM_OPTION,
 752         EXYNOS_PAD_RET_JTAG_OPTION,
 753         EXYNOS5420_PAD_RET_GPIO_OPTION,
 754         EXYNOS5420_PAD_RET_UART_OPTION,
 755         EXYNOS5420_PAD_RET_MMCA_OPTION,
 756         EXYNOS5420_PAD_RET_MMCB_OPTION,
 757         EXYNOS5420_PAD_RET_MMCC_OPTION,
 758         EXYNOS5420_PAD_RET_HSI_OPTION,
 759         EXYNOS_PAD_RET_EBIA_OPTION,
 760         EXYNOS_PAD_RET_EBIB_OPTION,
 761         EXYNOS5420_PAD_RET_SPI_OPTION,
 762         EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION,
 763 };
 764
 765 static const struct samsung_retention_data exynos5420_retention_data __initconst = {
 766         .regs    = exynos5420_retention_regs,
 767         .nr_regs = ARRAY_SIZE(exynos5420_retention_regs),
 768         .value   = EXYNOS_WAKEUP_FROM_LOWPWR,
 769         .refcnt  = &exynos_shared_retention_refcnt,
 770         .init    = exynos_retention_init,
 771 };
 772
 773 /*
 774  * Samsung pinctrl driver data for Exynos5420 SoC. Exynos5420 SoC includes
 775  * four gpio/pin-mux/pinconfig controllers.
 776  */
 777 const struct samsung_pin_ctrl exynos5420_pin_ctrl[] __initconst = {
 778         {
 779                 /* pin-controller instance 0 data */
 780                 .pin_banks      = exynos5420_pin_banks0,
 781                 .nr_banks       = ARRAY_SIZE(exynos5420_pin_banks0),
 782                 .eint_gpio_init = exynos_eint_gpio_init,
 783                 .eint_wkup_init = exynos_eint_wkup_init,
 784                 .retention_data = &exynos5420_retention_data,
 785         }, {
 786                 /* pin-controller instance 1 data */
 787                 .pin_banks      = exynos5420_pin_banks1,
 788                 .nr_banks       = ARRAY_SIZE(exynos5420_pin_banks1),
 789                 .eint_gpio_init = exynos_eint_gpio_init,
 790                 .retention_data = &exynos5420_retention_data,
 791         }, {
 792                 /* pin-controller instance 2 data */
 793                 .pin_banks      = exynos5420_pin_banks2,
 794                 .nr_banks       = ARRAY_SIZE(exynos5420_pin_banks2),
 795                 .eint_gpio_init = exynos_eint_gpio_init,
 796                 .retention_data = &exynos5420_retention_data,
 797         }, {
 798                 /* pin-controller instance 3 data */
 799                 .pin_banks      = exynos5420_pin_banks3,
 800                 .nr_banks       = ARRAY_SIZE(exynos5420_pin_banks3),
 801                 .eint_gpio_init = exynos_eint_gpio_init,
 802                 .retention_data = &exynos5420_retention_data,
 803         }, {
 804                 /* pin-controller instance 4 data */
 805                 .pin_banks      = exynos5420_pin_banks4,
 806                 .nr_banks       = ARRAY_SIZE(exynos5420_pin_banks4),
 807                 .eint_gpio_init = exynos_eint_gpio_init,
 808                 .retention_data = &exynos4_audio_retention_data,
 809         },
 810 };